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ARMv7-M SysTick fix.
[qemu.git] / hw / stellaris.c
CommitLineData
9ee6e8bb
PB		 1/*
2 * Luminary Micro Stellaris preipherals
3 *
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licenced under the GPL.
8 */
9
87ecb68b
PB		 10#include "hw.h"
11#include "arm-misc.h"
12#include "primecell.h"
13#include "devices.h"
14#include "qemu-timer.h"
15#include "i2c.h"
16#include "sysemu.h"
17#include "boards.h"
9ee6e8bb 18
cf0dbb21
PB		 19#define GPIO_A 0
20#define GPIO_B 1
21#define GPIO_C 2
22#define GPIO_D 3
23#define GPIO_E 4
24#define GPIO_F 5
25#define GPIO_G 6
26
27#define BP_OLED_I2C 0x01
28#define BP_OLED_SSI 0x02
29#define BP_GAMEPAD 0x04
30
9ee6e8bb
PB		 31typedef const struct {
32 const char *name;
33 uint32_t did0;
34 uint32_t did1;
35 uint32_t dc0;
36 uint32_t dc1;
37 uint32_t dc2;
38 uint32_t dc3;
39 uint32_t dc4;
cf0dbb21 40 uint32_t peripherals;
9ee6e8bb
PB		 41} stellaris_board_info;
42
43/* General purpose timer module. */
44
9ee6e8bb
PB		 45typedef struct gptm_state {
46 uint32_t config;
47 uint32_t mode[2];
48 uint32_t control;
49 uint32_t state;
50 uint32_t mask;
51 uint32_t load[2];
52 uint32_t match[2];
53 uint32_t prescale[2];
54 uint32_t match_prescale[2];
55 uint32_t rtc;
56 int64_t tick[2];
57 struct gptm_state *opaque[2];
58 uint32_t base;
59 QEMUTimer *timer[2];
60 /* The timers have an alternate output used to trigger the ADC. */
61 qemu_irq trigger;
62 qemu_irq irq;
63} gptm_state;
64
65static void gptm_update_irq(gptm_state *s)
66{
67 int level;
68 level = (s->state & s->mask) != 0;
69 qemu_set_irq(s->irq, level);
70}
71
72static void gptm_stop(gptm_state *s, int n)
73{
74 qemu_del_timer(s->timer[n]);
75}
76
77static void gptm_reload(gptm_state *s, int n, int reset)
78{
79 int64_t tick;
80 if (reset)
81 tick = qemu_get_clock(vm_clock);
82 else
83 tick = s->tick[n];
84
85 if (s->config == 0) {
86 /* 32-bit CountDown. */
87 uint32_t count;
88 count = s->load[0] | (s->load[1] << 16);
e57ec016 89 tick += (int64_t)count * system_clock_scale;
9ee6e8bb
PB		 90 } else if (s->config == 1) {
91 /* 32-bit RTC. 1Hz tick. */
92 tick += ticks_per_sec;
93 } else if (s->mode[n] == 0xa) {
94 /* PWM mode. Not implemented. */
95 } else {
96 cpu_abort(cpu_single_env, "TODO: 16-bit timer mode 0x%x\n",
97 s->mode[n]);
98 }
99 s->tick[n] = tick;
100 qemu_mod_timer(s->timer[n], tick);
101}
102
103static void gptm_tick(void *opaque)
104{
105 gptm_state **p = (gptm_state **)opaque;
106 gptm_state *s;
107 int n;
108
109 s = *p;
110 n = p - s->opaque;
111 if (s->config == 0) {
112 s->state |= 1;
113 if ((s->control & 0x20)) {
114 /* Output trigger. */
115 qemu_irq_raise(s->trigger);
116 qemu_irq_lower(s->trigger);
117 }
118 if (s->mode[0] & 1) {
119 /* One-shot. */
120 s->control &= ~1;
121 } else {
122 /* Periodic. */
123 gptm_reload(s, 0, 0);
124 }
125 } else if (s->config == 1) {
126 /* RTC. */
127 uint32_t match;
128 s->rtc++;
129 match = s->match[0] | (s->match[1] << 16);
130 if (s->rtc > match)
131 s->rtc = 0;
132 if (s->rtc == 0) {
133 s->state |= 8;
134 }
135 gptm_reload(s, 0, 0);
136 } else if (s->mode[n] == 0xa) {
137 /* PWM mode. Not implemented. */
138 } else {
139 cpu_abort(cpu_single_env, "TODO: 16-bit timer mode 0x%x\n",
140 s->mode[n]);
141 }
142 gptm_update_irq(s);
143}
144
145static uint32_t gptm_read(void *opaque, target_phys_addr_t offset)
146{
147 gptm_state *s = (gptm_state *)opaque;
148
149 offset -= s->base;
150 switch (offset) {
151 case 0x00: /* CFG */
152 return s->config;
153 case 0x04: /* TAMR */
154 return s->mode[0];
155 case 0x08: /* TBMR */
156 return s->mode[1];
157 case 0x0c: /* CTL */
158 return s->control;
159 case 0x18: /* IMR */
160 return s->mask;
161 case 0x1c: /* RIS */
162 return s->state;
163 case 0x20: /* MIS */
164 return s->state & s->mask;
165 case 0x24: /* CR */
166 return 0;
167 case 0x28: /* TAILR */
168 return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0);
169 case 0x2c: /* TBILR */
170 return s->load[1];
171 case 0x30: /* TAMARCHR */
172 return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0);
173 case 0x34: /* TBMATCHR */
174 return s->match[1];
175 case 0x38: /* TAPR */
176 return s->prescale[0];
177 case 0x3c: /* TBPR */
178 return s->prescale[1];
179 case 0x40: /* TAPMR */
180 return s->match_prescale[0];
181 case 0x44: /* TBPMR */
182 return s->match_prescale[1];
183 case 0x48: /* TAR */
184 if (s->control == 1)
185 return s->rtc;
186 case 0x4c: /* TBR */
187 cpu_abort(cpu_single_env, "TODO: Timer value read\n");
188 default:
189 cpu_abort(cpu_single_env, "gptm_read: Bad offset 0x%x\n", (int)offset);
190 return 0;
191 }
192}
193
194static void gptm_write(void *opaque, target_phys_addr_t offset, uint32_t value)
195{
196 gptm_state *s = (gptm_state *)opaque;
197 uint32_t oldval;
198
199 offset -= s->base;
200 /* The timers should be disabled before changing the configuration.
201 We take advantage of this and defer everything until the timer
202 is enabled. */
203 switch (offset) {
204 case 0x00: /* CFG */
205 s->config = value;
206 break;
207 case 0x04: /* TAMR */
208 s->mode[0] = value;
209 break;
210 case 0x08: /* TBMR */
211 s->mode[1] = value;
212 break;
213 case 0x0c: /* CTL */
214 oldval = s->control;
215 s->control = value;
216 /* TODO: Implement pause. */
217 if ((oldval ^ value) & 1) {
218 if (value & 1) {
219 gptm_reload(s, 0, 1);
220 } else {
221 gptm_stop(s, 0);
222 }
223 }
224 if (((oldval ^ value) & 0x100) && s->config >= 4) {
225 if (value & 0x100) {
226 gptm_reload(s, 1, 1);
227 } else {
228 gptm_stop(s, 1);
229 }
230 }
231 break;
232 case 0x18: /* IMR */
233 s->mask = value & 0x77;
234 gptm_update_irq(s);
235 break;
236 case 0x24: /* CR */
237 s->state &= ~value;
238 break;
239 case 0x28: /* TAILR */
240 s->load[0] = value & 0xffff;
241 if (s->config < 4) {
242 s->load[1] = value >> 16;
243 }
244 break;
245 case 0x2c: /* TBILR */
246 s->load[1] = value & 0xffff;
247 break;
248 case 0x30: /* TAMARCHR */
249 s->match[0] = value & 0xffff;
250 if (s->config < 4) {
251 s->match[1] = value >> 16;
252 }
253 break;
254 case 0x34: /* TBMATCHR */
255 s->match[1] = value >> 16;
256 break;
257 case 0x38: /* TAPR */
258 s->prescale[0] = value;
259 break;
260 case 0x3c: /* TBPR */
261 s->prescale[1] = value;
262 break;
263 case 0x40: /* TAPMR */
264 s->match_prescale[0] = value;
265 break;
266 case 0x44: /* TBPMR */
267 s->match_prescale[0] = value;
268 break;
269 default:
270 cpu_abort(cpu_single_env, "gptm_write: Bad offset 0x%x\n", (int)offset);
271 }
272 gptm_update_irq(s);
273}
274
275static CPUReadMemoryFunc *gptm_readfn[] = {
276 gptm_read,
277 gptm_read,
278 gptm_read
279};
280
281static CPUWriteMemoryFunc *gptm_writefn[] = {
282 gptm_write,
283 gptm_write,
284 gptm_write
285};
286
287static void stellaris_gptm_init(uint32_t base, qemu_irq irq, qemu_irq trigger)
288{
289 int iomemtype;
290 gptm_state *s;
291
292 s = (gptm_state *)qemu_mallocz(sizeof(gptm_state));
293 s->base = base;
294 s->irq = irq;
295 s->trigger = trigger;
296 s->opaque[0] = s->opaque[1] = s;
297
298 iomemtype = cpu_register_io_memory(0, gptm_readfn,
299 gptm_writefn, s);
300 cpu_register_physical_memory(base, 0x00001000, iomemtype);
301 s->timer[0] = qemu_new_timer(vm_clock, gptm_tick, &s->opaque[0]);
302 s->timer[1] = qemu_new_timer(vm_clock, gptm_tick, &s->opaque[1]);
303 /* ??? Save/restore. */
304}
305
306
307/* System controller. */
308
309typedef struct {
310 uint32_t base;
311 uint32_t pborctl;
312 uint32_t ldopctl;
313 uint32_t int_status;
314 uint32_t int_mask;
315 uint32_t resc;
316 uint32_t rcc;
317 uint32_t rcgc[3];
318 uint32_t scgc[3];
319 uint32_t dcgc[3];
320 uint32_t clkvclr;
321 uint32_t ldoarst;
322 qemu_irq irq;
323 stellaris_board_info *board;
324} ssys_state;
325
326static void ssys_update(ssys_state *s)
327{
328 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
329}
330
331static uint32_t pllcfg_sandstorm[16] = {
332 0x31c0, /* 1 Mhz */
333 0x1ae0, /* 1.8432 Mhz */
334 0x18c0, /* 2 Mhz */
335 0xd573, /* 2.4576 Mhz */
336 0x37a6, /* 3.57954 Mhz */
337 0x1ae2, /* 3.6864 Mhz */
338 0x0c40, /* 4 Mhz */
339 0x98bc, /* 4.906 Mhz */
340 0x935b, /* 4.9152 Mhz */
341 0x09c0, /* 5 Mhz */
342 0x4dee, /* 5.12 Mhz */
343 0x0c41, /* 6 Mhz */
344 0x75db, /* 6.144 Mhz */
345 0x1ae6, /* 7.3728 Mhz */
346 0x0600, /* 8 Mhz */
347 0x585b /* 8.192 Mhz */
348};
349
350static uint32_t pllcfg_fury[16] = {
351 0x3200, /* 1 Mhz */
352 0x1b20, /* 1.8432 Mhz */
353 0x1900, /* 2 Mhz */
354 0xf42b, /* 2.4576 Mhz */
355 0x37e3, /* 3.57954 Mhz */
356 0x1b21, /* 3.6864 Mhz */
357 0x0c80, /* 4 Mhz */
358 0x98ee, /* 4.906 Mhz */
359 0xd5b4, /* 4.9152 Mhz */
360 0x0a00, /* 5 Mhz */
361 0x4e27, /* 5.12 Mhz */
362 0x1902, /* 6 Mhz */
363 0xec1c, /* 6.144 Mhz */
364 0x1b23, /* 7.3728 Mhz */
365 0x0640, /* 8 Mhz */
366 0xb11c /* 8.192 Mhz */
367};
368
369static uint32_t ssys_read(void *opaque, target_phys_addr_t offset)
370{
371 ssys_state *s = (ssys_state *)opaque;
372
373 offset -= s->base;
374 switch (offset) {
375 case 0x000: /* DID0 */
376 return s->board->did0;
377 case 0x004: /* DID1 */
378 return s->board->did1;
379 case 0x008: /* DC0 */
380 return s->board->dc0;
381 case 0x010: /* DC1 */
382 return s->board->dc1;
383 case 0x014: /* DC2 */
384 return s->board->dc2;
385 case 0x018: /* DC3 */
386 return s->board->dc3;
387 case 0x01c: /* DC4 */
388 return s->board->dc4;
389 case 0x030: /* PBORCTL */
390 return s->pborctl;
391 case 0x034: /* LDOPCTL */
392 return s->ldopctl;
393 case 0x040: /* SRCR0 */
394 return 0;
395 case 0x044: /* SRCR1 */
396 return 0;
397 case 0x048: /* SRCR2 */
398 return 0;
399 case 0x050: /* RIS */
400 return s->int_status;
401 case 0x054: /* IMC */
402 return s->int_mask;
403 case 0x058: /* MISC */
404 return s->int_status & s->int_mask;
405 case 0x05c: /* RESC */
406 return s->resc;
407 case 0x060: /* RCC */
408 return s->rcc;
409 case 0x064: /* PLLCFG */
410 {
411 int xtal;
412 xtal = (s->rcc >> 6) & 0xf;
413 if (s->board->did0 & (1 << 16)) {
414 return pllcfg_fury[xtal];
415 } else {
416 return pllcfg_sandstorm[xtal];
417 }
418 }
419 case 0x100: /* RCGC0 */
420 return s->rcgc[0];
421 case 0x104: /* RCGC1 */
422 return s->rcgc[1];
423 case 0x108: /* RCGC2 */
424 return s->rcgc[2];
425 case 0x110: /* SCGC0 */
426 return s->scgc[0];
427 case 0x114: /* SCGC1 */
428 return s->scgc[1];
429 case 0x118: /* SCGC2 */
430 return s->scgc[2];
431 case 0x120: /* DCGC0 */
432 return s->dcgc[0];
433 case 0x124: /* DCGC1 */
434 return s->dcgc[1];
435 case 0x128: /* DCGC2 */
436 return s->dcgc[2];
437 case 0x150: /* CLKVCLR */
438 return s->clkvclr;
439 case 0x160: /* LDOARST */
440 return s->ldoarst;
441 default:
79b02417 442 cpu_abort(cpu_single_env, "ssys_read: Bad offset 0x%x\n", (int)offset);
9ee6e8bb
PB		 443 return 0;
444 }
445}
446
447static void ssys_write(void *opaque, target_phys_addr_t offset, uint32_t value)
448{
449 ssys_state *s = (ssys_state *)opaque;
450
451 offset -= s->base;
452 switch (offset) {
453 case 0x030: /* PBORCTL */
454 s->pborctl = value & 0xffff;
455 break;
456 case 0x034: /* LDOPCTL */
457 s->ldopctl = value & 0x1f;
458 break;
459 case 0x040: /* SRCR0 */
460 case 0x044: /* SRCR1 */
461 case 0x048: /* SRCR2 */
462 fprintf(stderr, "Peripheral reset not implemented\n");
463 break;
464 case 0x054: /* IMC */
465 s->int_mask = value & 0x7f;
466 break;
467 case 0x058: /* MISC */
468 s->int_status &= ~value;
469 break;
470 case 0x05c: /* RESC */
471 s->resc = value & 0x3f;
472 break;
473 case 0x060: /* RCC */
474 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
475 /* PLL enable. */
476 s->int_status |= (1 << 6);
477 }
478 s->rcc = value;
e57ec016 479 system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
9ee6e8bb
PB		 480 break;
481 case 0x100: /* RCGC0 */
482 s->rcgc[0] = value;
483 break;
484 case 0x104: /* RCGC1 */
485 s->rcgc[1] = value;
486 break;
487 case 0x108: /* RCGC2 */
488 s->rcgc[2] = value;
489 break;
490 case 0x110: /* SCGC0 */
491 s->scgc[0] = value;
492 break;
493 case 0x114: /* SCGC1 */
494 s->scgc[1] = value;
495 break;
496 case 0x118: /* SCGC2 */
497 s->scgc[2] = value;
498 break;
499 case 0x120: /* DCGC0 */
500 s->dcgc[0] = value;
501 break;
502 case 0x124: /* DCGC1 */
503 s->dcgc[1] = value;
504 break;
505 case 0x128: /* DCGC2 */
506 s->dcgc[2] = value;
507 break;
508 case 0x150: /* CLKVCLR */
509 s->clkvclr = value;
510 break;
511 case 0x160: /* LDOARST */
512 s->ldoarst = value;
513 break;
514 default:
79b02417 515 cpu_abort(cpu_single_env, "ssys_write: Bad offset 0x%x\n", (int)offset);
9ee6e8bb
PB		 516 }
517 ssys_update(s);
518}
519
520static CPUReadMemoryFunc *ssys_readfn[] = {
521 ssys_read,
522 ssys_read,
523 ssys_read
524};
525
526static CPUWriteMemoryFunc *ssys_writefn[] = {
527 ssys_write,
528 ssys_write,
529 ssys_write
530};
531
9596ebb7 532static void ssys_reset(void *opaque)
9ee6e8bb
PB		 533{
534 ssys_state *s = (ssys_state *)opaque;
535
536 s->pborctl = 0x7ffd;
537 s->rcc = 0x078e3ac0;
538 s->rcgc[0] = 1;
539 s->scgc[0] = 1;
540 s->dcgc[0] = 1;
541}
542
543static void stellaris_sys_init(uint32_t base, qemu_irq irq,
544 stellaris_board_info * board)
545{
546 int iomemtype;
547 ssys_state *s;
548
549 s = (ssys_state *)qemu_mallocz(sizeof(ssys_state));
550 s->base = base;
551 s->irq = irq;
552 s->board = board;
553
554 iomemtype = cpu_register_io_memory(0, ssys_readfn,
555 ssys_writefn, s);
556 cpu_register_physical_memory(base, 0x00001000, iomemtype);
557 ssys_reset(s);
558 /* ??? Save/restore. */
559}
560
561
562/* I2C controller. */
563
564typedef struct {
565 i2c_bus *bus;
566 qemu_irq irq;
567 uint32_t base;
568 uint32_t msa;
569 uint32_t mcs;
570 uint32_t mdr;
571 uint32_t mtpr;
572 uint32_t mimr;
573 uint32_t mris;
574 uint32_t mcr;
575} stellaris_i2c_state;
576
577#define STELLARIS_I2C_MCS_BUSY 0x01
578#define STELLARIS_I2C_MCS_ERROR 0x02
579#define STELLARIS_I2C_MCS_ADRACK 0x04
580#define STELLARIS_I2C_MCS_DATACK 0x08
581#define STELLARIS_I2C_MCS_ARBLST 0x10
582#define STELLARIS_I2C_MCS_IDLE 0x20
583#define STELLARIS_I2C_MCS_BUSBSY 0x40
584
585static uint32_t stellaris_i2c_read(void *opaque, target_phys_addr_t offset)
586{
587 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
588
589 offset -= s->base;
590 switch (offset) {
591 case 0x00: /* MSA */
592 return s->msa;
593 case 0x04: /* MCS */
594 /* We don't emulate timing, so the controller is never busy. */
595 return s->mcs | STELLARIS_I2C_MCS_IDLE;
596 case 0x08: /* MDR */
597 return s->mdr;
598 case 0x0c: /* MTPR */
599 return s->mtpr;
600 case 0x10: /* MIMR */
601 return s->mimr;
602 case 0x14: /* MRIS */
603 return s->mris;
604 case 0x18: /* MMIS */
605 return s->mris & s->mimr;
606 case 0x20: /* MCR */
607 return s->mcr;
608 default:
609 cpu_abort(cpu_single_env, "strllaris_i2c_read: Bad offset 0x%x\n",
610 (int)offset);
611 return 0;
612 }
613}
614
615static void stellaris_i2c_update(stellaris_i2c_state *s)
616{
617 int level;
618
619 level = (s->mris & s->mimr) != 0;
620 qemu_set_irq(s->irq, level);
621}
622
623static void stellaris_i2c_write(void *opaque, target_phys_addr_t offset,
624 uint32_t value)
625{
626 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
627
628 offset -= s->base;
629 switch (offset) {
630 case 0x00: /* MSA */
631 s->msa = value & 0xff;
632 break;
633 case 0x04: /* MCS */
634 if ((s->mcr & 0x10) == 0) {
635 /* Disabled. Do nothing. */
636 break;
637 }
638 /* Grab the bus if this is starting a transfer. */
639 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
640 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
641 s->mcs |= STELLARIS_I2C_MCS_ARBLST;
642 } else {
643 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
644 s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
645 }
646 }
647 /* If we don't have the bus then indicate an error. */
648 if (!i2c_bus_busy(s->bus)
649 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
650 s->mcs |= STELLARIS_I2C_MCS_ERROR;
651 break;
652 }
653 s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
654 if (value & 1) {
655 /* Transfer a byte. */
656 /* TODO: Handle errors. */
657 if (s->msa & 1) {
658 /* Recv */
659 s->mdr = i2c_recv(s->bus) & 0xff;
660 } else {
661 /* Send */
662 i2c_send(s->bus, s->mdr);
663 }
664 /* Raise an interrupt. */
665 s->mris |= 1;
666 }
667 if (value & 4) {
668 /* Finish transfer. */
669 i2c_end_transfer(s->bus);
670 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
671 }
672 break;
673 case 0x08: /* MDR */
674 s->mdr = value & 0xff;
675 break;
676 case 0x0c: /* MTPR */
677 s->mtpr = value & 0xff;
678 break;
679 case 0x10: /* MIMR */
680 s->mimr = 1;
681 break;
682 case 0x1c: /* MICR */
683 s->mris &= ~value;
684 break;
685 case 0x20: /* MCR */
686 if (value & 1)
687 cpu_abort(cpu_single_env,
688 "stellaris_i2c_write: Loopback not implemented\n");
689 if (value & 0x20)
690 cpu_abort(cpu_single_env,
691 "stellaris_i2c_write: Slave mode not implemented\n");
692 s->mcr = value & 0x31;
693 break;
694 default:
695 cpu_abort(cpu_single_env, "stellaris_i2c_write: Bad offset 0x%x\n",
696 (int)offset);
697 }
698 stellaris_i2c_update(s);
699}
700
701static void stellaris_i2c_reset(stellaris_i2c_state *s)
702{
703 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
704 i2c_end_transfer(s->bus);
705
706 s->msa = 0;
707 s->mcs = 0;
708 s->mdr = 0;
709 s->mtpr = 1;
710 s->mimr = 0;
711 s->mris = 0;
712 s->mcr = 0;
713 stellaris_i2c_update(s);
714}
715
716static CPUReadMemoryFunc *stellaris_i2c_readfn[] = {
717 stellaris_i2c_read,
718 stellaris_i2c_read,
719 stellaris_i2c_read
720};
721
722static CPUWriteMemoryFunc *stellaris_i2c_writefn[] = {
723 stellaris_i2c_write,
724 stellaris_i2c_write,
725 stellaris_i2c_write
726};
727
728static void stellaris_i2c_init(uint32_t base, qemu_irq irq, i2c_bus *bus)
729{
730 stellaris_i2c_state *s;
731 int iomemtype;
732
733 s = (stellaris_i2c_state *)qemu_mallocz(sizeof(stellaris_i2c_state));
734 s->base = base;
735 s->irq = irq;
736 s->bus = bus;
737
738 iomemtype = cpu_register_io_memory(0, stellaris_i2c_readfn,
739 stellaris_i2c_writefn, s);
740 cpu_register_physical_memory(base, 0x00001000, iomemtype);
741 /* ??? For now we only implement the master interface. */
742 stellaris_i2c_reset(s);
743}
744
745/* Analogue to Digital Converter. This is only partially implemented,
746 enough for applications that use a combined ADC and timer tick. */
747
748#define STELLARIS_ADC_EM_CONTROLLER 0
749#define STELLARIS_ADC_EM_COMP 1
750#define STELLARIS_ADC_EM_EXTERNAL 4
751#define STELLARIS_ADC_EM_TIMER 5
752#define STELLARIS_ADC_EM_PWM0 6
753#define STELLARIS_ADC_EM_PWM1 7
754#define STELLARIS_ADC_EM_PWM2 8
755
756#define STELLARIS_ADC_FIFO_EMPTY 0x0100
757#define STELLARIS_ADC_FIFO_FULL 0x1000
758
759typedef struct
760{
761 uint32_t base;
762 uint32_t actss;
763 uint32_t ris;
764 uint32_t im;
765 uint32_t emux;
766 uint32_t ostat;
767 uint32_t ustat;
768 uint32_t sspri;
769 uint32_t sac;
770 struct {
771 uint32_t state;
772 uint32_t data[16];
773 } fifo[4];
774 uint32_t ssmux[4];
775 uint32_t ssctl[4];
776 qemu_irq irq;
777} stellaris_adc_state;
778
779static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
780{
781 int tail;
782
783 tail = s->fifo[n].state & 0xf;
784 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
785 s->ustat |= 1 << n;
786 } else {
787 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
788 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
789 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
790 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
791 }
792 return s->fifo[n].data[tail];
793}
794
795static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
796 uint32_t value)
797{
798 int head;
799
800 head = (s->fifo[n].state >> 4) & 0xf;
801 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
802 s->ostat |= 1 << n;
803 return;
804 }
805 s->fifo[n].data[head] = value;
806 head = (head + 1) & 0xf;
807 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
808 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
809 if ((s->fifo[n].state & 0xf) == head)
810 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
811}
812
813static void stellaris_adc_update(stellaris_adc_state *s)
814{
815 int level;
816
817 level = (s->ris & s->im) != 0;
818 qemu_set_irq(s->irq, level);
819}
820
821static void stellaris_adc_trigger(void *opaque, int irq, int level)
822{
823 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
824 /* Some applications use the ADC as a random number source, so introduce
825 some variation into the signal. */
826 static uint32_t noise = 0;
827
828 if ((s->actss & 1) == 0) {
829 return;
830 }
831
832 noise = noise * 314159 + 1;
833 /* ??? actual inputs not implemented. Return an arbitrary value. */
834 stellaris_adc_fifo_write(s, 0, 0x200 + ((noise >> 16) & 7));
835 s->ris |= 1;
836 stellaris_adc_update(s);
837}
838
839static void stellaris_adc_reset(stellaris_adc_state *s)
840{
841 int n;
842
843 for (n = 0; n < 4; n++) {
844 s->ssmux[n] = 0;
845 s->ssctl[n] = 0;
846 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
847 }
848}
849
850static uint32_t stellaris_adc_read(void *opaque, target_phys_addr_t offset)
851{
852 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
853
854 /* TODO: Implement this. */
855 offset -= s->base;
856 if (offset >= 0x40 && offset < 0xc0) {
857 int n;
858 n = (offset - 0x40) >> 5;
859 switch (offset & 0x1f) {
860 case 0x00: /* SSMUX */
861 return s->ssmux[n];
862 case 0x04: /* SSCTL */
863 return s->ssctl[n];
864 case 0x08: /* SSFIFO */
865 return stellaris_adc_fifo_read(s, n);
866 case 0x0c: /* SSFSTAT */
867 return s->fifo[n].state;
868 default:
869 break;
870 }
871 }
872 switch (offset) {
873 case 0x00: /* ACTSS */
874 return s->actss;
875 case 0x04: /* RIS */
876 return s->ris;
877 case 0x08: /* IM */
878 return s->im;
879 case 0x0c: /* ISC */
880 return s->ris & s->im;
881 case 0x10: /* OSTAT */
882 return s->ostat;
883 case 0x14: /* EMUX */
884 return s->emux;
885 case 0x18: /* USTAT */
886 return s->ustat;
887 case 0x20: /* SSPRI */
888 return s->sspri;
889 case 0x30: /* SAC */
890 return s->sac;
891 default:
892 cpu_abort(cpu_single_env, "strllaris_adc_read: Bad offset 0x%x\n",
893 (int)offset);
894 return 0;
895 }
896}
897
898static void stellaris_adc_write(void *opaque, target_phys_addr_t offset,
899 uint32_t value)
900{
901 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
902
903 /* TODO: Implement this. */
904 offset -= s->base;
905 if (offset >= 0x40 && offset < 0xc0) {
906 int n;
907 n = (offset - 0x40) >> 5;
908 switch (offset & 0x1f) {
909 case 0x00: /* SSMUX */
910 s->ssmux[n] = value & 0x33333333;
911 return;
912 case 0x04: /* SSCTL */
913 if (value != 6) {
914 cpu_abort(cpu_single_env, "ADC: Unimplemented sequence %x\n",
915 value);
916 }
917 s->ssctl[n] = value;
918 return;
919 default:
920 break;
921 }
922 }
923 switch (offset) {
924 case 0x00: /* ACTSS */
925 s->actss = value & 0xf;
926 if (value & 0xe) {
927 cpu_abort(cpu_single_env,
928 "Not implemented: ADC sequencers 1-3\n");
929 }
930 break;
931 case 0x08: /* IM */
932 s->im = value;
933 break;
934 case 0x0c: /* ISC */
935 s->ris &= ~value;
936 break;
937 case 0x10: /* OSTAT */
938 s->ostat &= ~value;
939 break;
940 case 0x14: /* EMUX */
941 s->emux = value;
942 break;
943 case 0x18: /* USTAT */
944 s->ustat &= ~value;
945 break;
946 case 0x20: /* SSPRI */
947 s->sspri = value;
948 break;
949 case 0x28: /* PSSI */
950 cpu_abort(cpu_single_env, "Not implemented: ADC sample initiate\n");
951 break;
952 case 0x30: /* SAC */
953 s->sac = value;
954 break;
955 default:
956 cpu_abort(cpu_single_env, "stellaris_adc_write: Bad offset 0x%x\n",
957 (int)offset);
958 }
959 stellaris_adc_update(s);
960}
961
962static CPUReadMemoryFunc *stellaris_adc_readfn[] = {
963 stellaris_adc_read,
964 stellaris_adc_read,
965 stellaris_adc_read
966};
967
968static CPUWriteMemoryFunc *stellaris_adc_writefn[] = {
969 stellaris_adc_write,
970 stellaris_adc_write,
971 stellaris_adc_write
972};
973
974static qemu_irq stellaris_adc_init(uint32_t base, qemu_irq irq)
975{
976 stellaris_adc_state *s;
977 int iomemtype;
978 qemu_irq *qi;
979
980 s = (stellaris_adc_state *)qemu_mallocz(sizeof(stellaris_adc_state));
981 s->base = base;
982 s->irq = irq;
983
984 iomemtype = cpu_register_io_memory(0, stellaris_adc_readfn,
985 stellaris_adc_writefn, s);
986 cpu_register_physical_memory(base, 0x00001000, iomemtype);
987 stellaris_adc_reset(s);
988 qi = qemu_allocate_irqs(stellaris_adc_trigger, s, 1);
989 return qi[0];
990}
991
992/* Board init. */
993static stellaris_board_info stellaris_boards[] = {
994 { "LM3S811EVB",
995 0,
996 0x0032000e,
997 0x001f001f, /* dc0 */
998 0x001132bf,
999 0x01071013,
1000 0x3f0f01ff,
1001 0x0000001f,
cf0dbb21 1002 BP_OLED_I2C
9ee6e8bb
PB		 1003 },
1004 { "LM3S6965EVB",
1005 0x10010002,
1006 0x1073402e,
1007 0x00ff007f, /* dc0 */
1008 0x001133ff,
1009 0x030f5317,
1010 0x0f0f87ff,
1011 0x5000007f,
cf0dbb21 1012 BP_OLED_SSI | BP_GAMEPAD
9ee6e8bb
PB		 1013 }
1014};
1015
1016static void stellaris_init(const char *kernel_filename, const char *cpu_model,
1017 DisplayState *ds, stellaris_board_info *board)
1018{
1019 static const int uart_irq[] = {5, 6, 33, 34};
1020 static const int timer_irq[] = {19, 21, 23, 35};
1021 static const uint32_t gpio_addr[7] =
1022 { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1023 0x40024000, 0x40025000, 0x40026000};
1024 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
1025
1026 qemu_irq *pic;
1027 qemu_irq *gpio_in[5];
1028 qemu_irq *gpio_out[5];
1029 qemu_irq adc;
1030 int sram_size;
1031 int flash_size;
1032 i2c_bus *i2c;
1033 int i;
1034
1035 flash_size = ((board->dc0 & 0xffff) + 1) << 1;
1036 sram_size = (board->dc0 >> 18) + 1;
1037 pic = armv7m_init(flash_size, sram_size, kernel_filename, cpu_model);
1038
1039 if (board->dc1 & (1 << 16)) {
1040 adc = stellaris_adc_init(0x40038000, pic[14]);
1041 } else {
1042 adc = NULL;
1043 }
1044 for (i = 0; i < 4; i++) {
1045 if (board->dc2 & (0x10000 << i)) {
1046 stellaris_gptm_init(0x40030000 + i * 0x1000,
1047 pic[timer_irq[i]], adc);
1048 }
1049 }
1050
1051 stellaris_sys_init(0x400fe000, pic[28], board);
1052
1053 for (i = 0; i < 7; i++) {
1054 if (board->dc4 & (1 << i)) {
1055 gpio_in[i] = pl061_init(gpio_addr[i], pic[gpio_irq[i]],
1056 &gpio_out[i]);
1057 }
1058 }
1059
1060 if (board->dc2 & (1 << 12)) {
1061 i2c = i2c_init_bus();
1062 stellaris_i2c_init(0x40020000, pic[8], i2c);
cf0dbb21 1063 if (board->peripherals & BP_OLED_I2C) {
9ee6e8bb
PB		 1064 ssd0303_init(ds, i2c, 0x3d);
1065 }
1066 }
1067
1068 for (i = 0; i < 4; i++) {
1069 if (board->dc2 & (1 << i)) {
1070 pl011_init(0x4000c000 + i * 0x1000, pic[uart_irq[i]],
1071 serial_hds[i], PL011_LUMINARY);
1072 }
1073 }
1074 if (board->dc2 & (1 << 4)) {
cf0dbb21 1075 if (board->peripherals & BP_OLED_SSI) {
9ee6e8bb
PB		 1076 void * oled;
1077 /* FIXME: Implement chip select for OLED/MMC. */
cf0dbb21 1078 oled = ssd0323_init(ds, &gpio_out[GPIO_C][7]);
9ee6e8bb
PB		 1079 pl022_init(0x40008000, pic[7], ssd0323_xfer_ssi, oled);
1080 } else {
1081 pl022_init(0x40008000, pic[7], NULL, NULL);
1082 }
1083 }
cf0dbb21
PB		 1084 if (board->peripherals & BP_GAMEPAD) {
1085 qemu_irq gpad_irq[5];
1086 static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1087
1088 gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */
1089 gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */
1090 gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */
1091 gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */
1092 gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */
1093
1094 stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
1095 }
9ee6e8bb
PB		 1096}
1097
1098/* FIXME: Figure out how to generate these from stellaris_boards. */
1099static void lm3s811evb_init(int ram_size, int vga_ram_size,
1100 const char *boot_device, DisplayState *ds,
9ee6e8bb
PB		 1101 const char *kernel_filename, const char *kernel_cmdline,
1102 const char *initrd_filename, const char *cpu_model)
1103{
1104 stellaris_init(kernel_filename, cpu_model, ds, &stellaris_boards[0]);
1105}
1106
1107static void lm3s6965evb_init(int ram_size, int vga_ram_size,
1108 const char *boot_device, DisplayState *ds,
9ee6e8bb
PB		 1109 const char *kernel_filename, const char *kernel_cmdline,
1110 const char *initrd_filename, const char *cpu_model)
1111{
1112 stellaris_init(kernel_filename, cpu_model, ds, &stellaris_boards[1]);
1113}
1114
1115QEMUMachine lm3s811evb_machine = {
1116 "lm3s811evb",
1117 "Stellaris LM3S811EVB",
1118 lm3s811evb_init,
1119};
1120
1121QEMUMachine lm3s6965evb_machine = {
1122 "lm3s6965evb",
1123 "Stellaris LM3S6965EVB",
1124 lm3s6965evb_init,
1125};
Empty description
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