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tcg/arm: explicitely list clobbered/reserved regs
[qemu.git] / tcg / arm / tcg-target.c
CommitLineData
811d4cf4
AZ		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Andrzej Zaborowski
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
d4a9eb1f
BS		 24
25#ifndef NDEBUG
26static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
811d4cf4
AZ		 27 "%r0",
28 "%r1",
29 "%r2",
30 "%r3",
31 "%r4",
32 "%r5",
33 "%r6",
34 "%r7",
35 "%r8",
36 "%r9",
37 "%r10",
38 "%r11",
39 "%r12",
40 "%r13",
41 "%r14",
e4a7d5e8 42 "%pc",
811d4cf4 43};
d4a9eb1f 44#endif
811d4cf4 45
d4a9eb1f 46static const int tcg_target_reg_alloc_order[] = {
811d4cf4
AZ		 47 TCG_REG_R0,
48 TCG_REG_R1,
49 TCG_REG_R2,
50 TCG_REG_R3,
51 TCG_REG_R4,
52 TCG_REG_R5,
53 TCG_REG_R6,
54 TCG_REG_R7,
55 TCG_REG_R8,
56 TCG_REG_R9,
57 TCG_REG_R10,
58 TCG_REG_R11,
59 TCG_REG_R12,
60 TCG_REG_R13,
61 TCG_REG_R14,
62};
63
d4a9eb1f 64static const int tcg_target_call_iarg_regs[4] = {
811d4cf4
AZ		 65 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
66};
d4a9eb1f 67static const int tcg_target_call_oarg_regs[2] = {
811d4cf4
AZ		 68 TCG_REG_R0, TCG_REG_R1
69};
70
650bbb36 71static void patch_reloc(uint8_t *code_ptr, int type,
811d4cf4
AZ		 72 tcg_target_long value, tcg_target_long addend)
73{
74 switch (type) {
75 case R_ARM_ABS32:
76 *(uint32_t *) code_ptr = value;
77 break;
78
79 case R_ARM_CALL:
80 case R_ARM_JUMP24:
81 default:
82 tcg_abort();
83
84 case R_ARM_PC24:
eae6ce52 85 *(uint32_t *) code_ptr = ((*(uint32_t *) code_ptr) & 0xff000000) |
e936243a 86 (((value - ((tcg_target_long) code_ptr + 8)) >> 2) & 0xffffff);
811d4cf4
AZ		 87 break;
88 }
89}
90
91/* maximum number of register used for input function arguments */
92static inline int tcg_target_get_call_iarg_regs_count(int flags)
93{
94 return 4;
95}
96
811d4cf4 97/* parse target specific constraints */
d4a9eb1f 98static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
811d4cf4
AZ		 99{
100 const char *ct_str;
101
102 ct_str = *pct_str;
103 switch (ct_str[0]) {
cb4e581f
LD		 104 case 'I':
105 ct->ct |= TCG_CT_CONST_ARM;
106 break;
107
811d4cf4
AZ		 108 case 'r':
109#ifndef CONFIG_SOFTMMU
110 case 'd':
111 case 'D':
112 case 'x':
113 case 'X':
114#endif
115 ct->ct |= TCG_CT_REG;
116 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
117 break;
118
119#ifdef CONFIG_SOFTMMU
d0660ed4 120 /* qemu_ld/st inputs (unless 'X', 'd' or 'D') */
811d4cf4
AZ		 121 case 'x':
122 ct->ct |= TCG_CT_REG;
123 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
811d4cf4
AZ		 124 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
125 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
811d4cf4
AZ		 126 break;
127
d0660ed4
AZ		 128 /* qemu_ld64 data_reg */
129 case 'd':
130 ct->ct |= TCG_CT_REG;
131 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
132 /* r1 is still needed to load data_reg2, so don't use it. */
133 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
134 break;
135
811d4cf4
AZ		 136 /* qemu_ld/st64 data_reg2 */
137 case 'D':
138 ct->ct |= TCG_CT_REG;
139 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
140 /* r0, r1 and optionally r2 will be overwritten by the address
141 * and the low word of data, so don't use these. */
142 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
143 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
144# if TARGET_LONG_BITS == 64
145 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
146# endif
147 break;
148
149# if TARGET_LONG_BITS == 64
150 /* qemu_ld/st addr_reg2 */
151 case 'X':
152 ct->ct |= TCG_CT_REG;
153 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
154 /* r0 will be overwritten by the low word of base, so don't use it. */
155 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
811d4cf4 156 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
811d4cf4
AZ		 157 break;
158# endif
159#endif
160
811d4cf4
AZ		 161 default:
162 return -1;
163 }
164 ct_str++;
165 *pct_str = ct_str;
166
167 return 0;
168}
169
94953e6d
LD		 170static inline uint32_t rotl(uint32_t val, int n)
171{
172 return (val << n) | (val >> (32 - n));
173}
174
175/* ARM immediates for ALU instructions are made of an unsigned 8-bit
176 right-rotated by an even amount between 0 and 30. */
177static inline int encode_imm(uint32_t imm)
178{
4e6f6d4c
LD		 179 int shift;
180
94953e6d
LD		 181 /* simple case, only lower bits */
182 if ((imm & ~0xff) == 0)
183 return 0;
184 /* then try a simple even shift */
185 shift = ctz32(imm) & ~1;
186 if (((imm >> shift) & ~0xff) == 0)
187 return 32 - shift;
188 /* now try harder with rotations */
189 if ((rotl(imm, 2) & ~0xff) == 0)
190 return 2;
191 if ((rotl(imm, 4) & ~0xff) == 0)
192 return 4;
193 if ((rotl(imm, 6) & ~0xff) == 0)
194 return 6;
195 /* imm can't be encoded */
196 return -1;
197}
cb4e581f
LD		 198
199static inline int check_fit_imm(uint32_t imm)
200{
94953e6d 201 return encode_imm(imm) >= 0;
cb4e581f
LD		 202}
203
811d4cf4
AZ		 204/* Test if a constant matches the constraint.
205 * TODO: define constraints for:
206 *
207 * ldr/str offset: between -0xfff and 0xfff
208 * ldrh/strh offset: between -0xff and 0xff
209 * mov operand2: values represented with x << (2 * y), x < 0x100
210 * add, sub, eor...: ditto
211 */
212static inline int tcg_target_const_match(tcg_target_long val,
213 const TCGArgConstraint *arg_ct)
214{
215 int ct;
216 ct = arg_ct->ct;
217 if (ct & TCG_CT_CONST)
218 return 1;
cb4e581f
LD		 219 else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val))
220 return 1;
811d4cf4
AZ		 221 else
222 return 0;
223}
224
225enum arm_data_opc_e {
226 ARITH_AND = 0x0,
227 ARITH_EOR = 0x1,
228 ARITH_SUB = 0x2,
229 ARITH_RSB = 0x3,
230 ARITH_ADD = 0x4,
231 ARITH_ADC = 0x5,
232 ARITH_SBC = 0x6,
233 ARITH_RSC = 0x7,
3979144c 234 ARITH_TST = 0x8,
811d4cf4
AZ		 235 ARITH_CMP = 0xa,
236 ARITH_CMN = 0xb,
237 ARITH_ORR = 0xc,
238 ARITH_MOV = 0xd,
239 ARITH_BIC = 0xe,
240 ARITH_MVN = 0xf,
241};
242
3979144c
PB		 243#define TO_CPSR(opc) \
244 ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
811d4cf4
AZ		 245
246#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
247#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
248#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
249#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
250#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
251#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
252#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
253#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
254
255enum arm_cond_code_e {
256 COND_EQ = 0x0,
257 COND_NE = 0x1,
258 COND_CS = 0x2, /* Unsigned greater or equal */
259 COND_CC = 0x3, /* Unsigned less than */
260 COND_MI = 0x4, /* Negative */
261 COND_PL = 0x5, /* Zero or greater */
262 COND_VS = 0x6, /* Overflow */
263 COND_VC = 0x7, /* No overflow */
264 COND_HI = 0x8, /* Unsigned greater than */
265 COND_LS = 0x9, /* Unsigned less or equal */
266 COND_GE = 0xa,
267 COND_LT = 0xb,
268 COND_GT = 0xc,
269 COND_LE = 0xd,
270 COND_AL = 0xe,
271};
272
273static const uint8_t tcg_cond_to_arm_cond[10] = {
274 [TCG_COND_EQ] = COND_EQ,
275 [TCG_COND_NE] = COND_NE,
276 [TCG_COND_LT] = COND_LT,
277 [TCG_COND_GE] = COND_GE,
278 [TCG_COND_LE] = COND_LE,
279 [TCG_COND_GT] = COND_GT,
280 /* unsigned */
281 [TCG_COND_LTU] = COND_CC,
282 [TCG_COND_GEU] = COND_CS,
283 [TCG_COND_LEU] = COND_LS,
284 [TCG_COND_GTU] = COND_HI,
285};
286
287static inline void tcg_out_bx(TCGContext *s, int cond, int rn)
288{
289 tcg_out32(s, (cond << 28) | 0x012fff10 | rn);
290}
291
292static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
293{
294 tcg_out32(s, (cond << 28) | 0x0a000000 |
295 (((offset - 8) >> 2) & 0x00ffffff));
296}
297
e936243a
AZ		 298static inline void tcg_out_b_noaddr(TCGContext *s, int cond)
299{
e2542fe2 300#ifdef HOST_WORDS_BIGENDIAN
e936243a
AZ		 301 tcg_out8(s, (cond << 4) | 0x0a);
302 s->code_ptr += 3;
303#else
304 s->code_ptr += 3;
305 tcg_out8(s, (cond << 4) | 0x0a);
306#endif
307}
308
811d4cf4
AZ		 309static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset)
310{
311 tcg_out32(s, (cond << 28) | 0x0b000000 |
312 (((offset - 8) >> 2) & 0x00ffffff));
313}
314
315static inline void tcg_out_dat_reg(TCGContext *s,
316 int cond, int opc, int rd, int rn, int rm, int shift)
317{
318 tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) |
319 (rn << 16) | (rd << 12) | shift | rm);
320}
321
322static inline void tcg_out_dat_reg2(TCGContext *s,
323 int cond, int opc0, int opc1, int rd0, int rd1,
324 int rn0, int rn1, int rm0, int rm1, int shift)
325{
0c9c3a9e
AZ		 326 if (rd0 == rn1 || rd0 == rm1) {
327 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
328 (rn0 << 16) | (8 << 12) | shift | rm0);
329 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
330 (rn1 << 16) | (rd1 << 12) | shift | rm1);
331 tcg_out_dat_reg(s, cond, ARITH_MOV,
332 rd0, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
333 } else {
334 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
335 (rn0 << 16) | (rd0 << 12) | shift | rm0);
336 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
337 (rn1 << 16) | (rd1 << 12) | shift | rm1);
338 }
811d4cf4
AZ		 339}
340
341static inline void tcg_out_dat_imm(TCGContext *s,
342 int cond, int opc, int rd, int rn, int im)
343{
3979144c 344 tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) | TO_CPSR(opc) |
811d4cf4
AZ		 345 (rn << 16) | (rd << 12) | im);
346}
347
348static inline void tcg_out_movi32(TCGContext *s,
349 int cond, int rd, int32_t arg)
350{
351 int offset = (uint32_t) arg - ((uint32_t) s->code_ptr + 8);
352
353 /* TODO: This is very suboptimal, we can easily have a constant
354 * pool somewhere after all the instructions. */
355
356 if (arg < 0 && arg > -0x100)
357 return tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, (~arg) & 0xff);
358
359 if (offset < 0x100 && offset > -0x100)
360 return offset >= 0 ?
361 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, 15, offset) :
362 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, 15, -offset);
363
cb4e581f
LD		 364#ifdef __ARM_ARCH_7A__
365 /* use movw/movt */
366 /* movw */
367 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12)
368 | ((arg << 4) & 0x000f0000) | (arg & 0xfff));
369 if (arg & 0xffff0000)
370 /* movt */
371 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12)
372 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff));
373#else
811d4cf4
AZ		 374 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, arg & 0xff);
375 if (arg & 0x0000ff00)
376 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
377 ((arg >> 8) & 0xff) | 0xc00);
378 if (arg & 0x00ff0000)
379 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
380 ((arg >> 16) & 0xff) | 0x800);
381 if (arg & 0xff000000)
382 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
383 ((arg >> 24) & 0xff) | 0x400);
cb4e581f 384#endif
811d4cf4
AZ		 385}
386
387static inline void tcg_out_mul32(TCGContext *s,
388 int cond, int rd, int rs, int rm)
389{
390 if (rd != rm)
391 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
392 (rs << 8) | 0x90 | rm);
393 else if (rd != rs)
394 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
395 (rm << 8) | 0x90 | rs);
396 else {
397 tcg_out32(s, (cond << 28) | ( 8 << 16) | (0 << 12) |
398 (rs << 8) | 0x90 | rm);
399 tcg_out_dat_reg(s, cond, ARITH_MOV,
400 rd, 0, 8, SHIFT_IMM_LSL(0));
401 }
402}
403
404static inline void tcg_out_umull32(TCGContext *s,
405 int cond, int rd0, int rd1, int rs, int rm)
406{
407 if (rd0 != rm && rd1 != rm)
408 tcg_out32(s, (cond << 28) | 0x800090 |
409 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
410 else if (rd0 != rs && rd1 != rs)
411 tcg_out32(s, (cond << 28) | 0x800090 |
412 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
413 else {
414 tcg_out_dat_reg(s, cond, ARITH_MOV,
415 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
416 tcg_out32(s, (cond << 28) | 0x800098 |
417 (rd1 << 16) | (rd0 << 12) | (rs << 8));
418 }
419}
420
421static inline void tcg_out_smull32(TCGContext *s,
422 int cond, int rd0, int rd1, int rs, int rm)
423{
424 if (rd0 != rm && rd1 != rm)
425 tcg_out32(s, (cond << 28) | 0xc00090 |
426 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
427 else if (rd0 != rs && rd1 != rs)
428 tcg_out32(s, (cond << 28) | 0xc00090 |
429 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
430 else {
431 tcg_out_dat_reg(s, cond, ARITH_MOV,
432 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
433 tcg_out32(s, (cond << 28) | 0xc00098 |
434 (rd1 << 16) | (rd0 << 12) | (rs << 8));
435 }
436}
437
438static inline void tcg_out_ld32_12(TCGContext *s, int cond,
439 int rd, int rn, tcg_target_long im)
440{
441 if (im >= 0)
442 tcg_out32(s, (cond << 28) | 0x05900000 |
443 (rn << 16) | (rd << 12) | (im & 0xfff));
444 else
445 tcg_out32(s, (cond << 28) | 0x05100000 |
446 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
447}
448
449static inline void tcg_out_st32_12(TCGContext *s, int cond,
450 int rd, int rn, tcg_target_long im)
451{
452 if (im >= 0)
453 tcg_out32(s, (cond << 28) | 0x05800000 |
454 (rn << 16) | (rd << 12) | (im & 0xfff));
455 else
456 tcg_out32(s, (cond << 28) | 0x05000000 |
457 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
458}
459
460static inline void tcg_out_ld32_r(TCGContext *s, int cond,
461 int rd, int rn, int rm)
462{
463 tcg_out32(s, (cond << 28) | 0x07900000 |
464 (rn << 16) | (rd << 12) | rm);
465}
466
467static inline void tcg_out_st32_r(TCGContext *s, int cond,
468 int rd, int rn, int rm)
469{
470 tcg_out32(s, (cond << 28) | 0x07800000 |
471 (rn << 16) | (rd << 12) | rm);
472}
473
3979144c
PB		 474/* Register pre-increment with base writeback. */
475static inline void tcg_out_ld32_rwb(TCGContext *s, int cond,
476 int rd, int rn, int rm)
477{
478 tcg_out32(s, (cond << 28) | 0x07b00000 |
479 (rn << 16) | (rd << 12) | rm);
480}
481
482static inline void tcg_out_st32_rwb(TCGContext *s, int cond,
483 int rd, int rn, int rm)
484{
485 tcg_out32(s, (cond << 28) | 0x07a00000 |
486 (rn << 16) | (rd << 12) | rm);
487}
488
811d4cf4
AZ		 489static inline void tcg_out_ld16u_8(TCGContext *s, int cond,
490 int rd, int rn, tcg_target_long im)
491{
492 if (im >= 0)
493 tcg_out32(s, (cond << 28) | 0x01d000b0 |
494 (rn << 16) | (rd << 12) |
495 ((im & 0xf0) << 4) | (im & 0xf));
496 else
497 tcg_out32(s, (cond << 28) | 0x015000b0 |
498 (rn << 16) | (rd << 12) |
499 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
500}
501
502static inline void tcg_out_st16u_8(TCGContext *s, int cond,
503 int rd, int rn, tcg_target_long im)
504{
505 if (im >= 0)
506 tcg_out32(s, (cond << 28) | 0x01c000b0 |
507 (rn << 16) | (rd << 12) |
508 ((im & 0xf0) << 4) | (im & 0xf));
509 else
510 tcg_out32(s, (cond << 28) | 0x014000b0 |
511 (rn << 16) | (rd << 12) |
512 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
513}
514
515static inline void tcg_out_ld16u_r(TCGContext *s, int cond,
516 int rd, int rn, int rm)
517{
518 tcg_out32(s, (cond << 28) | 0x019000b0 |
519 (rn << 16) | (rd << 12) | rm);
520}
521
522static inline void tcg_out_st16u_r(TCGContext *s, int cond,
523 int rd, int rn, int rm)
524{
525 tcg_out32(s, (cond << 28) | 0x018000b0 |
526 (rn << 16) | (rd << 12) | rm);
527}
528
529static inline void tcg_out_ld16s_8(TCGContext *s, int cond,
530 int rd, int rn, tcg_target_long im)
531{
532 if (im >= 0)
533 tcg_out32(s, (cond << 28) | 0x01d000f0 |
534 (rn << 16) | (rd << 12) |
535 ((im & 0xf0) << 4) | (im & 0xf));
536 else
537 tcg_out32(s, (cond << 28) | 0x015000f0 |
538 (rn << 16) | (rd << 12) |
539 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
540}
541
542static inline void tcg_out_st16s_8(TCGContext *s, int cond,
543 int rd, int rn, tcg_target_long im)
544{
545 if (im >= 0)
546 tcg_out32(s, (cond << 28) | 0x01c000f0 |
547 (rn << 16) | (rd << 12) |
548 ((im & 0xf0) << 4) | (im & 0xf));
549 else
550 tcg_out32(s, (cond << 28) | 0x014000f0 |
551 (rn << 16) | (rd << 12) |
552 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
553}
554
555static inline void tcg_out_ld16s_r(TCGContext *s, int cond,
556 int rd, int rn, int rm)
557{
558 tcg_out32(s, (cond << 28) | 0x019000f0 |
559 (rn << 16) | (rd << 12) | rm);
560}
561
562static inline void tcg_out_st16s_r(TCGContext *s, int cond,
563 int rd, int rn, int rm)
564{
565 tcg_out32(s, (cond << 28) | 0x018000f0 |
566 (rn << 16) | (rd << 12) | rm);
567}
568
569static inline void tcg_out_ld8_12(TCGContext *s, int cond,
570 int rd, int rn, tcg_target_long im)
571{
572 if (im >= 0)
573 tcg_out32(s, (cond << 28) | 0x05d00000 |
574 (rn << 16) | (rd << 12) | (im & 0xfff));
575 else
576 tcg_out32(s, (cond << 28) | 0x05500000 |
577 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
578}
579
580static inline void tcg_out_st8_12(TCGContext *s, int cond,
581 int rd, int rn, tcg_target_long im)
582{
583 if (im >= 0)
584 tcg_out32(s, (cond << 28) | 0x05c00000 |
585 (rn << 16) | (rd << 12) | (im & 0xfff));
586 else
587 tcg_out32(s, (cond << 28) | 0x05400000 |
588 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
589}
590
591static inline void tcg_out_ld8_r(TCGContext *s, int cond,
592 int rd, int rn, int rm)
593{
594 tcg_out32(s, (cond << 28) | 0x07d00000 |
595 (rn << 16) | (rd << 12) | rm);
596}
597
598static inline void tcg_out_st8_r(TCGContext *s, int cond,
599 int rd, int rn, int rm)
600{
601 tcg_out32(s, (cond << 28) | 0x07c00000 |
602 (rn << 16) | (rd << 12) | rm);
603}
604
605static inline void tcg_out_ld8s_8(TCGContext *s, int cond,
606 int rd, int rn, tcg_target_long im)
607{
608 if (im >= 0)
609 tcg_out32(s, (cond << 28) | 0x01d000d0 |
610 (rn << 16) | (rd << 12) |
611 ((im & 0xf0) << 4) | (im & 0xf));
612 else
613 tcg_out32(s, (cond << 28) | 0x015000d0 |
614 (rn << 16) | (rd << 12) |
615 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
616}
617
618static inline void tcg_out_st8s_8(TCGContext *s, int cond,
619 int rd, int rn, tcg_target_long im)
620{
621 if (im >= 0)
622 tcg_out32(s, (cond << 28) | 0x01c000d0 |
623 (rn << 16) | (rd << 12) |
624 ((im & 0xf0) << 4) | (im & 0xf));
625 else
626 tcg_out32(s, (cond << 28) | 0x014000d0 |
627 (rn << 16) | (rd << 12) |
628 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
629}
630
631static inline void tcg_out_ld8s_r(TCGContext *s, int cond,
632 int rd, int rn, int rm)
633{
204c1674 634 tcg_out32(s, (cond << 28) | 0x019000d0 |
811d4cf4
AZ		 635 (rn << 16) | (rd << 12) | rm);
636}
637
638static inline void tcg_out_st8s_r(TCGContext *s, int cond,
639 int rd, int rn, int rm)
640{
204c1674 641 tcg_out32(s, (cond << 28) | 0x018000d0 |
811d4cf4
AZ		 642 (rn << 16) | (rd << 12) | rm);
643}
644
645static inline void tcg_out_ld32u(TCGContext *s, int cond,
646 int rd, int rn, int32_t offset)
647{
648 if (offset > 0xfff || offset < -0xfff) {
649 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
650 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_R8);
651 } else
652 tcg_out_ld32_12(s, cond, rd, rn, offset);
653}
654
655static inline void tcg_out_st32(TCGContext *s, int cond,
656 int rd, int rn, int32_t offset)
657{
658 if (offset > 0xfff || offset < -0xfff) {
659 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
660 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_R8);
661 } else
662 tcg_out_st32_12(s, cond, rd, rn, offset);
663}
664
665static inline void tcg_out_ld16u(TCGContext *s, int cond,
666 int rd, int rn, int32_t offset)
667{
668 if (offset > 0xff || offset < -0xff) {
669 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
670 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_R8);
671 } else
672 tcg_out_ld16u_8(s, cond, rd, rn, offset);
673}
674
675static inline void tcg_out_ld16s(TCGContext *s, int cond,
676 int rd, int rn, int32_t offset)
677{
678 if (offset > 0xff || offset < -0xff) {
679 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
680 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_R8);
681 } else
682 tcg_out_ld16s_8(s, cond, rd, rn, offset);
683}
684
685static inline void tcg_out_st16u(TCGContext *s, int cond,
686 int rd, int rn, int32_t offset)
687{
688 if (offset > 0xff || offset < -0xff) {
689 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
690 tcg_out_st16u_r(s, cond, rd, rn, TCG_REG_R8);
691 } else
692 tcg_out_st16u_8(s, cond, rd, rn, offset);
693}
694
695static inline void tcg_out_ld8u(TCGContext *s, int cond,
696 int rd, int rn, int32_t offset)
697{
698 if (offset > 0xfff || offset < -0xfff) {
699 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
700 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_R8);
701 } else
702 tcg_out_ld8_12(s, cond, rd, rn, offset);
703}
704
705static inline void tcg_out_ld8s(TCGContext *s, int cond,
706 int rd, int rn, int32_t offset)
707{
708 if (offset > 0xff || offset < -0xff) {
709 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
710 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_R8);
711 } else
712 tcg_out_ld8s_8(s, cond, rd, rn, offset);
713}
714
715static inline void tcg_out_st8u(TCGContext *s, int cond,
716 int rd, int rn, int32_t offset)
717{
718 if (offset > 0xfff || offset < -0xfff) {
719 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
720 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_R8);
721 } else
722 tcg_out_st8_12(s, cond, rd, rn, offset);
723}
724
725static inline void tcg_out_goto(TCGContext *s, int cond, uint32_t addr)
726{
727 int32_t val;
728
729 val = addr - (tcg_target_long) s->code_ptr;
730 if (val - 8 < 0x01fffffd && val - 8 > -0x01fffffd)
731 tcg_out_b(s, cond, val);
732 else {
733#if 1
734 tcg_abort();
735#else
736 if (cond == COND_AL) {
737 tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
738 tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
739 } else {
740 tcg_out_movi32(s, cond, TCG_REG_R8, val - 8);
741 tcg_out_dat_reg(s, cond, ARITH_ADD,
742 15, 15, TCG_REG_R8, SHIFT_IMM_LSL(0));
743 }
744#endif
745 }
746}
747
748static inline void tcg_out_call(TCGContext *s, int cond, uint32_t addr)
749{
750 int32_t val;
751
811d4cf4
AZ		 752 val = addr - (tcg_target_long) s->code_ptr;
753 if (val < 0x01fffffd && val > -0x01fffffd)
754 tcg_out_bl(s, cond, val);
755 else {
756#if 1
757 tcg_abort();
758#else
759 if (cond == COND_AL) {
760 tcg_out_dat_imm(s, cond, ARITH_ADD, 14, 15, 4);
761 tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
762 tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
763 } else {
764 tcg_out_movi32(s, cond, TCG_REG_R9, addr);
765 tcg_out_dat_imm(s, cond, ARITH_MOV, 14, 0, 15);
766 tcg_out_bx(s, cond, TCG_REG_R9);
767 }
768#endif
769 }
811d4cf4
AZ		 770}
771
772static inline void tcg_out_callr(TCGContext *s, int cond, int arg)
773{
811d4cf4
AZ		 774 /* TODO: on ARMv5 and ARMv6 replace with tcg_out_blx(s, cond, arg); */
775 tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, 15, SHIFT_IMM_LSL(0));
776 tcg_out_bx(s, cond, arg);
811d4cf4
AZ		 777}
778
779static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index)
780{
781 TCGLabel *l = &s->labels[label_index];
782
783 if (l->has_value)
784 tcg_out_goto(s, cond, l->u.value);
785 else if (cond == COND_AL) {
786 tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
787 tcg_out_reloc(s, s->code_ptr, R_ARM_ABS32, label_index, 31337);
788 s->code_ptr += 4;
789 } else {
790 /* Probably this should be preferred even for COND_AL... */
791 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, label_index, 31337);
e936243a 792 tcg_out_b_noaddr(s, cond);
811d4cf4
AZ		 793 }
794}
795
811d4cf4 796#ifdef CONFIG_SOFTMMU
79383c9c
BS		 797
798#include "../../softmmu_defs.h"
811d4cf4
AZ		 799
800static void *qemu_ld_helpers[4] = {
801 __ldb_mmu,
802 __ldw_mmu,
803 __ldl_mmu,
804 __ldq_mmu,
805};
806
807static void *qemu_st_helpers[4] = {
808 __stb_mmu,
809 __stw_mmu,
810 __stl_mmu,
811 __stq_mmu,
812};
813#endif
814
3979144c
PB		 815#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
816
811d4cf4
AZ		 817static inline void tcg_out_qemu_ld(TCGContext *s, int cond,
818 const TCGArg *args, int opc)
819{
820 int addr_reg, data_reg, data_reg2;
821#ifdef CONFIG_SOFTMMU
822 int mem_index, s_bits;
823# if TARGET_LONG_BITS == 64
824 int addr_reg2;
825# endif
811d4cf4 826 uint32_t *label_ptr;
811d4cf4
AZ		 827#endif
828
829 data_reg = *args++;
830 if (opc == 3)
831 data_reg2 = *args++;
832 else
d89c682f 833 data_reg2 = 0; /* suppress warning */
811d4cf4 834 addr_reg = *args++;
811d4cf4 835#ifdef CONFIG_SOFTMMU
aef3a282
AZ		 836# if TARGET_LONG_BITS == 64
837 addr_reg2 = *args++;
838# endif
811d4cf4
AZ		 839 mem_index = *args;
840 s_bits = opc & 3;
841
91a3c1b0 842 /* Should generate something like the following:
3979144c 843 * shr r8, addr_reg, #TARGET_PAGE_BITS
91a3c1b0 844 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
3979144c 845 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
91a3c1b0
AZ		 846 */
847# if CPU_TLB_BITS > 8
848# error
849# endif
811d4cf4 850 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
3979144c 851 8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
811d4cf4
AZ		 852 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
853 0, 8, CPU_TLB_SIZE - 1);
854 tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
855 0, TCG_AREG0, 0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
91a3c1b0
AZ		 856 /* In the
857 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_read))]
858 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
859 * not exceed otherwise, so use an
860 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
861 * before.
862 */
225b4376
AZ		 863 if (mem_index)
864 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, 0, 0,
865 (mem_index << (TLB_SHIFT & 1)) |
866 ((16 - (TLB_SHIFT >> 1)) << 8));
811d4cf4 867 tcg_out_ld32_12(s, COND_AL, 1, 0,
225b4376 868 offsetof(CPUState, tlb_table[0][0].addr_read));
811d4cf4
AZ		 869 tcg_out_dat_reg(s, COND_AL, ARITH_CMP,
870 0, 1, 8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
3979144c
PB		 871 /* Check alignment. */
872 if (s_bits)
873 tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
874 0, addr_reg, (1 << s_bits) - 1);
811d4cf4
AZ		 875# if TARGET_LONG_BITS == 64
876 /* XXX: possibly we could use a block data load or writeback in
877 * the first access. */
878 tcg_out_ld32_12(s, COND_EQ, 1, 0,
225b4376 879 offsetof(CPUState, tlb_table[0][0].addr_read) + 4);
811d4cf4
AZ		 880 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP,
881 0, 1, addr_reg2, SHIFT_IMM_LSL(0));
882# endif
883 tcg_out_ld32_12(s, COND_EQ, 1, 0,
225b4376 884 offsetof(CPUState, tlb_table[0][0].addend));
811d4cf4
AZ		 885
886 switch (opc) {
887 case 0:
888 tcg_out_ld8_r(s, COND_EQ, data_reg, addr_reg, 1);
889 break;
890 case 0 | 4:
891 tcg_out_ld8s_r(s, COND_EQ, data_reg, addr_reg, 1);
892 break;
893 case 1:
894 tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, 1);
895 break;
896 case 1 | 4:
897 tcg_out_ld16s_r(s, COND_EQ, data_reg, addr_reg, 1);
898 break;
899 case 2:
900 default:
901 tcg_out_ld32_r(s, COND_EQ, data_reg, addr_reg, 1);
902 break;
903 case 3:
3979144c 904 tcg_out_ld32_rwb(s, COND_EQ, data_reg, 1, addr_reg);
811d4cf4
AZ		 905 tcg_out_ld32_12(s, COND_EQ, data_reg2, 1, 4);
906 break;
907 }
908
909 label_ptr = (void *) s->code_ptr;
910 tcg_out_b(s, COND_EQ, 8);
811d4cf4 911
811d4cf4
AZ		 912 /* TODO: move this code to where the constants pool will be */
913 if (addr_reg)
914 tcg_out_dat_reg(s, cond, ARITH_MOV,
915 0, 0, addr_reg, SHIFT_IMM_LSL(0));
916# if TARGET_LONG_BITS == 32
917 tcg_out_dat_imm(s, cond, ARITH_MOV, 1, 0, mem_index);
918# else
919 if (addr_reg2 != 1)
920 tcg_out_dat_reg(s, cond, ARITH_MOV,
921 1, 0, addr_reg2, SHIFT_IMM_LSL(0));
922 tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
923# endif
650bbb36 924 tcg_out_bl(s, cond, (tcg_target_long) qemu_ld_helpers[s_bits] -
811d4cf4
AZ		 925 (tcg_target_long) s->code_ptr);
926
927 switch (opc) {
928 case 0 | 4:
929 tcg_out_dat_reg(s, cond, ARITH_MOV,
930 0, 0, 0, SHIFT_IMM_LSL(24));
931 tcg_out_dat_reg(s, cond, ARITH_MOV,
932 data_reg, 0, 0, SHIFT_IMM_ASR(24));
933 break;
934 case 1 | 4:
935 tcg_out_dat_reg(s, cond, ARITH_MOV,
936 0, 0, 0, SHIFT_IMM_LSL(16));
937 tcg_out_dat_reg(s, cond, ARITH_MOV,
938 data_reg, 0, 0, SHIFT_IMM_ASR(16));
939 break;
940 case 0:
941 case 1:
942 case 2:
943 default:
944 if (data_reg)
945 tcg_out_dat_reg(s, cond, ARITH_MOV,
946 data_reg, 0, 0, SHIFT_IMM_LSL(0));
947 break;
948 case 3:
d0660ed4
AZ		 949 if (data_reg != 0)
950 tcg_out_dat_reg(s, cond, ARITH_MOV,
951 data_reg, 0, 0, SHIFT_IMM_LSL(0));
811d4cf4
AZ		 952 if (data_reg2 != 1)
953 tcg_out_dat_reg(s, cond, ARITH_MOV,
954 data_reg2, 0, 1, SHIFT_IMM_LSL(0));
811d4cf4
AZ		 955 break;
956 }
957
811d4cf4 958 *label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
379f6698
PB		 959#else /* !CONFIG_SOFTMMU */
960 if (GUEST_BASE) {
961 uint32_t offset = GUEST_BASE;
962 int i;
963 int rot;
964
965 while (offset) {
966 i = ctz32(offset) & ~1;
967 rot = ((32 - i) << 7) & 0xf00;
968
969 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, 8, addr_reg,
970 ((offset >> i) & 0xff) | rot);
971 addr_reg = 8;
972 offset &= ~(0xff << i);
973 }
974 }
811d4cf4
AZ		 975 switch (opc) {
976 case 0:
977 tcg_out_ld8_12(s, COND_AL, data_reg, addr_reg, 0);
978 break;
979 case 0 | 4:
980 tcg_out_ld8s_8(s, COND_AL, data_reg, addr_reg, 0);
981 break;
982 case 1:
983 tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
984 break;
985 case 1 | 4:
986 tcg_out_ld16s_8(s, COND_AL, data_reg, addr_reg, 0);
987 break;
988 case 2:
989 default:
990 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
991 break;
992 case 3:
eae6ce52
AZ		 993 /* TODO: use block load -
994 * check that data_reg2 > data_reg or the other way */
419bafa5
AJ		 995 if (data_reg == addr_reg) {
996 tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4);
997 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
998 } else {
999 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
1000 tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4);
1001 }
811d4cf4
AZ		 1002 break;
1003 }
1004#endif
1005}
1006
1007static inline void tcg_out_qemu_st(TCGContext *s, int cond,
1008 const TCGArg *args, int opc)
1009{
1010 int addr_reg, data_reg, data_reg2;
1011#ifdef CONFIG_SOFTMMU
1012 int mem_index, s_bits;
1013# if TARGET_LONG_BITS == 64
1014 int addr_reg2;
1015# endif
811d4cf4 1016 uint32_t *label_ptr;
811d4cf4
AZ		 1017#endif
1018
1019 data_reg = *args++;
1020 if (opc == 3)
1021 data_reg2 = *args++;
1022 else
d89c682f 1023 data_reg2 = 0; /* suppress warning */
811d4cf4 1024 addr_reg = *args++;
811d4cf4 1025#ifdef CONFIG_SOFTMMU
aef3a282
AZ		 1026# if TARGET_LONG_BITS == 64
1027 addr_reg2 = *args++;
1028# endif
811d4cf4
AZ		 1029 mem_index = *args;
1030 s_bits = opc & 3;
1031
91a3c1b0 1032 /* Should generate something like the following:
3979144c 1033 * shr r8, addr_reg, #TARGET_PAGE_BITS
91a3c1b0 1034 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
3979144c 1035 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
91a3c1b0 1036 */
811d4cf4 1037 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
3979144c 1038 8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
811d4cf4
AZ		 1039 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
1040 0, 8, CPU_TLB_SIZE - 1);
1041 tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
1042 0, TCG_AREG0, 0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
91a3c1b0
AZ		 1043 /* In the
1044 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_write))]
1045 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
1046 * not exceed otherwise, so use an
1047 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
1048 * before.
1049 */
225b4376
AZ		 1050 if (mem_index)
1051 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, 0, 0,
1052 (mem_index << (TLB_SHIFT & 1)) |
1053 ((16 - (TLB_SHIFT >> 1)) << 8));
811d4cf4 1054 tcg_out_ld32_12(s, COND_AL, 1, 0,
225b4376 1055 offsetof(CPUState, tlb_table[0][0].addr_write));
811d4cf4
AZ		 1056 tcg_out_dat_reg(s, COND_AL, ARITH_CMP,
1057 0, 1, 8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
3979144c
PB		 1058 /* Check alignment. */
1059 if (s_bits)
1060 tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
1061 0, addr_reg, (1 << s_bits) - 1);
811d4cf4
AZ		 1062# if TARGET_LONG_BITS == 64
1063 /* XXX: possibly we could use a block data load or writeback in
1064 * the first access. */
1065 tcg_out_ld32_12(s, COND_EQ, 1, 0,
225b4376 1066 offsetof(CPUState, tlb_table[0][0].addr_write)
811d4cf4
AZ		 1067 + 4);
1068 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP,
1069 0, 1, addr_reg2, SHIFT_IMM_LSL(0));
1070# endif
1071 tcg_out_ld32_12(s, COND_EQ, 1, 0,
225b4376 1072 offsetof(CPUState, tlb_table[0][0].addend));
811d4cf4
AZ		 1073
1074 switch (opc) {
1075 case 0:
1076 tcg_out_st8_r(s, COND_EQ, data_reg, addr_reg, 1);
1077 break;
1078 case 0 | 4:
1079 tcg_out_st8s_r(s, COND_EQ, data_reg, addr_reg, 1);
1080 break;
1081 case 1:
1082 tcg_out_st16u_r(s, COND_EQ, data_reg, addr_reg, 1);
1083 break;
1084 case 1 | 4:
1085 tcg_out_st16s_r(s, COND_EQ, data_reg, addr_reg, 1);
1086 break;
1087 case 2:
1088 default:
1089 tcg_out_st32_r(s, COND_EQ, data_reg, addr_reg, 1);
1090 break;
1091 case 3:
3979144c 1092 tcg_out_st32_rwb(s, COND_EQ, data_reg, 1, addr_reg);
811d4cf4
AZ		 1093 tcg_out_st32_12(s, COND_EQ, data_reg2, 1, 4);
1094 break;
1095 }
1096
1097 label_ptr = (void *) s->code_ptr;
1098 tcg_out_b(s, COND_EQ, 8);
811d4cf4 1099
811d4cf4
AZ		 1100 /* TODO: move this code to where the constants pool will be */
1101 if (addr_reg)
1102 tcg_out_dat_reg(s, cond, ARITH_MOV,
1103 0, 0, addr_reg, SHIFT_IMM_LSL(0));
1104# if TARGET_LONG_BITS == 32
1105 switch (opc) {
1106 case 0:
1107 tcg_out_dat_imm(s, cond, ARITH_AND, 1, data_reg, 0xff);
1108 tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
1109 break;
1110 case 1:
1111 tcg_out_dat_reg(s, cond, ARITH_MOV,
1112 1, 0, data_reg, SHIFT_IMM_LSL(16));
1113 tcg_out_dat_reg(s, cond, ARITH_MOV,
1114 1, 0, 1, SHIFT_IMM_LSR(16));
1115 tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
1116 break;
1117 case 2:
1118 if (data_reg != 1)
1119 tcg_out_dat_reg(s, cond, ARITH_MOV,
1120 1, 0, data_reg, SHIFT_IMM_LSL(0));
1121 tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
1122 break;
1123 case 3:
1124 if (data_reg != 1)
1125 tcg_out_dat_reg(s, cond, ARITH_MOV,
1126 1, 0, data_reg, SHIFT_IMM_LSL(0));
1127 if (data_reg2 != 2)
1128 tcg_out_dat_reg(s, cond, ARITH_MOV,
1129 2, 0, data_reg2, SHIFT_IMM_LSL(0));
1130 tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1131 break;
1132 }
1133# else
1134 if (addr_reg2 != 1)
1135 tcg_out_dat_reg(s, cond, ARITH_MOV,
1136 1, 0, addr_reg2, SHIFT_IMM_LSL(0));
1137 switch (opc) {
1138 case 0:
1139 tcg_out_dat_imm(s, cond, ARITH_AND, 2, data_reg, 0xff);
1140 tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1141 break;
1142 case 1:
1143 tcg_out_dat_reg(s, cond, ARITH_MOV,
1144 2, 0, data_reg, SHIFT_IMM_LSL(16));
1145 tcg_out_dat_reg(s, cond, ARITH_MOV,
1146 2, 0, 2, SHIFT_IMM_LSR(16));
1147 tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1148 break;
1149 case 2:
1150 if (data_reg != 2)
1151 tcg_out_dat_reg(s, cond, ARITH_MOV,
1152 2, 0, data_reg, SHIFT_IMM_LSL(0));
1153 tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1154 break;
1155 case 3:
91a3c1b0
AZ		 1156 tcg_out_dat_imm(s, cond, ARITH_MOV, 8, 0, mem_index);
1157 tcg_out32(s, (cond << 28) | 0x052d8010); /* str r8, [sp, #-0x10]! */
811d4cf4
AZ		 1158 if (data_reg != 2)
1159 tcg_out_dat_reg(s, cond, ARITH_MOV,
1160 2, 0, data_reg, SHIFT_IMM_LSL(0));
1161 if (data_reg2 != 3)
1162 tcg_out_dat_reg(s, cond, ARITH_MOV,
1163 3, 0, data_reg2, SHIFT_IMM_LSL(0));
1164 break;
1165 }
1166# endif
1167
204c1674 1168 tcg_out_bl(s, cond, (tcg_target_long) qemu_st_helpers[s_bits] -
811d4cf4 1169 (tcg_target_long) s->code_ptr);
811d4cf4
AZ		 1170# if TARGET_LONG_BITS == 64
1171 if (opc == 3)
1172 tcg_out_dat_imm(s, cond, ARITH_ADD, 13, 13, 0x10);
1173# endif
1174
811d4cf4 1175 *label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
379f6698
PB		 1176#else /* !CONFIG_SOFTMMU */
1177 if (GUEST_BASE) {
1178 uint32_t offset = GUEST_BASE;
1179 int i;
1180 int rot;
1181
1182 while (offset) {
1183 i = ctz32(offset) & ~1;
1184 rot = ((32 - i) << 7) & 0xf00;
1185
1186 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, 8, addr_reg,
1187 ((offset >> i) & 0xff) | rot);
1188 addr_reg = 8;
1189 offset &= ~(0xff << i);
1190 }
1191 }
811d4cf4
AZ		 1192 switch (opc) {
1193 case 0:
1194 tcg_out_st8_12(s, COND_AL, data_reg, addr_reg, 0);
1195 break;
1196 case 0 | 4:
204c1674 1197 tcg_out_st8s_8(s, COND_AL, data_reg, addr_reg, 0);
811d4cf4
AZ		 1198 break;
1199 case 1:
1200 tcg_out_st16u_8(s, COND_AL, data_reg, addr_reg, 0);
1201 break;
1202 case 1 | 4:
1203 tcg_out_st16s_8(s, COND_AL, data_reg, addr_reg, 0);
1204 break;
1205 case 2:
1206 default:
1207 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1208 break;
1209 case 3:
eae6ce52
AZ		 1210 /* TODO: use block store -
1211 * check that data_reg2 > data_reg or the other way */
811d4cf4
AZ		 1212 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1213 tcg_out_st32_12(s, COND_AL, data_reg2, addr_reg, 4);
1214 break;
1215 }
1216#endif
1217}
1218
811d4cf4
AZ		 1219static uint8_t *tb_ret_addr;
1220
a9751609 1221static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
811d4cf4
AZ		 1222 const TCGArg *args, const int *const_args)
1223{
1224 int c;
1225
1226 switch (opc) {
1227 case INDEX_op_exit_tb:
fe33867b
AZ		 1228 {
1229 uint8_t *ld_ptr = s->code_ptr;
1230 if (args[0] >> 8)
1231 tcg_out_ld32_12(s, COND_AL, 0, 15, 0);
1232 else
1233 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, 0, 0, args[0]);
1234 tcg_out_goto(s, COND_AL, (tcg_target_ulong) tb_ret_addr);
1235 if (args[0] >> 8) {
1236 *ld_ptr = (uint8_t) (s->code_ptr - ld_ptr) - 8;
1237 tcg_out32(s, args[0]);
1238 }
1239 }
811d4cf4
AZ		 1240 break;
1241 case INDEX_op_goto_tb:
1242 if (s->tb_jmp_offset) {
1243 /* Direct jump method */
fe33867b 1244#if defined(USE_DIRECT_JUMP)
811d4cf4
AZ		 1245 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1246 tcg_out_b(s, COND_AL, 8);
1247#else
1248 tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
1249 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1250 tcg_out32(s, 0);
1251#endif
1252 } else {
1253 /* Indirect jump method */
1254#if 1
1255 c = (int) (s->tb_next + args[0]) - ((int) s->code_ptr + 8);
1256 if (c > 0xfff || c < -0xfff) {
1257 tcg_out_movi32(s, COND_AL, TCG_REG_R0,
1258 (tcg_target_long) (s->tb_next + args[0]));
1259 tcg_out_ld32_12(s, COND_AL, 15, TCG_REG_R0, 0);
1260 } else
1261 tcg_out_ld32_12(s, COND_AL, 15, 15, c);
1262#else
1263 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, 15, 0);
1264 tcg_out_ld32_12(s, COND_AL, 15, TCG_REG_R0, 0);
1265 tcg_out32(s, (tcg_target_long) (s->tb_next + args[0]));
1266#endif
1267 }
1268 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1269 break;
1270 case INDEX_op_call:
1271 if (const_args[0])
1272 tcg_out_call(s, COND_AL, args[0]);
1273 else
1274 tcg_out_callr(s, COND_AL, args[0]);
1275 break;
1276 case INDEX_op_jmp:
1277 if (const_args[0])
1278 tcg_out_goto(s, COND_AL, args[0]);
1279 else
1280 tcg_out_bx(s, COND_AL, args[0]);
1281 break;
1282 case INDEX_op_br:
1283 tcg_out_goto_label(s, COND_AL, args[0]);
1284 break;
1285
1286 case INDEX_op_ld8u_i32:
1287 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]);
1288 break;
1289 case INDEX_op_ld8s_i32:
1290 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]);
1291 break;
1292 case INDEX_op_ld16u_i32:
1293 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]);
1294 break;
1295 case INDEX_op_ld16s_i32:
1296 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]);
1297 break;
1298 case INDEX_op_ld_i32:
1299 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]);
1300 break;
1301 case INDEX_op_st8_i32:
1302 tcg_out_st8u(s, COND_AL, args[0], args[1], args[2]);
1303 break;
1304 case INDEX_op_st16_i32:
1305 tcg_out_st16u(s, COND_AL, args[0], args[1], args[2]);
1306 break;
1307 case INDEX_op_st_i32:
1308 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);
1309 break;
1310
1311 case INDEX_op_mov_i32:
1312 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1313 args[0], 0, args[1], SHIFT_IMM_LSL(0));
1314 break;
1315 case INDEX_op_movi_i32:
1316 tcg_out_movi32(s, COND_AL, args[0], args[1]);
1317 break;
1318 case INDEX_op_add_i32:
1319 c = ARITH_ADD;
1320 goto gen_arith;
1321 case INDEX_op_sub_i32:
1322 c = ARITH_SUB;
1323 goto gen_arith;
1324 case INDEX_op_and_i32:
1325 c = ARITH_AND;
1326 goto gen_arith;
932234f6
AJ		 1327 case INDEX_op_andc_i32:
1328 c = ARITH_BIC;
1329 goto gen_arith;
811d4cf4
AZ		 1330 case INDEX_op_or_i32:
1331 c = ARITH_ORR;
1332 goto gen_arith;
1333 case INDEX_op_xor_i32:
1334 c = ARITH_EOR;
1335 /* Fall through. */
1336 gen_arith:
94953e6d
LD		 1337 if (const_args[2]) {
1338 int rot;
1339 rot = encode_imm(args[2]);
cb4e581f 1340 tcg_out_dat_imm(s, COND_AL, c,
94953e6d
LD		 1341 args[0], args[1], rotl(args[2], rot) | (rot << 7));
1342 } else
cb4e581f
LD		 1343 tcg_out_dat_reg(s, COND_AL, c,
1344 args[0], args[1], args[2], SHIFT_IMM_LSL(0));
811d4cf4
AZ		 1345 break;
1346 case INDEX_op_add2_i32:
1347 tcg_out_dat_reg2(s, COND_AL, ARITH_ADD, ARITH_ADC,
1348 args[0], args[1], args[2], args[3],
1349 args[4], args[5], SHIFT_IMM_LSL(0));
1350 break;
1351 case INDEX_op_sub2_i32:
1352 tcg_out_dat_reg2(s, COND_AL, ARITH_SUB, ARITH_SBC,
1353 args[0], args[1], args[2], args[3],
1354 args[4], args[5], SHIFT_IMM_LSL(0));
1355 break;
650bbb36
AZ		 1356 case INDEX_op_neg_i32:
1357 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
1358 break;
f878d2d2
LD		 1359 case INDEX_op_not_i32:
1360 tcg_out_dat_reg(s, COND_AL,
1361 ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0));
1362 break;
811d4cf4
AZ		 1363 case INDEX_op_mul_i32:
1364 tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
1365 break;
1366 case INDEX_op_mulu2_i32:
1367 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]);
1368 break;
811d4cf4
AZ		 1369 /* XXX: Perhaps args[2] & 0x1f is wrong */
1370 case INDEX_op_shl_i32:
1371 c = const_args[2] ?
1372 SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]);
1373 goto gen_shift32;
1374 case INDEX_op_shr_i32:
1375 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) :
1376 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]);
1377 goto gen_shift32;
1378 case INDEX_op_sar_i32:
1379 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) :
1380 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]);
1381 /* Fall through. */
1382 gen_shift32:
1383 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c);
1384 break;
1385
1386 case INDEX_op_brcond_i32:
023e77f8
AJ		 1387 if (const_args[1]) {
1388 int rot;
1389 rot = encode_imm(args[1]);
1390 tcg_out_dat_imm(s, COND_AL, ARITH_CMP,
1391 0, args[0], rotl(args[1], rot) | (rot << 7));
1392 } else {
1393 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1394 args[0], args[1], SHIFT_IMM_LSL(0));
1395 }
811d4cf4
AZ		 1396 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], args[3]);
1397 break;
1398 case INDEX_op_brcond2_i32:
1399 /* The resulting conditions are:
1400 * TCG_COND_EQ --> a0 == a2 && a1 == a3,
1401 * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3,
1402 * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3,
1403 * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1404 * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1405 * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3,
1406 */
1407 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1408 args[1], args[3], SHIFT_IMM_LSL(0));
1409 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1410 args[0], args[2], SHIFT_IMM_LSL(0));
1411 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], args[5]);
1412 break;
f72a6cd7 1413 case INDEX_op_setcond_i32:
023e77f8
AJ		 1414 if (const_args[2]) {
1415 int rot;
1416 rot = encode_imm(args[2]);
1417 tcg_out_dat_imm(s, COND_AL, ARITH_CMP,
1418 0, args[1], rotl(args[2], rot) | (rot << 7));
1419 } else {
1420 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1421 args[1], args[2], SHIFT_IMM_LSL(0));
1422 }
f72a6cd7
AJ		 1423 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]],
1424 ARITH_MOV, args[0], 0, 1);
1425 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
1426 ARITH_MOV, args[0], 0, 0);
1427 break;
e0404769
AJ		 1428 case INDEX_op_setcond2_i32:
1429 /* See brcond2_i32 comment */
1430 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1431 args[2], args[4], SHIFT_IMM_LSL(0));
1432 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1433 args[1], args[3], SHIFT_IMM_LSL(0));
1434 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[5]],
1435 ARITH_MOV, args[0], 0, 1);
1436 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[5])],
1437 ARITH_MOV, args[0], 0, 0);
b525f0a9 1438 break;
811d4cf4
AZ		 1439
1440 case INDEX_op_qemu_ld8u:
1441 tcg_out_qemu_ld(s, COND_AL, args, 0);
1442 break;
1443 case INDEX_op_qemu_ld8s:
1444 tcg_out_qemu_ld(s, COND_AL, args, 0 | 4);
1445 break;
1446 case INDEX_op_qemu_ld16u:
1447 tcg_out_qemu_ld(s, COND_AL, args, 1);
1448 break;
1449 case INDEX_op_qemu_ld16s:
1450 tcg_out_qemu_ld(s, COND_AL, args, 1 | 4);
1451 break;
86feb1c8 1452 case INDEX_op_qemu_ld32:
811d4cf4
AZ		 1453 tcg_out_qemu_ld(s, COND_AL, args, 2);
1454 break;
1455 case INDEX_op_qemu_ld64:
1456 tcg_out_qemu_ld(s, COND_AL, args, 3);
1457 break;
650bbb36 1458
811d4cf4
AZ		 1459 case INDEX_op_qemu_st8:
1460 tcg_out_qemu_st(s, COND_AL, args, 0);
1461 break;
1462 case INDEX_op_qemu_st16:
1463 tcg_out_qemu_st(s, COND_AL, args, 1);
1464 break;
1465 case INDEX_op_qemu_st32:
1466 tcg_out_qemu_st(s, COND_AL, args, 2);
1467 break;
1468 case INDEX_op_qemu_st64:
1469 tcg_out_qemu_st(s, COND_AL, args, 3);
1470 break;
1471
1472 case INDEX_op_ext8s_i32:
7990496d
LD		 1473#ifdef __ARM_ARCH_7A__
1474 /* sxtb */
1475 tcg_out32(s, 0xe6af0070 | (args[0] << 12) | args[1]);
1476#else
811d4cf4
AZ		 1477 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1478 args[0], 0, args[1], SHIFT_IMM_LSL(24));
1479 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1480 args[0], 0, args[0], SHIFT_IMM_ASR(24));
7990496d 1481#endif
811d4cf4
AZ		 1482 break;
1483 case INDEX_op_ext16s_i32:
7990496d
LD		 1484#ifdef __ARM_ARCH_7A__
1485 /* sxth */
1486 tcg_out32(s, 0xe6bf0070 | (args[0] << 12) | args[1]);
1487#else
811d4cf4
AZ		 1488 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1489 args[0], 0, args[1], SHIFT_IMM_LSL(16));
1490 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1491 args[0], 0, args[0], SHIFT_IMM_ASR(16));
7990496d 1492#endif
811d4cf4
AZ		 1493 break;
1494
1495 default:
1496 tcg_abort();
1497 }
1498}
1499
1500static const TCGTargetOpDef arm_op_defs[] = {
1501 { INDEX_op_exit_tb, { } },
1502 { INDEX_op_goto_tb, { } },
1503 { INDEX_op_call, { "ri" } },
1504 { INDEX_op_jmp, { "ri" } },
1505 { INDEX_op_br, { } },
1506
1507 { INDEX_op_mov_i32, { "r", "r" } },
1508 { INDEX_op_movi_i32, { "r" } },
1509
1510 { INDEX_op_ld8u_i32, { "r", "r" } },
1511 { INDEX_op_ld8s_i32, { "r", "r" } },
1512 { INDEX_op_ld16u_i32, { "r", "r" } },
1513 { INDEX_op_ld16s_i32, { "r", "r" } },
1514 { INDEX_op_ld_i32, { "r", "r" } },
1515 { INDEX_op_st8_i32, { "r", "r" } },
1516 { INDEX_op_st16_i32, { "r", "r" } },
1517 { INDEX_op_st_i32, { "r", "r" } },
1518
1519 /* TODO: "r", "r", "ri" */
cb4e581f
LD		 1520 { INDEX_op_add_i32, { "r", "r", "rI" } },
1521 { INDEX_op_sub_i32, { "r", "r", "rI" } },
811d4cf4
AZ		 1522 { INDEX_op_mul_i32, { "r", "r", "r" } },
1523 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
cb4e581f 1524 { INDEX_op_and_i32, { "r", "r", "rI" } },
932234f6 1525 { INDEX_op_andc_i32, { "r", "r", "rI" } },
cb4e581f
LD		 1526 { INDEX_op_or_i32, { "r", "r", "rI" } },
1527 { INDEX_op_xor_i32, { "r", "r", "rI" } },
650bbb36 1528 { INDEX_op_neg_i32, { "r", "r" } },
f878d2d2 1529 { INDEX_op_not_i32, { "r", "r" } },
811d4cf4
AZ		 1530
1531 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1532 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1533 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1534
023e77f8
AJ		 1535 { INDEX_op_brcond_i32, { "r", "rI" } },
1536 { INDEX_op_setcond_i32, { "r", "r", "rI" } },
811d4cf4
AZ		 1537
1538 /* TODO: "r", "r", "r", "r", "ri", "ri" */
1539 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1540 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1541 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
e0404769 1542 { INDEX_op_setcond2_i32, { "r", "r", "r", "r", "r" } },
811d4cf4 1543
26c5d372
AJ		 1544#if TARGET_LONG_BITS == 32
1545 { INDEX_op_qemu_ld8u, { "r", "x" } },
1546 { INDEX_op_qemu_ld8s, { "r", "x" } },
1547 { INDEX_op_qemu_ld16u, { "r", "x" } },
1548 { INDEX_op_qemu_ld16s, { "r", "x" } },
1584c845 1549 { INDEX_op_qemu_ld32, { "r", "x" } },
26c5d372
AJ		 1550 { INDEX_op_qemu_ld64, { "d", "r", "x" } },
1551
1552 { INDEX_op_qemu_st8, { "x", "x" } },
1553 { INDEX_op_qemu_st16, { "x", "x" } },
1554 { INDEX_op_qemu_st32, { "x", "x" } },
1555 { INDEX_op_qemu_st64, { "x", "D", "x" } },
1556#else
811d4cf4
AZ		 1557 { INDEX_op_qemu_ld8u, { "r", "x", "X" } },
1558 { INDEX_op_qemu_ld8s, { "r", "x", "X" } },
1559 { INDEX_op_qemu_ld16u, { "r", "x", "X" } },
1560 { INDEX_op_qemu_ld16s, { "r", "x", "X" } },
86feb1c8 1561 { INDEX_op_qemu_ld32, { "r", "x", "X" } },
d0660ed4 1562 { INDEX_op_qemu_ld64, { "d", "r", "x", "X" } },
811d4cf4 1563
3979144c
PB		 1564 { INDEX_op_qemu_st8, { "x", "x", "X" } },
1565 { INDEX_op_qemu_st16, { "x", "x", "X" } },
1566 { INDEX_op_qemu_st32, { "x", "x", "X" } },
1567 { INDEX_op_qemu_st64, { "x", "D", "x", "X" } },
26c5d372 1568#endif
811d4cf4
AZ		 1569
1570 { INDEX_op_ext8s_i32, { "r", "r" } },
1571 { INDEX_op_ext16s_i32, { "r", "r" } },
1572
1573 { -1 },
1574};
1575
1576void tcg_target_init(TCGContext *s)
1577{
20cb400d 1578#if !defined(CONFIG_USER_ONLY)
811d4cf4
AZ		 1579 /* fail safe */
1580 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1581 tcg_abort();
20cb400d 1582#endif
811d4cf4 1583
e4a7d5e8 1584 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
811d4cf4 1585 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
e4a7d5e8
AJ		 1586 (1 << TCG_REG_R0) |
1587 (1 << TCG_REG_R1) |
1588 (1 << TCG_REG_R2) |
1589 (1 << TCG_REG_R3) |
1590 (1 << TCG_REG_R12) |
1591 (1 << TCG_REG_R14));
811d4cf4
AZ		 1592
1593 tcg_regset_clear(s->reserved_regs);
811d4cf4
AZ		 1594 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
1595 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R8);
e4a7d5e8 1596 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
811d4cf4
AZ		 1597
1598 tcg_add_target_add_op_defs(arm_op_defs);
1599}
1600
1601static inline void tcg_out_ld(TCGContext *s, TCGType type, int arg,
1602 int arg1, tcg_target_long arg2)
1603{
1604 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
1605}
1606
1607static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
1608 int arg1, tcg_target_long arg2)
1609{
1610 tcg_out_st32(s, COND_AL, arg, arg1, arg2);
1611}
1612
2d69f359 1613static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
811d4cf4
AZ		 1614{
1615 if (val > 0)
1616 if (val < 0x100)
1617 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, reg, reg, val);
1618 else
1619 tcg_abort();
1620 else if (val < 0) {
1621 if (val > -0x100)
1622 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, reg, reg, -val);
1623 else
1624 tcg_abort();
1625 }
1626}
1627
1628static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
1629{
1630 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0));
1631}
1632
1633static inline void tcg_out_movi(TCGContext *s, TCGType type,
1634 int ret, tcg_target_long arg)
1635{
1636 tcg_out_movi32(s, COND_AL, ret, arg);
1637}
1638
1639void tcg_target_qemu_prologue(TCGContext *s)
1640{
9e97d8e9
AJ		 1641 /* There is no need to save r7, it is used to store the address
1642 of the env structure and is not modified by GCC. */
4e17eae9 1643
9e97d8e9
AJ		 1644 /* stmdb sp!, { r4 - r6, r8 - r11, lr } */
1645 tcg_out32(s, (COND_AL << 28) | 0x092d4f70);
811d4cf4
AZ		 1646
1647 tcg_out_bx(s, COND_AL, TCG_REG_R0);
1648 tb_ret_addr = s->code_ptr;
1649
9e97d8e9
AJ		 1650 /* ldmia sp!, { r4 - r6, r8 - r11, pc } */
1651 tcg_out32(s, (COND_AL << 28) | 0x08bd8f70);
811d4cf4 1652}
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