[qemu.git] / target-i386 / machine.c

#include "hw/hw.h"
#include "hw/boards.h"
#include "hw/pc.h"
#include "hw/isa.h"

#include "cpu.h"
#include "kvm.h"

static const VMStateDescription vmstate_segment = {
    .name = "segment",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT32(selector, SegmentCache),
        VMSTATE_UINTTL(base, SegmentCache),
        VMSTATE_UINT32(limit, SegmentCache),
        VMSTATE_UINT32(flags, SegmentCache),
        VMSTATE_END_OF_LIST()
    }
};

#define VMSTATE_SEGMENT(_field, _state) {                            \
    .name       = (stringify(_field)),                               \
    .size       = sizeof(SegmentCache),                              \
    .vmsd       = &vmstate_segment,                                  \
    .flags      = VMS_STRUCT,                                        \
    .offset     = offsetof(_state, _field)                           \
            + type_check(SegmentCache,typeof_field(_state, _field))  \
}

#define VMSTATE_SEGMENT_ARRAY(_field, _state, _n)                    \
    VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache)

static const VMStateDescription vmstate_xmm_reg = {
    .name = "xmm_reg",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT64(XMM_Q(0), XMMReg),
        VMSTATE_UINT64(XMM_Q(1), XMMReg),
        VMSTATE_END_OF_LIST()
    }
};

#define VMSTATE_XMM_REGS(_field, _state, _n)                         \
    VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_xmm_reg, XMMReg)

/* YMMH format is the same as XMM */
static const VMStateDescription vmstate_ymmh_reg = {
    .name = "ymmh_reg",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT64(XMM_Q(0), XMMReg),
        VMSTATE_UINT64(XMM_Q(1), XMMReg),
        VMSTATE_END_OF_LIST()
    }
};

#define VMSTATE_YMMH_REGS_VARS(_field, _state, _n, _v)                         \
    VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_ymmh_reg, XMMReg)

static const VMStateDescription vmstate_mtrr_var = {
    .name = "mtrr_var",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT64(base, MTRRVar),
        VMSTATE_UINT64(mask, MTRRVar),
        VMSTATE_END_OF_LIST()
    }
};

#define VMSTATE_MTRR_VARS(_field, _state, _n, _v)                    \
    VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar)

static void put_fpreg_error(QEMUFile *f, void *opaque, size_t size)
{
    fprintf(stderr, "call put_fpreg() with invalid arguments\n");
    exit(0);
}

/* XXX: add that in a FPU generic layer */
union x86_longdouble {
    uint64_t mant;
    uint16_t exp;
};

#define MANTD1(fp)	(fp & ((1LL << 52) - 1))
#define EXPBIAS1 1023
#define EXPD1(fp)	((fp >> 52) & 0x7FF)
#define SIGND1(fp)	((fp >> 32) & 0x80000000)

static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
{
    int e;
    /* mantissa */
    p->mant = (MANTD1(temp) << 11) | (1LL << 63);
    /* exponent + sign */
    e = EXPD1(temp) - EXPBIAS1 + 16383;
    e |= SIGND1(temp) >> 16;
    p->exp = e;
}

static int get_fpreg(QEMUFile *f, void *opaque, size_t size)
{
    FPReg *fp_reg = opaque;
    uint64_t mant;
    uint16_t exp;

    qemu_get_be64s(f, &mant);
    qemu_get_be16s(f, &exp);
    fp_reg->d = cpu_set_fp80(mant, exp);
    return 0;
}

static void put_fpreg(QEMUFile *f, void *opaque, size_t size)
{
    FPReg *fp_reg = opaque;
    uint64_t mant;
    uint16_t exp;
    /* we save the real CPU data (in case of MMX usage only 'mant'
       contains the MMX register */
    cpu_get_fp80(&mant, &exp, fp_reg->d);
    qemu_put_be64s(f, &mant);
    qemu_put_be16s(f, &exp);
}

static const VMStateInfo vmstate_fpreg = {
    .name = "fpreg",
    .get  = get_fpreg,
    .put  = put_fpreg,
};

static int get_fpreg_1_mmx(QEMUFile *f, void *opaque, size_t size)
{
    union x86_longdouble *p = opaque;
    uint64_t mant;

    qemu_get_be64s(f, &mant);
    p->mant = mant;
    p->exp = 0xffff;
    return 0;
}

static const VMStateInfo vmstate_fpreg_1_mmx = {
    .name = "fpreg_1_mmx",
    .get  = get_fpreg_1_mmx,
    .put  = put_fpreg_error,
};

static int get_fpreg_1_no_mmx(QEMUFile *f, void *opaque, size_t size)
{
    union x86_longdouble *p = opaque;
    uint64_t mant;

    qemu_get_be64s(f, &mant);
    fp64_to_fp80(p, mant);
    return 0;
}

static const VMStateInfo vmstate_fpreg_1_no_mmx = {
    .name = "fpreg_1_no_mmx",
    .get  = get_fpreg_1_no_mmx,
    .put  = put_fpreg_error,
};

static bool fpregs_is_0(void *opaque, int version_id)
{
    CPUX86State *env = opaque;

    return (env->fpregs_format_vmstate == 0);
}

static bool fpregs_is_1_mmx(void *opaque, int version_id)
{
    CPUX86State *env = opaque;
    int guess_mmx;

    guess_mmx = ((env->fptag_vmstate == 0xff) &&
                 (env->fpus_vmstate & 0x3800) == 0);
    return (guess_mmx && (env->fpregs_format_vmstate == 1));
}

static bool fpregs_is_1_no_mmx(void *opaque, int version_id)
{
    CPUX86State *env = opaque;
    int guess_mmx;

    guess_mmx = ((env->fptag_vmstate == 0xff) &&
                 (env->fpus_vmstate & 0x3800) == 0);
    return (!guess_mmx && (env->fpregs_format_vmstate == 1));
}

#define VMSTATE_FP_REGS(_field, _state, _n)                               \
    VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0, vmstate_fpreg, FPReg), \
    VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_mmx, vmstate_fpreg_1_mmx, FPReg), \
    VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_no_mmx, vmstate_fpreg_1_no_mmx, FPReg)

static bool version_is_5(void *opaque, int version_id)
{
    return version_id == 5;
}

#ifdef TARGET_X86_64
static bool less_than_7(void *opaque, int version_id)
{
    return version_id < 7;
}

static int get_uint64_as_uint32(QEMUFile *f, void *pv, size_t size)
{
    uint64_t *v = pv;
    *v = qemu_get_be32(f);
    return 0;
}

static void put_uint64_as_uint32(QEMUFile *f, void *pv, size_t size)
{
    uint64_t *v = pv;
    qemu_put_be32(f, *v);
}

static const VMStateInfo vmstate_hack_uint64_as_uint32 = {
    .name = "uint64_as_uint32",
    .get  = get_uint64_as_uint32,
    .put  = put_uint64_as_uint32,
};

#define VMSTATE_HACK_UINT32(_f, _s, _t)                                  \
    VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint64_as_uint32, uint64_t)
#endif

static void cpu_pre_save(void *opaque)
{
    CPUX86State *env = opaque;
    int i;

    /* FPU */
    env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
    env->fptag_vmstate = 0;
    for(i = 0; i < 8; i++) {
        env->fptag_vmstate |= ((!env->fptags[i]) << i);
    }

    env->fpregs_format_vmstate = 0;
}

static int cpu_post_load(void *opaque, int version_id)
{
    CPUX86State *env = opaque;
    int i;

    /* XXX: restore FPU round state */
    env->fpstt = (env->fpus_vmstate >> 11) & 7;
    env->fpus = env->fpus_vmstate & ~0x3800;
    env->fptag_vmstate ^= 0xff;
    for(i = 0; i < 8; i++) {
        env->fptags[i] = (env->fptag_vmstate >> i) & 1;
    }

    cpu_breakpoint_remove_all(env, BP_CPU);
    cpu_watchpoint_remove_all(env, BP_CPU);
    for (i = 0; i < 4; i++)
        hw_breakpoint_insert(env, i);

    tlb_flush(env, 1);
    return 0;
}

static bool async_pf_msr_needed(void *opaque)
{
    CPUX86State *cpu = opaque;

    return cpu->async_pf_en_msr != 0;
}

static bool pv_eoi_msr_needed(void *opaque)
{
    CPUX86State *cpu = opaque;

    return cpu->pv_eoi_en_msr != 0;
}

static const VMStateDescription vmstate_async_pf_msr = {
    .name = "cpu/async_pf_msr",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT64(async_pf_en_msr, CPUX86State),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pv_eoi_msr = {
    .name = "cpu/async_pv_eoi_msr",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT64(pv_eoi_en_msr, CPUX86State),
        VMSTATE_END_OF_LIST()
    }
};

static bool fpop_ip_dp_needed(void *opaque)
{
    CPUX86State *env = opaque;

    return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0;
}

static const VMStateDescription vmstate_fpop_ip_dp = {
    .name = "cpu/fpop_ip_dp",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT16(fpop, CPUX86State),
        VMSTATE_UINT64(fpip, CPUX86State),
        VMSTATE_UINT64(fpdp, CPUX86State),
        VMSTATE_END_OF_LIST()
    }
};

static bool tscdeadline_needed(void *opaque)
{
    CPUX86State *env = opaque;

    return env->tsc_deadline != 0;
}

static const VMStateDescription vmstate_msr_tscdeadline = {
    .name = "cpu/msr_tscdeadline",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT64(tsc_deadline, CPUX86State),
        VMSTATE_END_OF_LIST()
    }
};

static bool misc_enable_needed(void *opaque)
{
    CPUX86State *env = opaque;

    return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;
}

static const VMStateDescription vmstate_msr_ia32_misc_enable = {
    .name = "cpu/msr_ia32_misc_enable",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT64(msr_ia32_misc_enable, CPUX86State),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_cpu = {
    .name = "cpu",
    .version_id = CPU_SAVE_VERSION,
    .minimum_version_id = 3,
    .minimum_version_id_old = 3,
    .pre_save = cpu_pre_save,
    .post_load = cpu_post_load,
    .fields      = (VMStateField []) {
        VMSTATE_UINTTL_ARRAY(regs, CPUX86State, CPU_NB_REGS),
        VMSTATE_UINTTL(eip, CPUX86State),
        VMSTATE_UINTTL(eflags, CPUX86State),
        VMSTATE_UINT32(hflags, CPUX86State),
        /* FPU */
        VMSTATE_UINT16(fpuc, CPUX86State),
        VMSTATE_UINT16(fpus_vmstate, CPUX86State),
        VMSTATE_UINT16(fptag_vmstate, CPUX86State),
        VMSTATE_UINT16(fpregs_format_vmstate, CPUX86State),
        VMSTATE_FP_REGS(fpregs, CPUX86State, 8),

        VMSTATE_SEGMENT_ARRAY(segs, CPUX86State, 6),
        VMSTATE_SEGMENT(ldt, CPUX86State),
        VMSTATE_SEGMENT(tr, CPUX86State),
        VMSTATE_SEGMENT(gdt, CPUX86State),
        VMSTATE_SEGMENT(idt, CPUX86State),

        VMSTATE_UINT32(sysenter_cs, CPUX86State),
#ifdef TARGET_X86_64
        /* Hack: In v7 size changed from 32 to 64 bits on x86_64 */
        VMSTATE_HACK_UINT32(sysenter_esp, CPUX86State, less_than_7),
        VMSTATE_HACK_UINT32(sysenter_eip, CPUX86State, less_than_7),
        VMSTATE_UINTTL_V(sysenter_esp, CPUX86State, 7),
        VMSTATE_UINTTL_V(sysenter_eip, CPUX86State, 7),
#else
        VMSTATE_UINTTL(sysenter_esp, CPUX86State),
        VMSTATE_UINTTL(sysenter_eip, CPUX86State),
#endif

        VMSTATE_UINTTL(cr[0], CPUX86State),
        VMSTATE_UINTTL(cr[2], CPUX86State),
        VMSTATE_UINTTL(cr[3], CPUX86State),
        VMSTATE_UINTTL(cr[4], CPUX86State),
        VMSTATE_UINTTL_ARRAY(dr, CPUX86State, 8),
        /* MMU */
        VMSTATE_INT32(a20_mask, CPUX86State),
        /* XMM */
        VMSTATE_UINT32(mxcsr, CPUX86State),
        VMSTATE_XMM_REGS(xmm_regs, CPUX86State, CPU_NB_REGS),

#ifdef TARGET_X86_64
        VMSTATE_UINT64(efer, CPUX86State),
        VMSTATE_UINT64(star, CPUX86State),
        VMSTATE_UINT64(lstar, CPUX86State),
        VMSTATE_UINT64(cstar, CPUX86State),
        VMSTATE_UINT64(fmask, CPUX86State),
        VMSTATE_UINT64(kernelgsbase, CPUX86State),
#endif
        VMSTATE_UINT32_V(smbase, CPUX86State, 4),

        VMSTATE_UINT64_V(pat, CPUX86State, 5),
        VMSTATE_UINT32_V(hflags2, CPUX86State, 5),

        VMSTATE_UINT32_TEST(halted, CPUX86State, version_is_5),
        VMSTATE_UINT64_V(vm_hsave, CPUX86State, 5),
        VMSTATE_UINT64_V(vm_vmcb, CPUX86State, 5),
        VMSTATE_UINT64_V(tsc_offset, CPUX86State, 5),
        VMSTATE_UINT64_V(intercept, CPUX86State, 5),
        VMSTATE_UINT16_V(intercept_cr_read, CPUX86State, 5),
        VMSTATE_UINT16_V(intercept_cr_write, CPUX86State, 5),
        VMSTATE_UINT16_V(intercept_dr_read, CPUX86State, 5),
        VMSTATE_UINT16_V(intercept_dr_write, CPUX86State, 5),
        VMSTATE_UINT32_V(intercept_exceptions, CPUX86State, 5),
        VMSTATE_UINT8_V(v_tpr, CPUX86State, 5),
        /* MTRRs */
        VMSTATE_UINT64_ARRAY_V(mtrr_fixed, CPUX86State, 11, 8),
        VMSTATE_UINT64_V(mtrr_deftype, CPUX86State, 8),
        VMSTATE_MTRR_VARS(mtrr_var, CPUX86State, 8, 8),
        /* KVM-related states */
        VMSTATE_INT32_V(interrupt_injected, CPUX86State, 9),
        VMSTATE_UINT32_V(mp_state, CPUX86State, 9),
        VMSTATE_UINT64_V(tsc, CPUX86State, 9),
        VMSTATE_INT32_V(exception_injected, CPUX86State, 11),
        VMSTATE_UINT8_V(soft_interrupt, CPUX86State, 11),
        VMSTATE_UINT8_V(nmi_injected, CPUX86State, 11),
        VMSTATE_UINT8_V(nmi_pending, CPUX86State, 11),
        VMSTATE_UINT8_V(has_error_code, CPUX86State, 11),
        VMSTATE_UINT32_V(sipi_vector, CPUX86State, 11),
        /* MCE */
        VMSTATE_UINT64_V(mcg_cap, CPUX86State, 10),
        VMSTATE_UINT64_V(mcg_status, CPUX86State, 10),
        VMSTATE_UINT64_V(mcg_ctl, CPUX86State, 10),
        VMSTATE_UINT64_ARRAY_V(mce_banks, CPUX86State, MCE_BANKS_DEF *4, 10),
        /* rdtscp */
        VMSTATE_UINT64_V(tsc_aux, CPUX86State, 11),
        /* KVM pvclock msr */
        VMSTATE_UINT64_V(system_time_msr, CPUX86State, 11),
        VMSTATE_UINT64_V(wall_clock_msr, CPUX86State, 11),
        /* XSAVE related fields */
        VMSTATE_UINT64_V(xcr0, CPUX86State, 12),
        VMSTATE_UINT64_V(xstate_bv, CPUX86State, 12),
        VMSTATE_YMMH_REGS_VARS(ymmh_regs, CPUX86State, CPU_NB_REGS, 12),
        VMSTATE_END_OF_LIST()
        /* The above list is not sorted /wrt version numbers, watch out! */
    },
    .subsections = (VMStateSubsection []) {
        {
            .vmsd = &vmstate_async_pf_msr,
            .needed = async_pf_msr_needed,
        } , {
            .vmsd = &vmstate_pv_eoi_msr,
            .needed = pv_eoi_msr_needed,
        } , {
            .vmsd = &vmstate_fpop_ip_dp,
            .needed = fpop_ip_dp_needed,
        }, {
            .vmsd = &vmstate_msr_tscdeadline,
            .needed = tscdeadline_needed,
        }, {
            .vmsd = &vmstate_msr_ia32_misc_enable,
            .needed = misc_enable_needed,
        } , {
            /* empty */
        }
    }
};

void cpu_save(QEMUFile *f, void *opaque)
{
    vmstate_save_state(f, &vmstate_cpu, opaque);
}

int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
    return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
}
Commit	Line	Data
8dd3dca3 AJ	1	#include "hw/hw.h"
	2	#include "hw/boards.h"
	3	#include "hw/pc.h"
	4	#include "hw/isa.h"
	5
2b41f10e	6	#include "cpu.h"
b0a46a33	7	#include "kvm.h"
8dd3dca3	8
66e6d55b JQ	9	static const VMStateDescription vmstate_segment = {
	10	.name = "segment",
	11	.version_id = 1,
	12	.minimum_version_id = 1,
	13	.minimum_version_id_old = 1,
	14	.fields = (VMStateField []) {
	15	VMSTATE_UINT32(selector, SegmentCache),
	16	VMSTATE_UINTTL(base, SegmentCache),
	17	VMSTATE_UINT32(limit, SegmentCache),
	18	VMSTATE_UINT32(flags, SegmentCache),
	19	VMSTATE_END_OF_LIST()
	20	}
	21	};
	22
0cb892aa JQ	23	#define VMSTATE_SEGMENT(_field, _state) { \
	24	.name = (stringify(_field)), \
	25	.size = sizeof(SegmentCache), \
	26	.vmsd = &vmstate_segment, \
	27	.flags = VMS_STRUCT, \
	28	.offset = offsetof(_state, _field) \
	29	+ type_check(SegmentCache,typeof_field(_state, _field)) \
8dd3dca3 AJ	30	}
8dd3dca3 AJ	31
0cb892aa JQ	32	#define VMSTATE_SEGMENT_ARRAY(_field, _state, _n) \
0cb892aa JQ	33	VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache)
8dd3dca3	34
fc3b0aa2 JQ	35	static const VMStateDescription vmstate_xmm_reg = {
	36	.name = "xmm_reg",
	37	.version_id = 1,
	38	.minimum_version_id = 1,
	39	.minimum_version_id_old = 1,
	40	.fields = (VMStateField []) {
	41	VMSTATE_UINT64(XMM_Q(0), XMMReg),
	42	VMSTATE_UINT64(XMM_Q(1), XMMReg),
	43	VMSTATE_END_OF_LIST()
	44	}
	45	};
	46
0cb892aa JQ	47	#define VMSTATE_XMM_REGS(_field, _state, _n) \
0cb892aa JQ	48	VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_xmm_reg, XMMReg)
fc3b0aa2	49
f1665b21 SY	50	/* YMMH format is the same as XMM */
	51	static const VMStateDescription vmstate_ymmh_reg = {
	52	.name = "ymmh_reg",
	53	.version_id = 1,
	54	.minimum_version_id = 1,
	55	.minimum_version_id_old = 1,
	56	.fields = (VMStateField []) {
	57	VMSTATE_UINT64(XMM_Q(0), XMMReg),
	58	VMSTATE_UINT64(XMM_Q(1), XMMReg),
	59	VMSTATE_END_OF_LIST()
	60	}
	61	};
	62
	63	#define VMSTATE_YMMH_REGS_VARS(_field, _state, _n, _v) \
	64	VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_ymmh_reg, XMMReg)
	65
216c07c3 JQ	66	static const VMStateDescription vmstate_mtrr_var = {
	67	.name = "mtrr_var",
	68	.version_id = 1,
	69	.minimum_version_id = 1,
	70	.minimum_version_id_old = 1,
	71	.fields = (VMStateField []) {
	72	VMSTATE_UINT64(base, MTRRVar),
	73	VMSTATE_UINT64(mask, MTRRVar),
	74	VMSTATE_END_OF_LIST()
	75	}
	76	};
	77
0cb892aa JQ	78	#define VMSTATE_MTRR_VARS(_field, _state, _n, _v) \
0cb892aa JQ	79	VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar)
216c07c3	80
0cb892aa	81	static void put_fpreg_error(QEMUFile f, void opaque, size_t size)
216c07c3	82	{
0cb892aa JQ	83	fprintf(stderr, "call put_fpreg() with invalid arguments\n");
0cb892aa JQ	84	exit(0);
216c07c3 JQ	85	}
216c07c3 JQ	86
3c8ce630 JQ	87	/* XXX: add that in a FPU generic layer */
	88	union x86_longdouble {
	89	uint64_t mant;
	90	uint16_t exp;
	91	};
	92
	93	#define MANTD1(fp) (fp & ((1LL << 52) - 1))
	94	#define EXPBIAS1 1023
	95	#define EXPD1(fp) ((fp >> 52) & 0x7FF)
	96	#define SIGND1(fp) ((fp >> 32) & 0x80000000)
	97
	98	static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
	99	{
	100	int e;
	101	/* mantissa */
	102	p->mant = (MANTD1(temp) << 11) \| (1LL << 63);
	103	/* exponent + sign */
	104	e = EXPD1(temp) - EXPBIAS1 + 16383;
	105	e \|= SIGND1(temp) >> 16;
	106	p->exp = e;
	107	}
	108
	109	static int get_fpreg(QEMUFile f, void opaque, size_t size)
	110	{
	111	FPReg *fp_reg = opaque;
	112	uint64_t mant;
	113	uint16_t exp;
	114
	115	qemu_get_be64s(f, &mant);
	116	qemu_get_be16s(f, &exp);
	117	fp_reg->d = cpu_set_fp80(mant, exp);
	118	return 0;
	119	}
	120
	121	static void put_fpreg(QEMUFile f, void opaque, size_t size)
	122	{
	123	FPReg *fp_reg = opaque;
	124	uint64_t mant;
	125	uint16_t exp;
	126	/* we save the real CPU data (in case of MMX usage only 'mant'
	127	contains the MMX register */
	128	cpu_get_fp80(&mant, &exp, fp_reg->d);
	129	qemu_put_be64s(f, &mant);
	130	qemu_put_be16s(f, &exp);
	131	}
	132
976b2037	133	static const VMStateInfo vmstate_fpreg = {
0cb892aa JQ	134	.name = "fpreg",
	135	.get = get_fpreg,
	136	.put = put_fpreg,
	137	};
	138
3c8ce630 JQ	139	static int get_fpreg_1_mmx(QEMUFile f, void opaque, size_t size)
	140	{
	141	union x86_longdouble *p = opaque;
	142	uint64_t mant;
	143
	144	qemu_get_be64s(f, &mant);
	145	p->mant = mant;
	146	p->exp = 0xffff;
	147	return 0;
	148	}
	149
976b2037	150	static const VMStateInfo vmstate_fpreg_1_mmx = {
0cb892aa JQ	151	.name = "fpreg_1_mmx",
	152	.get = get_fpreg_1_mmx,
	153	.put = put_fpreg_error,
	154	};
	155
3c8ce630 JQ	156	static int get_fpreg_1_no_mmx(QEMUFile f, void opaque, size_t size)
	157	{
	158	union x86_longdouble *p = opaque;
	159	uint64_t mant;
	160
	161	qemu_get_be64s(f, &mant);
	162	fp64_to_fp80(p, mant);
	163	return 0;
	164	}
	165
976b2037	166	static const VMStateInfo vmstate_fpreg_1_no_mmx = {
0cb892aa JQ	167	.name = "fpreg_1_no_mmx",
	168	.get = get_fpreg_1_no_mmx,
	169	.put = put_fpreg_error,
	170	};
	171
	172	static bool fpregs_is_0(void *opaque, int version_id)
	173	{
317ac620	174	CPUX86State *env = opaque;
0cb892aa JQ	175
	176	return (env->fpregs_format_vmstate == 0);
	177	}
	178
	179	static bool fpregs_is_1_mmx(void *opaque, int version_id)
	180	{
317ac620	181	CPUX86State *env = opaque;
0cb892aa JQ	182	int guess_mmx;
	183
	184	guess_mmx = ((env->fptag_vmstate == 0xff) &&
	185	(env->fpus_vmstate & 0x3800) == 0);
	186	return (guess_mmx && (env->fpregs_format_vmstate == 1));
	187	}
	188
	189	static bool fpregs_is_1_no_mmx(void *opaque, int version_id)
	190	{
317ac620	191	CPUX86State *env = opaque;
0cb892aa JQ	192	int guess_mmx;
	193
	194	guess_mmx = ((env->fptag_vmstate == 0xff) &&
	195	(env->fpus_vmstate & 0x3800) == 0);
	196	return (!guess_mmx && (env->fpregs_format_vmstate == 1));
	197	}
	198
	199	#define VMSTATE_FP_REGS(_field, _state, _n) \
	200	VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0, vmstate_fpreg, FPReg), \
	201	VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_mmx, vmstate_fpreg_1_mmx, FPReg), \
	202	VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_no_mmx, vmstate_fpreg_1_no_mmx, FPReg)
	203
0cb892aa JQ	204	static bool version_is_5(void *opaque, int version_id)
	205	{
	206	return version_id == 5;
	207	}
	208
	209	#ifdef TARGET_X86_64
	210	static bool less_than_7(void *opaque, int version_id)
	211	{
	212	return version_id < 7;
	213	}
	214
	215	static int get_uint64_as_uint32(QEMUFile f, void pv, size_t size)
	216	{
	217	uint64_t *v = pv;
	218	*v = qemu_get_be32(f);
	219	return 0;
	220	}
	221
	222	static void put_uint64_as_uint32(QEMUFile f, void pv, size_t size)
	223	{
	224	uint64_t *v = pv;
	225	qemu_put_be32(f, *v);
	226	}
	227
976b2037	228	static const VMStateInfo vmstate_hack_uint64_as_uint32 = {
0cb892aa JQ	229	.name = "uint64_as_uint32",
	230	.get = get_uint64_as_uint32,
	231	.put = put_uint64_as_uint32,
	232	};
	233
	234	#define VMSTATE_HACK_UINT32(_f, _s, _t) \
d4829d49	235	VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint64_as_uint32, uint64_t)
0cb892aa JQ	236	#endif
0cb892aa JQ	237
c4c38c8c	238	static void cpu_pre_save(void *opaque)
8dd3dca3	239	{
317ac620	240	CPUX86State *env = opaque;
0e607a80	241	int i;
8dd3dca3	242
8dd3dca3	243	/* FPU */
67b8f419	244	env->fpus_vmstate = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
cdc0c58f	245	env->fptag_vmstate = 0;
8dd3dca3	246	for(i = 0; i < 8; i++) {
cdc0c58f	247	env->fptag_vmstate \|= ((!env->fptags[i]) << i);
8dd3dca3 AJ	248	}
8dd3dca3 AJ	249
60a902f1	250	env->fpregs_format_vmstate = 0;
c4c38c8c JQ	251	}
c4c38c8c JQ	252
468f6581 JQ	253	static int cpu_post_load(void *opaque, int version_id)
468f6581 JQ	254	{
317ac620	255	CPUX86State *env = opaque;
468f6581 JQ	256	int i;
	257
	258	/* XXX: restore FPU round state */
	259	env->fpstt = (env->fpus_vmstate >> 11) & 7;
	260	env->fpus = env->fpus_vmstate & ~0x3800;
	261	env->fptag_vmstate ^= 0xff;
	262	for(i = 0; i < 8; i++) {
	263	env->fptags[i] = (env->fptag_vmstate >> i) & 1;
	264	}
	265
	266	cpu_breakpoint_remove_all(env, BP_CPU);
	267	cpu_watchpoint_remove_all(env, BP_CPU);
	268	for (i = 0; i < 4; i++)
	269	hw_breakpoint_insert(env, i);
	270
1e7fbc6d JQ	271	tlb_flush(env, 1);
1e7fbc6d JQ	272	return 0;
468f6581 JQ	273	}
468f6581 JQ	274
f6584ee2 GN	275	static bool async_pf_msr_needed(void *opaque)
f6584ee2 GN	276	{
317ac620	277	CPUX86State *cpu = opaque;
f6584ee2 GN	278
	279	return cpu->async_pf_en_msr != 0;
	280	}
	281
bc9a839d MT	282	static bool pv_eoi_msr_needed(void *opaque)
	283	{
	284	CPUX86State *cpu = opaque;
	285
	286	return cpu->pv_eoi_en_msr != 0;
	287	}
	288
f6584ee2 GN	289	static const VMStateDescription vmstate_async_pf_msr = {
	290	.name = "cpu/async_pf_msr",
	291	.version_id = 1,
	292	.minimum_version_id = 1,
	293	.minimum_version_id_old = 1,
	294	.fields = (VMStateField []) {
317ac620	295	VMSTATE_UINT64(async_pf_en_msr, CPUX86State),
f6584ee2 GN	296	VMSTATE_END_OF_LIST()
	297	}
	298	};
	299
bc9a839d MT	300	static const VMStateDescription vmstate_pv_eoi_msr = {
	301	.name = "cpu/async_pv_eoi_msr",
	302	.version_id = 1,
	303	.minimum_version_id = 1,
	304	.minimum_version_id_old = 1,
	305	.fields = (VMStateField []) {
	306	VMSTATE_UINT64(pv_eoi_en_msr, CPUX86State),
	307	VMSTATE_END_OF_LIST()
	308	}
	309	};
	310
42cc8fa6 JK	311	static bool fpop_ip_dp_needed(void *opaque)
42cc8fa6 JK	312	{
317ac620	313	CPUX86State *env = opaque;
42cc8fa6 JK	314
	315	return env->fpop != 0 \|\| env->fpip != 0 \|\| env->fpdp != 0;
	316	}
	317
	318	static const VMStateDescription vmstate_fpop_ip_dp = {
	319	.name = "cpu/fpop_ip_dp",
	320	.version_id = 1,
	321	.minimum_version_id = 1,
	322	.minimum_version_id_old = 1,
	323	.fields = (VMStateField []) {
317ac620 AF	324	VMSTATE_UINT16(fpop, CPUX86State),
	325	VMSTATE_UINT64(fpip, CPUX86State),
	326	VMSTATE_UINT64(fpdp, CPUX86State),
42cc8fa6 JK	327	VMSTATE_END_OF_LIST()
	328	}
	329	};
	330
aa82ba54 LJ	331	static bool tscdeadline_needed(void *opaque)
aa82ba54 LJ	332	{
317ac620	333	CPUX86State *env = opaque;
aa82ba54 LJ	334
	335	return env->tsc_deadline != 0;
	336	}
	337
	338	static const VMStateDescription vmstate_msr_tscdeadline = {
	339	.name = "cpu/msr_tscdeadline",
	340	.version_id = 1,
	341	.minimum_version_id = 1,
	342	.minimum_version_id_old = 1,
	343	.fields = (VMStateField []) {
317ac620	344	VMSTATE_UINT64(tsc_deadline, CPUX86State),
aa82ba54 LJ	345	VMSTATE_END_OF_LIST()
	346	}
	347	};
	348
21e87c46 AK	349	static bool misc_enable_needed(void *opaque)
21e87c46 AK	350	{
317ac620	351	CPUX86State *env = opaque;
21e87c46 AK	352
	353	return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;
	354	}
	355
	356	static const VMStateDescription vmstate_msr_ia32_misc_enable = {
	357	.name = "cpu/msr_ia32_misc_enable",
	358	.version_id = 1,
	359	.minimum_version_id = 1,
	360	.minimum_version_id_old = 1,
	361	.fields = (VMStateField []) {
317ac620	362	VMSTATE_UINT64(msr_ia32_misc_enable, CPUX86State),
21e87c46 AK	363	VMSTATE_END_OF_LIST()
	364	}
	365	};
	366
976b2037	367	static const VMStateDescription vmstate_cpu = {
0cb892aa JQ	368	.name = "cpu",
	369	.version_id = CPU_SAVE_VERSION,
	370	.minimum_version_id = 3,
	371	.minimum_version_id_old = 3,
	372	.pre_save = cpu_pre_save,
0cb892aa JQ	373	.post_load = cpu_post_load,
0cb892aa JQ	374	.fields = (VMStateField []) {
317ac620 AF	375	VMSTATE_UINTTL_ARRAY(regs, CPUX86State, CPU_NB_REGS),
	376	VMSTATE_UINTTL(eip, CPUX86State),
	377	VMSTATE_UINTTL(eflags, CPUX86State),
	378	VMSTATE_UINT32(hflags, CPUX86State),
0cb892aa	379	/* FPU */
317ac620 AF	380	VMSTATE_UINT16(fpuc, CPUX86State),
	381	VMSTATE_UINT16(fpus_vmstate, CPUX86State),
	382	VMSTATE_UINT16(fptag_vmstate, CPUX86State),
	383	VMSTATE_UINT16(fpregs_format_vmstate, CPUX86State),
	384	VMSTATE_FP_REGS(fpregs, CPUX86State, 8),
	385
	386	VMSTATE_SEGMENT_ARRAY(segs, CPUX86State, 6),
	387	VMSTATE_SEGMENT(ldt, CPUX86State),
	388	VMSTATE_SEGMENT(tr, CPUX86State),
	389	VMSTATE_SEGMENT(gdt, CPUX86State),
	390	VMSTATE_SEGMENT(idt, CPUX86State),
	391
	392	VMSTATE_UINT32(sysenter_cs, CPUX86State),
0cb892aa JQ	393	#ifdef TARGET_X86_64
0cb892aa JQ	394	/* Hack: In v7 size changed from 32 to 64 bits on x86_64 */
317ac620 AF	395	VMSTATE_HACK_UINT32(sysenter_esp, CPUX86State, less_than_7),
	396	VMSTATE_HACK_UINT32(sysenter_eip, CPUX86State, less_than_7),
	397	VMSTATE_UINTTL_V(sysenter_esp, CPUX86State, 7),
	398	VMSTATE_UINTTL_V(sysenter_eip, CPUX86State, 7),
8dd3dca3	399	#else
317ac620 AF	400	VMSTATE_UINTTL(sysenter_esp, CPUX86State),
317ac620 AF	401	VMSTATE_UINTTL(sysenter_eip, CPUX86State),
3c8ce630	402	#endif
8dd3dca3	403
317ac620 AF	404	VMSTATE_UINTTL(cr[0], CPUX86State),
	405	VMSTATE_UINTTL(cr[2], CPUX86State),
	406	VMSTATE_UINTTL(cr[3], CPUX86State),
	407	VMSTATE_UINTTL(cr[4], CPUX86State),
	408	VMSTATE_UINTTL_ARRAY(dr, CPUX86State, 8),
0cb892aa	409	/* MMU */
317ac620	410	VMSTATE_INT32(a20_mask, CPUX86State),
0cb892aa	411	/* XMM */
317ac620 AF	412	VMSTATE_UINT32(mxcsr, CPUX86State),
317ac620 AF	413	VMSTATE_XMM_REGS(xmm_regs, CPUX86State, CPU_NB_REGS),
8dd3dca3 AJ	414
8dd3dca3 AJ	415	#ifdef TARGET_X86_64
317ac620 AF	416	VMSTATE_UINT64(efer, CPUX86State),
	417	VMSTATE_UINT64(star, CPUX86State),
	418	VMSTATE_UINT64(lstar, CPUX86State),
	419	VMSTATE_UINT64(cstar, CPUX86State),
	420	VMSTATE_UINT64(fmask, CPUX86State),
	421	VMSTATE_UINT64(kernelgsbase, CPUX86State),
8dd3dca3	422	#endif
317ac620 AF	423	VMSTATE_UINT32_V(smbase, CPUX86State, 4),
	424
	425	VMSTATE_UINT64_V(pat, CPUX86State, 5),
	426	VMSTATE_UINT32_V(hflags2, CPUX86State, 5),
	427
	428	VMSTATE_UINT32_TEST(halted, CPUX86State, version_is_5),
	429	VMSTATE_UINT64_V(vm_hsave, CPUX86State, 5),
	430	VMSTATE_UINT64_V(vm_vmcb, CPUX86State, 5),
	431	VMSTATE_UINT64_V(tsc_offset, CPUX86State, 5),
	432	VMSTATE_UINT64_V(intercept, CPUX86State, 5),
	433	VMSTATE_UINT16_V(intercept_cr_read, CPUX86State, 5),
	434	VMSTATE_UINT16_V(intercept_cr_write, CPUX86State, 5),
	435	VMSTATE_UINT16_V(intercept_dr_read, CPUX86State, 5),
	436	VMSTATE_UINT16_V(intercept_dr_write, CPUX86State, 5),
	437	VMSTATE_UINT32_V(intercept_exceptions, CPUX86State, 5),
	438	VMSTATE_UINT8_V(v_tpr, CPUX86State, 5),
dd5e3b17	439	/* MTRRs */
317ac620 AF	440	VMSTATE_UINT64_ARRAY_V(mtrr_fixed, CPUX86State, 11, 8),
	441	VMSTATE_UINT64_V(mtrr_deftype, CPUX86State, 8),
	442	VMSTATE_MTRR_VARS(mtrr_var, CPUX86State, 8, 8),
0cb892aa	443	/* KVM-related states */
317ac620 AF	444	VMSTATE_INT32_V(interrupt_injected, CPUX86State, 9),
	445	VMSTATE_UINT32_V(mp_state, CPUX86State, 9),
	446	VMSTATE_UINT64_V(tsc, CPUX86State, 9),
	447	VMSTATE_INT32_V(exception_injected, CPUX86State, 11),
	448	VMSTATE_UINT8_V(soft_interrupt, CPUX86State, 11),
	449	VMSTATE_UINT8_V(nmi_injected, CPUX86State, 11),
	450	VMSTATE_UINT8_V(nmi_pending, CPUX86State, 11),
	451	VMSTATE_UINT8_V(has_error_code, CPUX86State, 11),
	452	VMSTATE_UINT32_V(sipi_vector, CPUX86State, 11),
0cb892aa	453	/* MCE */
317ac620 AF	454	VMSTATE_UINT64_V(mcg_cap, CPUX86State, 10),
	455	VMSTATE_UINT64_V(mcg_status, CPUX86State, 10),
	456	VMSTATE_UINT64_V(mcg_ctl, CPUX86State, 10),
	457	VMSTATE_UINT64_ARRAY_V(mce_banks, CPUX86State, MCE_BANKS_DEF *4, 10),
0cb892aa	458	/* rdtscp */
317ac620	459	VMSTATE_UINT64_V(tsc_aux, CPUX86State, 11),
1a03675d	460	/* KVM pvclock msr */
317ac620 AF	461	VMSTATE_UINT64_V(system_time_msr, CPUX86State, 11),
317ac620 AF	462	VMSTATE_UINT64_V(wall_clock_msr, CPUX86State, 11),
f1665b21	463	/* XSAVE related fields */
317ac620 AF	464	VMSTATE_UINT64_V(xcr0, CPUX86State, 12),
	465	VMSTATE_UINT64_V(xstate_bv, CPUX86State, 12),
	466	VMSTATE_YMMH_REGS_VARS(ymmh_regs, CPUX86State, CPU_NB_REGS, 12),
0cb892aa	467	VMSTATE_END_OF_LIST()
a0fb002c	468	/* The above list is not sorted /wrt version numbers, watch out! */
f6584ee2 GN	469	},
	470	.subsections = (VMStateSubsection []) {
	471	{
	472	.vmsd = &vmstate_async_pf_msr,
	473	.needed = async_pf_msr_needed,
bc9a839d MT	474	} , {
	475	.vmsd = &vmstate_pv_eoi_msr,
	476	.needed = pv_eoi_msr_needed,
42cc8fa6 JK	477	} , {
	478	.vmsd = &vmstate_fpop_ip_dp,
	479	.needed = fpop_ip_dp_needed,
aa82ba54 LJ	480	}, {
	481	.vmsd = &vmstate_msr_tscdeadline,
	482	.needed = tscdeadline_needed,
21e87c46 AK	483	}, {
	484	.vmsd = &vmstate_msr_ia32_misc_enable,
	485	.needed = misc_enable_needed,
f6584ee2 GN	486	} , {
	487	/* empty */
	488	}
79c4f6b0	489	}
0cb892aa	490	};
79c4f6b0	491
0cb892aa JQ	492	void cpu_save(QEMUFile f, void opaque)
	493	{
	494	vmstate_save_state(f, &vmstate_cpu, opaque);
	495	}
1f76b9b9	496
0cb892aa JQ	497	int cpu_load(QEMUFile f, void opaque, int version_id)
	498	{
	499	return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
8dd3dca3	500	}