[qemu.git] / target-arm / machine.c

#include "qemu/osdep.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/hw.h"
#include "hw/boards.h"
#include "qemu/error-report.h"
#include "sysemu/kvm.h"
#include "kvm_arm.h"
#include "internals.h"
#include "migration/cpu.h"

static bool vfp_needed(void *opaque)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;

    return arm_feature(env, ARM_FEATURE_VFP);
}

static int get_fpscr(QEMUFile *f, void *opaque, size_t size)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;
    uint32_t val = qemu_get_be32(f);

    vfp_set_fpscr(env, val);
    return 0;
}

static void put_fpscr(QEMUFile *f, void *opaque, size_t size)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;

    qemu_put_be32(f, vfp_get_fpscr(env));
}

static const VMStateInfo vmstate_fpscr = {
    .name = "fpscr",
    .get = get_fpscr,
    .put = put_fpscr,
};

static const VMStateDescription vmstate_vfp = {
    .name = "cpu/vfp",
    .version_id = 3,
    .minimum_version_id = 3,
    .needed = vfp_needed,
    .fields = (VMStateField[]) {
        VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64),
        /* The xregs array is a little awkward because element 1 (FPSCR)
         * requires a specific accessor, so we have to split it up in
         * the vmstate:
         */
        VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU),
        VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14),
        {
            .name = "fpscr",
            .version_id = 0,
            .size = sizeof(uint32_t),
            .info = &vmstate_fpscr,
            .flags = VMS_SINGLE,
            .offset = 0,
        },
        VMSTATE_END_OF_LIST()
    }
};

static bool iwmmxt_needed(void *opaque)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;

    return arm_feature(env, ARM_FEATURE_IWMMXT);
}

static const VMStateDescription vmstate_iwmmxt = {
    .name = "cpu/iwmmxt",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = iwmmxt_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
        VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
        VMSTATE_END_OF_LIST()
    }
};

static bool m_needed(void *opaque)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;

    return arm_feature(env, ARM_FEATURE_M);
}

static const VMStateDescription vmstate_m = {
    .name = "cpu/m",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = m_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
        VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
        VMSTATE_UINT32(env.v7m.basepri, ARMCPU),
        VMSTATE_UINT32(env.v7m.control, ARMCPU),
        VMSTATE_INT32(env.v7m.current_sp, ARMCPU),
        VMSTATE_INT32(env.v7m.exception, ARMCPU),
        VMSTATE_END_OF_LIST()
    }
};

static bool thumb2ee_needed(void *opaque)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;

    return arm_feature(env, ARM_FEATURE_THUMB2EE);
}

static const VMStateDescription vmstate_thumb2ee = {
    .name = "cpu/thumb2ee",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = thumb2ee_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(env.teecr, ARMCPU),
        VMSTATE_UINT32(env.teehbr, ARMCPU),
        VMSTATE_END_OF_LIST()
    }
};

static bool pmsav7_needed(void *opaque)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;

    return arm_feature(env, ARM_FEATURE_MPU) &&
           arm_feature(env, ARM_FEATURE_V7);
}

static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id)
{
    ARMCPU *cpu = opaque;

    return cpu->env.cp15.c6_rgnr < cpu->pmsav7_dregion;
}

static const VMStateDescription vmstate_pmsav7 = {
    .name = "cpu/pmsav7",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = pmsav7_needed,
    .fields = (VMStateField[]) {
        VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0,
                              vmstate_info_uint32, uint32_t),
        VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0,
                              vmstate_info_uint32, uint32_t),
        VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0,
                              vmstate_info_uint32, uint32_t),
        VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate),
        VMSTATE_END_OF_LIST()
    }
};

static int get_cpsr(QEMUFile *f, void *opaque, size_t size)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;
    uint32_t val = qemu_get_be32(f);

    env->aarch64 = ((val & PSTATE_nRW) == 0);

    if (is_a64(env)) {
        pstate_write(env, val);
        return 0;
    }

    cpsr_write(env, val, 0xffffffff, CPSRWriteRaw);
    return 0;
}

static void put_cpsr(QEMUFile *f, void *opaque, size_t size)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;
    uint32_t val;

    if (is_a64(env)) {
        val = pstate_read(env);
    } else {
        val = cpsr_read(env);
    }

    qemu_put_be32(f, val);
}

static const VMStateInfo vmstate_cpsr = {
    .name = "cpsr",
    .get = get_cpsr,
    .put = put_cpsr,
};

static void cpu_pre_save(void *opaque)
{
    ARMCPU *cpu = opaque;

    if (kvm_enabled()) {
        if (!write_kvmstate_to_list(cpu)) {
            /* This should never fail */
            abort();
        }
    } else {
        if (!write_cpustate_to_list(cpu)) {
            /* This should never fail. */
            abort();
        }
    }

    cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
    memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes,
           cpu->cpreg_array_len * sizeof(uint64_t));
    memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values,
           cpu->cpreg_array_len * sizeof(uint64_t));
}

static int cpu_post_load(void *opaque, int version_id)
{
    ARMCPU *cpu = opaque;
    int i, v;

    /* Update the values list from the incoming migration data.
     * Anything in the incoming data which we don't know about is
     * a migration failure; anything we know about but the incoming
     * data doesn't specify retains its current (reset) value.
     * The indexes list remains untouched -- we only inspect the
     * incoming migration index list so we can match the values array
     * entries with the right slots in our own values array.
     */

    for (i = 0, v = 0; i < cpu->cpreg_array_len
             && v < cpu->cpreg_vmstate_array_len; i++) {
        if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) {
            /* register in our list but not incoming : skip it */
            continue;
        }
        if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) {
            /* register in their list but not ours: fail migration */
            return -1;
        }
        /* matching register, copy the value over */
        cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v];
        v++;
    }

    if (kvm_enabled()) {
        if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) {
            return -1;
        }
        /* Note that it's OK for the TCG side not to know about
         * every register in the list; KVM is authoritative if
         * we're using it.
         */
        write_list_to_cpustate(cpu);
    } else {
        if (!write_list_to_cpustate(cpu)) {
            return -1;
        }
    }

    hw_breakpoint_update_all(cpu);
    hw_watchpoint_update_all(cpu);

    return 0;
}

const VMStateDescription vmstate_arm_cpu = {
    .name = "cpu",
    .version_id = 22,
    .minimum_version_id = 22,
    .pre_save = cpu_pre_save,
    .post_load = cpu_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
        VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32),
        VMSTATE_UINT64(env.pc, ARMCPU),
        {
            .name = "cpsr",
            .version_id = 0,
            .size = sizeof(uint32_t),
            .info = &vmstate_cpsr,
            .flags = VMS_SINGLE,
            .offset = 0,
        },
        VMSTATE_UINT32(env.spsr, ARMCPU),
        VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8),
        VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8),
        VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8),
        VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
        VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
        VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4),
        VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4),
        /* The length-check must come before the arrays to avoid
         * incoming data possibly overflowing the array.
         */
        VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU),
        VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU,
                             cpreg_vmstate_array_len,
                             0, vmstate_info_uint64, uint64_t),
        VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU,
                             cpreg_vmstate_array_len,
                             0, vmstate_info_uint64, uint64_t),
        VMSTATE_UINT64(env.exclusive_addr, ARMCPU),
        VMSTATE_UINT64(env.exclusive_val, ARMCPU),
        VMSTATE_UINT64(env.exclusive_high, ARMCPU),
        VMSTATE_UINT64(env.features, ARMCPU),
        VMSTATE_UINT32(env.exception.syndrome, ARMCPU),
        VMSTATE_UINT32(env.exception.fsr, ARMCPU),
        VMSTATE_UINT64(env.exception.vaddress, ARMCPU),
        VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU),
        VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU),
        VMSTATE_BOOL(powered_off, ARMCPU),
        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription*[]) {
        &vmstate_vfp,
        &vmstate_iwmmxt,
        &vmstate_m,
        &vmstate_thumb2ee,
        &vmstate_pmsav7,
        NULL
    }
};

const char *gicv3_class_name(void)
{
    if (kvm_irqchip_in_kernel()) {
#ifdef TARGET_AARCH64
        return "kvm-arm-gicv3";
#else
        error_report("KVM GICv3 acceleration is not supported on this "
                     "platform");
        exit(1);
#endif
    } else {
        return "arm-gicv3";
    }
}
Commit	Line	Data
74c21bd0	1	#include "qemu/osdep.h"
33c11879 PB	2	#include "qemu-common.h"
33c11879 PB	3	#include "cpu.h"
8dd3dca3 AJ	4	#include "hw/hw.h"
8dd3dca3 AJ	5	#include "hw/boards.h"
a7bf3034	6	#include "qemu/error-report.h"
ff047453 PM	7	#include "sysemu/kvm.h"
ff047453 PM	8	#include "kvm_arm.h"
9ee98ce8	9	#include "internals.h"
1e00b8d5	10	#include "migration/cpu.h"
8dd3dca3	11
3cc1d208	12	static bool vfp_needed(void *opaque)
8dd3dca3	13	{
3cc1d208 JQ	14	ARMCPU *cpu = opaque;
3cc1d208 JQ	15	CPUARMState *env = &cpu->env;
8dd3dca3	16
3cc1d208 JQ	17	return arm_feature(env, ARM_FEATURE_VFP);
3cc1d208 JQ	18	}
8dd3dca3	19
e91f229a PM	20	static int get_fpscr(QEMUFile f, void opaque, size_t size)
	21	{
	22	ARMCPU *cpu = opaque;
	23	CPUARMState *env = &cpu->env;
	24	uint32_t val = qemu_get_be32(f);
	25
	26	vfp_set_fpscr(env, val);
	27	return 0;
	28	}
	29
	30	static void put_fpscr(QEMUFile f, void opaque, size_t size)
	31	{
	32	ARMCPU *cpu = opaque;
	33	CPUARMState *env = &cpu->env;
	34
	35	qemu_put_be32(f, vfp_get_fpscr(env));
	36	}
	37
	38	static const VMStateInfo vmstate_fpscr = {
	39	.name = "fpscr",
	40	.get = get_fpscr,
	41	.put = put_fpscr,
	42	};
	43
3cc1d208 JQ	44	static const VMStateDescription vmstate_vfp = {
3cc1d208 JQ	45	.name = "cpu/vfp",
3926cc84 AG	46	.version_id = 3,
3926cc84 AG	47	.minimum_version_id = 3,
5cd8cada	48	.needed = vfp_needed,
3cc1d208	49	.fields = (VMStateField[]) {
3926cc84	50	VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64),
e91f229a PM	51	/* The xregs array is a little awkward because element 1 (FPSCR)
	52	* requires a specific accessor, so we have to split it up in
	53	* the vmstate:
	54	*/
	55	VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU),
	56	VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14),
	57	{
	58	.name = "fpscr",
	59	.version_id = 0,
	60	.size = sizeof(uint32_t),
	61	.info = &vmstate_fpscr,
	62	.flags = VMS_SINGLE,
	63	.offset = 0,
	64	},
3cc1d208	65	VMSTATE_END_OF_LIST()
8dd3dca3	66	}
3cc1d208	67	};
8dd3dca3	68
3cc1d208 JQ	69	static bool iwmmxt_needed(void *opaque)
	70	{
	71	ARMCPU *cpu = opaque;
	72	CPUARMState *env = &cpu->env;
8dd3dca3	73
3cc1d208 JQ	74	return arm_feature(env, ARM_FEATURE_IWMMXT);
3cc1d208 JQ	75	}
ffe47d33	76
3cc1d208 JQ	77	static const VMStateDescription vmstate_iwmmxt = {
	78	.name = "cpu/iwmmxt",
	79	.version_id = 1,
	80	.minimum_version_id = 1,
5cd8cada	81	.needed = iwmmxt_needed,
3cc1d208 JQ	82	.fields = (VMStateField[]) {
	83	VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
	84	VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
	85	VMSTATE_END_OF_LIST()
ffe47d33	86	}
3cc1d208 JQ	87	};
	88
	89	static bool m_needed(void *opaque)
	90	{
	91	ARMCPU *cpu = opaque;
	92	CPUARMState *env = &cpu->env;
	93
	94	return arm_feature(env, ARM_FEATURE_M);
8dd3dca3 AJ	95	}
8dd3dca3 AJ	96
6df05bdd	97	static const VMStateDescription vmstate_m = {
3cc1d208 JQ	98	.name = "cpu/m",
	99	.version_id = 1,
	100	.minimum_version_id = 1,
5cd8cada	101	.needed = m_needed,
3cc1d208 JQ	102	.fields = (VMStateField[]) {
	103	VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
	104	VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
	105	VMSTATE_UINT32(env.v7m.basepri, ARMCPU),
	106	VMSTATE_UINT32(env.v7m.control, ARMCPU),
	107	VMSTATE_INT32(env.v7m.current_sp, ARMCPU),
	108	VMSTATE_INT32(env.v7m.exception, ARMCPU),
	109	VMSTATE_END_OF_LIST()
	110	}
	111	};
	112
	113	static bool thumb2ee_needed(void *opaque)
8dd3dca3	114	{
3cc1d208 JQ	115	ARMCPU *cpu = opaque;
3cc1d208 JQ	116	CPUARMState *env = &cpu->env;
8dd3dca3	117
3cc1d208 JQ	118	return arm_feature(env, ARM_FEATURE_THUMB2EE);
3cc1d208 JQ	119	}
8dd3dca3	120
3cc1d208 JQ	121	static const VMStateDescription vmstate_thumb2ee = {
	122	.name = "cpu/thumb2ee",
	123	.version_id = 1,
	124	.minimum_version_id = 1,
5cd8cada	125	.needed = thumb2ee_needed,
3cc1d208 JQ	126	.fields = (VMStateField[]) {
	127	VMSTATE_UINT32(env.teecr, ARMCPU),
	128	VMSTATE_UINT32(env.teehbr, ARMCPU),
	129	VMSTATE_END_OF_LIST()
8dd3dca3	130	}
3cc1d208 JQ	131	};
3cc1d208 JQ	132
6cb0b013 PC	133	static bool pmsav7_needed(void *opaque)
	134	{
	135	ARMCPU *cpu = opaque;
	136	CPUARMState *env = &cpu->env;
	137
	138	return arm_feature(env, ARM_FEATURE_MPU) &&
	139	arm_feature(env, ARM_FEATURE_V7);
	140	}
	141
	142	static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id)
	143	{
	144	ARMCPU *cpu = opaque;
	145
	146	return cpu->env.cp15.c6_rgnr < cpu->pmsav7_dregion;
	147	}
	148
	149	static const VMStateDescription vmstate_pmsav7 = {
	150	.name = "cpu/pmsav7",
	151	.version_id = 1,
	152	.minimum_version_id = 1,
	153	.needed = pmsav7_needed,
	154	.fields = (VMStateField[]) {
	155	VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0,
	156	vmstate_info_uint32, uint32_t),
	157	VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0,
	158	vmstate_info_uint32, uint32_t),
	159	VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0,
	160	vmstate_info_uint32, uint32_t),
	161	VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate),
	162	VMSTATE_END_OF_LIST()
	163	}
	164	};
	165
3cc1d208 JQ	166	static int get_cpsr(QEMUFile f, void opaque, size_t size)
	167	{
	168	ARMCPU *cpu = opaque;
	169	CPUARMState *env = &cpu->env;
	170	uint32_t val = qemu_get_be32(f);
	171
a7130a3e PM	172	env->aarch64 = ((val & PSTATE_nRW) == 0);
	173
	174	if (is_a64(env)) {
	175	pstate_write(env, val);
	176	return 0;
	177	}
	178
50866ba5	179	cpsr_write(env, val, 0xffffffff, CPSRWriteRaw);
3cc1d208 JQ	180	return 0;
3cc1d208 JQ	181	}
8dd3dca3	182
3cc1d208 JQ	183	static void put_cpsr(QEMUFile f, void opaque, size_t size)
	184	{
	185	ARMCPU *cpu = opaque;
	186	CPUARMState *env = &cpu->env;
a7130a3e PM	187	uint32_t val;
	188
	189	if (is_a64(env)) {
	190	val = pstate_read(env);
	191	} else {
	192	val = cpsr_read(env);
	193	}
8dd3dca3	194
a7130a3e	195	qemu_put_be32(f, val);
3cc1d208	196	}
8dd3dca3	197
3cc1d208 JQ	198	static const VMStateInfo vmstate_cpsr = {
	199	.name = "cpsr",
	200	.get = get_cpsr,
	201	.put = put_cpsr,
	202	};
	203
721fae12 PM	204	static void cpu_pre_save(void *opaque)
	205	{
	206	ARMCPU *cpu = opaque;
	207
ff047453 PM	208	if (kvm_enabled()) {
	209	if (!write_kvmstate_to_list(cpu)) {
	210	/* This should never fail */
	211	abort();
	212	}
	213	} else {
	214	if (!write_cpustate_to_list(cpu)) {
	215	/* This should never fail. */
	216	abort();
	217	}
721fae12 PM	218	}
	219
	220	cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
	221	memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes,
	222	cpu->cpreg_array_len * sizeof(uint64_t));
	223	memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values,
	224	cpu->cpreg_array_len * sizeof(uint64_t));
	225	}
	226
	227	static int cpu_post_load(void *opaque, int version_id)
	228	{
	229	ARMCPU *cpu = opaque;
	230	int i, v;
	231
	232	/* Update the values list from the incoming migration data.
	233	* Anything in the incoming data which we don't know about is
	234	* a migration failure; anything we know about but the incoming
	235	* data doesn't specify retains its current (reset) value.
	236	* The indexes list remains untouched -- we only inspect the
	237	* incoming migration index list so we can match the values array
	238	* entries with the right slots in our own values array.
	239	*/
	240
	241	for (i = 0, v = 0; i < cpu->cpreg_array_len
	242	&& v < cpu->cpreg_vmstate_array_len; i++) {
	243	if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) {
	244	/* register in our list but not incoming : skip it */
	245	continue;
	246	}
	247	if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) {
	248	/* register in their list but not ours: fail migration */
	249	return -1;
	250	}
	251	/* matching register, copy the value over */
	252	cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v];
	253	v++;
	254	}
	255
ff047453	256	if (kvm_enabled()) {
4b7a6bf4	257	if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) {
ff047453 PM	258	return -1;
	259	}
	260	/* Note that it's OK for the TCG side not to know about
	261	* every register in the list; KVM is authoritative if
	262	* we're using it.
	263	*/
	264	write_list_to_cpustate(cpu);
	265	} else {
	266	if (!write_list_to_cpustate(cpu)) {
	267	return -1;
	268	}
721fae12 PM	269	}
721fae12 PM	270
46747d15	271	hw_breakpoint_update_all(cpu);
9ee98ce8 PM	272	hw_watchpoint_update_all(cpu);
9ee98ce8 PM	273
721fae12 PM	274	return 0;
	275	}
	276
3cc1d208 JQ	277	const VMStateDescription vmstate_arm_cpu = {
3cc1d208 JQ	278	.name = "cpu",
a7130a3e PM	279	.version_id = 22,
a7130a3e PM	280	.minimum_version_id = 22,
721fae12 PM	281	.pre_save = cpu_pre_save,
721fae12 PM	282	.post_load = cpu_post_load,
3cc1d208 JQ	283	.fields = (VMStateField[]) {
3cc1d208 JQ	284	VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
a7130a3e PM	285	VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32),
a7130a3e PM	286	VMSTATE_UINT64(env.pc, ARMCPU),
3cc1d208 JQ	287	{
	288	.name = "cpsr",
	289	.version_id = 0,
	290	.size = sizeof(uint32_t),
	291	.info = &vmstate_cpsr,
	292	.flags = VMS_SINGLE,
	293	.offset = 0,
	294	},
	295	VMSTATE_UINT32(env.spsr, ARMCPU),
28c9457d	296	VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8),
0b7d409d FA	297	VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8),
0b7d409d FA	298	VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8),
3cc1d208 JQ	299	VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
3cc1d208 JQ	300	VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
1b174238	301	VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4),
73fb3b76	302	VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4),
721fae12 PM	303	/* The length-check must come before the arrays to avoid
	304	* incoming data possibly overflowing the array.
	305	*/
3476436a	306	VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU),
721fae12 PM	307	VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU,
	308	cpreg_vmstate_array_len,
	309	0, vmstate_info_uint64, uint64_t),
	310	VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU,
	311	cpreg_vmstate_array_len,
	312	0, vmstate_info_uint64, uint64_t),
03d05e2d PM	313	VMSTATE_UINT64(env.exclusive_addr, ARMCPU),
	314	VMSTATE_UINT64(env.exclusive_val, ARMCPU),
	315	VMSTATE_UINT64(env.exclusive_high, ARMCPU),
3cc1d208	316	VMSTATE_UINT64(env.features, ARMCPU),
abf1172f PM	317	VMSTATE_UINT32(env.exception.syndrome, ARMCPU),
	318	VMSTATE_UINT32(env.exception.fsr, ARMCPU),
	319	VMSTATE_UINT64(env.exception.vaddress, ARMCPU),
e720677e PB	320	VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU),
e720677e PB	321	VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU),
543486db	322	VMSTATE_BOOL(powered_off, ARMCPU),
3cc1d208 JQ	323	VMSTATE_END_OF_LIST()
3cc1d208 JQ	324	},
5cd8cada JQ	325	.subsections = (const VMStateDescription*[]) {
	326	&vmstate_vfp,
	327	&vmstate_iwmmxt,
	328	&vmstate_m,
	329	&vmstate_thumb2ee,
6cb0b013	330	&vmstate_pmsav7,
5cd8cada	331	NULL
ffe47d33	332	}
3cc1d208	333	};
a7bf3034 PF	334
	335	const char *gicv3_class_name(void)
	336	{
	337	if (kvm_irqchip_in_kernel()) {
	338	#ifdef TARGET_AARCH64
	339	return "kvm-arm-gicv3";
	340	#else
	341	error_report("KVM GICv3 acceleration is not supported on this "
9af9e0fe	342	"platform");
ff9d3e9c	343	exit(1);
a7bf3034 PF	344	#endif
a7bf3034 PF	345	} else {
5de8229d	346	return "arm-gicv3";
a7bf3034	347	}
a7bf3034	348	}