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move CONFIG_* values from yes to y
[qemu.git] / cpu-exec.c
CommitLineData
7d13299d
FB		 1/*
2 * i386 emulator main execution loop
5fafdf24 3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0
FB		 16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
fad6cb1a 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
7d13299d 19 */
e4533c7a 20#include "config.h"
93ac68bc 21#include "exec.h"
956034d7 22#include "disas.h"
7cb69cae 23#include "tcg.h"
7ba1e619 24#include "kvm.h"
7d13299d 25
fbf9eeb3
FB		 26#if !defined(CONFIG_SOFTMMU)
27#undef EAX
28#undef ECX
29#undef EDX
30#undef EBX
31#undef ESP
32#undef EBP
33#undef ESI
34#undef EDI
35#undef EIP
36#include <signal.h>
84778508 37#ifdef __linux__
fbf9eeb3
FB		 38#include <sys/ucontext.h>
39#endif
84778508 40#endif
fbf9eeb3 41
572a9d4a
BS		 42#if defined(__sparc__) && !defined(HOST_SOLARIS)
43// Work around ugly bugs in glibc that mangle global register contents
44#undef env
45#define env cpu_single_env
46#endif
47
36bdbe54
FB		 48int tb_invalidated_flag;
49
dc99065b 50//#define DEBUG_EXEC
9de5e440 51//#define DEBUG_SIGNAL
7d13299d 52
6a4955a8
AL		 53int qemu_cpu_has_work(CPUState *env)
54{
55 return cpu_has_work(env);
56}
57
e4533c7a
FB		 58void cpu_loop_exit(void)
59{
bfed01fc
TS		 60 /* NOTE: the register at this point must be saved by hand because
61 longjmp restore them */
62 regs_to_env();
e4533c7a
FB		 63 longjmp(env->jmp_env, 1);
64}
bfed01fc 65
fbf9eeb3
FB		 66/* exit the current TB from a signal handler. The host registers are
67 restored in a state compatible with the CPU emulator
68 */
5fafdf24 69void cpu_resume_from_signal(CPUState *env1, void *puc)
fbf9eeb3
FB		 70{
71#if !defined(CONFIG_SOFTMMU)
84778508 72#ifdef __linux__
fbf9eeb3 73 struct ucontext *uc = puc;
84778508
BS		 74#elif defined(__OpenBSD__)
75 struct sigcontext *uc = puc;
76#endif
fbf9eeb3
FB		 77#endif
78
79 env = env1;
80
81 /* XXX: restore cpu registers saved in host registers */
82
83#if !defined(CONFIG_SOFTMMU)
84 if (puc) {
85 /* XXX: use siglongjmp ? */
84778508 86#ifdef __linux__
fbf9eeb3 87 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
84778508
BS		 88#elif defined(__OpenBSD__)
89 sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
90#endif
fbf9eeb3
FB		 91 }
92#endif
9a3ea654 93 env->exception_index = -1;
fbf9eeb3
FB		 94 longjmp(env->jmp_env, 1);
95}
96
2e70f6ef
PB		 97/* Execute the code without caching the generated code. An interpreter
98 could be used if available. */
99static void cpu_exec_nocache(int max_cycles, TranslationBlock *orig_tb)
100{
101 unsigned long next_tb;
102 TranslationBlock *tb;
103
104 /* Should never happen.
105 We only end up here when an existing TB is too long. */
106 if (max_cycles > CF_COUNT_MASK)
107 max_cycles = CF_COUNT_MASK;
108
109 tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
110 max_cycles);
111 env->current_tb = tb;
112 /* execute the generated code */
113 next_tb = tcg_qemu_tb_exec(tb->tc_ptr);
114
115 if ((next_tb & 3) == 2) {
116 /* Restore PC. This may happen if async event occurs before
117 the TB starts executing. */
622ed360 118 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 119 }
120 tb_phys_invalidate(tb, -1);
121 tb_free(tb);
122}
123
8a40a180
FB		 124static TranslationBlock *tb_find_slow(target_ulong pc,
125 target_ulong cs_base,
c068688b 126 uint64_t flags)
8a40a180
FB		 127{
128 TranslationBlock *tb, **ptb1;
8a40a180
FB		 129 unsigned int h;
130 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
3b46e624 131
8a40a180 132 tb_invalidated_flag = 0;
3b46e624 133
8a40a180 134 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
3b46e624 135
8a40a180
FB		 136 /* find translated block using physical mappings */
137 phys_pc = get_phys_addr_code(env, pc);
138 phys_page1 = phys_pc & TARGET_PAGE_MASK;
139 phys_page2 = -1;
140 h = tb_phys_hash_func(phys_pc);
141 ptb1 = &tb_phys_hash[h];
142 for(;;) {
143 tb = *ptb1;
144 if (!tb)
145 goto not_found;
5fafdf24 146 if (tb->pc == pc &&
8a40a180 147 tb->page_addr[0] == phys_page1 &&
5fafdf24 148 tb->cs_base == cs_base &&
8a40a180
FB		 149 tb->flags == flags) {
150 /* check next page if needed */
151 if (tb->page_addr[1] != -1) {
5fafdf24 152 virt_page2 = (pc & TARGET_PAGE_MASK) +
8a40a180
FB		 153 TARGET_PAGE_SIZE;
154 phys_page2 = get_phys_addr_code(env, virt_page2);
155 if (tb->page_addr[1] == phys_page2)
156 goto found;
157 } else {
158 goto found;
159 }
160 }
161 ptb1 = &tb->phys_hash_next;
162 }
163 not_found:
2e70f6ef
PB		 164 /* if no translated code available, then translate it now */
165 tb = tb_gen_code(env, pc, cs_base, flags, 0);
3b46e624 166
8a40a180 167 found:
8a40a180
FB		 168 /* we add the TB in the virtual pc hash table */
169 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
8a40a180
FB		 170 return tb;
171}
172
173static inline TranslationBlock *tb_find_fast(void)
174{
175 TranslationBlock *tb;
176 target_ulong cs_base, pc;
6b917547 177 int flags;
8a40a180
FB		 178
179 /* we record a subset of the CPU state. It will
180 always be the same before a given translated block
181 is executed. */
6b917547 182 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
bce61846 183 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
551bd27f
TS		 184 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
185 tb->flags != flags)) {
8a40a180
FB		 186 tb = tb_find_slow(pc, cs_base, flags);
187 }
188 return tb;
189}
190
dde2367e
AL		 191static CPUDebugExcpHandler *debug_excp_handler;
192
193CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
194{
195 CPUDebugExcpHandler *old_handler = debug_excp_handler;
196
197 debug_excp_handler = handler;
198 return old_handler;
199}
200
6e140f28
AL		 201static void cpu_handle_debug_exception(CPUState *env)
202{
203 CPUWatchpoint *wp;
204
205 if (!env->watchpoint_hit)
c0ce998e 206 TAILQ_FOREACH(wp, &env->watchpoints, entry)
6e140f28 207 wp->flags &= ~BP_WATCHPOINT_HIT;
dde2367e
AL		 208
209 if (debug_excp_handler)
210 debug_excp_handler(env);
6e140f28
AL		 211}
212
7d13299d
FB		 213/* main execution loop */
214
e4533c7a 215int cpu_exec(CPUState *env1)
7d13299d 216{
1057eaa7
PB		 217#define DECLARE_HOST_REGS 1
218#include "hostregs_helper.h"
8a40a180 219 int ret, interrupt_request;
8a40a180 220 TranslationBlock *tb;
c27004ec 221 uint8_t *tc_ptr;
d5975363 222 unsigned long next_tb;
8c6939c0 223
bfed01fc
TS		 224 if (cpu_halted(env1) == EXCP_HALTED)
225 return EXCP_HALTED;
5a1e3cfc 226
5fafdf24 227 cpu_single_env = env1;
6a00d601 228
7d13299d 229 /* first we save global registers */
1057eaa7
PB		 230#define SAVE_HOST_REGS 1
231#include "hostregs_helper.h"
c27004ec 232 env = env1;
e4533c7a 233
0d1a29f9 234 env_to_regs();
ecb644f4 235#if defined(TARGET_I386)
9de5e440 236 /* put eflags in CPU temporary format */
fc2b4c48
FB		 237 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
238 DF = 1 - (2 * ((env->eflags >> 10) & 1));
9de5e440 239 CC_OP = CC_OP_EFLAGS;
fc2b4c48 240 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
93ac68bc 241#elif defined(TARGET_SPARC)
e6e5906b
PB		 242#elif defined(TARGET_M68K)
243 env->cc_op = CC_OP_FLAGS;
244 env->cc_dest = env->sr & 0xf;
245 env->cc_x = (env->sr >> 4) & 1;
ecb644f4
TS		 246#elif defined(TARGET_ALPHA)
247#elif defined(TARGET_ARM)
248#elif defined(TARGET_PPC)
b779e29e 249#elif defined(TARGET_MICROBLAZE)
6af0bf9c 250#elif defined(TARGET_MIPS)
fdf9b3e8 251#elif defined(TARGET_SH4)
f1ccf904 252#elif defined(TARGET_CRIS)
fdf9b3e8 253 /* XXXXX */
e4533c7a
FB		 254#else
255#error unsupported target CPU
256#endif
3fb2ded1 257 env->exception_index = -1;
9d27abd9 258
7d13299d 259 /* prepare setjmp context for exception handling */
3fb2ded1
FB		 260 for(;;) {
261 if (setjmp(env->jmp_env) == 0) {
9ddff3d2
BS		 262#if defined(__sparc__) && !defined(HOST_SOLARIS)
263#undef env
264 env = cpu_single_env;
265#define env cpu_single_env
266#endif
ee8b7021 267 env->current_tb = NULL;
3fb2ded1
FB		 268 /* if an exception is pending, we execute it here */
269 if (env->exception_index >= 0) {
270 if (env->exception_index >= EXCP_INTERRUPT) {
271 /* exit request from the cpu execution loop */
272 ret = env->exception_index;
6e140f28
AL		 273 if (ret == EXCP_DEBUG)
274 cpu_handle_debug_exception(env);
3fb2ded1 275 break;
72d239ed
AJ		 276 } else {
277#if defined(CONFIG_USER_ONLY)
3fb2ded1 278 /* if user mode only, we simulate a fake exception
9f083493 279 which will be handled outside the cpu execution
3fb2ded1 280 loop */
83479e77 281#if defined(TARGET_I386)
5fafdf24
TS		 282 do_interrupt_user(env->exception_index,
283 env->exception_is_int,
284 env->error_code,
3fb2ded1 285 env->exception_next_eip);
eba01623
FB		 286 /* successfully delivered */
287 env->old_exception = -1;
83479e77 288#endif
3fb2ded1
FB		 289 ret = env->exception_index;
290 break;
72d239ed 291#else
83479e77 292#if defined(TARGET_I386)
3fb2ded1
FB		 293 /* simulate a real cpu exception. On i386, it can
294 trigger new exceptions, but we do not handle
295 double or triple faults yet. */
5fafdf24
TS		 296 do_interrupt(env->exception_index,
297 env->exception_is_int,
298 env->error_code,
d05e66d2 299 env->exception_next_eip, 0);
678dde13
TS		 300 /* successfully delivered */
301 env->old_exception = -1;
ce09776b
FB		 302#elif defined(TARGET_PPC)
303 do_interrupt(env);
b779e29e
EI		 304#elif defined(TARGET_MICROBLAZE)
305 do_interrupt(env);
6af0bf9c
FB		 306#elif defined(TARGET_MIPS)
307 do_interrupt(env);
e95c8d51 308#elif defined(TARGET_SPARC)
f2bc7e7f 309 do_interrupt(env);
b5ff1b31
FB		 310#elif defined(TARGET_ARM)
311 do_interrupt(env);
fdf9b3e8
FB		 312#elif defined(TARGET_SH4)
313 do_interrupt(env);
eddf68a6
JM		 314#elif defined(TARGET_ALPHA)
315 do_interrupt(env);
f1ccf904
TS		 316#elif defined(TARGET_CRIS)
317 do_interrupt(env);
0633879f
PB		 318#elif defined(TARGET_M68K)
319 do_interrupt(0);
72d239ed 320#endif
83479e77 321#endif
3fb2ded1
FB		 322 }
323 env->exception_index = -1;
5fafdf24 324 }
640f42e4 325#ifdef CONFIG_KQEMU
be214e6c 326 if (kqemu_is_ok(env) && env->interrupt_request == 0 && env->exit_request == 0) {
9df217a3 327 int ret;
a7812ae4 328 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
9df217a3
FB		 329 ret = kqemu_cpu_exec(env);
330 /* put eflags in CPU temporary format */
331 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
332 DF = 1 - (2 * ((env->eflags >> 10) & 1));
333 CC_OP = CC_OP_EFLAGS;
334 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
335 if (ret == 1) {
336 /* exception */
337 longjmp(env->jmp_env, 1);
338 } else if (ret == 2) {
339 /* softmmu execution needed */
340 } else {
be214e6c 341 if (env->interrupt_request != 0 || env->exit_request != 0) {
9df217a3
FB		 342 /* hardware interrupt will be executed just after */
343 } else {
344 /* otherwise, we restart */
345 longjmp(env->jmp_env, 1);
346 }
347 }
3fb2ded1 348 }
9df217a3
FB		 349#endif
350
7ba1e619 351 if (kvm_enabled()) {
becfc390
AL		 352 kvm_cpu_exec(env);
353 longjmp(env->jmp_env, 1);
7ba1e619
AL		 354 }
355
b5fc09ae 356 next_tb = 0; /* force lookup of first TB */
3fb2ded1 357 for(;;) {
68a79315 358 interrupt_request = env->interrupt_request;
e1638bd8 359 if (unlikely(interrupt_request)) {
360 if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
361 /* Mask out external interrupts for this step. */
362 interrupt_request &= ~(CPU_INTERRUPT_HARD |
363 CPU_INTERRUPT_FIQ |
364 CPU_INTERRUPT_SMI |
365 CPU_INTERRUPT_NMI);
366 }
6658ffb8
PB		 367 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
368 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
369 env->exception_index = EXCP_DEBUG;
370 cpu_loop_exit();
371 }
a90b7318 372#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
b779e29e
EI		 373 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
374 defined(TARGET_MICROBLAZE)
a90b7318
AZ		 375 if (interrupt_request & CPU_INTERRUPT_HALT) {
376 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
377 env->halted = 1;
378 env->exception_index = EXCP_HLT;
379 cpu_loop_exit();
380 }
381#endif
68a79315 382#if defined(TARGET_I386)
b09ea7d5
GN		 383 if (interrupt_request & CPU_INTERRUPT_INIT) {
384 svm_check_intercept(SVM_EXIT_INIT);
385 do_cpu_init(env);
386 env->exception_index = EXCP_HALTED;
387 cpu_loop_exit();
388 } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
389 do_cpu_sipi(env);
390 } else if (env->hflags2 & HF2_GIF_MASK) {
db620f46
FB		 391 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
392 !(env->hflags & HF_SMM_MASK)) {
393 svm_check_intercept(SVM_EXIT_SMI);
394 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
395 do_smm_enter();
396 next_tb = 0;
397 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
398 !(env->hflags2 & HF2_NMI_MASK)) {
399 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
400 env->hflags2 |= HF2_NMI_MASK;
401 do_interrupt(EXCP02_NMI, 0, 0, 0, 1);
402 next_tb = 0;
403 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
404 (((env->hflags2 & HF2_VINTR_MASK) &&
405 (env->hflags2 & HF2_HIF_MASK)) ||
406 (!(env->hflags2 & HF2_VINTR_MASK) &&
407 (env->eflags & IF_MASK &&
408 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
409 int intno;
410 svm_check_intercept(SVM_EXIT_INTR);
411 env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
412 intno = cpu_get_pic_interrupt(env);
93fcfe39 413 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
9ddff3d2
BS		 414#if defined(__sparc__) && !defined(HOST_SOLARIS)
415#undef env
416 env = cpu_single_env;
417#define env cpu_single_env
418#endif
db620f46
FB		 419 do_interrupt(intno, 0, 0, 0, 1);
420 /* ensure that no TB jump will be modified as
421 the program flow was changed */
422 next_tb = 0;
0573fbfc 423#if !defined(CONFIG_USER_ONLY)
db620f46
FB		 424 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
425 (env->eflags & IF_MASK) &&
426 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
427 int intno;
428 /* FIXME: this should respect TPR */
429 svm_check_intercept(SVM_EXIT_VINTR);
db620f46 430 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
93fcfe39 431 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
db620f46 432 do_interrupt(intno, 0, 0, 0, 1);
d40c54d6 433 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
db620f46 434 next_tb = 0;
907a5b26 435#endif
db620f46 436 }
68a79315 437 }
ce09776b 438#elif defined(TARGET_PPC)
9fddaa0c
FB		 439#if 0
440 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
441 cpu_ppc_reset(env);
442 }
443#endif
47103572 444 if (interrupt_request & CPU_INTERRUPT_HARD) {
e9df014c
JM		 445 ppc_hw_interrupt(env);
446 if (env->pending_interrupts == 0)
447 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
b5fc09ae 448 next_tb = 0;
ce09776b 449 }
b779e29e
EI		 450#elif defined(TARGET_MICROBLAZE)
451 if ((interrupt_request & CPU_INTERRUPT_HARD)
452 && (env->sregs[SR_MSR] & MSR_IE)
453 && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
454 && !(env->iflags & (D_FLAG | IMM_FLAG))) {
455 env->exception_index = EXCP_IRQ;
456 do_interrupt(env);
457 next_tb = 0;
458 }
6af0bf9c
FB		 459#elif defined(TARGET_MIPS)
460 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
24c7b0e3 461 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
6af0bf9c 462 (env->CP0_Status & (1 << CP0St_IE)) &&
24c7b0e3
TS		 463 !(env->CP0_Status & (1 << CP0St_EXL)) &&
464 !(env->CP0_Status & (1 << CP0St_ERL)) &&
6af0bf9c
FB		 465 !(env->hflags & MIPS_HFLAG_DM)) {
466 /* Raise it */
467 env->exception_index = EXCP_EXT_INTERRUPT;
468 env->error_code = 0;
469 do_interrupt(env);
b5fc09ae 470 next_tb = 0;
6af0bf9c 471 }
e95c8d51 472#elif defined(TARGET_SPARC)
66321a11
FB		 473 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
474 (env->psret != 0)) {
475 int pil = env->interrupt_index & 15;
476 int type = env->interrupt_index & 0xf0;
477
478 if (((type == TT_EXTINT) &&
479 (pil == 15 || pil > env->psrpil)) ||
480 type != TT_EXTINT) {
481 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
f2bc7e7f
BS		 482 env->exception_index = env->interrupt_index;
483 do_interrupt(env);
66321a11 484 env->interrupt_index = 0;
327ac2e7
BS		 485#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
486 cpu_check_irqs(env);
487#endif
b5fc09ae 488 next_tb = 0;
66321a11 489 }
e95c8d51
FB		 490 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
491 //do_interrupt(0, 0, 0, 0, 0);
492 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
a90b7318 493 }
b5ff1b31
FB		 494#elif defined(TARGET_ARM)
495 if (interrupt_request & CPU_INTERRUPT_FIQ
496 && !(env->uncached_cpsr & CPSR_F)) {
497 env->exception_index = EXCP_FIQ;
498 do_interrupt(env);
b5fc09ae 499 next_tb = 0;
b5ff1b31 500 }
9ee6e8bb
PB		 501 /* ARMv7-M interrupt return works by loading a magic value
502 into the PC. On real hardware the load causes the
503 return to occur. The qemu implementation performs the
504 jump normally, then does the exception return when the
505 CPU tries to execute code at the magic address.
506 This will cause the magic PC value to be pushed to
507 the stack if an interrupt occured at the wrong time.
508 We avoid this by disabling interrupts when
509 pc contains a magic address. */
b5ff1b31 510 if (interrupt_request & CPU_INTERRUPT_HARD
9ee6e8bb
PB		 511 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
512 || !(env->uncached_cpsr & CPSR_I))) {
b5ff1b31
FB		 513 env->exception_index = EXCP_IRQ;
514 do_interrupt(env);
b5fc09ae 515 next_tb = 0;
b5ff1b31 516 }
fdf9b3e8 517#elif defined(TARGET_SH4)
e96e2044
TS		 518 if (interrupt_request & CPU_INTERRUPT_HARD) {
519 do_interrupt(env);
b5fc09ae 520 next_tb = 0;
e96e2044 521 }
eddf68a6
JM		 522#elif defined(TARGET_ALPHA)
523 if (interrupt_request & CPU_INTERRUPT_HARD) {
524 do_interrupt(env);
b5fc09ae 525 next_tb = 0;
eddf68a6 526 }
f1ccf904 527#elif defined(TARGET_CRIS)
1b1a38b0
EI		 528 if (interrupt_request & CPU_INTERRUPT_HARD
529 && (env->pregs[PR_CCS] & I_FLAG)) {
530 env->exception_index = EXCP_IRQ;
531 do_interrupt(env);
532 next_tb = 0;
533 }
534 if (interrupt_request & CPU_INTERRUPT_NMI
535 && (env->pregs[PR_CCS] & M_FLAG)) {
536 env->exception_index = EXCP_NMI;
f1ccf904 537 do_interrupt(env);
b5fc09ae 538 next_tb = 0;
f1ccf904 539 }
0633879f
PB		 540#elif defined(TARGET_M68K)
541 if (interrupt_request & CPU_INTERRUPT_HARD
542 && ((env->sr & SR_I) >> SR_I_SHIFT)
543 < env->pending_level) {
544 /* Real hardware gets the interrupt vector via an
545 IACK cycle at this point. Current emulated
546 hardware doesn't rely on this, so we
547 provide/save the vector when the interrupt is
548 first signalled. */
549 env->exception_index = env->pending_vector;
550 do_interrupt(1);
b5fc09ae 551 next_tb = 0;
0633879f 552 }
68a79315 553#endif
9d05095e
FB		 554 /* Don't use the cached interupt_request value,
555 do_interrupt may have updated the EXITTB flag. */
b5ff1b31 556 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bf3e8bf1
FB		 557 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
558 /* ensure that no TB jump will be modified as
559 the program flow was changed */
b5fc09ae 560 next_tb = 0;
bf3e8bf1 561 }
be214e6c
AJ		 562 }
563 if (unlikely(env->exit_request)) {
564 env->exit_request = 0;
565 env->exception_index = EXCP_INTERRUPT;
566 cpu_loop_exit();
3fb2ded1 567 }
7d13299d 568#ifdef DEBUG_EXEC
8fec2b8c 569 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
3fb2ded1 570 /* restore flags in standard format */
ecb644f4
TS		 571 regs_to_env();
572#if defined(TARGET_I386)
a7812ae4 573 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
93fcfe39 574 log_cpu_state(env, X86_DUMP_CCOP);
3fb2ded1 575 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 576#elif defined(TARGET_ARM)
93fcfe39 577 log_cpu_state(env, 0);
93ac68bc 578#elif defined(TARGET_SPARC)
93fcfe39 579 log_cpu_state(env, 0);
67867308 580#elif defined(TARGET_PPC)
93fcfe39 581 log_cpu_state(env, 0);
e6e5906b
PB		 582#elif defined(TARGET_M68K)
583 cpu_m68k_flush_flags(env, env->cc_op);
584 env->cc_op = CC_OP_FLAGS;
585 env->sr = (env->sr & 0xffe0)
586 | env->cc_dest | (env->cc_x << 4);
93fcfe39 587 log_cpu_state(env, 0);
b779e29e
EI		 588#elif defined(TARGET_MICROBLAZE)
589 log_cpu_state(env, 0);
6af0bf9c 590#elif defined(TARGET_MIPS)
93fcfe39 591 log_cpu_state(env, 0);
fdf9b3e8 592#elif defined(TARGET_SH4)
93fcfe39 593 log_cpu_state(env, 0);
eddf68a6 594#elif defined(TARGET_ALPHA)
93fcfe39 595 log_cpu_state(env, 0);
f1ccf904 596#elif defined(TARGET_CRIS)
93fcfe39 597 log_cpu_state(env, 0);
e4533c7a 598#else
5fafdf24 599#error unsupported target CPU
e4533c7a 600#endif
3fb2ded1 601 }
7d13299d 602#endif
d5975363 603 spin_lock(&tb_lock);
8a40a180 604 tb = tb_find_fast();
d5975363
PB		 605 /* Note: we do it here to avoid a gcc bug on Mac OS X when
606 doing it in tb_find_slow */
607 if (tb_invalidated_flag) {
608 /* as some TB could have been invalidated because
609 of memory exceptions while generating the code, we
610 must recompute the hash index here */
611 next_tb = 0;
2e70f6ef 612 tb_invalidated_flag = 0;
d5975363 613 }
9d27abd9 614#ifdef DEBUG_EXEC
93fcfe39
AL		 615 qemu_log_mask(CPU_LOG_EXEC, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
616 (long)tb->tc_ptr, tb->pc,
617 lookup_symbol(tb->pc));
9d27abd9 618#endif
8a40a180
FB		 619 /* see if we can patch the calling TB. When the TB
620 spans two pages, we cannot safely do a direct
621 jump. */
c27004ec 622 {
b5fc09ae 623 if (next_tb != 0 &&
640f42e4 624#ifdef CONFIG_KQEMU
f32fc648
FB		 625 (env->kqemu_enabled != 2) &&
626#endif
ec6338ba 627 tb->page_addr[1] == -1) {
b5fc09ae 628 tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
3fb2ded1 629 }
c27004ec 630 }
d5975363 631 spin_unlock(&tb_lock);
83479e77 632 env->current_tb = tb;
55e8b85e 633
634 /* cpu_interrupt might be called while translating the
635 TB, but before it is linked into a potentially
636 infinite loop and becomes env->current_tb. Avoid
637 starting execution if there is a pending interrupt. */
be214e6c 638 if (unlikely (env->exit_request))
55e8b85e 639 env->current_tb = NULL;
640
2e70f6ef
PB		 641 while (env->current_tb) {
642 tc_ptr = tb->tc_ptr;
3fb2ded1 643 /* execute the generated code */
572a9d4a
BS		 644#if defined(__sparc__) && !defined(HOST_SOLARIS)
645#undef env
2e70f6ef 646 env = cpu_single_env;
572a9d4a
BS		 647#define env cpu_single_env
648#endif
2e70f6ef
PB		 649 next_tb = tcg_qemu_tb_exec(tc_ptr);
650 env->current_tb = NULL;
651 if ((next_tb & 3) == 2) {
bf20dc07 652 /* Instruction counter expired. */
2e70f6ef
PB		 653 int insns_left;
654 tb = (TranslationBlock *)(long)(next_tb & ~3);
655 /* Restore PC. */
622ed360 656 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 657 insns_left = env->icount_decr.u32;
658 if (env->icount_extra && insns_left >= 0) {
659 /* Refill decrementer and continue execution. */
660 env->icount_extra += insns_left;
661 if (env->icount_extra > 0xffff) {
662 insns_left = 0xffff;
663 } else {
664 insns_left = env->icount_extra;
665 }
666 env->icount_extra -= insns_left;
667 env->icount_decr.u16.low = insns_left;
668 } else {
669 if (insns_left > 0) {
670 /* Execute remaining instructions. */
671 cpu_exec_nocache(insns_left, tb);
672 }
673 env->exception_index = EXCP_INTERRUPT;
674 next_tb = 0;
675 cpu_loop_exit();
676 }
677 }
678 }
4cbf74b6
FB		 679 /* reset soft MMU for next block (it can currently
680 only be set by a memory fault) */
640f42e4 681#if defined(CONFIG_KQEMU)
f32fc648
FB		 682#define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
683 if (kqemu_is_ok(env) &&
684 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
685 cpu_loop_exit();
686 }
4cbf74b6 687#endif
50a518e3 688 } /* for(;;) */
3fb2ded1 689 } else {
0d1a29f9 690 env_to_regs();
7d13299d 691 }
3fb2ded1
FB		 692 } /* for(;;) */
693
7d13299d 694
e4533c7a 695#if defined(TARGET_I386)
9de5e440 696 /* restore flags in standard format */
a7812ae4 697 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
e4533c7a 698#elif defined(TARGET_ARM)
b7bcbe95 699 /* XXX: Save/restore host fpu exception state?. */
93ac68bc 700#elif defined(TARGET_SPARC)
67867308 701#elif defined(TARGET_PPC)
e6e5906b
PB		 702#elif defined(TARGET_M68K)
703 cpu_m68k_flush_flags(env, env->cc_op);
704 env->cc_op = CC_OP_FLAGS;
705 env->sr = (env->sr & 0xffe0)
706 | env->cc_dest | (env->cc_x << 4);
b779e29e 707#elif defined(TARGET_MICROBLAZE)
6af0bf9c 708#elif defined(TARGET_MIPS)
fdf9b3e8 709#elif defined(TARGET_SH4)
eddf68a6 710#elif defined(TARGET_ALPHA)
f1ccf904 711#elif defined(TARGET_CRIS)
fdf9b3e8 712 /* XXXXX */
e4533c7a
FB		 713#else
714#error unsupported target CPU
715#endif
1057eaa7
PB		 716
717 /* restore global registers */
1057eaa7
PB		 718#include "hostregs_helper.h"
719
6a00d601 720 /* fail safe : never use cpu_single_env outside cpu_exec() */
5fafdf24 721 cpu_single_env = NULL;
7d13299d
FB		 722 return ret;
723}
6dbad63e 724
fbf9eeb3
FB		 725/* must only be called from the generated code as an exception can be
726 generated */
727void tb_invalidate_page_range(target_ulong start, target_ulong end)
728{
dc5d0b3d
FB		 729 /* XXX: cannot enable it yet because it yields to MMU exception
730 where NIP != read address on PowerPC */
731#if 0
fbf9eeb3
FB		 732 target_ulong phys_addr;
733 phys_addr = get_phys_addr_code(env, start);
734 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
dc5d0b3d 735#endif
fbf9eeb3
FB		 736}
737
1a18c71b 738#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
e4533c7a 739
6dbad63e
FB		 740void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
741{
742 CPUX86State *saved_env;
743
744 saved_env = env;
745 env = s;
a412ac57 746 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
a513fe19 747 selector &= 0xffff;
5fafdf24 748 cpu_x86_load_seg_cache(env, seg_reg, selector,
c27004ec 749 (selector << 4), 0xffff, 0);
a513fe19 750 } else {
5d97559d 751 helper_load_seg(seg_reg, selector);
a513fe19 752 }
6dbad63e
FB		 753 env = saved_env;
754}
9de5e440 755
6f12a2a6 756void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32)
d0a1ffc9
FB		 757{
758 CPUX86State *saved_env;
759
760 saved_env = env;
761 env = s;
3b46e624 762
6f12a2a6 763 helper_fsave(ptr, data32);
d0a1ffc9
FB		 764
765 env = saved_env;
766}
767
6f12a2a6 768void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32)
d0a1ffc9
FB		 769{
770 CPUX86State *saved_env;
771
772 saved_env = env;
773 env = s;
3b46e624 774
6f12a2a6 775 helper_frstor(ptr, data32);
d0a1ffc9
FB		 776
777 env = saved_env;
778}
779
e4533c7a
FB		 780#endif /* TARGET_I386 */
781
67b915a5
FB		 782#if !defined(CONFIG_SOFTMMU)
783
3fb2ded1
FB		 784#if defined(TARGET_I386)
785
b56dad1c 786/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6
FB		 787 the effective address of the memory exception. 'is_write' is 1 if a
788 write caused the exception and otherwise 0'. 'old_set' is the
789 signal set which should be restored */
2b413144 790static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
5fafdf24 791 int is_write, sigset_t *old_set,
bf3e8bf1 792 void *puc)
9de5e440 793{
a513fe19
FB		 794 TranslationBlock *tb;
795 int ret;
68a79315 796
83479e77
FB		 797 if (cpu_single_env)
798 env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6 799#if defined(DEBUG_SIGNAL)
5fafdf24 800 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
bf3e8bf1 801 pc, address, is_write, *(unsigned long *)old_set);
9de5e440 802#endif
25eb4484 803 /* XXX: locking issue */
53a5960a 804 if (is_write && page_unprotect(h2g(address), pc, puc)) {
fd6ce8f6
FB		 805 return 1;
806 }
fbf9eeb3 807
3fb2ded1 808 /* see if it is an MMU fault */
6ebbf390 809 ret = cpu_x86_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
3fb2ded1
FB		 810 if (ret < 0)
811 return 0; /* not an MMU fault */
812 if (ret == 0)
813 return 1; /* the MMU fault was handled without causing real CPU fault */
814 /* now we have a real cpu fault */
a513fe19
FB		 815 tb = tb_find_pc(pc);
816 if (tb) {
9de5e440
FB		 817 /* the PC is inside the translated code. It means that we have
818 a virtual CPU fault */
bf3e8bf1 819 cpu_restore_state(tb, env, pc, puc);
3fb2ded1 820 }
4cbf74b6 821 if (ret == 1) {
3fb2ded1 822#if 0
5fafdf24 823 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
4cbf74b6 824 env->eip, env->cr[2], env->error_code);
3fb2ded1 825#endif
4cbf74b6
FB		 826 /* we restore the process signal mask as the sigreturn should
827 do it (XXX: use sigsetjmp) */
828 sigprocmask(SIG_SETMASK, old_set, NULL);
54ca9095 829 raise_exception_err(env->exception_index, env->error_code);
4cbf74b6
FB		 830 } else {
831 /* activate soft MMU for this block */
3f337316 832 env->hflags |= HF_SOFTMMU_MASK;
fbf9eeb3 833 cpu_resume_from_signal(env, puc);
4cbf74b6 834 }
3fb2ded1
FB		 835 /* never comes here */
836 return 1;
837}
838
e4533c7a 839#elif defined(TARGET_ARM)
3fb2ded1 840static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 841 int is_write, sigset_t *old_set,
842 void *puc)
3fb2ded1 843{
68016c62
FB		 844 TranslationBlock *tb;
845 int ret;
846
847 if (cpu_single_env)
848 env = cpu_single_env; /* XXX: find a correct solution for multithread */
849#if defined(DEBUG_SIGNAL)
5fafdf24 850 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
68016c62
FB		 851 pc, address, is_write, *(unsigned long *)old_set);
852#endif
9f0777ed 853 /* XXX: locking issue */
53a5960a 854 if (is_write && page_unprotect(h2g(address), pc, puc)) {
9f0777ed
FB		 855 return 1;
856 }
68016c62 857 /* see if it is an MMU fault */
6ebbf390 858 ret = cpu_arm_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
68016c62
FB		 859 if (ret < 0)
860 return 0; /* not an MMU fault */
861 if (ret == 0)
862 return 1; /* the MMU fault was handled without causing real CPU fault */
863 /* now we have a real cpu fault */
864 tb = tb_find_pc(pc);
865 if (tb) {
866 /* the PC is inside the translated code. It means that we have
867 a virtual CPU fault */
868 cpu_restore_state(tb, env, pc, puc);
869 }
870 /* we restore the process signal mask as the sigreturn should
871 do it (XXX: use sigsetjmp) */
872 sigprocmask(SIG_SETMASK, old_set, NULL);
873 cpu_loop_exit();
968c74da
AJ		 874 /* never comes here */
875 return 1;
3fb2ded1 876}
93ac68bc
FB		 877#elif defined(TARGET_SPARC)
878static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 879 int is_write, sigset_t *old_set,
880 void *puc)
93ac68bc 881{
68016c62
FB		 882 TranslationBlock *tb;
883 int ret;
884
885 if (cpu_single_env)
886 env = cpu_single_env; /* XXX: find a correct solution for multithread */
887#if defined(DEBUG_SIGNAL)
5fafdf24 888 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
68016c62
FB		 889 pc, address, is_write, *(unsigned long *)old_set);
890#endif
b453b70b 891 /* XXX: locking issue */
53a5960a 892 if (is_write && page_unprotect(h2g(address), pc, puc)) {
b453b70b
FB		 893 return 1;
894 }
68016c62 895 /* see if it is an MMU fault */
6ebbf390 896 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
68016c62
FB		 897 if (ret < 0)
898 return 0; /* not an MMU fault */
899 if (ret == 0)
900 return 1; /* the MMU fault was handled without causing real CPU fault */
901 /* now we have a real cpu fault */
902 tb = tb_find_pc(pc);
903 if (tb) {
904 /* the PC is inside the translated code. It means that we have
905 a virtual CPU fault */
906 cpu_restore_state(tb, env, pc, puc);
907 }
908 /* we restore the process signal mask as the sigreturn should
909 do it (XXX: use sigsetjmp) */
910 sigprocmask(SIG_SETMASK, old_set, NULL);
911 cpu_loop_exit();
968c74da
AJ		 912 /* never comes here */
913 return 1;
93ac68bc 914}
67867308
FB		 915#elif defined (TARGET_PPC)
916static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 917 int is_write, sigset_t *old_set,
918 void *puc)
67867308
FB		 919{
920 TranslationBlock *tb;
ce09776b 921 int ret;
3b46e624 922
67867308
FB		 923 if (cpu_single_env)
924 env = cpu_single_env; /* XXX: find a correct solution for multithread */
67867308 925#if defined(DEBUG_SIGNAL)
5fafdf24 926 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
67867308
FB		 927 pc, address, is_write, *(unsigned long *)old_set);
928#endif
929 /* XXX: locking issue */
53a5960a 930 if (is_write && page_unprotect(h2g(address), pc, puc)) {
67867308
FB		 931 return 1;
932 }
933
ce09776b 934 /* see if it is an MMU fault */
6ebbf390 935 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
ce09776b
FB		 936 if (ret < 0)
937 return 0; /* not an MMU fault */
938 if (ret == 0)
939 return 1; /* the MMU fault was handled without causing real CPU fault */
940
67867308
FB		 941 /* now we have a real cpu fault */
942 tb = tb_find_pc(pc);
943 if (tb) {
944 /* the PC is inside the translated code. It means that we have
945 a virtual CPU fault */
bf3e8bf1 946 cpu_restore_state(tb, env, pc, puc);
67867308 947 }
ce09776b 948 if (ret == 1) {
67867308 949#if 0
5fafdf24 950 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
ce09776b 951 env->nip, env->error_code, tb);
67867308
FB		 952#endif
953 /* we restore the process signal mask as the sigreturn should
954 do it (XXX: use sigsetjmp) */
bf3e8bf1 955 sigprocmask(SIG_SETMASK, old_set, NULL);
e06fcd75 956 cpu_loop_exit();
ce09776b
FB		 957 } else {
958 /* activate soft MMU for this block */
fbf9eeb3 959 cpu_resume_from_signal(env, puc);
ce09776b 960 }
67867308 961 /* never comes here */
e6e5906b
PB		 962 return 1;
963}
964
965#elif defined(TARGET_M68K)
966static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
967 int is_write, sigset_t *old_set,
968 void *puc)
969{
970 TranslationBlock *tb;
971 int ret;
972
973 if (cpu_single_env)
974 env = cpu_single_env; /* XXX: find a correct solution for multithread */
975#if defined(DEBUG_SIGNAL)
5fafdf24 976 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
e6e5906b
PB		 977 pc, address, is_write, *(unsigned long *)old_set);
978#endif
979 /* XXX: locking issue */
980 if (is_write && page_unprotect(address, pc, puc)) {
981 return 1;
982 }
983 /* see if it is an MMU fault */
6ebbf390 984 ret = cpu_m68k_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
e6e5906b
PB		 985 if (ret < 0)
986 return 0; /* not an MMU fault */
987 if (ret == 0)
988 return 1; /* the MMU fault was handled without causing real CPU fault */
989 /* now we have a real cpu fault */
990 tb = tb_find_pc(pc);
991 if (tb) {
992 /* the PC is inside the translated code. It means that we have
993 a virtual CPU fault */
994 cpu_restore_state(tb, env, pc, puc);
995 }
996 /* we restore the process signal mask as the sigreturn should
997 do it (XXX: use sigsetjmp) */
998 sigprocmask(SIG_SETMASK, old_set, NULL);
999 cpu_loop_exit();
1000 /* never comes here */
67867308
FB		 1001 return 1;
1002}
6af0bf9c
FB		 1003
1004#elif defined (TARGET_MIPS)
1005static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1006 int is_write, sigset_t *old_set,
1007 void *puc)
1008{
1009 TranslationBlock *tb;
1010 int ret;
3b46e624 1011
6af0bf9c
FB		 1012 if (cpu_single_env)
1013 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1014#if defined(DEBUG_SIGNAL)
5fafdf24 1015 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
6af0bf9c
FB		 1016 pc, address, is_write, *(unsigned long *)old_set);
1017#endif
1018 /* XXX: locking issue */
53a5960a 1019 if (is_write && page_unprotect(h2g(address), pc, puc)) {
6af0bf9c
FB		 1020 return 1;
1021 }
1022
1023 /* see if it is an MMU fault */
6ebbf390 1024 ret = cpu_mips_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
6af0bf9c
FB		 1025 if (ret < 0)
1026 return 0; /* not an MMU fault */
1027 if (ret == 0)
1028 return 1; /* the MMU fault was handled without causing real CPU fault */
1029
1030 /* now we have a real cpu fault */
1031 tb = tb_find_pc(pc);
1032 if (tb) {
1033 /* the PC is inside the translated code. It means that we have
1034 a virtual CPU fault */
1035 cpu_restore_state(tb, env, pc, puc);
1036 }
1037 if (ret == 1) {
1038#if 0
5fafdf24 1039 printf("PF exception: PC=0x" TARGET_FMT_lx " error=0x%x %p\n",
1eb5207b 1040 env->PC, env->error_code, tb);
b779e29e
EI		 1041#endif
1042 /* we restore the process signal mask as the sigreturn should
1043 do it (XXX: use sigsetjmp) */
1044 sigprocmask(SIG_SETMASK, old_set, NULL);
1045 cpu_loop_exit();
1046 } else {
1047 /* activate soft MMU for this block */
1048 cpu_resume_from_signal(env, puc);
1049 }
1050 /* never comes here */
1051 return 1;
1052}
1053
1054#elif defined (TARGET_MICROBLAZE)
1055static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1056 int is_write, sigset_t *old_set,
1057 void *puc)
1058{
1059 TranslationBlock *tb;
1060 int ret;
1061
1062 if (cpu_single_env)
1063 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1064#if defined(DEBUG_SIGNAL)
1065 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1066 pc, address, is_write, *(unsigned long *)old_set);
1067#endif
1068 /* XXX: locking issue */
1069 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1070 return 1;
1071 }
1072
1073 /* see if it is an MMU fault */
1074 ret = cpu_mb_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
1075 if (ret < 0)
1076 return 0; /* not an MMU fault */
1077 if (ret == 0)
1078 return 1; /* the MMU fault was handled without causing real CPU fault */
1079
1080 /* now we have a real cpu fault */
1081 tb = tb_find_pc(pc);
1082 if (tb) {
1083 /* the PC is inside the translated code. It means that we have
1084 a virtual CPU fault */
1085 cpu_restore_state(tb, env, pc, puc);
1086 }
1087 if (ret == 1) {
1088#if 0
1089 printf("PF exception: PC=0x" TARGET_FMT_lx " error=0x%x %p\n",
1090 env->PC, env->error_code, tb);
6af0bf9c
FB		 1091#endif
1092 /* we restore the process signal mask as the sigreturn should
1093 do it (XXX: use sigsetjmp) */
1094 sigprocmask(SIG_SETMASK, old_set, NULL);
f9480ffc 1095 cpu_loop_exit();
6af0bf9c
FB		 1096 } else {
1097 /* activate soft MMU for this block */
1098 cpu_resume_from_signal(env, puc);
1099 }
1100 /* never comes here */
1101 return 1;
1102}
1103
fdf9b3e8
FB		 1104#elif defined (TARGET_SH4)
1105static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1106 int is_write, sigset_t *old_set,
1107 void *puc)
1108{
1109 TranslationBlock *tb;
1110 int ret;
3b46e624 1111
fdf9b3e8
FB		 1112 if (cpu_single_env)
1113 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1114#if defined(DEBUG_SIGNAL)
5fafdf24 1115 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
fdf9b3e8
FB		 1116 pc, address, is_write, *(unsigned long *)old_set);
1117#endif
1118 /* XXX: locking issue */
1119 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1120 return 1;
1121 }
1122
1123 /* see if it is an MMU fault */
6ebbf390 1124 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
fdf9b3e8
FB		 1125 if (ret < 0)
1126 return 0; /* not an MMU fault */
1127 if (ret == 0)
1128 return 1; /* the MMU fault was handled without causing real CPU fault */
1129
1130 /* now we have a real cpu fault */
eddf68a6
JM		 1131 tb = tb_find_pc(pc);
1132 if (tb) {
1133 /* the PC is inside the translated code. It means that we have
1134 a virtual CPU fault */
1135 cpu_restore_state(tb, env, pc, puc);
1136 }
1137#if 0
5fafdf24 1138 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
eddf68a6
JM		 1139 env->nip, env->error_code, tb);
1140#endif
1141 /* we restore the process signal mask as the sigreturn should
1142 do it (XXX: use sigsetjmp) */
1143 sigprocmask(SIG_SETMASK, old_set, NULL);
1144 cpu_loop_exit();
1145 /* never comes here */
1146 return 1;
1147}
1148
1149#elif defined (TARGET_ALPHA)
1150static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1151 int is_write, sigset_t *old_set,
1152 void *puc)
1153{
1154 TranslationBlock *tb;
1155 int ret;
3b46e624 1156
eddf68a6
JM		 1157 if (cpu_single_env)
1158 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1159#if defined(DEBUG_SIGNAL)
5fafdf24 1160 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
eddf68a6
JM		 1161 pc, address, is_write, *(unsigned long *)old_set);
1162#endif
1163 /* XXX: locking issue */
1164 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1165 return 1;
1166 }
1167
1168 /* see if it is an MMU fault */
6ebbf390 1169 ret = cpu_alpha_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
eddf68a6
JM		 1170 if (ret < 0)
1171 return 0; /* not an MMU fault */
1172 if (ret == 0)
1173 return 1; /* the MMU fault was handled without causing real CPU fault */
1174
1175 /* now we have a real cpu fault */
fdf9b3e8
FB		 1176 tb = tb_find_pc(pc);
1177 if (tb) {
1178 /* the PC is inside the translated code. It means that we have
1179 a virtual CPU fault */
1180 cpu_restore_state(tb, env, pc, puc);
1181 }
fdf9b3e8 1182#if 0
5fafdf24 1183 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
fdf9b3e8
FB		 1184 env->nip, env->error_code, tb);
1185#endif
1186 /* we restore the process signal mask as the sigreturn should
1187 do it (XXX: use sigsetjmp) */
355fb23d
PB		 1188 sigprocmask(SIG_SETMASK, old_set, NULL);
1189 cpu_loop_exit();
fdf9b3e8
FB		 1190 /* never comes here */
1191 return 1;
1192}
f1ccf904
TS		 1193#elif defined (TARGET_CRIS)
1194static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1195 int is_write, sigset_t *old_set,
1196 void *puc)
1197{
1198 TranslationBlock *tb;
1199 int ret;
1200
1201 if (cpu_single_env)
1202 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1203#if defined(DEBUG_SIGNAL)
1204 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1205 pc, address, is_write, *(unsigned long *)old_set);
1206#endif
1207 /* XXX: locking issue */
1208 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1209 return 1;
1210 }
1211
1212 /* see if it is an MMU fault */
6ebbf390 1213 ret = cpu_cris_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
f1ccf904
TS		 1214 if (ret < 0)
1215 return 0; /* not an MMU fault */
1216 if (ret == 0)
1217 return 1; /* the MMU fault was handled without causing real CPU fault */
1218
1219 /* now we have a real cpu fault */
1220 tb = tb_find_pc(pc);
1221 if (tb) {
1222 /* the PC is inside the translated code. It means that we have
1223 a virtual CPU fault */
1224 cpu_restore_state(tb, env, pc, puc);
1225 }
f1ccf904
TS		 1226 /* we restore the process signal mask as the sigreturn should
1227 do it (XXX: use sigsetjmp) */
1228 sigprocmask(SIG_SETMASK, old_set, NULL);
1229 cpu_loop_exit();
1230 /* never comes here */
1231 return 1;
1232}
1233
e4533c7a
FB		 1234#else
1235#error unsupported target CPU
1236#endif
9de5e440 1237
2b413144
FB		 1238#if defined(__i386__)
1239
d8ecc0b9
FB		 1240#if defined(__APPLE__)
1241# include <sys/ucontext.h>
1242
1243# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1244# define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
1245# define ERROR_sig(context) ((context)->uc_mcontext->es.err)
d39bb24a
BS		 1246# define MASK_sig(context) ((context)->uc_sigmask)
1247#elif defined(__OpenBSD__)
1248# define EIP_sig(context) ((context)->sc_eip)
1249# define TRAP_sig(context) ((context)->sc_trapno)
1250# define ERROR_sig(context) ((context)->sc_err)
1251# define MASK_sig(context) ((context)->sc_mask)
d8ecc0b9
FB		 1252#else
1253# define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
1254# define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1255# define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
d39bb24a 1256# define MASK_sig(context) ((context)->uc_sigmask)
d8ecc0b9
FB		 1257#endif
1258
5fafdf24 1259int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1260 void *puc)
9de5e440 1261{
5a7b542b 1262 siginfo_t *info = pinfo;
d39bb24a
BS		 1263#if defined(__OpenBSD__)
1264 struct sigcontext *uc = puc;
1265#else
9de5e440 1266 struct ucontext *uc = puc;
d39bb24a 1267#endif
9de5e440 1268 unsigned long pc;
bf3e8bf1 1269 int trapno;
97eb5b14 1270
d691f669
FB		 1271#ifndef REG_EIP
1272/* for glibc 2.1 */
fd6ce8f6
FB		 1273#define REG_EIP EIP
1274#define REG_ERR ERR
1275#define REG_TRAPNO TRAPNO
d691f669 1276#endif
d8ecc0b9
FB		 1277 pc = EIP_sig(uc);
1278 trapno = TRAP_sig(uc);
ec6338ba
FB		 1279 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1280 trapno == 0xe ?
1281 (ERROR_sig(uc) >> 1) & 1 : 0,
d39bb24a 1282 &MASK_sig(uc), puc);
2b413144
FB		 1283}
1284
bc51c5c9
FB		 1285#elif defined(__x86_64__)
1286
b3efe5c8 1287#ifdef __NetBSD__
d397abbd
BS		 1288#define PC_sig(context) _UC_MACHINE_PC(context)
1289#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
1290#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
1291#define MASK_sig(context) ((context)->uc_sigmask)
1292#elif defined(__OpenBSD__)
1293#define PC_sig(context) ((context)->sc_rip)
1294#define TRAP_sig(context) ((context)->sc_trapno)
1295#define ERROR_sig(context) ((context)->sc_err)
1296#define MASK_sig(context) ((context)->sc_mask)
b3efe5c8 1297#else
d397abbd
BS		 1298#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
1299#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1300#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1301#define MASK_sig(context) ((context)->uc_sigmask)
b3efe5c8
BS		 1302#endif
1303
5a7b542b 1304int cpu_signal_handler(int host_signum, void *pinfo,
bc51c5c9
FB		 1305 void *puc)
1306{
5a7b542b 1307 siginfo_t *info = pinfo;
bc51c5c9 1308 unsigned long pc;
b3efe5c8
BS		 1309#ifdef __NetBSD__
1310 ucontext_t *uc = puc;
d397abbd
BS		 1311#elif defined(__OpenBSD__)
1312 struct sigcontext *uc = puc;
b3efe5c8
BS		 1313#else
1314 struct ucontext *uc = puc;
1315#endif
bc51c5c9 1316
d397abbd 1317 pc = PC_sig(uc);
5fafdf24 1318 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
d397abbd
BS		 1319 TRAP_sig(uc) == 0xe ?
1320 (ERROR_sig(uc) >> 1) & 1 : 0,
1321 &MASK_sig(uc), puc);
bc51c5c9
FB		 1322}
1323
e58ffeb3 1324#elif defined(_ARCH_PPC)
2b413144 1325
83fb7adf
FB		 1326/***********************************************************************
1327 * signal context platform-specific definitions
1328 * From Wine
1329 */
1330#ifdef linux
1331/* All Registers access - only for local access */
1332# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1333/* Gpr Registers access */
1334# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1335# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1336# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1337# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1338# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1339# define LR_sig(context) REG_sig(link, context) /* Link register */
1340# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1341/* Float Registers access */
1342# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1343# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1344/* Exception Registers access */
1345# define DAR_sig(context) REG_sig(dar, context)
1346# define DSISR_sig(context) REG_sig(dsisr, context)
1347# define TRAP_sig(context) REG_sig(trap, context)
1348#endif /* linux */
1349
1350#ifdef __APPLE__
1351# include <sys/ucontext.h>
1352typedef struct ucontext SIGCONTEXT;
1353/* All Registers access - only for local access */
1354# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1355# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1356# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1357# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1358/* Gpr Registers access */
1359# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1360# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1361# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1362# define CTR_sig(context) REG_sig(ctr, context)
1363# define XER_sig(context) REG_sig(xer, context) /* Link register */
1364# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1365# define CR_sig(context) REG_sig(cr, context) /* Condition register */
1366/* Float Registers access */
1367# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1368# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1369/* Exception Registers access */
1370# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1371# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1372# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1373#endif /* __APPLE__ */
1374
5fafdf24 1375int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1376 void *puc)
2b413144 1377{
5a7b542b 1378 siginfo_t *info = pinfo;
25eb4484 1379 struct ucontext *uc = puc;
25eb4484 1380 unsigned long pc;
25eb4484
FB		 1381 int is_write;
1382
83fb7adf 1383 pc = IAR_sig(uc);
25eb4484
FB		 1384 is_write = 0;
1385#if 0
1386 /* ppc 4xx case */
83fb7adf 1387 if (DSISR_sig(uc) & 0x00800000)
25eb4484
FB		 1388 is_write = 1;
1389#else
83fb7adf 1390 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
25eb4484
FB		 1391 is_write = 1;
1392#endif
5fafdf24 1393 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1394 is_write, &uc->uc_sigmask, puc);
2b413144
FB		 1395}
1396
2f87c607
FB		 1397#elif defined(__alpha__)
1398
5fafdf24 1399int cpu_signal_handler(int host_signum, void *pinfo,
2f87c607
FB		 1400 void *puc)
1401{
5a7b542b 1402 siginfo_t *info = pinfo;
2f87c607
FB		 1403 struct ucontext *uc = puc;
1404 uint32_t *pc = uc->uc_mcontext.sc_pc;
1405 uint32_t insn = *pc;
1406 int is_write = 0;
1407
8c6939c0 1408 /* XXX: need kernel patch to get write flag faster */
2f87c607
FB		 1409 switch (insn >> 26) {
1410 case 0x0d: // stw
1411 case 0x0e: // stb
1412 case 0x0f: // stq_u
1413 case 0x24: // stf
1414 case 0x25: // stg
1415 case 0x26: // sts
1416 case 0x27: // stt
1417 case 0x2c: // stl
1418 case 0x2d: // stq
1419 case 0x2e: // stl_c
1420 case 0x2f: // stq_c
1421 is_write = 1;
1422 }
1423
5fafdf24 1424 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1425 is_write, &uc->uc_sigmask, puc);
2f87c607 1426}
8c6939c0
FB		 1427#elif defined(__sparc__)
1428
5fafdf24 1429int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1430 void *puc)
8c6939c0 1431{
5a7b542b 1432 siginfo_t *info = pinfo;
8c6939c0
FB		 1433 int is_write;
1434 uint32_t insn;
6b4c11cd 1435#if !defined(__arch64__) || defined(HOST_SOLARIS)
c9e1e2b0
BS		 1436 uint32_t *regs = (uint32_t *)(info + 1);
1437 void *sigmask = (regs + 20);
8c6939c0 1438 /* XXX: is there a standard glibc define ? */
c9e1e2b0
BS		 1439 unsigned long pc = regs[1];
1440#else
84778508 1441#ifdef __linux__
c9e1e2b0
BS		 1442 struct sigcontext *sc = puc;
1443 unsigned long pc = sc->sigc_regs.tpc;
1444 void *sigmask = (void *)sc->sigc_mask;
84778508
BS		 1445#elif defined(__OpenBSD__)
1446 struct sigcontext *uc = puc;
1447 unsigned long pc = uc->sc_pc;
1448 void *sigmask = (void *)(long)uc->sc_mask;
1449#endif
c9e1e2b0
BS		 1450#endif
1451
8c6939c0
FB		 1452 /* XXX: need kernel patch to get write flag faster */
1453 is_write = 0;
1454 insn = *(uint32_t *)pc;
1455 if ((insn >> 30) == 3) {
1456 switch((insn >> 19) & 0x3f) {
1457 case 0x05: // stb
d877fa5a 1458 case 0x15: // stba
8c6939c0 1459 case 0x06: // sth
d877fa5a 1460 case 0x16: // stha
8c6939c0 1461 case 0x04: // st
d877fa5a 1462 case 0x14: // sta
8c6939c0 1463 case 0x07: // std
d877fa5a
BS		 1464 case 0x17: // stda
1465 case 0x0e: // stx
1466 case 0x1e: // stxa
8c6939c0 1467 case 0x24: // stf
d877fa5a 1468 case 0x34: // stfa
8c6939c0 1469 case 0x27: // stdf
d877fa5a
BS		 1470 case 0x37: // stdfa
1471 case 0x26: // stqf
1472 case 0x36: // stqfa
8c6939c0 1473 case 0x25: // stfsr
d877fa5a
BS		 1474 case 0x3c: // casa
1475 case 0x3e: // casxa
8c6939c0
FB		 1476 is_write = 1;
1477 break;
1478 }
1479 }
5fafdf24 1480 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1481 is_write, sigmask, NULL);
8c6939c0
FB		 1482}
1483
1484#elif defined(__arm__)
1485
5fafdf24 1486int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1487 void *puc)
8c6939c0 1488{
5a7b542b 1489 siginfo_t *info = pinfo;
8c6939c0
FB		 1490 struct ucontext *uc = puc;
1491 unsigned long pc;
1492 int is_write;
3b46e624 1493
48bbf11b 1494#if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
5c49b363
AZ		 1495 pc = uc->uc_mcontext.gregs[R15];
1496#else
4eee57f5 1497 pc = uc->uc_mcontext.arm_pc;
5c49b363 1498#endif
8c6939c0
FB		 1499 /* XXX: compute is_write */
1500 is_write = 0;
5fafdf24 1501 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
8c6939c0 1502 is_write,
f3a9676a 1503 &uc->uc_sigmask, puc);
8c6939c0
FB		 1504}
1505
38e584a0
FB		 1506#elif defined(__mc68000)
1507
5fafdf24 1508int cpu_signal_handler(int host_signum, void *pinfo,
38e584a0
FB		 1509 void *puc)
1510{
5a7b542b 1511 siginfo_t *info = pinfo;
38e584a0
FB		 1512 struct ucontext *uc = puc;
1513 unsigned long pc;
1514 int is_write;
3b46e624 1515
38e584a0
FB		 1516 pc = uc->uc_mcontext.gregs[16];
1517 /* XXX: compute is_write */
1518 is_write = 0;
5fafdf24 1519 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
38e584a0 1520 is_write,
bf3e8bf1 1521 &uc->uc_sigmask, puc);
38e584a0
FB		 1522}
1523
b8076a74
FB		 1524#elif defined(__ia64)
1525
1526#ifndef __ISR_VALID
1527 /* This ought to be in <bits/siginfo.h>... */
1528# define __ISR_VALID 1
b8076a74
FB		 1529#endif
1530
5a7b542b 1531int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
b8076a74 1532{
5a7b542b 1533 siginfo_t *info = pinfo;
b8076a74
FB		 1534 struct ucontext *uc = puc;
1535 unsigned long ip;
1536 int is_write = 0;
1537
1538 ip = uc->uc_mcontext.sc_ip;
1539 switch (host_signum) {
1540 case SIGILL:
1541 case SIGFPE:
1542 case SIGSEGV:
1543 case SIGBUS:
1544 case SIGTRAP:
fd4a43e4 1545 if (info->si_code && (info->si_segvflags & __ISR_VALID))
b8076a74
FB		 1546 /* ISR.W (write-access) is bit 33: */
1547 is_write = (info->si_isr >> 33) & 1;
1548 break;
1549
1550 default:
1551 break;
1552 }
1553 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1554 is_write,
1555 &uc->uc_sigmask, puc);
1556}
1557
90cb9493
FB		 1558#elif defined(__s390__)
1559
5fafdf24 1560int cpu_signal_handler(int host_signum, void *pinfo,
90cb9493
FB		 1561 void *puc)
1562{
5a7b542b 1563 siginfo_t *info = pinfo;
90cb9493
FB		 1564 struct ucontext *uc = puc;
1565 unsigned long pc;
1566 int is_write;
3b46e624 1567
90cb9493
FB		 1568 pc = uc->uc_mcontext.psw.addr;
1569 /* XXX: compute is_write */
1570 is_write = 0;
5fafdf24 1571 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
c4b89d18
TS		 1572 is_write, &uc->uc_sigmask, puc);
1573}
1574
1575#elif defined(__mips__)
1576
5fafdf24 1577int cpu_signal_handler(int host_signum, void *pinfo,
c4b89d18
TS		 1578 void *puc)
1579{
9617efe8 1580 siginfo_t *info = pinfo;
c4b89d18
TS		 1581 struct ucontext *uc = puc;
1582 greg_t pc = uc->uc_mcontext.pc;
1583 int is_write;
3b46e624 1584
c4b89d18
TS		 1585 /* XXX: compute is_write */
1586 is_write = 0;
5fafdf24 1587 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
c4b89d18 1588 is_write, &uc->uc_sigmask, puc);
90cb9493
FB		 1589}
1590
f54b3f92
AJ		 1591#elif defined(__hppa__)
1592
1593int cpu_signal_handler(int host_signum, void *pinfo,
1594 void *puc)
1595{
1596 struct siginfo *info = pinfo;
1597 struct ucontext *uc = puc;
1598 unsigned long pc;
1599 int is_write;
1600
1601 pc = uc->uc_mcontext.sc_iaoq[0];
1602 /* FIXME: compute is_write */
1603 is_write = 0;
1604 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1605 is_write,
1606 &uc->uc_sigmask, puc);
1607}
1608
9de5e440 1609#else
2b413144 1610
3fb2ded1 1611#error host CPU specific signal handler needed
2b413144 1612
9de5e440 1613#endif
67b915a5
FB		 1614
1615#endif /* !defined(CONFIG_SOFTMMU) */
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