[qemu.git] / include / exec / softmmu_template.h

/*
 *  Software MMU support
 *
 * Generate helpers used by TCG for qemu_ld/st ops and code load
 * functions.
 *
 * Included from target op helpers and exec.c.
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#include "qemu/timer.h"
#include "exec/memory.h"

#define DATA_SIZE (1 << SHIFT)

#if DATA_SIZE == 8
#define SUFFIX q
#define USUFFIX q
#define DATA_TYPE uint64_t
#elif DATA_SIZE == 4
#define SUFFIX l
#define USUFFIX l
#define DATA_TYPE uint32_t
#elif DATA_SIZE == 2
#define SUFFIX w
#define USUFFIX uw
#define DATA_TYPE uint16_t
#elif DATA_SIZE == 1
#define SUFFIX b
#define USUFFIX ub
#define DATA_TYPE uint8_t
#else
#error unsupported data size
#endif

#ifdef SOFTMMU_CODE_ACCESS
#define READ_ACCESS_TYPE 2
#define ADDR_READ addr_code
#else
#define READ_ACCESS_TYPE 0
#define ADDR_READ addr_read
#endif

static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env,
                                                        target_ulong addr,
                                                        int mmu_idx,
                                                        uintptr_t retaddr);
static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
                                              hwaddr physaddr,
                                              target_ulong addr,
                                              uintptr_t retaddr)
{
    uint64_t val;
    MemoryRegion *mr = iotlb_to_region(physaddr);

    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
    env->mem_io_pc = retaddr;
    if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) {
        cpu_io_recompile(env, retaddr);
    }

    env->mem_io_vaddr = addr;
    io_mem_read(mr, physaddr, &val, 1 << SHIFT);
    return val;
}

/* handle all cases except unaligned access which span two pages */
#ifdef SOFTMMU_CODE_ACCESS
static
#endif
DATA_TYPE
glue(glue(helper_ret_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env,
                                             target_ulong addr, int mmu_idx,
                                             uintptr_t retaddr)
{
    DATA_TYPE res;
    int index;
    target_ulong tlb_addr;
    hwaddr ioaddr;

    /* test if there is match for unaligned or IO access */
    /* XXX: could done more in memory macro in a non portable way */
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            ioaddr = env->iotlb[mmu_idx][index];
            res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
            /* slow unaligned access (it spans two pages or IO) */
        do_unaligned_access:
#ifdef ALIGNED_ONLY
            do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
#endif
            res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr,
                                                         mmu_idx, retaddr);
        } else {
            /* unaligned/aligned access in the same page */
            uintptr_t addend;
#ifdef ALIGNED_ONLY
            if ((addr & (DATA_SIZE - 1)) != 0) {
                do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
            }
#endif
            addend = env->tlb_table[mmu_idx][index].addend;
            res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(intptr_t)
                                                (addr + addend));
        }
    } else {
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0)
            do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
#endif
        tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
        goto redo;
    }
    return res;
}

DATA_TYPE
glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
                                         int mmu_idx)
{
    return glue(glue(helper_ret_ld, SUFFIX), MMUSUFFIX)(env, addr, mmu_idx,
                                                        GETPC_EXT());
}

/* handle all unaligned cases */
static DATA_TYPE
glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env,
                                       target_ulong addr,
                                       int mmu_idx,
                                       uintptr_t retaddr)
{
    DATA_TYPE res, res1, res2;
    int index, shift;
    hwaddr ioaddr;
    target_ulong tlb_addr, addr1, addr2;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            ioaddr = env->iotlb[mmu_idx][index];
            res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            /* slow unaligned access (it spans two pages) */
            addr1 = addr & ~(DATA_SIZE - 1);
            addr2 = addr1 + DATA_SIZE;
            res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr1,
                                                          mmu_idx, retaddr);
            res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr2,
                                                          mmu_idx, retaddr);
            shift = (addr & (DATA_SIZE - 1)) * 8;
#ifdef TARGET_WORDS_BIGENDIAN
            res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
#else
            res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
#endif
            res = (DATA_TYPE)res;
        } else {
            /* unaligned/aligned access in the same page */
            uintptr_t addend = env->tlb_table[mmu_idx][index].addend;
            res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(intptr_t)
                                                (addr + addend));
        }
    } else {
        /* the page is not in the TLB : fill it */
        tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
        goto redo;
    }
    return res;
}

#ifndef SOFTMMU_CODE_ACCESS

static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
                                                   target_ulong addr,
                                                   DATA_TYPE val,
                                                   int mmu_idx,
                                                   uintptr_t retaddr);

static inline void glue(io_write, SUFFIX)(CPUArchState *env,
                                          hwaddr physaddr,
                                          DATA_TYPE val,
                                          target_ulong addr,
                                          uintptr_t retaddr)
{
    MemoryRegion *mr = iotlb_to_region(physaddr);

    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
    if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) {
        cpu_io_recompile(env, retaddr);
    }

    env->mem_io_vaddr = addr;
    env->mem_io_pc = retaddr;
    io_mem_write(mr, physaddr, val, 1 << SHIFT);
}

void
glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
                                             target_ulong addr, DATA_TYPE val,
                                             int mmu_idx, uintptr_t retaddr)
{
    hwaddr ioaddr;
    target_ulong tlb_addr;
    int index;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            ioaddr = env->iotlb[mmu_idx][index];
            glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
#ifdef ALIGNED_ONLY
            do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
#endif
            glue(glue(slow_st, SUFFIX), MMUSUFFIX)(env, addr, val,
                                                   mmu_idx, retaddr);
        } else {
            /* aligned/unaligned access in the same page */
            uintptr_t addend;
#ifdef ALIGNED_ONLY
            if ((addr & (DATA_SIZE - 1)) != 0) {
                do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
            }
#endif
            addend = env->tlb_table[mmu_idx][index].addend;
            glue(glue(st, SUFFIX), _raw)((uint8_t *)(intptr_t)
                                         (addr + addend), val);
        }
    } else {
        /* the page is not in the TLB : fill it */
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0)
            do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
#endif
        tlb_fill(env, addr, 1, mmu_idx, retaddr);
        goto redo;
    }
}

void
glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
                                         DATA_TYPE val, int mmu_idx)
{
    glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(env, addr, val, mmu_idx,
                                                 GETPC_EXT());
}

/* handles all unaligned cases */
static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
                                                   target_ulong addr,
                                                   DATA_TYPE val,
                                                   int mmu_idx,
                                                   uintptr_t retaddr)
{
    hwaddr ioaddr;
    target_ulong tlb_addr;
    int index, i;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            ioaddr = env->iotlb[mmu_idx][index];
            glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            /* XXX: not efficient, but simple */
            /* Note: relies on the fact that tlb_fill() does not remove the
             * previous page from the TLB cache.  */
            for(i = DATA_SIZE - 1; i >= 0; i--) {
#ifdef TARGET_WORDS_BIGENDIAN
                glue(slow_stb, MMUSUFFIX)(env, addr + i,
                                          val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
                                          mmu_idx, retaddr);
#else
                glue(slow_stb, MMUSUFFIX)(env, addr + i,
                                          val >> (i * 8),
                                          mmu_idx, retaddr);
#endif
            }
        } else {
            /* aligned/unaligned access in the same page */
            uintptr_t addend = env->tlb_table[mmu_idx][index].addend;
            glue(glue(st, SUFFIX), _raw)((uint8_t *)(intptr_t)
                                         (addr + addend), val);
        }
    } else {
        /* the page is not in the TLB : fill it */
        tlb_fill(env, addr, 1, mmu_idx, retaddr);
        goto redo;
    }
}

#endif /* !defined(SOFTMMU_CODE_ACCESS) */

#undef READ_ACCESS_TYPE
#undef SHIFT
#undef DATA_TYPE
#undef SUFFIX
#undef USUFFIX
#undef DATA_SIZE
#undef ADDR_READ
Commit	Line	Data
b92e5a22 FB	1	/*
b92e5a22 FB	2	* Software MMU support
5fafdf24	3	*
efbf29b6 BS	4	* Generate helpers used by TCG for qemu_ld/st ops and code load
	5	* functions.
	6	*
	7	* Included from target op helpers and exec.c.
	8	*
b92e5a22 FB	9	* Copyright (c) 2003 Fabrice Bellard
	10	*
	11	* This library is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU Lesser General Public
	13	* License as published by the Free Software Foundation; either
	14	* version 2 of the License, or (at your option) any later version.
	15	*
	16	* This library is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	19	* Lesser General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU Lesser General Public
8167ee88	22	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
b92e5a22	23	*/
1de7afc9	24	#include "qemu/timer.h"
022c62cb	25	#include "exec/memory.h"
29e922b6	26
b92e5a22 FB	27	#define DATA_SIZE (1 << SHIFT)
	28
	29	#if DATA_SIZE == 8
	30	#define SUFFIX q
61382a50	31	#define USUFFIX q
b92e5a22 FB	32	#define DATA_TYPE uint64_t
	33	#elif DATA_SIZE == 4
	34	#define SUFFIX l
61382a50	35	#define USUFFIX l
b92e5a22 FB	36	#define DATA_TYPE uint32_t
	37	#elif DATA_SIZE == 2
	38	#define SUFFIX w
61382a50	39	#define USUFFIX uw
b92e5a22 FB	40	#define DATA_TYPE uint16_t
	41	#elif DATA_SIZE == 1
	42	#define SUFFIX b
61382a50	43	#define USUFFIX ub
b92e5a22 FB	44	#define DATA_TYPE uint8_t
	45	#else
	46	#error unsupported data size
	47	#endif
	48
b769d8fe FB	49	#ifdef SOFTMMU_CODE_ACCESS
b769d8fe FB	50	#define READ_ACCESS_TYPE 2
84b7b8e7	51	#define ADDR_READ addr_code
b769d8fe FB	52	#else
b769d8fe FB	53	#define READ_ACCESS_TYPE 0
84b7b8e7	54	#define ADDR_READ addr_read
b769d8fe FB	55	#endif
b769d8fe FB	56
89c33337	57	static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env,
e141ab52	58	target_ulong addr,
6ebbf390	59	int mmu_idx,
20503968	60	uintptr_t retaddr);
89c33337	61	static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
a8170e5e	62	hwaddr physaddr,
2e70f6ef	63	target_ulong addr,
20503968	64	uintptr_t retaddr)
b92e5a22	65	{
791af8c8	66	uint64_t val;
37ec01d4 AK	67	MemoryRegion *mr = iotlb_to_region(physaddr);
37ec01d4 AK	68
0f459d16	69	physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
20503968	70	env->mem_io_pc = retaddr;
0844e007	71	if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) {
2e70f6ef PB	72	cpu_io_recompile(env, retaddr);
2e70f6ef PB	73	}
b92e5a22	74
db8886d3	75	env->mem_io_vaddr = addr;
791af8c8 PB	76	io_mem_read(mr, physaddr, &val, 1 << SHIFT);
791af8c8 PB	77	return val;
b92e5a22 FB	78	}
b92e5a22 FB	79
b92e5a22	80	/* handle all cases except unaligned access which span two pages */
e25c3887 RH	81	#ifdef SOFTMMU_CODE_ACCESS
	82	static
	83	#endif
e141ab52	84	DATA_TYPE
e25c3887 RH	85	glue(glue(helper_ret_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env,
	86	target_ulong addr, int mmu_idx,
	87	uintptr_t retaddr)
b92e5a22 FB	88	{
b92e5a22 FB	89	DATA_TYPE res;
61382a50	90	int index;
c27004ec	91	target_ulong tlb_addr;
a8170e5e	92	hwaddr ioaddr;
3b46e624	93
b92e5a22 FB	94	/* test if there is match for unaligned or IO access */
b92e5a22 FB	95	/* XXX: could done more in memory macro in a non portable way */
b92e5a22 FB	96	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	97	redo:
6ebbf390	98	tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
b92e5a22	99	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	100	if (tlb_addr & ~TARGET_PAGE_MASK) {
	101	/* IO access */
	102	if ((addr & (DATA_SIZE - 1)) != 0)
	103	goto do_unaligned_access;
37ec01d4	104	ioaddr = env->iotlb[mmu_idx][index];
89c33337	105	res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
98699967	106	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	107	/* slow unaligned access (it spans two pages or IO) */
b92e5a22 FB	108	do_unaligned_access:
a64d4718	109	#ifdef ALIGNED_ONLY
89c33337	110	do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718	111	#endif
89c33337	112	res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr,
6ebbf390	113	mmu_idx, retaddr);
b92e5a22	114	} else {
a64d4718	115	/* unaligned/aligned access in the same page */
b065927a	116	uintptr_t addend;
a64d4718 FB	117	#ifdef ALIGNED_ONLY
a64d4718 FB	118	if ((addr & (DATA_SIZE - 1)) != 0) {
89c33337	119	do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718 FB	120	}
a64d4718 FB	121	#endif
0f459d16	122	addend = env->tlb_table[mmu_idx][index].addend;
b065927a SW	123	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(intptr_t)
b065927a SW	124	(addr + addend));
b92e5a22 FB	125	}
b92e5a22 FB	126	} else {
a64d4718 FB	127	#ifdef ALIGNED_ONLY
a64d4718 FB	128	if ((addr & (DATA_SIZE - 1)) != 0)
89c33337	129	do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718	130	#endif
bccd9ec5	131	tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
b92e5a22 FB	132	goto redo;
	133	}
	134	return res;
	135	}
	136
e25c3887 RH	137	DATA_TYPE
	138	glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
	139	int mmu_idx)
	140	{
	141	return glue(glue(helper_ret_ld, SUFFIX), MMUSUFFIX)(env, addr, mmu_idx,
	142	GETPC_EXT());
	143	}
	144
b92e5a22	145	/* handle all unaligned cases */
e141ab52	146	static DATA_TYPE
89c33337	147	glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env,
e141ab52 BS	148	target_ulong addr,
e141ab52 BS	149	int mmu_idx,
20503968	150	uintptr_t retaddr)
b92e5a22 FB	151	{
b92e5a22 FB	152	DATA_TYPE res, res1, res2;
61382a50	153	int index, shift;
a8170e5e	154	hwaddr ioaddr;
c27004ec	155	target_ulong tlb_addr, addr1, addr2;
b92e5a22	156
b92e5a22 FB	157	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	158	redo:
6ebbf390	159	tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
b92e5a22	160	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	161	if (tlb_addr & ~TARGET_PAGE_MASK) {
	162	/* IO access */
	163	if ((addr & (DATA_SIZE - 1)) != 0)
	164	goto do_unaligned_access;
37ec01d4	165	ioaddr = env->iotlb[mmu_idx][index];
89c33337	166	res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
98699967	167	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	168	do_unaligned_access:
	169	/* slow unaligned access (it spans two pages) */
	170	addr1 = addr & ~(DATA_SIZE - 1);
	171	addr2 = addr1 + DATA_SIZE;
89c33337	172	res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr1,
6ebbf390	173	mmu_idx, retaddr);
89c33337	174	res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr2,
6ebbf390	175	mmu_idx, retaddr);
b92e5a22 FB	176	shift = (addr & (DATA_SIZE - 1)) * 8;
	177	#ifdef TARGET_WORDS_BIGENDIAN
	178	res = (res1 << shift) \| (res2 >> ((DATA_SIZE * 8) - shift));
	179	#else
	180	res = (res1 >> shift) \| (res2 << ((DATA_SIZE * 8) - shift));
	181	#endif
6986f88c	182	res = (DATA_TYPE)res;
b92e5a22 FB	183	} else {
b92e5a22 FB	184	/* unaligned/aligned access in the same page */
b065927a SW	185	uintptr_t addend = env->tlb_table[mmu_idx][index].addend;
	186	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(intptr_t)
	187	(addr + addend));
b92e5a22 FB	188	}
	189	} else {
	190	/* the page is not in the TLB : fill it */
bccd9ec5	191	tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
b92e5a22 FB	192	goto redo;
	193	}
	194	return res;
	195	}
	196
b769d8fe FB	197	#ifndef SOFTMMU_CODE_ACCESS
b769d8fe FB	198
89c33337	199	static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
e141ab52	200	target_ulong addr,
5fafdf24	201	DATA_TYPE val,
6ebbf390	202	int mmu_idx,
20503968	203	uintptr_t retaddr);
b769d8fe	204
89c33337	205	static inline void glue(io_write, SUFFIX)(CPUArchState *env,
a8170e5e	206	hwaddr physaddr,
b769d8fe	207	DATA_TYPE val,
0f459d16	208	target_ulong addr,
20503968	209	uintptr_t retaddr)
b769d8fe	210	{
37ec01d4 AK	211	MemoryRegion *mr = iotlb_to_region(physaddr);
37ec01d4 AK	212
0f459d16	213	physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
0844e007	214	if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) {
2e70f6ef PB	215	cpu_io_recompile(env, retaddr);
2e70f6ef PB	216	}
b769d8fe	217
2e70f6ef	218	env->mem_io_vaddr = addr;
20503968	219	env->mem_io_pc = retaddr;
37ec01d4	220	io_mem_write(mr, physaddr, val, 1 << SHIFT);
b769d8fe	221	}
b92e5a22	222
e25c3887 RH	223	void
	224	glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
	225	target_ulong addr, DATA_TYPE val,
	226	int mmu_idx, uintptr_t retaddr)
b92e5a22	227	{
a8170e5e	228	hwaddr ioaddr;
c27004ec	229	target_ulong tlb_addr;
61382a50	230	int index;
3b46e624	231
b92e5a22 FB	232	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	233	redo:
6ebbf390	234	tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
b92e5a22	235	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	236	if (tlb_addr & ~TARGET_PAGE_MASK) {
	237	/* IO access */
	238	if ((addr & (DATA_SIZE - 1)) != 0)
	239	goto do_unaligned_access;
37ec01d4	240	ioaddr = env->iotlb[mmu_idx][index];
89c33337	241	glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
98699967	242	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22	243	do_unaligned_access:
a64d4718	244	#ifdef ALIGNED_ONLY
89c33337	245	do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
a64d4718	246	#endif
89c33337	247	glue(glue(slow_st, SUFFIX), MMUSUFFIX)(env, addr, val,
6ebbf390	248	mmu_idx, retaddr);
b92e5a22 FB	249	} else {
b92e5a22 FB	250	/* aligned/unaligned access in the same page */
b065927a	251	uintptr_t addend;
a64d4718 FB	252	#ifdef ALIGNED_ONLY
a64d4718 FB	253	if ((addr & (DATA_SIZE - 1)) != 0) {
89c33337	254	do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
a64d4718 FB	255	}
a64d4718 FB	256	#endif
0f459d16	257	addend = env->tlb_table[mmu_idx][index].addend;
b065927a SW	258	glue(glue(st, SUFFIX), _raw)((uint8_t *)(intptr_t)
b065927a SW	259	(addr + addend), val);
b92e5a22 FB	260	}
	261	} else {
	262	/* the page is not in the TLB : fill it */
a64d4718 FB	263	#ifdef ALIGNED_ONLY
a64d4718 FB	264	if ((addr & (DATA_SIZE - 1)) != 0)
89c33337	265	do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
a64d4718	266	#endif
bccd9ec5	267	tlb_fill(env, addr, 1, mmu_idx, retaddr);
b92e5a22 FB	268	goto redo;
	269	}
	270	}
	271
e25c3887 RH	272	void
	273	glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
	274	DATA_TYPE val, int mmu_idx)
	275	{
	276	glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(env, addr, val, mmu_idx,
	277	GETPC_EXT());
	278	}
	279
b92e5a22	280	/* handles all unaligned cases */
89c33337	281	static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
e141ab52	282	target_ulong addr,
61382a50	283	DATA_TYPE val,
6ebbf390	284	int mmu_idx,
20503968	285	uintptr_t retaddr)
b92e5a22	286	{
a8170e5e	287	hwaddr ioaddr;
c27004ec	288	target_ulong tlb_addr;
61382a50	289	int index, i;
b92e5a22	290
b92e5a22 FB	291	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	292	redo:
6ebbf390	293	tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
b92e5a22	294	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	295	if (tlb_addr & ~TARGET_PAGE_MASK) {
	296	/* IO access */
	297	if ((addr & (DATA_SIZE - 1)) != 0)
	298	goto do_unaligned_access;
37ec01d4	299	ioaddr = env->iotlb[mmu_idx][index];
89c33337	300	glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
98699967	301	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	302	do_unaligned_access:
b92e5a22 FB	303	/* XXX: not efficient, but simple */
6c41b272 AZ	304	/* Note: relies on the fact that tlb_fill() does not remove the
6c41b272 AZ	305	* previous page from the TLB cache. */
7221fa98	306	for(i = DATA_SIZE - 1; i >= 0; i--) {
b92e5a22	307	#ifdef TARGET_WORDS_BIGENDIAN
89c33337	308	glue(slow_stb, MMUSUFFIX)(env, addr + i,
e141ab52	309	val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
6ebbf390	310	mmu_idx, retaddr);
b92e5a22	311	#else
89c33337	312	glue(slow_stb, MMUSUFFIX)(env, addr + i,
e141ab52	313	val >> (i * 8),
6ebbf390	314	mmu_idx, retaddr);
b92e5a22 FB	315	#endif
	316	}
	317	} else {
	318	/* aligned/unaligned access in the same page */
b065927a SW	319	uintptr_t addend = env->tlb_table[mmu_idx][index].addend;
	320	glue(glue(st, SUFFIX), _raw)((uint8_t *)(intptr_t)
	321	(addr + addend), val);
b92e5a22 FB	322	}
	323	} else {
	324	/* the page is not in the TLB : fill it */
bccd9ec5	325	tlb_fill(env, addr, 1, mmu_idx, retaddr);
b92e5a22 FB	326	goto redo;
	327	}
	328	}
	329
b769d8fe FB	330	#endif /* !defined(SOFTMMU_CODE_ACCESS) */
	331
	332	#undef READ_ACCESS_TYPE
b92e5a22 FB	333	#undef SHIFT
	334	#undef DATA_TYPE
	335	#undef SUFFIX
61382a50	336	#undef USUFFIX
b92e5a22	337	#undef DATA_SIZE
84b7b8e7	338	#undef ADDR_READ