[qemu.git] / hw / sparc64 / niagara.c

/*
 * QEMU Sun4v/Niagara System Emulator
 *
 * Copyright (c) 2016 Artyom Tarasenko
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/hw.h"
#include "hw/boards.h"
#include "hw/char/serial.h"
#include "hw/empty_slot.h"
#include "hw/loader.h"
#include "hw/sparc/sparc64.h"
#include "hw/timer/sun4v-rtc.h"
#include "exec/address-spaces.h"
#include "sysemu/block-backend.h"
#include "qemu/error-report.h"
#include "sysemu/qtest.h"


typedef struct NiagaraBoardState {
    MemoryRegion hv_ram;
    MemoryRegion partition_ram;
    MemoryRegion nvram;
    MemoryRegion md_rom;
    MemoryRegion hv_rom;
    MemoryRegion vdisk_ram;
    MemoryRegion prom;
} NiagaraBoardState;

#define NIAGARA_HV_RAM_BASE 0x100000ULL
#define NIAGARA_HV_RAM_SIZE 0x3f00000ULL /* 63 MiB */

#define NIAGARA_PARTITION_RAM_BASE 0x80000000ULL

#define NIAGARA_UART_BASE   0x1f10000000ULL

#define NIAGARA_NVRAM_BASE  0x1f11000000ULL
#define NIAGARA_NVRAM_SIZE  0x2000

#define NIAGARA_MD_ROM_BASE 0x1f12000000ULL
#define NIAGARA_MD_ROM_SIZE 0x2000

#define NIAGARA_HV_ROM_BASE 0x1f12080000ULL
#define NIAGARA_HV_ROM_SIZE 0x2000

#define NIAGARA_IOBBASE     0x9800000000ULL
#define NIAGARA_IOBSIZE     0x0100000000ULL

#define NIAGARA_VDISK_BASE  0x1f40000000ULL
#define NIAGARA_RTC_BASE    0xfff0c1fff8ULL
#define NIAGARA_UART_BASE   0x1f10000000ULL

/* Firmware layout
 *
 * |------------------|
 * |   openboot.bin   |
 * |------------------| PROM_ADDR + OBP_OFFSET
 * |      q.bin       |
 * |------------------| PROM_ADDR + Q_OFFSET
 * |     reset.bin    |
 * |------------------| PROM_ADDR
 */
#define NIAGARA_PROM_BASE   0xfff0000000ULL
#define NIAGARA_Q_OFFSET    0x10000ULL
#define NIAGARA_OBP_OFFSET  0x80000ULL
#define PROM_SIZE_MAX       (4 * 1024 * 1024)

static void add_rom_or_fail(const char *file, const hwaddr addr)
{
    /* XXX remove qtest_enabled() check once firmware files are
     * in the qemu tree
     */
    if (!qtest_enabled() && rom_add_file_fixed(file, addr, -1)) {
        error_report("Unable to load a firmware for -M niagara");
        exit(1);
    }

}
/* Niagara hardware initialisation */
static void niagara_init(MachineState *machine)
{
    NiagaraBoardState *s = g_new(NiagaraBoardState, 1);
    DriveInfo *dinfo = drive_get_next(IF_PFLASH);
    MemoryRegion *sysmem = get_system_memory();

    /* init CPUs */
    sparc64_cpu_devinit(machine->cpu_type, NIAGARA_PROM_BASE);
    /* set up devices */
    memory_region_allocate_system_memory(&s->hv_ram, NULL, "sun4v-hv.ram",
                                         NIAGARA_HV_RAM_SIZE);
    memory_region_add_subregion(sysmem, NIAGARA_HV_RAM_BASE, &s->hv_ram);

    memory_region_allocate_system_memory(&s->partition_ram, NULL,
                                         "sun4v-partition.ram",
                                         machine->ram_size);
    memory_region_add_subregion(sysmem, NIAGARA_PARTITION_RAM_BASE,
                                &s->partition_ram);

    memory_region_allocate_system_memory(&s->nvram, NULL,
                                         "sun4v.nvram", NIAGARA_NVRAM_SIZE);
    memory_region_add_subregion(sysmem, NIAGARA_NVRAM_BASE, &s->nvram);
    memory_region_allocate_system_memory(&s->md_rom, NULL,
                                         "sun4v-md.rom", NIAGARA_MD_ROM_SIZE);
    memory_region_add_subregion(sysmem, NIAGARA_MD_ROM_BASE, &s->md_rom);
    memory_region_allocate_system_memory(&s->hv_rom, NULL,
                                         "sun4v-hv.rom", NIAGARA_HV_ROM_SIZE);
    memory_region_add_subregion(sysmem, NIAGARA_HV_ROM_BASE, &s->hv_rom);
    memory_region_allocate_system_memory(&s->prom, NULL,
                                         "sun4v.prom", PROM_SIZE_MAX);
    memory_region_add_subregion(sysmem, NIAGARA_PROM_BASE, &s->prom);

    add_rom_or_fail("nvram1", NIAGARA_NVRAM_BASE);
    add_rom_or_fail("1up-md.bin", NIAGARA_MD_ROM_BASE);
    add_rom_or_fail("1up-hv.bin", NIAGARA_HV_ROM_BASE);

    add_rom_or_fail("reset.bin", NIAGARA_PROM_BASE);
    add_rom_or_fail("q.bin", NIAGARA_PROM_BASE + NIAGARA_Q_OFFSET);
    add_rom_or_fail("openboot.bin", NIAGARA_PROM_BASE + NIAGARA_OBP_OFFSET);

    /* the virtual ramdisk is kind of initrd, but it resides
       outside of the partition RAM */
    if (dinfo) {
        BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
        int size = blk_getlength(blk);
        if (size > 0) {
            memory_region_allocate_system_memory(&s->vdisk_ram, NULL,
                                                 "sun4v_vdisk.ram", size);
            memory_region_add_subregion(get_system_memory(),
                                        NIAGARA_VDISK_BASE, &s->vdisk_ram);
            dinfo->is_default = 1;
            rom_add_file_fixed(blk_bs(blk)->filename, NIAGARA_VDISK_BASE, -1);
        } else {
            error_report("could not load ram disk '%s'",
                         blk_bs(blk)->filename);
            exit(1);
        }
    }
    if (serial_hds[0]) {
        serial_mm_init(sysmem, NIAGARA_UART_BASE, 0, NULL, 115200,
                       serial_hds[0], DEVICE_BIG_ENDIAN);
    }
    empty_slot_init(NIAGARA_IOBBASE, NIAGARA_IOBSIZE);
    sun4v_rtc_init(NIAGARA_RTC_BASE);
}

static void niagara_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "Sun4v platform, Niagara";
    mc->init = niagara_init;
    mc->max_cpus = 1; /* XXX for now */
    mc->default_boot_order = "c";
    mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
}

static const TypeInfo niagara_type = {
    .name = MACHINE_TYPE_NAME("niagara"),
    .parent = TYPE_MACHINE,
    .class_init = niagara_class_init,
};

static void niagara_register_types(void)
{
    type_register_static(&niagara_type);
}

type_init(niagara_register_types)
Commit	Line	Data
a2664ca0 AT	1	/*
	2	* QEMU Sun4v/Niagara System Emulator
	3	*
	4	* Copyright (c) 2016 Artyom Tarasenko
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#include "qemu/osdep.h"
a2664ca0 AT	26	#include "qemu-common.h"
	27	#include "cpu.h"
	28	#include "hw/hw.h"
	29	#include "hw/boards.h"
	30	#include "hw/char/serial.h"
	31	#include "hw/empty_slot.h"
	32	#include "hw/loader.h"
	33	#include "hw/sparc/sparc64.h"
	34	#include "hw/timer/sun4v-rtc.h"
	35	#include "exec/address-spaces.h"
	36	#include "sysemu/block-backend.h"
5e3a5494 AT	37	#include "qemu/error-report.h"
5e3a5494 AT	38	#include "sysemu/qtest.h"
a2664ca0 AT	39
	40
	41	typedef struct NiagaraBoardState {
	42	MemoryRegion hv_ram;
	43	MemoryRegion partition_ram;
	44	MemoryRegion nvram;
	45	MemoryRegion md_rom;
	46	MemoryRegion hv_rom;
	47	MemoryRegion vdisk_ram;
	48	MemoryRegion prom;
	49	} NiagaraBoardState;
	50
	51	#define NIAGARA_HV_RAM_BASE 0x100000ULL
	52	#define NIAGARA_HV_RAM_SIZE 0x3f00000ULL /* 63 MiB */
	53
	54	#define NIAGARA_PARTITION_RAM_BASE 0x80000000ULL
	55
	56	#define NIAGARA_UART_BASE 0x1f10000000ULL
	57
	58	#define NIAGARA_NVRAM_BASE 0x1f11000000ULL
	59	#define NIAGARA_NVRAM_SIZE 0x2000
	60
	61	#define NIAGARA_MD_ROM_BASE 0x1f12000000ULL
	62	#define NIAGARA_MD_ROM_SIZE 0x2000
	63
	64	#define NIAGARA_HV_ROM_BASE 0x1f12080000ULL
	65	#define NIAGARA_HV_ROM_SIZE 0x2000
	66
	67	#define NIAGARA_IOBBASE 0x9800000000ULL
	68	#define NIAGARA_IOBSIZE 0x0100000000ULL
	69
	70	#define NIAGARA_VDISK_BASE 0x1f40000000ULL
	71	#define NIAGARA_RTC_BASE 0xfff0c1fff8ULL
	72	#define NIAGARA_UART_BASE 0x1f10000000ULL
	73
	74	/* Firmware layout
	75	*
	76	* \|------------------\|
	77	* \| openboot.bin \|
	78	* \|------------------\| PROM_ADDR + OBP_OFFSET
	79	* \| q.bin \|
	80	* \|------------------\| PROM_ADDR + Q_OFFSET
	81	* \| reset.bin \|
	82	* \|------------------\| PROM_ADDR
	83	*/
	84	#define NIAGARA_PROM_BASE 0xfff0000000ULL
	85	#define NIAGARA_Q_OFFSET 0x10000ULL
	86	#define NIAGARA_OBP_OFFSET 0x80000ULL
	87	#define PROM_SIZE_MAX (4 * 1024 * 1024)
	88
5e3a5494 AT	89	static void add_rom_or_fail(const char *file, const hwaddr addr)
	90	{
	91	/* XXX remove qtest_enabled() check once firmware files are
	92	* in the qemu tree
	93	*/
	94	if (!qtest_enabled() && rom_add_file_fixed(file, addr, -1)) {
	95	error_report("Unable to load a firmware for -M niagara");
	96	exit(1);
	97	}
	98
	99	}
a2664ca0 AT	100	/* Niagara hardware initialisation */
	101	static void niagara_init(MachineState *machine)
	102	{
	103	NiagaraBoardState *s = g_new(NiagaraBoardState, 1);
	104	DriveInfo *dinfo = drive_get_next(IF_PFLASH);
	105	MemoryRegion *sysmem = get_system_memory();
	106
	107	/* init CPUs */
58530461	108	sparc64_cpu_devinit(machine->cpu_type, NIAGARA_PROM_BASE);
a2664ca0 AT	109	/* set up devices */
	110	memory_region_allocate_system_memory(&s->hv_ram, NULL, "sun4v-hv.ram",
	111	NIAGARA_HV_RAM_SIZE);
	112	memory_region_add_subregion(sysmem, NIAGARA_HV_RAM_BASE, &s->hv_ram);
	113
	114	memory_region_allocate_system_memory(&s->partition_ram, NULL,
	115	"sun4v-partition.ram",
	116	machine->ram_size);
	117	memory_region_add_subregion(sysmem, NIAGARA_PARTITION_RAM_BASE,
	118	&s->partition_ram);
	119
	120	memory_region_allocate_system_memory(&s->nvram, NULL,
	121	"sun4v.nvram", NIAGARA_NVRAM_SIZE);
	122	memory_region_add_subregion(sysmem, NIAGARA_NVRAM_BASE, &s->nvram);
	123	memory_region_allocate_system_memory(&s->md_rom, NULL,
	124	"sun4v-md.rom", NIAGARA_MD_ROM_SIZE);
	125	memory_region_add_subregion(sysmem, NIAGARA_MD_ROM_BASE, &s->md_rom);
	126	memory_region_allocate_system_memory(&s->hv_rom, NULL,
	127	"sun4v-hv.rom", NIAGARA_HV_ROM_SIZE);
	128	memory_region_add_subregion(sysmem, NIAGARA_HV_ROM_BASE, &s->hv_rom);
	129	memory_region_allocate_system_memory(&s->prom, NULL,
	130	"sun4v.prom", PROM_SIZE_MAX);
	131	memory_region_add_subregion(sysmem, NIAGARA_PROM_BASE, &s->prom);
	132
5e3a5494 AT	133	add_rom_or_fail("nvram1", NIAGARA_NVRAM_BASE);
	134	add_rom_or_fail("1up-md.bin", NIAGARA_MD_ROM_BASE);
	135	add_rom_or_fail("1up-hv.bin", NIAGARA_HV_ROM_BASE);
a2664ca0	136
5e3a5494 AT	137	add_rom_or_fail("reset.bin", NIAGARA_PROM_BASE);
	138	add_rom_or_fail("q.bin", NIAGARA_PROM_BASE + NIAGARA_Q_OFFSET);
	139	add_rom_or_fail("openboot.bin", NIAGARA_PROM_BASE + NIAGARA_OBP_OFFSET);
a2664ca0 AT	140
	141	/* the virtual ramdisk is kind of initrd, but it resides
	142	outside of the partition RAM */
	143	if (dinfo) {
	144	BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
	145	int size = blk_getlength(blk);
	146	if (size > 0) {
	147	memory_region_allocate_system_memory(&s->vdisk_ram, NULL,
	148	"sun4v_vdisk.ram", size);
	149	memory_region_add_subregion(get_system_memory(),
	150	NIAGARA_VDISK_BASE, &s->vdisk_ram);
	151	dinfo->is_default = 1;
	152	rom_add_file_fixed(blk_bs(blk)->filename, NIAGARA_VDISK_BASE, -1);
	153	} else {
29bd7231 AF	154	error_report("could not load ram disk '%s'",
29bd7231 AF	155	blk_bs(blk)->filename);
a2664ca0 AT	156	exit(1);
	157	}
	158	}
a5a08302 AT	159	if (serial_hds[0]) {
	160	serial_mm_init(sysmem, NIAGARA_UART_BASE, 0, NULL, 115200,
	161	serial_hds[0], DEVICE_BIG_ENDIAN);
	162	}
a2664ca0 AT	163	empty_slot_init(NIAGARA_IOBBASE, NIAGARA_IOBSIZE);
	164	sun4v_rtc_init(NIAGARA_RTC_BASE);
	165	}
	166
	167	static void niagara_class_init(ObjectClass oc, void data)
	168	{
	169	MachineClass *mc = MACHINE_CLASS(oc);
	170
	171	mc->desc = "Sun4v platform, Niagara";
	172	mc->init = niagara_init;
	173	mc->max_cpus = 1; /* XXX for now */
	174	mc->default_boot_order = "c";
58530461	175	mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
a2664ca0 AT	176	}
	177
	178	static const TypeInfo niagara_type = {
	179	.name = MACHINE_TYPE_NAME("niagara"),
	180	.parent = TYPE_MACHINE,
	181	.class_init = niagara_class_init,
	182	};
	183
	184	static void niagara_register_types(void)
	185	{
	186	type_register_static(&niagara_type);
	187	}
	188
	189	type_init(niagara_register_types)