]>
Commit | Line | Data |
---|---|---|
17ff8e18 SG |
1 | /* |
2 | * QTest testcase for Microbit board using the Nordic Semiconductor nRF51 SoC. | |
3 | * | |
4 | * nRF51: | |
5 | * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf | |
6 | * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf | |
7 | * | |
8 | * Microbit Board: http://microbit.org/ | |
9 | * | |
10 | * Copyright 2018 Steffen Görtz <[email protected]> | |
11 | * | |
12 | * This code is licensed under the GPL version 2 or later. See | |
13 | * the COPYING file in the top-level directory. | |
14 | */ | |
15 | ||
16 | ||
17 | #include "qemu/osdep.h" | |
18 | #include "exec/hwaddr.h" | |
19 | #include "libqtest.h" | |
20 | ||
21 | #include "hw/arm/nrf51.h" | |
46a6603b | 22 | #include "hw/char/nrf51_uart.h" |
17ff8e18 | 23 | #include "hw/gpio/nrf51_gpio.h" |
7743b70f | 24 | #include "hw/nvram/nrf51_nvm.h" |
7ec543e4 | 25 | #include "hw/timer/nrf51_timer.h" |
b36356f6 SH |
26 | #include "hw/i2c/microbit_i2c.h" |
27 | ||
46a6603b JS |
28 | static bool uart_wait_for_event(QTestState *qts, uint32_t event_addr) |
29 | { | |
30 | time_t now, start = time(NULL); | |
31 | ||
32 | while (true) { | |
33 | if (qtest_readl(qts, event_addr) == 1) { | |
34 | qtest_writel(qts, event_addr, 0x00); | |
35 | return true; | |
36 | } | |
37 | ||
38 | /* Wait at most 10 minutes */ | |
39 | now = time(NULL); | |
40 | if (now - start > 600) { | |
41 | break; | |
42 | } | |
43 | g_usleep(10000); | |
44 | } | |
45 | ||
46 | return false; | |
47 | } | |
48 | ||
49 | static void uart_rw_to_rxd(QTestState *qts, int sock_fd, const char *in, | |
50 | char *out) | |
51 | { | |
52 | int i, in_len = strlen(in); | |
53 | ||
54 | g_assert_true(write(sock_fd, in, in_len) == in_len); | |
55 | for (i = 0; i < in_len; i++) { | |
56 | g_assert_true(uart_wait_for_event(qts, NRF51_UART_BASE + | |
57 | A_UART_RXDRDY)); | |
58 | out[i] = qtest_readl(qts, NRF51_UART_BASE + A_UART_RXD); | |
59 | } | |
60 | out[i] = '\0'; | |
61 | } | |
62 | ||
63 | static void uart_w_to_txd(QTestState *qts, const char *in) | |
64 | { | |
65 | int i, in_len = strlen(in); | |
66 | ||
67 | for (i = 0; i < in_len; i++) { | |
68 | qtest_writel(qts, NRF51_UART_BASE + A_UART_TXD, in[i]); | |
69 | g_assert_true(uart_wait_for_event(qts, NRF51_UART_BASE + | |
70 | A_UART_TXDRDY)); | |
71 | } | |
72 | } | |
73 | ||
74 | static void test_nrf51_uart(void) | |
75 | { | |
76 | int sock_fd; | |
77 | char s[10]; | |
78 | QTestState *qts = qtest_init_with_serial("-M microbit", &sock_fd); | |
79 | ||
80 | g_assert_true(write(sock_fd, "c", 1) == 1); | |
81 | g_assert_cmphex(qtest_readl(qts, NRF51_UART_BASE + A_UART_RXD), ==, 0x00); | |
82 | ||
83 | qtest_writel(qts, NRF51_UART_BASE + A_UART_ENABLE, 0x04); | |
84 | qtest_writel(qts, NRF51_UART_BASE + A_UART_STARTRX, 0x01); | |
85 | ||
86 | g_assert_true(uart_wait_for_event(qts, NRF51_UART_BASE + A_UART_RXDRDY)); | |
87 | qtest_writel(qts, NRF51_UART_BASE + A_UART_RXDRDY, 0x00); | |
88 | g_assert_cmphex(qtest_readl(qts, NRF51_UART_BASE + A_UART_RXD), ==, 'c'); | |
89 | ||
90 | qtest_writel(qts, NRF51_UART_BASE + A_UART_INTENSET, 0x04); | |
91 | g_assert_cmphex(qtest_readl(qts, NRF51_UART_BASE + A_UART_INTEN), ==, 0x04); | |
92 | qtest_writel(qts, NRF51_UART_BASE + A_UART_INTENCLR, 0x04); | |
93 | g_assert_cmphex(qtest_readl(qts, NRF51_UART_BASE + A_UART_INTEN), ==, 0x00); | |
94 | ||
95 | uart_rw_to_rxd(qts, sock_fd, "hello", s); | |
96 | g_assert_true(memcmp(s, "hello", 5) == 0); | |
97 | ||
98 | qtest_writel(qts, NRF51_UART_BASE + A_UART_STARTTX, 0x01); | |
99 | uart_w_to_txd(qts, "d"); | |
100 | g_assert_true(read(sock_fd, s, 10) == 1); | |
101 | g_assert_cmphex(s[0], ==, 'd'); | |
102 | ||
103 | qtest_writel(qts, NRF51_UART_BASE + A_UART_SUSPEND, 0x01); | |
104 | qtest_writel(qts, NRF51_UART_BASE + A_UART_TXD, 'h'); | |
105 | qtest_writel(qts, NRF51_UART_BASE + A_UART_STARTTX, 0x01); | |
106 | uart_w_to_txd(qts, "world"); | |
107 | g_assert_true(read(sock_fd, s, 10) == 5); | |
108 | g_assert_true(memcmp(s, "world", 5) == 0); | |
109 | ||
110 | close(sock_fd); | |
111 | ||
112 | qtest_quit(qts); | |
113 | } | |
114 | ||
b36356f6 | 115 | /* Read a byte from I2C device at @addr from register @reg */ |
7cf19e73 | 116 | static uint32_t i2c_read_byte(QTestState *qts, uint32_t addr, uint32_t reg) |
b36356f6 SH |
117 | { |
118 | uint32_t val; | |
119 | ||
7cf19e73 JS |
120 | qtest_writel(qts, NRF51_TWI_BASE + NRF51_TWI_REG_ADDRESS, addr); |
121 | qtest_writel(qts, NRF51_TWI_BASE + NRF51_TWI_TASK_STARTTX, 1); | |
122 | qtest_writel(qts, NRF51_TWI_BASE + NRF51_TWI_REG_TXD, reg); | |
123 | val = qtest_readl(qts, NRF51_TWI_BASE + NRF51_TWI_EVENT_TXDSENT); | |
b36356f6 | 124 | g_assert_cmpuint(val, ==, 1); |
7cf19e73 | 125 | qtest_writel(qts, NRF51_TWI_BASE + NRF51_TWI_TASK_STOP, 1); |
b36356f6 | 126 | |
7cf19e73 JS |
127 | qtest_writel(qts, NRF51_TWI_BASE + NRF51_TWI_TASK_STARTRX, 1); |
128 | val = qtest_readl(qts, NRF51_TWI_BASE + NRF51_TWI_EVENT_RXDREADY); | |
b36356f6 | 129 | g_assert_cmpuint(val, ==, 1); |
7cf19e73 JS |
130 | val = qtest_readl(qts, NRF51_TWI_BASE + NRF51_TWI_REG_RXD); |
131 | qtest_writel(qts, NRF51_TWI_BASE + NRF51_TWI_TASK_STOP, 1); | |
b36356f6 SH |
132 | |
133 | return val; | |
134 | } | |
135 | ||
136 | static void test_microbit_i2c(void) | |
137 | { | |
138 | uint32_t val; | |
7cf19e73 | 139 | QTestState *qts = qtest_init("-M microbit"); |
b36356f6 SH |
140 | |
141 | /* We don't program pins/irqs but at least enable the device */ | |
7cf19e73 | 142 | qtest_writel(qts, NRF51_TWI_BASE + NRF51_TWI_REG_ENABLE, 5); |
b36356f6 SH |
143 | |
144 | /* MMA8653 magnetometer detection */ | |
7cf19e73 | 145 | val = i2c_read_byte(qts, 0x3A, 0x0D); |
b36356f6 SH |
146 | g_assert_cmpuint(val, ==, 0x5A); |
147 | ||
7cf19e73 | 148 | val = i2c_read_byte(qts, 0x3A, 0x0D); |
b36356f6 SH |
149 | g_assert_cmpuint(val, ==, 0x5A); |
150 | ||
151 | /* LSM303 accelerometer detection */ | |
7cf19e73 | 152 | val = i2c_read_byte(qts, 0x3C, 0x4F); |
b36356f6 SH |
153 | g_assert_cmpuint(val, ==, 0x40); |
154 | ||
7cf19e73 JS |
155 | qtest_writel(qts, NRF51_TWI_BASE + NRF51_TWI_REG_ENABLE, 0); |
156 | ||
157 | qtest_quit(qts); | |
b36356f6 | 158 | } |
17ff8e18 | 159 | |
7743b70f SG |
160 | #define FLASH_SIZE (256 * NRF51_PAGE_SIZE) |
161 | ||
162 | static void fill_and_erase(QTestState *qts, hwaddr base, hwaddr size, | |
163 | uint32_t address_reg) | |
164 | { | |
165 | hwaddr i; | |
166 | ||
167 | /* Erase Page */ | |
168 | qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x02); | |
169 | qtest_writel(qts, NRF51_NVMC_BASE + address_reg, base); | |
170 | qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); | |
171 | ||
172 | /* Check memory */ | |
173 | for (i = 0; i < size / 4; i++) { | |
174 | g_assert_cmpuint(qtest_readl(qts, base + i * 4), ==, 0xFFFFFFFF); | |
175 | } | |
176 | ||
177 | /* Fill memory */ | |
178 | qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x01); | |
179 | for (i = 0; i < size / 4; i++) { | |
180 | qtest_writel(qts, base + i * 4, i); | |
181 | g_assert_cmpuint(qtest_readl(qts, base + i * 4), ==, i); | |
182 | } | |
183 | qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); | |
184 | } | |
185 | ||
186 | static void test_nrf51_nvmc(void) | |
187 | { | |
188 | uint32_t value; | |
189 | hwaddr i; | |
190 | QTestState *qts = qtest_init("-M microbit"); | |
191 | ||
192 | /* Test always ready */ | |
193 | value = qtest_readl(qts, NRF51_NVMC_BASE + NRF51_NVMC_READY); | |
194 | g_assert_cmpuint(value & 0x01, ==, 0x01); | |
195 | ||
196 | /* Test write-read config register */ | |
197 | qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x03); | |
198 | g_assert_cmpuint(qtest_readl(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG), | |
199 | ==, 0x03); | |
200 | qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); | |
201 | g_assert_cmpuint(qtest_readl(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG), | |
202 | ==, 0x00); | |
203 | ||
204 | /* Test PCR0 */ | |
205 | fill_and_erase(qts, NRF51_FLASH_BASE, NRF51_PAGE_SIZE, | |
206 | NRF51_NVMC_ERASEPCR0); | |
207 | fill_and_erase(qts, NRF51_FLASH_BASE + NRF51_PAGE_SIZE, | |
208 | NRF51_PAGE_SIZE, NRF51_NVMC_ERASEPCR0); | |
209 | ||
210 | /* Test PCR1 */ | |
211 | fill_and_erase(qts, NRF51_FLASH_BASE, NRF51_PAGE_SIZE, | |
212 | NRF51_NVMC_ERASEPCR1); | |
213 | fill_and_erase(qts, NRF51_FLASH_BASE + NRF51_PAGE_SIZE, | |
214 | NRF51_PAGE_SIZE, NRF51_NVMC_ERASEPCR1); | |
215 | ||
216 | /* Erase all */ | |
217 | qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x02); | |
218 | qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_ERASEALL, 0x01); | |
219 | qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); | |
220 | ||
221 | qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x01); | |
222 | for (i = 0; i < FLASH_SIZE / 4; i++) { | |
223 | qtest_writel(qts, NRF51_FLASH_BASE + i * 4, i); | |
224 | g_assert_cmpuint(qtest_readl(qts, NRF51_FLASH_BASE + i * 4), ==, i); | |
225 | } | |
226 | qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); | |
227 | ||
228 | qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x02); | |
229 | qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_ERASEALL, 0x01); | |
230 | qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); | |
231 | ||
232 | for (i = 0; i < FLASH_SIZE / 4; i++) { | |
233 | g_assert_cmpuint(qtest_readl(qts, NRF51_FLASH_BASE + i * 4), | |
234 | ==, 0xFFFFFFFF); | |
235 | } | |
236 | ||
237 | /* Erase UICR */ | |
238 | qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x02); | |
239 | qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_ERASEUICR, 0x01); | |
240 | qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); | |
241 | ||
242 | for (i = 0; i < NRF51_UICR_SIZE / 4; i++) { | |
243 | g_assert_cmpuint(qtest_readl(qts, NRF51_UICR_BASE + i * 4), | |
244 | ==, 0xFFFFFFFF); | |
245 | } | |
246 | ||
247 | qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x01); | |
248 | for (i = 0; i < NRF51_UICR_SIZE / 4; i++) { | |
249 | qtest_writel(qts, NRF51_UICR_BASE + i * 4, i); | |
250 | g_assert_cmpuint(qtest_readl(qts, NRF51_UICR_BASE + i * 4), ==, i); | |
251 | } | |
252 | qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); | |
253 | ||
254 | qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x02); | |
255 | qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_ERASEUICR, 0x01); | |
256 | qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); | |
257 | ||
258 | for (i = 0; i < NRF51_UICR_SIZE / 4; i++) { | |
259 | g_assert_cmpuint(qtest_readl(qts, NRF51_UICR_BASE + i * 4), | |
260 | ==, 0xFFFFFFFF); | |
261 | } | |
262 | ||
263 | qtest_quit(qts); | |
264 | } | |
265 | ||
17ff8e18 SG |
266 | static void test_nrf51_gpio(void) |
267 | { | |
268 | size_t i; | |
269 | uint32_t actual, expected; | |
270 | ||
271 | struct { | |
272 | hwaddr addr; | |
273 | uint32_t expected; | |
274 | } const reset_state[] = { | |
275 | {NRF51_GPIO_REG_OUT, 0x00000000}, {NRF51_GPIO_REG_OUTSET, 0x00000000}, | |
276 | {NRF51_GPIO_REG_OUTCLR, 0x00000000}, {NRF51_GPIO_REG_IN, 0x00000000}, | |
277 | {NRF51_GPIO_REG_DIR, 0x00000000}, {NRF51_GPIO_REG_DIRSET, 0x00000000}, | |
278 | {NRF51_GPIO_REG_DIRCLR, 0x00000000} | |
279 | }; | |
280 | ||
7cf19e73 JS |
281 | QTestState *qts = qtest_init("-M microbit"); |
282 | ||
17ff8e18 SG |
283 | /* Check reset state */ |
284 | for (i = 0; i < ARRAY_SIZE(reset_state); i++) { | |
285 | expected = reset_state[i].expected; | |
7cf19e73 | 286 | actual = qtest_readl(qts, NRF51_GPIO_BASE + reset_state[i].addr); |
17ff8e18 SG |
287 | g_assert_cmpuint(actual, ==, expected); |
288 | } | |
289 | ||
290 | for (i = 0; i < NRF51_GPIO_PINS; i++) { | |
291 | expected = 0x00000002; | |
7cf19e73 JS |
292 | actual = qtest_readl(qts, NRF51_GPIO_BASE + |
293 | NRF51_GPIO_REG_CNF_START + i * 4); | |
17ff8e18 SG |
294 | g_assert_cmpuint(actual, ==, expected); |
295 | } | |
296 | ||
297 | /* Check dir bit consistency between dir and cnf */ | |
298 | /* Check set via DIRSET */ | |
299 | expected = 0x80000001; | |
7cf19e73 JS |
300 | qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_DIRSET, expected); |
301 | actual = qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR); | |
17ff8e18 | 302 | g_assert_cmpuint(actual, ==, expected); |
7cf19e73 JS |
303 | actual = qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START) |
304 | & 0x01; | |
17ff8e18 | 305 | g_assert_cmpuint(actual, ==, 0x01); |
7cf19e73 | 306 | actual = qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_END) & 0x01; |
17ff8e18 SG |
307 | g_assert_cmpuint(actual, ==, 0x01); |
308 | ||
309 | /* Check clear via DIRCLR */ | |
7cf19e73 JS |
310 | qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_DIRCLR, 0x80000001); |
311 | actual = qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR); | |
17ff8e18 | 312 | g_assert_cmpuint(actual, ==, 0x00000000); |
7cf19e73 JS |
313 | actual = qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START) |
314 | & 0x01; | |
17ff8e18 | 315 | g_assert_cmpuint(actual, ==, 0x00); |
7cf19e73 | 316 | actual = qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_END) & 0x01; |
17ff8e18 SG |
317 | g_assert_cmpuint(actual, ==, 0x00); |
318 | ||
319 | /* Check set via DIR */ | |
320 | expected = 0x80000001; | |
7cf19e73 JS |
321 | qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR, expected); |
322 | actual = qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR); | |
17ff8e18 | 323 | g_assert_cmpuint(actual, ==, expected); |
7cf19e73 JS |
324 | actual = qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START) |
325 | & 0x01; | |
17ff8e18 | 326 | g_assert_cmpuint(actual, ==, 0x01); |
7cf19e73 | 327 | actual = qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_END) & 0x01; |
17ff8e18 SG |
328 | g_assert_cmpuint(actual, ==, 0x01); |
329 | ||
330 | /* Reset DIR */ | |
7cf19e73 | 331 | qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR, 0x00000000); |
17ff8e18 SG |
332 | |
333 | /* Check Input propagates */ | |
7cf19e73 JS |
334 | qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x00); |
335 | qtest_set_irq_in(qts, "/machine/nrf51", "unnamed-gpio-in", 0, 0); | |
336 | actual = qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; | |
17ff8e18 | 337 | g_assert_cmpuint(actual, ==, 0x00); |
7cf19e73 JS |
338 | qtest_set_irq_in(qts, "/machine/nrf51", "unnamed-gpio-in", 0, 1); |
339 | actual = qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; | |
17ff8e18 | 340 | g_assert_cmpuint(actual, ==, 0x01); |
7cf19e73 JS |
341 | qtest_set_irq_in(qts, "/machine/nrf51", "unnamed-gpio-in", 0, -1); |
342 | actual = qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; | |
17ff8e18 | 343 | g_assert_cmpuint(actual, ==, 0x01); |
7cf19e73 | 344 | qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x02); |
17ff8e18 SG |
345 | |
346 | /* Check pull-up working */ | |
7cf19e73 JS |
347 | qtest_set_irq_in(qts, "/machine/nrf51", "unnamed-gpio-in", 0, 0); |
348 | qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0000); | |
349 | actual = qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; | |
17ff8e18 | 350 | g_assert_cmpuint(actual, ==, 0x00); |
7cf19e73 JS |
351 | qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b1110); |
352 | actual = qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; | |
17ff8e18 | 353 | g_assert_cmpuint(actual, ==, 0x01); |
7cf19e73 | 354 | qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x02); |
17ff8e18 SG |
355 | |
356 | /* Check pull-down working */ | |
7cf19e73 JS |
357 | qtest_set_irq_in(qts, "/machine/nrf51", "unnamed-gpio-in", 0, 1); |
358 | qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0000); | |
359 | actual = qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; | |
17ff8e18 | 360 | g_assert_cmpuint(actual, ==, 0x01); |
7cf19e73 JS |
361 | qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0110); |
362 | actual = qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; | |
17ff8e18 | 363 | g_assert_cmpuint(actual, ==, 0x00); |
7cf19e73 JS |
364 | qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x02); |
365 | qtest_set_irq_in(qts, "/machine/nrf51", "unnamed-gpio-in", 0, -1); | |
17ff8e18 SG |
366 | |
367 | /* Check Output propagates */ | |
7cf19e73 JS |
368 | qtest_irq_intercept_out(qts, "/machine/nrf51"); |
369 | qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0011); | |
370 | qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTSET, 0x01); | |
371 | g_assert_true(qtest_get_irq(qts, 0)); | |
372 | qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTCLR, 0x01); | |
373 | g_assert_false(qtest_get_irq(qts, 0)); | |
17ff8e18 SG |
374 | |
375 | /* Check self-stimulation */ | |
7cf19e73 JS |
376 | qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b01); |
377 | qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTSET, 0x01); | |
378 | actual = qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; | |
17ff8e18 SG |
379 | g_assert_cmpuint(actual, ==, 0x01); |
380 | ||
7cf19e73 JS |
381 | qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTCLR, 0x01); |
382 | actual = qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; | |
17ff8e18 SG |
383 | g_assert_cmpuint(actual, ==, 0x00); |
384 | ||
385 | /* | |
386 | * Check short-circuit - generates an guest_error which must be checked | |
387 | * manually as long as qtest can not scan qemu_log messages | |
388 | */ | |
7cf19e73 JS |
389 | qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b01); |
390 | qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTSET, 0x01); | |
391 | qtest_set_irq_in(qts, "/machine/nrf51", "unnamed-gpio-in", 0, 0); | |
392 | ||
393 | qtest_quit(qts); | |
17ff8e18 SG |
394 | } |
395 | ||
7cf19e73 | 396 | static void timer_task(QTestState *qts, hwaddr task) |
7ec543e4 | 397 | { |
7cf19e73 | 398 | qtest_writel(qts, NRF51_TIMER_BASE + task, NRF51_TRIGGER_TASK); |
7ec543e4 SG |
399 | } |
400 | ||
7cf19e73 | 401 | static void timer_clear_event(QTestState *qts, hwaddr event) |
7ec543e4 | 402 | { |
7cf19e73 | 403 | qtest_writel(qts, NRF51_TIMER_BASE + event, NRF51_EVENT_CLEAR); |
7ec543e4 SG |
404 | } |
405 | ||
7cf19e73 | 406 | static void timer_set_bitmode(QTestState *qts, uint8_t mode) |
7ec543e4 | 407 | { |
7cf19e73 | 408 | qtest_writel(qts, NRF51_TIMER_BASE + NRF51_TIMER_REG_BITMODE, mode); |
7ec543e4 SG |
409 | } |
410 | ||
7cf19e73 | 411 | static void timer_set_prescaler(QTestState *qts, uint8_t prescaler) |
7ec543e4 | 412 | { |
7cf19e73 | 413 | qtest_writel(qts, NRF51_TIMER_BASE + NRF51_TIMER_REG_PRESCALER, prescaler); |
7ec543e4 SG |
414 | } |
415 | ||
7cf19e73 | 416 | static void timer_set_cc(QTestState *qts, size_t idx, uint32_t value) |
7ec543e4 | 417 | { |
7cf19e73 | 418 | qtest_writel(qts, NRF51_TIMER_BASE + NRF51_TIMER_REG_CC0 + idx * 4, value); |
7ec543e4 SG |
419 | } |
420 | ||
7cf19e73 JS |
421 | static void timer_assert_events(QTestState *qts, uint32_t ev0, uint32_t ev1, |
422 | uint32_t ev2, uint32_t ev3) | |
7ec543e4 | 423 | { |
7cf19e73 JS |
424 | g_assert(qtest_readl(qts, NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE_0) |
425 | == ev0); | |
426 | g_assert(qtest_readl(qts, NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE_1) | |
427 | == ev1); | |
428 | g_assert(qtest_readl(qts, NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE_2) | |
429 | == ev2); | |
430 | g_assert(qtest_readl(qts, NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE_3) | |
431 | == ev3); | |
7ec543e4 SG |
432 | } |
433 | ||
434 | static void test_nrf51_timer(void) | |
435 | { | |
436 | uint32_t steps_to_overflow = 408; | |
7cf19e73 | 437 | QTestState *qts = qtest_init("-M microbit"); |
7ec543e4 SG |
438 | |
439 | /* Compare Match */ | |
7cf19e73 JS |
440 | timer_task(qts, NRF51_TIMER_TASK_STOP); |
441 | timer_task(qts, NRF51_TIMER_TASK_CLEAR); | |
7ec543e4 | 442 | |
7cf19e73 JS |
443 | timer_clear_event(qts, NRF51_TIMER_EVENT_COMPARE_0); |
444 | timer_clear_event(qts, NRF51_TIMER_EVENT_COMPARE_1); | |
445 | timer_clear_event(qts, NRF51_TIMER_EVENT_COMPARE_2); | |
446 | timer_clear_event(qts, NRF51_TIMER_EVENT_COMPARE_3); | |
7ec543e4 | 447 | |
7cf19e73 JS |
448 | timer_set_bitmode(qts, NRF51_TIMER_WIDTH_16); /* 16 MHz Timer */ |
449 | timer_set_prescaler(qts, 0); | |
7ec543e4 | 450 | /* Swept over in first step */ |
7cf19e73 | 451 | timer_set_cc(qts, 0, 2); |
7ec543e4 | 452 | /* Barely miss on first step */ |
7cf19e73 | 453 | timer_set_cc(qts, 1, 162); |
7ec543e4 | 454 | /* Spot on on third step */ |
7cf19e73 | 455 | timer_set_cc(qts, 2, 480); |
7ec543e4 | 456 | |
7cf19e73 | 457 | timer_assert_events(qts, 0, 0, 0, 0); |
7ec543e4 | 458 | |
7cf19e73 JS |
459 | timer_task(qts, NRF51_TIMER_TASK_START); |
460 | qtest_clock_step(qts, 10000); | |
461 | timer_assert_events(qts, 1, 0, 0, 0); | |
7ec543e4 SG |
462 | |
463 | /* Swept over on first overflow */ | |
7cf19e73 | 464 | timer_set_cc(qts, 3, 114); |
7ec543e4 | 465 | |
7cf19e73 JS |
466 | qtest_clock_step(qts, 10000); |
467 | timer_assert_events(qts, 1, 1, 0, 0); | |
7ec543e4 | 468 | |
7cf19e73 JS |
469 | qtest_clock_step(qts, 10000); |
470 | timer_assert_events(qts, 1, 1, 1, 0); | |
7ec543e4 SG |
471 | |
472 | /* Wrap time until internal counter overflows */ | |
473 | while (steps_to_overflow--) { | |
7cf19e73 JS |
474 | timer_assert_events(qts, 1, 1, 1, 0); |
475 | qtest_clock_step(qts, 10000); | |
7ec543e4 SG |
476 | } |
477 | ||
7cf19e73 | 478 | timer_assert_events(qts, 1, 1, 1, 1); |
7ec543e4 | 479 | |
7cf19e73 JS |
480 | timer_clear_event(qts, NRF51_TIMER_EVENT_COMPARE_0); |
481 | timer_clear_event(qts, NRF51_TIMER_EVENT_COMPARE_1); | |
482 | timer_clear_event(qts, NRF51_TIMER_EVENT_COMPARE_2); | |
483 | timer_clear_event(qts, NRF51_TIMER_EVENT_COMPARE_3); | |
484 | timer_assert_events(qts, 0, 0, 0, 0); | |
7ec543e4 | 485 | |
7cf19e73 | 486 | timer_task(qts, NRF51_TIMER_TASK_STOP); |
7ec543e4 SG |
487 | |
488 | /* Test Proposal: Stop/Shutdown */ | |
489 | /* Test Proposal: Shortcut Compare -> Clear */ | |
490 | /* Test Proposal: Shortcut Compare -> Stop */ | |
491 | /* Test Proposal: Counter Mode */ | |
7cf19e73 JS |
492 | |
493 | qtest_quit(qts); | |
7ec543e4 SG |
494 | } |
495 | ||
17ff8e18 SG |
496 | int main(int argc, char **argv) |
497 | { | |
17ff8e18 SG |
498 | g_test_init(&argc, &argv, NULL); |
499 | ||
46a6603b | 500 | qtest_add_func("/microbit/nrf51/uart", test_nrf51_uart); |
17ff8e18 | 501 | qtest_add_func("/microbit/nrf51/gpio", test_nrf51_gpio); |
7743b70f | 502 | qtest_add_func("/microbit/nrf51/nvmc", test_nrf51_nvmc); |
7ec543e4 | 503 | qtest_add_func("/microbit/nrf51/timer", test_nrf51_timer); |
b36356f6 | 504 | qtest_add_func("/microbit/microbit/i2c", test_microbit_i2c); |
17ff8e18 | 505 | |
7cf19e73 | 506 | return g_test_run(); |
17ff8e18 | 507 | } |