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[qemu.git] / hw / pxa2xx_lcd.c
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a171fe39
AZ		 1/*
2 * Intel XScale PXA255/270 LCDC emulation.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <[email protected]>
6 *
7 * This code is licensed under the GPLv2.
8 */
9
87ecb68b
PB		 10#include "hw.h"
11#include "console.h"
12#include "pxa.h"
e27f01ef 13#include "pixel_ops.h"
87ecb68b
PB		 14/* FIXME: For graphic_rotate. Should probably be done in common code. */
15#include "sysemu.h"
714fa308 16#include "framebuffer.h"
a171fe39 17
2b7251e0
JQ		 18struct DMAChannel {
19 target_phys_addr_t branch;
46995409 20 uint8_t up;
2b7251e0
JQ		 21 uint8_t palette[1024];
22 uint8_t pbuffer[1024];
23 void (*redraw)(PXA2xxLCDState *s, target_phys_addr_t addr,
24 int *miny, int *maxy);
25
26 target_phys_addr_t descriptor;
27 target_phys_addr_t source;
28 uint32_t id;
29 uint32_t command;
30};
31
bc24a225 32struct PXA2xxLCDState {
a171fe39
AZ		 33 qemu_irq irq;
34 int irqlevel;
35
36 int invalidated;
37 DisplayState *ds;
38 drawfn *line_fn[2];
39 int dest_width;
40 int xres, yres;
41 int pal_for;
42 int transp;
43 enum {
44 pxa_lcdc_2bpp = 1,
45 pxa_lcdc_4bpp = 2,
46 pxa_lcdc_8bpp = 3,
47 pxa_lcdc_16bpp = 4,
48 pxa_lcdc_18bpp = 5,
49 pxa_lcdc_18pbpp = 6,
50 pxa_lcdc_19bpp = 7,
51 pxa_lcdc_19pbpp = 8,
52 pxa_lcdc_24bpp = 9,
53 pxa_lcdc_25bpp = 10,
54 } bpp;
55
56 uint32_t control[6];
57 uint32_t status[2];
58 uint32_t ovl1c[2];
59 uint32_t ovl2c[2];
60 uint32_t ccr;
61 uint32_t cmdcr;
62 uint32_t trgbr;
63 uint32_t tcr;
64 uint32_t liidr;
65 uint8_t bscntr;
66
2b7251e0 67 struct DMAChannel dma_ch[7];
a171fe39 68
38641a52 69 qemu_irq vsync_cb;
a171fe39
AZ		 70 int orientation;
71};
72
541dc0d4 73typedef struct QEMU_PACKED {
a171fe39
AZ		 74 uint32_t fdaddr;
75 uint32_t fsaddr;
76 uint32_t fidr;
77 uint32_t ldcmd;
bc24a225 78} PXAFrameDescriptor;
a171fe39
AZ		 79
80#define LCCR0 0x000 /* LCD Controller Control register 0 */
81#define LCCR1 0x004 /* LCD Controller Control register 1 */
82#define LCCR2 0x008 /* LCD Controller Control register 2 */
83#define LCCR3 0x00c /* LCD Controller Control register 3 */
84#define LCCR4 0x010 /* LCD Controller Control register 4 */
85#define LCCR5 0x014 /* LCD Controller Control register 5 */
86
87#define FBR0 0x020 /* DMA Channel 0 Frame Branch register */
88#define FBR1 0x024 /* DMA Channel 1 Frame Branch register */
89#define FBR2 0x028 /* DMA Channel 2 Frame Branch register */
90#define FBR3 0x02c /* DMA Channel 3 Frame Branch register */
91#define FBR4 0x030 /* DMA Channel 4 Frame Branch register */
92#define FBR5 0x110 /* DMA Channel 5 Frame Branch register */
93#define FBR6 0x114 /* DMA Channel 6 Frame Branch register */
94
95#define LCSR1 0x034 /* LCD Controller Status register 1 */
96#define LCSR0 0x038 /* LCD Controller Status register 0 */
97#define LIIDR 0x03c /* LCD Controller Interrupt ID register */
98
99#define TRGBR 0x040 /* TMED RGB Seed register */
100#define TCR 0x044 /* TMED Control register */
101
102#define OVL1C1 0x050 /* Overlay 1 Control register 1 */
103#define OVL1C2 0x060 /* Overlay 1 Control register 2 */
104#define OVL2C1 0x070 /* Overlay 2 Control register 1 */
105#define OVL2C2 0x080 /* Overlay 2 Control register 2 */
106#define CCR 0x090 /* Cursor Control register */
107
108#define CMDCR 0x100 /* Command Control register */
109#define PRSR 0x104 /* Panel Read Status register */
110
111#define PXA_LCDDMA_CHANS 7
112#define DMA_FDADR 0x00 /* Frame Descriptor Address register */
113#define DMA_FSADR 0x04 /* Frame Source Address register */
114#define DMA_FIDR 0x08 /* Frame ID register */
115#define DMA_LDCMD 0x0c /* Command register */
116
117/* LCD Buffer Strength Control register */
118#define BSCNTR 0x04000054
119
120/* Bitfield masks */
121#define LCCR0_ENB (1 << 0)
122#define LCCR0_CMS (1 << 1)
123#define LCCR0_SDS (1 << 2)
124#define LCCR0_LDM (1 << 3)
125#define LCCR0_SOFM0 (1 << 4)
126#define LCCR0_IUM (1 << 5)
127#define LCCR0_EOFM0 (1 << 6)
128#define LCCR0_PAS (1 << 7)
129#define LCCR0_DPD (1 << 9)
130#define LCCR0_DIS (1 << 10)
131#define LCCR0_QDM (1 << 11)
132#define LCCR0_PDD (0xff << 12)
133#define LCCR0_BSM0 (1 << 20)
134#define LCCR0_OUM (1 << 21)
135#define LCCR0_LCDT (1 << 22)
136#define LCCR0_RDSTM (1 << 23)
137#define LCCR0_CMDIM (1 << 24)
138#define LCCR0_OUC (1 << 25)
139#define LCCR0_LDDALT (1 << 26)
140#define LCCR1_PPL(x) ((x) & 0x3ff)
141#define LCCR2_LPP(x) ((x) & 0x3ff)
142#define LCCR3_API (15 << 16)
143#define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8))
144#define LCCR3_PDFOR(x) (((x) >> 30) & 3)
145#define LCCR4_K1(x) (((x) >> 0) & 7)
146#define LCCR4_K2(x) (((x) >> 3) & 7)
147#define LCCR4_K3(x) (((x) >> 6) & 7)
148#define LCCR4_PALFOR(x) (((x) >> 15) & 3)
149#define LCCR5_SOFM(ch) (1 << (ch - 1))
150#define LCCR5_EOFM(ch) (1 << (ch + 7))
151#define LCCR5_BSM(ch) (1 << (ch + 15))
152#define LCCR5_IUM(ch) (1 << (ch + 23))
153#define OVLC1_EN (1 << 31)
154#define CCR_CEN (1 << 31)
155#define FBR_BRA (1 << 0)
156#define FBR_BINT (1 << 1)
157#define FBR_SRCADDR (0xfffffff << 4)
158#define LCSR0_LDD (1 << 0)
159#define LCSR0_SOF0 (1 << 1)
160#define LCSR0_BER (1 << 2)
161#define LCSR0_ABC (1 << 3)
162#define LCSR0_IU0 (1 << 4)
163#define LCSR0_IU1 (1 << 5)
164#define LCSR0_OU (1 << 6)
165#define LCSR0_QD (1 << 7)
166#define LCSR0_EOF0 (1 << 8)
167#define LCSR0_BS0 (1 << 9)
168#define LCSR0_SINT (1 << 10)
169#define LCSR0_RDST (1 << 11)
170#define LCSR0_CMDINT (1 << 12)
171#define LCSR0_BERCH(x) (((x) & 7) << 28)
172#define LCSR1_SOF(ch) (1 << (ch - 1))
173#define LCSR1_EOF(ch) (1 << (ch + 7))
174#define LCSR1_BS(ch) (1 << (ch + 15))
175#define LCSR1_IU(ch) (1 << (ch + 23))
176#define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
177#define LDCMD_EOFINT (1 << 21)
178#define LDCMD_SOFINT (1 << 22)
179#define LDCMD_PAL (1 << 26)
180
181/* Route internal interrupt lines to the global IC */
bc24a225 182static void pxa2xx_lcdc_int_update(PXA2xxLCDState *s)
a171fe39
AZ		 183{
184 int level = 0;
185 level |= (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LDM);
186 level |= (s->status[0] & LCSR0_SOF0) && !(s->control[0] & LCCR0_SOFM0);
187 level |= (s->status[0] & LCSR0_IU0) && !(s->control[0] & LCCR0_IUM);
188 level |= (s->status[0] & LCSR0_IU1) && !(s->control[5] & LCCR5_IUM(1));
189 level |= (s->status[0] & LCSR0_OU) && !(s->control[0] & LCCR0_OUM);
190 level |= (s->status[0] & LCSR0_QD) && !(s->control[0] & LCCR0_QDM);
191 level |= (s->status[0] & LCSR0_EOF0) && !(s->control[0] & LCCR0_EOFM0);
192 level |= (s->status[0] & LCSR0_BS0) && !(s->control[0] & LCCR0_BSM0);
193 level |= (s->status[0] & LCSR0_RDST) && !(s->control[0] & LCCR0_RDSTM);
194 level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM);
195 level |= (s->status[1] & ~s->control[5]);
196
197 qemu_set_irq(s->irq, !!level);
198 s->irqlevel = level;
199}
200
201/* Set Branch Status interrupt high and poke associated registers */
bc24a225 202static inline void pxa2xx_dma_bs_set(PXA2xxLCDState *s, int ch)
a171fe39
AZ		 203{
204 int unmasked;
205 if (ch == 0) {
206 s->status[0] |= LCSR0_BS0;
207 unmasked = !(s->control[0] & LCCR0_BSM0);
208 } else {
209 s->status[1] |= LCSR1_BS(ch);
210 unmasked = !(s->control[5] & LCCR5_BSM(ch));
211 }
212
213 if (unmasked) {
214 if (s->irqlevel)
215 s->status[0] |= LCSR0_SINT;
216 else
217 s->liidr = s->dma_ch[ch].id;
218 }
219}
220
221/* Set Start Of Frame Status interrupt high and poke associated registers */
bc24a225 222static inline void pxa2xx_dma_sof_set(PXA2xxLCDState *s, int ch)
a171fe39
AZ		 223{
224 int unmasked;
225 if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
226 return;
227
228 if (ch == 0) {
229 s->status[0] |= LCSR0_SOF0;
230 unmasked = !(s->control[0] & LCCR0_SOFM0);
231 } else {
232 s->status[1] |= LCSR1_SOF(ch);
233 unmasked = !(s->control[5] & LCCR5_SOFM(ch));
234 }
235
236 if (unmasked) {
237 if (s->irqlevel)
238 s->status[0] |= LCSR0_SINT;
239 else
240 s->liidr = s->dma_ch[ch].id;
241 }
242}
243
244/* Set End Of Frame Status interrupt high and poke associated registers */
bc24a225 245static inline void pxa2xx_dma_eof_set(PXA2xxLCDState *s, int ch)
a171fe39
AZ		 246{
247 int unmasked;
248 if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
249 return;
250
251 if (ch == 0) {
252 s->status[0] |= LCSR0_EOF0;
253 unmasked = !(s->control[0] & LCCR0_EOFM0);
254 } else {
255 s->status[1] |= LCSR1_EOF(ch);
256 unmasked = !(s->control[5] & LCCR5_EOFM(ch));
257 }
258
259 if (unmasked) {
260 if (s->irqlevel)
261 s->status[0] |= LCSR0_SINT;
262 else
263 s->liidr = s->dma_ch[ch].id;
264 }
265}
266
267/* Set Bus Error Status interrupt high and poke associated registers */
bc24a225 268static inline void pxa2xx_dma_ber_set(PXA2xxLCDState *s, int ch)
a171fe39
AZ		 269{
270 s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
271 if (s->irqlevel)
272 s->status[0] |= LCSR0_SINT;
273 else
274 s->liidr = s->dma_ch[ch].id;
275}
276
277/* Set Read Status interrupt high and poke associated registers */
bc24a225 278static inline void pxa2xx_dma_rdst_set(PXA2xxLCDState *s)
a171fe39
AZ		 279{
280 s->status[0] |= LCSR0_RDST;
281 if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM))
282 s->status[0] |= LCSR0_SINT;
283}
284
285/* Load new Frame Descriptors from DMA */
bc24a225 286static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
a171fe39 287{
bc24a225 288 PXAFrameDescriptor desc;
c227f099 289 target_phys_addr_t descptr;
a171fe39
AZ		 290 int i;
291
292 for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
a171fe39
AZ		 293 s->dma_ch[i].source = 0;
294
295 if (!s->dma_ch[i].up)
296 continue;
297
298 if (s->dma_ch[i].branch & FBR_BRA) {
299 descptr = s->dma_ch[i].branch & FBR_SRCADDR;
300 if (s->dma_ch[i].branch & FBR_BINT)
301 pxa2xx_dma_bs_set(s, i);
302 s->dma_ch[i].branch &= ~FBR_BRA;
303 } else
304 descptr = s->dma_ch[i].descriptor;
305
d95b2f8d 306 if (!(descptr >= PXA2XX_SDRAM_BASE && descptr +
b0457b69 307 sizeof(desc) <= PXA2XX_SDRAM_BASE + ram_size))
a171fe39
AZ		 308 continue;
309
d7585251
PB		 310 cpu_physical_memory_read(descptr, (void *)&desc, sizeof(desc));
311 s->dma_ch[i].descriptor = tswap32(desc.fdaddr);
312 s->dma_ch[i].source = tswap32(desc.fsaddr);
313 s->dma_ch[i].id = tswap32(desc.fidr);
314 s->dma_ch[i].command = tswap32(desc.ldcmd);
a171fe39
AZ		 315 }
316}
317
c227f099 318static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset)
a171fe39 319{
bc24a225 320 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
a171fe39 321 int ch;
a171fe39
AZ		 322
323 switch (offset) {
324 case LCCR0:
325 return s->control[0];
326 case LCCR1:
327 return s->control[1];
328 case LCCR2:
329 return s->control[2];
330 case LCCR3:
331 return s->control[3];
332 case LCCR4:
333 return s->control[4];
334 case LCCR5:
335 return s->control[5];
336
337 case OVL1C1:
338 return s->ovl1c[0];
339 case OVL1C2:
340 return s->ovl1c[1];
341 case OVL2C1:
342 return s->ovl2c[0];
343 case OVL2C2:
344 return s->ovl2c[1];
345
346 case CCR:
347 return s->ccr;
348
349 case CMDCR:
350 return s->cmdcr;
351
352 case TRGBR:
353 return s->trgbr;
354 case TCR:
355 return s->tcr;
356
357 case 0x200 ... 0x1000: /* DMA per-channel registers */
358 ch = (offset - 0x200) >> 4;
359 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
360 goto fail;
361
362 switch (offset & 0xf) {
363 case DMA_FDADR:
364 return s->dma_ch[ch].descriptor;
365 case DMA_FSADR:
366 return s->dma_ch[ch].source;
367 case DMA_FIDR:
368 return s->dma_ch[ch].id;
369 case DMA_LDCMD:
370 return s->dma_ch[ch].command;
371 default:
372 goto fail;
373 }
374
375 case FBR0:
376 return s->dma_ch[0].branch;
377 case FBR1:
378 return s->dma_ch[1].branch;
379 case FBR2:
380 return s->dma_ch[2].branch;
381 case FBR3:
382 return s->dma_ch[3].branch;
383 case FBR4:
384 return s->dma_ch[4].branch;
385 case FBR5:
386 return s->dma_ch[5].branch;
387 case FBR6:
388 return s->dma_ch[6].branch;
389
390 case BSCNTR:
391 return s->bscntr;
392
393 case PRSR:
394 return 0;
395
396 case LCSR0:
397 return s->status[0];
398 case LCSR1:
399 return s->status[1];
400 case LIIDR:
401 return s->liidr;
402
403 default:
404 fail:
2ac71179 405 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
a171fe39
AZ		 406 }
407
408 return 0;
409}
410
411static void pxa2xx_lcdc_write(void *opaque,
c227f099 412 target_phys_addr_t offset, uint32_t value)
a171fe39 413{
bc24a225 414 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
a171fe39 415 int ch;
a171fe39
AZ		 416
417 switch (offset) {
418 case LCCR0:
419 /* ACK Quick Disable done */
420 if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB))
421 s->status[0] |= LCSR0_QD;
422
423 if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT))
424 printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
425
426 if ((s->control[3] & LCCR3_API) &&
427 (value & LCCR0_ENB) && !(value & LCCR0_LCDT))
428 s->status[0] |= LCSR0_ABC;
429
430 s->control[0] = value & 0x07ffffff;
431 pxa2xx_lcdc_int_update(s);
432
433 s->dma_ch[0].up = !!(value & LCCR0_ENB);
434 s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS);
435 break;
436
437 case LCCR1:
438 s->control[1] = value;
439 break;
440
441 case LCCR2:
442 s->control[2] = value;
443 break;
444
445 case LCCR3:
446 s->control[3] = value & 0xefffffff;
447 s->bpp = LCCR3_BPP(value);
448 break;
449
450 case LCCR4:
451 s->control[4] = value & 0x83ff81ff;
452 break;
453
454 case LCCR5:
455 s->control[5] = value & 0x3f3f3f3f;
456 break;
457
458 case OVL1C1:
459 if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN))
460 printf("%s: Overlay 1 not supported\n", __FUNCTION__);
461
462 s->ovl1c[0] = value & 0x80ffffff;
463 s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS);
464 break;
465
466 case OVL1C2:
467 s->ovl1c[1] = value & 0x000fffff;
468 break;
469
470 case OVL2C1:
471 if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN))
472 printf("%s: Overlay 2 not supported\n", __FUNCTION__);
473
474 s->ovl2c[0] = value & 0x80ffffff;
475 s->dma_ch[2].up = !!(value & OVLC1_EN);
476 s->dma_ch[3].up = !!(value & OVLC1_EN);
477 s->dma_ch[4].up = !!(value & OVLC1_EN);
478 break;
479
480 case OVL2C2:
481 s->ovl2c[1] = value & 0x007fffff;
482 break;
483
484 case CCR:
485 if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
486 printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
487
488 s->ccr = value & 0x81ffffe7;
489 s->dma_ch[5].up = !!(value & CCR_CEN);
490 break;
491
492 case CMDCR:
493 s->cmdcr = value & 0xff;
494 break;
495
496 case TRGBR:
497 s->trgbr = value & 0x00ffffff;
498 break;
499
500 case TCR:
501 s->tcr = value & 0x7fff;
502 break;
503
504 case 0x200 ... 0x1000: /* DMA per-channel registers */
505 ch = (offset - 0x200) >> 4;
506 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
507 goto fail;
508
509 switch (offset & 0xf) {
510 case DMA_FDADR:
511 s->dma_ch[ch].descriptor = value & 0xfffffff0;
512 break;
513
514 default:
515 goto fail;
516 }
517 break;
518
519 case FBR0:
520 s->dma_ch[0].branch = value & 0xfffffff3;
521 break;
522 case FBR1:
523 s->dma_ch[1].branch = value & 0xfffffff3;
524 break;
525 case FBR2:
526 s->dma_ch[2].branch = value & 0xfffffff3;
527 break;
528 case FBR3:
529 s->dma_ch[3].branch = value & 0xfffffff3;
530 break;
531 case FBR4:
532 s->dma_ch[4].branch = value & 0xfffffff3;
533 break;
534 case FBR5:
535 s->dma_ch[5].branch = value & 0xfffffff3;
536 break;
537 case FBR6:
538 s->dma_ch[6].branch = value & 0xfffffff3;
539 break;
540
541 case BSCNTR:
542 s->bscntr = value & 0xf;
543 break;
544
545 case PRSR:
546 break;
547
548 case LCSR0:
549 s->status[0] &= ~(value & 0xfff);
550 if (value & LCSR0_BER)
551 s->status[0] &= ~LCSR0_BERCH(7);
552 break;
553
554 case LCSR1:
555 s->status[1] &= ~(value & 0x3e3f3f);
556 break;
557
558 default:
559 fail:
2ac71179 560 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
a171fe39
AZ		 561 }
562}
563
d60efc6b 564static CPUReadMemoryFunc * const pxa2xx_lcdc_readfn[] = {
a171fe39
AZ		 565 pxa2xx_lcdc_read,
566 pxa2xx_lcdc_read,
567 pxa2xx_lcdc_read
568};
569
d60efc6b 570static CPUWriteMemoryFunc * const pxa2xx_lcdc_writefn[] = {
a171fe39
AZ		 571 pxa2xx_lcdc_write,
572 pxa2xx_lcdc_write,
573 pxa2xx_lcdc_write
574};
575
a171fe39 576/* Load new palette for a given DMA channel, convert to internal format */
bc24a225 577static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp)
a171fe39
AZ		 578{
579 int i, n, format, r, g, b, alpha;
580 uint32_t *dest, *src;
581 s->pal_for = LCCR4_PALFOR(s->control[4]);
582 format = s->pal_for;
583
584 switch (bpp) {
585 case pxa_lcdc_2bpp:
586 n = 4;
587 break;
588 case pxa_lcdc_4bpp:
589 n = 16;
590 break;
591 case pxa_lcdc_8bpp:
592 n = 256;
593 break;
594 default:
595 format = 0;
596 return;
597 }
598
599 src = (uint32_t *) s->dma_ch[ch].pbuffer;
600 dest = (uint32_t *) s->dma_ch[ch].palette;
601 alpha = r = g = b = 0;
602
603 for (i = 0; i < n; i ++) {
604 switch (format) {
605 case 0: /* 16 bpp, no transparency */
606 alpha = 0;
607 if (s->control[0] & LCCR0_CMS)
608 r = g = b = *src & 0xff;
609 else {
610 r = (*src & 0xf800) >> 8;
611 g = (*src & 0x07e0) >> 3;
612 b = (*src & 0x001f) << 3;
613 }
614 break;
615 case 1: /* 16 bpp plus transparency */
616 alpha = *src & (1 << 24);
617 if (s->control[0] & LCCR0_CMS)
618 r = g = b = *src & 0xff;
619 else {
620 r = (*src & 0xf800) >> 8;
621 g = (*src & 0x07e0) >> 3;
622 b = (*src & 0x001f) << 3;
623 }
624 break;
625 case 2: /* 18 bpp plus transparency */
626 alpha = *src & (1 << 24);
627 if (s->control[0] & LCCR0_CMS)
628 r = g = b = *src & 0xff;
629 else {
630 r = (*src & 0xf80000) >> 16;
631 g = (*src & 0x00fc00) >> 8;
632 b = (*src & 0x0000f8);
633 }
634 break;
635 case 3: /* 24 bpp plus transparency */
636 alpha = *src & (1 << 24);
637 if (s->control[0] & LCCR0_CMS)
638 r = g = b = *src & 0xff;
639 else {
640 r = (*src & 0xff0000) >> 16;
641 g = (*src & 0x00ff00) >> 8;
642 b = (*src & 0x0000ff);
643 }
644 break;
645 }
0e1f5a0c 646 switch (ds_get_bits_per_pixel(s->ds)) {
a171fe39
AZ		 647 case 8:
648 *dest = rgb_to_pixel8(r, g, b) | alpha;
649 break;
650 case 15:
651 *dest = rgb_to_pixel15(r, g, b) | alpha;
652 break;
653 case 16:
654 *dest = rgb_to_pixel16(r, g, b) | alpha;
655 break;
656 case 24:
657 *dest = rgb_to_pixel24(r, g, b) | alpha;
658 break;
659 case 32:
660 *dest = rgb_to_pixel32(r, g, b) | alpha;
661 break;
662 }
663 src ++;
664 dest ++;
665 }
666}
667
9312805d 668static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s,
c227f099 669 target_phys_addr_t addr, int *miny, int *maxy)
a171fe39 670{
714fa308 671 int src_width, dest_width;
b9d38e95 672 drawfn fn = NULL;
a171fe39
AZ		 673 if (s->dest_width)
674 fn = s->line_fn[s->transp][s->bpp];
675 if (!fn)
676 return;
677
a171fe39
AZ		 678 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
679 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
680 src_width *= 3;
681 else if (s->bpp > pxa_lcdc_16bpp)
682 src_width *= 4;
683 else if (s->bpp > pxa_lcdc_8bpp)
684 src_width *= 2;
685
a171fe39 686 dest_width = s->xres * s->dest_width;
714fa308
PB		 687 *miny = 0;
688 framebuffer_update_display(s->ds,
689 addr, s->xres, s->yres,
690 src_width, dest_width, s->dest_width,
691 s->invalidated,
692 fn, s->dma_ch[0].palette, miny, maxy);
a171fe39
AZ		 693}
694
9312805d 695static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s,
c227f099 696 target_phys_addr_t addr, int *miny, int *maxy)
a171fe39 697{
714fa308 698 int src_width, dest_width;
b9d38e95 699 drawfn fn = NULL;
a171fe39
AZ		 700 if (s->dest_width)
701 fn = s->line_fn[s->transp][s->bpp];
702 if (!fn)
703 return;
704
a171fe39
AZ		 705 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
706 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
707 src_width *= 3;
708 else if (s->bpp > pxa_lcdc_16bpp)
709 src_width *= 4;
710 else if (s->bpp > pxa_lcdc_8bpp)
711 src_width *= 2;
712
713 dest_width = s->yres * s->dest_width;
714fa308
PB		 714 *miny = 0;
715 framebuffer_update_display(s->ds,
716 addr, s->xres, s->yres,
717 src_width, s->dest_width, -dest_width,
718 s->invalidated,
719 fn, s->dma_ch[0].palette,
720 miny, maxy);
a171fe39
AZ		 721}
722
9312805d
VK		 723static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState *s,
724 target_phys_addr_t addr, int *miny, int *maxy)
725{
726 int src_width, dest_width;
727 drawfn fn = NULL;
728 if (s->dest_width) {
729 fn = s->line_fn[s->transp][s->bpp];
730 }
731 if (!fn) {
732 return;
733 }
734
735 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
736 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp) {
737 src_width *= 3;
738 } else if (s->bpp > pxa_lcdc_16bpp) {
739 src_width *= 4;
740 } else if (s->bpp > pxa_lcdc_8bpp) {
741 src_width *= 2;
742 }
743
744 dest_width = s->xres * s->dest_width;
745 *miny = 0;
746 framebuffer_update_display(s->ds,
747 addr, s->xres, s->yres,
748 src_width, -dest_width, -s->dest_width,
749 s->invalidated,
750 fn, s->dma_ch[0].palette, miny, maxy);
751}
752
753static void pxa2xx_lcdc_dma0_redraw_rot270(PXA2xxLCDState *s,
754 target_phys_addr_t addr, int *miny, int *maxy)
755{
756 int src_width, dest_width;
757 drawfn fn = NULL;
758 if (s->dest_width) {
759 fn = s->line_fn[s->transp][s->bpp];
760 }
761 if (!fn) {
762 return;
763 }
764
765 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
766 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp) {
767 src_width *= 3;
768 } else if (s->bpp > pxa_lcdc_16bpp) {
769 src_width *= 4;
770 } else if (s->bpp > pxa_lcdc_8bpp) {
771 src_width *= 2;
772 }
773
774 dest_width = s->yres * s->dest_width;
775 *miny = 0;
776 framebuffer_update_display(s->ds,
777 addr, s->xres, s->yres,
778 src_width, -s->dest_width, dest_width,
779 s->invalidated,
780 fn, s->dma_ch[0].palette,
781 miny, maxy);
782}
783
bc24a225 784static void pxa2xx_lcdc_resize(PXA2xxLCDState *s)
a171fe39
AZ		 785{
786 int width, height;
787 if (!(s->control[0] & LCCR0_ENB))
788 return;
789
790 width = LCCR1_PPL(s->control[1]) + 1;
791 height = LCCR2_LPP(s->control[2]) + 1;
792
793 if (width != s->xres || height != s->yres) {
9312805d 794 if (s->orientation == 90 || s->orientation == 270) {
3023f332 795 qemu_console_resize(s->ds, height, width);
9312805d 796 } else {
3023f332 797 qemu_console_resize(s->ds, width, height);
9312805d 798 }
a171fe39
AZ		 799 s->invalidated = 1;
800 s->xres = width;
801 s->yres = height;
802 }
803}
804
805static void pxa2xx_update_display(void *opaque)
806{
bc24a225 807 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
c227f099 808 target_phys_addr_t fbptr;
a171fe39
AZ		 809 int miny, maxy;
810 int ch;
811 if (!(s->control[0] & LCCR0_ENB))
812 return;
813
814 pxa2xx_descriptor_load(s);
815
816 pxa2xx_lcdc_resize(s);
817 miny = s->yres;
818 maxy = 0;
819 s->transp = s->dma_ch[2].up || s->dma_ch[3].up;
820 /* Note: With overlay planes the order depends on LCCR0 bit 25. */
821 for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++)
822 if (s->dma_ch[ch].up) {
823 if (!s->dma_ch[ch].source) {
824 pxa2xx_dma_ber_set(s, ch);
825 continue;
826 }
827 fbptr = s->dma_ch[ch].source;
d95b2f8d 828 if (!(fbptr >= PXA2XX_SDRAM_BASE &&
b0457b69 829 fbptr <= PXA2XX_SDRAM_BASE + ram_size)) {
a171fe39
AZ		 830 pxa2xx_dma_ber_set(s, ch);
831 continue;
832 }
a171fe39
AZ		 833
834 if (s->dma_ch[ch].command & LDCMD_PAL) {
714fa308
PB		 835 cpu_physical_memory_read(fbptr, s->dma_ch[ch].pbuffer,
836 MAX(LDCMD_LENGTH(s->dma_ch[ch].command),
837 sizeof(s->dma_ch[ch].pbuffer)));
a171fe39
AZ		 838 pxa2xx_palette_parse(s, ch, s->bpp);
839 } else {
840 /* Do we need to reparse palette */
841 if (LCCR4_PALFOR(s->control[4]) != s->pal_for)
842 pxa2xx_palette_parse(s, ch, s->bpp);
843
844 /* ACK frame start */
845 pxa2xx_dma_sof_set(s, ch);
846
714fa308 847 s->dma_ch[ch].redraw(s, fbptr, &miny, &maxy);
a171fe39
AZ		 848 s->invalidated = 0;
849
850 /* ACK frame completed */
851 pxa2xx_dma_eof_set(s, ch);
852 }
853 }
854
855 if (s->control[0] & LCCR0_DIS) {
856 /* ACK last frame completed */
857 s->control[0] &= ~LCCR0_ENB;
858 s->status[0] |= LCSR0_LDD;
859 }
860
714fa308 861 if (miny >= 0) {
9312805d
VK		 862 switch (s->orientation) {
863 case 0:
864 dpy_update(s->ds, 0, miny, s->xres, maxy - miny + 1);
865 break;
866 case 90:
867 dpy_update(s->ds, miny, 0, maxy - miny + 1, s->xres);
868 break;
869 case 180:
870 maxy = s->yres - maxy - 1;
871 miny = s->yres - miny - 1;
872 dpy_update(s->ds, 0, maxy, s->xres, miny - maxy + 1);
873 break;
874 case 270:
875 maxy = s->yres - maxy - 1;
876 miny = s->yres - miny - 1;
877 dpy_update(s->ds, maxy, 0, miny - maxy + 1, s->xres);
878 break;
879 }
714fa308 880 }
a171fe39
AZ		 881 pxa2xx_lcdc_int_update(s);
882
38641a52 883 qemu_irq_raise(s->vsync_cb);
a171fe39
AZ		 884}
885
886static void pxa2xx_invalidate_display(void *opaque)
887{
bc24a225 888 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
a171fe39
AZ		 889 s->invalidated = 1;
890}
891
892static void pxa2xx_screen_dump(void *opaque, const char *filename)
893{
894 /* TODO */
895}
896
9596ebb7 897static void pxa2xx_lcdc_orientation(void *opaque, int angle)
a171fe39 898{
bc24a225 899 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
a171fe39 900
9312805d
VK		 901 switch (angle) {
902 case 0:
903 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot0;
904 break;
905 case 90:
906 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot90;
907 break;
908 case 180:
909 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot180;
910 break;
911 case 270:
912 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot270;
913 break;
a171fe39
AZ		 914 }
915
916 s->orientation = angle;
917 s->xres = s->yres = -1;
918 pxa2xx_lcdc_resize(s);
919}
920
99838363
JQ		 921static const VMStateDescription vmstate_dma_channel = {
922 .name = "dma_channel",
923 .version_id = 0,
924 .minimum_version_id = 0,
925 .minimum_version_id_old = 0,
926 .fields = (VMStateField[]) {
927 VMSTATE_UINTTL(branch, struct DMAChannel),
928 VMSTATE_UINT8(up, struct DMAChannel),
929 VMSTATE_BUFFER(pbuffer, struct DMAChannel),
930 VMSTATE_UINTTL(descriptor, struct DMAChannel),
931 VMSTATE_UINTTL(source, struct DMAChannel),
932 VMSTATE_UINT32(id, struct DMAChannel),
933 VMSTATE_UINT32(command, struct DMAChannel),
934 VMSTATE_END_OF_LIST()
aa941b94 935 }
99838363 936};
aa941b94 937
99838363 938static int pxa2xx_lcdc_post_load(void *opaque, int version_id)
aa941b94 939{
99838363 940 PXA2xxLCDState *s = opaque;
aa941b94
AZ		 941
942 s->bpp = LCCR3_BPP(s->control[3]);
943 s->xres = s->yres = s->pal_for = -1;
944
945 return 0;
946}
947
99838363
JQ		 948static const VMStateDescription vmstate_pxa2xx_lcdc = {
949 .name = "pxa2xx_lcdc",
950 .version_id = 0,
951 .minimum_version_id = 0,
952 .minimum_version_id_old = 0,
953 .post_load = pxa2xx_lcdc_post_load,
954 .fields = (VMStateField[]) {
955 VMSTATE_INT32(irqlevel, PXA2xxLCDState),
956 VMSTATE_INT32(transp, PXA2xxLCDState),
957 VMSTATE_UINT32_ARRAY(control, PXA2xxLCDState, 6),
958 VMSTATE_UINT32_ARRAY(status, PXA2xxLCDState, 2),
959 VMSTATE_UINT32_ARRAY(ovl1c, PXA2xxLCDState, 2),
960 VMSTATE_UINT32_ARRAY(ovl2c, PXA2xxLCDState, 2),
961 VMSTATE_UINT32(ccr, PXA2xxLCDState),
962 VMSTATE_UINT32(cmdcr, PXA2xxLCDState),
963 VMSTATE_UINT32(trgbr, PXA2xxLCDState),
964 VMSTATE_UINT32(tcr, PXA2xxLCDState),
965 VMSTATE_UINT32(liidr, PXA2xxLCDState),
966 VMSTATE_UINT8(bscntr, PXA2xxLCDState),
967 VMSTATE_STRUCT_ARRAY(dma_ch, PXA2xxLCDState, 7, 0,
968 vmstate_dma_channel, struct DMAChannel),
969 VMSTATE_END_OF_LIST()
970 }
971};
972
a171fe39
AZ		 973#define BITS 8
974#include "pxa2xx_template.h"
975#define BITS 15
976#include "pxa2xx_template.h"
977#define BITS 16
978#include "pxa2xx_template.h"
979#define BITS 24
980#include "pxa2xx_template.h"
981#define BITS 32
982#include "pxa2xx_template.h"
983
c227f099 984PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq)
a171fe39
AZ		 985{
986 int iomemtype;
bc24a225 987 PXA2xxLCDState *s;
a171fe39 988
7267c094 989 s = (PXA2xxLCDState *) g_malloc0(sizeof(PXA2xxLCDState));
a171fe39
AZ		 990 s->invalidated = 1;
991 s->irq = irq;
a171fe39
AZ		 992
993 pxa2xx_lcdc_orientation(s, graphic_rotate);
994
1eed09cb 995 iomemtype = cpu_register_io_memory(pxa2xx_lcdc_readfn,
2507c12a 996 pxa2xx_lcdc_writefn, s, DEVICE_NATIVE_ENDIAN);
187337f8 997 cpu_register_physical_memory(base, 0x00100000, iomemtype);
a171fe39 998
3023f332
AL		 999 s->ds = graphic_console_init(pxa2xx_update_display,
1000 pxa2xx_invalidate_display,
1001 pxa2xx_screen_dump, NULL, s);
a171fe39 1002
0e1f5a0c 1003 switch (ds_get_bits_per_pixel(s->ds)) {
a171fe39
AZ		 1004 case 0:
1005 s->dest_width = 0;
1006 break;
1007 case 8:
1008 s->line_fn[0] = pxa2xx_draw_fn_8;
1009 s->line_fn[1] = pxa2xx_draw_fn_8t;
1010 s->dest_width = 1;
1011 break;
1012 case 15:
1013 s->line_fn[0] = pxa2xx_draw_fn_15;
1014 s->line_fn[1] = pxa2xx_draw_fn_15t;
1015 s->dest_width = 2;
1016 break;
1017 case 16:
1018 s->line_fn[0] = pxa2xx_draw_fn_16;
1019 s->line_fn[1] = pxa2xx_draw_fn_16t;
1020 s->dest_width = 2;
1021 break;
1022 case 24:
1023 s->line_fn[0] = pxa2xx_draw_fn_24;
1024 s->line_fn[1] = pxa2xx_draw_fn_24t;
1025 s->dest_width = 3;
1026 break;
1027 case 32:
1028 s->line_fn[0] = pxa2xx_draw_fn_32;
1029 s->line_fn[1] = pxa2xx_draw_fn_32t;
1030 s->dest_width = 4;
1031 break;
1032 default:
1033 fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
1034 exit(1);
1035 }
aa941b94 1036
99838363 1037 vmstate_register(NULL, 0, &vmstate_pxa2xx_lcdc, s);
aa941b94 1038
a171fe39
AZ		 1039 return s;
1040}
1041
bc24a225 1042void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler)
38641a52
AZ		 1043{
1044 s->vsync_cb = handler;
a171fe39 1045}
Empty description
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