[qemu.git] / tcg / tci / tcg-target.h

/*
 * Tiny Code Generator for QEMU
 *
 * Copyright (c) 2009, 2011 Stefan Weil
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/*
 * This code implements a TCG which does not generate machine code for some
 * real target machine but which generates virtual machine code for an
 * interpreter. Interpreted pseudo code is slow, but it works on any host.
 *
 * Some remarks might help in understanding the code:
 *
 * "target" or "TCG target" is the machine which runs the generated code.
 * This is different to the usual meaning in QEMU where "target" is the
 * emulated machine. So normally QEMU host is identical to TCG target.
 * Here the TCG target is a virtual machine, but this virtual machine must
 * use the same word size like the real machine.
 * Therefore, we need both 32 and 64 bit virtual machines (interpreter).
 */

#if !defined(TCG_TARGET_H)
#define TCG_TARGET_H

#include "config-host.h"

#define TCG_TARGET_INTERPRETER 1

#ifdef CONFIG_DEBUG_TCG
/* Enable debug output. */
#define CONFIG_DEBUG_TCG_INTERPRETER
#endif

#if 0 /* TCI tries to emulate a little endian host. */
#if defined(HOST_WORDS_BIGENDIAN)
# define TCG_TARGET_WORDS_BIGENDIAN
#endif
#endif

/* Optional instructions. */

#define TCG_TARGET_HAS_bswap16_i32      1
#define TCG_TARGET_HAS_bswap32_i32      1
/* Not more than one of the next two defines must be 1. */
#define TCG_TARGET_HAS_div_i32          1
#define TCG_TARGET_HAS_div2_i32         0
#define TCG_TARGET_HAS_ext8s_i32        1
#define TCG_TARGET_HAS_ext16s_i32       1
#define TCG_TARGET_HAS_ext8u_i32        1
#define TCG_TARGET_HAS_ext16u_i32       1
#define TCG_TARGET_HAS_andc_i32         0
#define TCG_TARGET_HAS_deposit_i32      0
#define TCG_TARGET_HAS_eqv_i32          0
#define TCG_TARGET_HAS_nand_i32         0
#define TCG_TARGET_HAS_nor_i32          0
#define TCG_TARGET_HAS_neg_i32          1
#define TCG_TARGET_HAS_not_i32          1
#define TCG_TARGET_HAS_orc_i32          0
#define TCG_TARGET_HAS_rot_i32          1

#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_bswap16_i64      1
#define TCG_TARGET_HAS_bswap32_i64      1
#define TCG_TARGET_HAS_bswap64_i64      1
#define TCG_TARGET_HAS_deposit_i64      0
/* Not more than one of the next two defines must be 1. */
#define TCG_TARGET_HAS_div_i64          0
#define TCG_TARGET_HAS_div2_i64         0
#define TCG_TARGET_HAS_ext8s_i64        1
#define TCG_TARGET_HAS_ext16s_i64       1
#define TCG_TARGET_HAS_ext32s_i64       1
#define TCG_TARGET_HAS_ext8u_i64        1
#define TCG_TARGET_HAS_ext16u_i64       1
#define TCG_TARGET_HAS_ext32u_i64       1
#define TCG_TARGET_HAS_andc_i64         0
#define TCG_TARGET_HAS_eqv_i64          0
#define TCG_TARGET_HAS_nand_i64         0
#define TCG_TARGET_HAS_nor_i64          0
#define TCG_TARGET_HAS_neg_i64          1
#define TCG_TARGET_HAS_not_i64          1
#define TCG_TARGET_HAS_orc_i64          0
#define TCG_TARGET_HAS_rot_i64          1
#endif /* TCG_TARGET_REG_BITS == 64 */

/* Offset to user memory in user mode. */
#define TCG_TARGET_HAS_GUEST_BASE

/* Number of registers available.
   For 32 bit hosts, we need more than 8 registers (call arguments). */
/* #define TCG_TARGET_NB_REGS 8 */
#define TCG_TARGET_NB_REGS 16
/* #define TCG_TARGET_NB_REGS 32 */

/* List of registers which are used by TCG. */
typedef enum {
    TCG_REG_R0 = 0,
    TCG_REG_R1,
    TCG_REG_R2,
    TCG_REG_R3,
    TCG_REG_R4,
    TCG_REG_R5,
    TCG_REG_R6,
    TCG_REG_R7,
    TCG_AREG0 = TCG_REG_R7,
#if TCG_TARGET_NB_REGS >= 16
    TCG_REG_R8,
    TCG_REG_R9,
    TCG_REG_R10,
    TCG_REG_R11,
    TCG_REG_R12,
    TCG_REG_R13,
    TCG_REG_R14,
    TCG_REG_R15,
#if TCG_TARGET_NB_REGS >= 32
    TCG_REG_R16,
    TCG_REG_R17,
    TCG_REG_R18,
    TCG_REG_R19,
    TCG_REG_R20,
    TCG_REG_R21,
    TCG_REG_R22,
    TCG_REG_R23,
    TCG_REG_R24,
    TCG_REG_R25,
    TCG_REG_R26,
    TCG_REG_R27,
    TCG_REG_R28,
    TCG_REG_R29,
    TCG_REG_R30,
    TCG_REG_R31,
#endif
#endif
    /* Special value UINT8_MAX is used by TCI to encode constant values. */
    TCG_CONST = UINT8_MAX
} TCGReg;

void tci_disas(uint8_t opc);

tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
#define tcg_qemu_tb_exec tcg_qemu_tb_exec

static inline void flush_icache_range(tcg_target_ulong start,
                                      tcg_target_ulong stop)
{
}

#endif /* TCG_TARGET_H */
Commit	Line	Data
7316329a SW	1	/*
	2	* Tiny Code Generator for QEMU
	3	*
	4	* Copyright (c) 2009, 2011 Stefan Weil
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	/*
	26	* This code implements a TCG which does not generate machine code for some
	27	* real target machine but which generates virtual machine code for an
	28	* interpreter. Interpreted pseudo code is slow, but it works on any host.
	29	*
	30	* Some remarks might help in understanding the code:
	31	*
	32	* "target" or "TCG target" is the machine which runs the generated code.
	33	* This is different to the usual meaning in QEMU where "target" is the
	34	* emulated machine. So normally QEMU host is identical to TCG target.
	35	* Here the TCG target is a virtual machine, but this virtual machine must
	36	* use the same word size like the real machine.
	37	* Therefore, we need both 32 and 64 bit virtual machines (interpreter).
	38	*/
	39
	40	#if !defined(TCG_TARGET_H)
	41	#define TCG_TARGET_H
	42
	43	#include "config-host.h"
	44
	45	#define TCG_TARGET_INTERPRETER 1
	46
	47	#ifdef CONFIG_DEBUG_TCG
	48	/* Enable debug output. */
	49	#define CONFIG_DEBUG_TCG_INTERPRETER
	50	#endif
	51
	52	#if 0 /* TCI tries to emulate a little endian host. */
	53	#if defined(HOST_WORDS_BIGENDIAN)
	54	# define TCG_TARGET_WORDS_BIGENDIAN
	55	#endif
	56	#endif
	57
	58	/* Optional instructions. */
	59
	60	#define TCG_TARGET_HAS_bswap16_i32 1
	61	#define TCG_TARGET_HAS_bswap32_i32 1
	62	/* Not more than one of the next two defines must be 1. */
	63	#define TCG_TARGET_HAS_div_i32 1
	64	#define TCG_TARGET_HAS_div2_i32 0
65	#define TCG_TARGET_HAS_ext8s_i32 1
66	#define TCG_TARGET_HAS_ext16s_i32 1
67	#define TCG_TARGET_HAS_ext8u_i32 1
68	#define TCG_TARGET_HAS_ext16u_i32 1
69	#define TCG_TARGET_HAS_andc_i32 0
70	#define TCG_TARGET_HAS_deposit_i32 0
71	#define TCG_TARGET_HAS_eqv_i32 0
72	#define TCG_TARGET_HAS_nand_i32 0
73	#define TCG_TARGET_HAS_nor_i32 0
74	#define TCG_TARGET_HAS_neg_i32 1
75	#define TCG_TARGET_HAS_not_i32 1
76	#define TCG_TARGET_HAS_orc_i32 0
77	#define TCG_TARGET_HAS_rot_i32 1
78
79	#if TCG_TARGET_REG_BITS == 64
80	#define TCG_TARGET_HAS_bswap16_i64 1
81	#define TCG_TARGET_HAS_bswap32_i64 1
82	#define TCG_TARGET_HAS_bswap64_i64 1
83	#define TCG_TARGET_HAS_deposit_i64 0
84	/* Not more than one of the next two defines must be 1. */
85	#define TCG_TARGET_HAS_div_i64 0
86	#define TCG_TARGET_HAS_div2_i64 0
87	#define TCG_TARGET_HAS_ext8s_i64 1
88	#define TCG_TARGET_HAS_ext16s_i64 1
89	#define TCG_TARGET_HAS_ext32s_i64 1
90	#define TCG_TARGET_HAS_ext8u_i64 1
91	#define TCG_TARGET_HAS_ext16u_i64 1
92	#define TCG_TARGET_HAS_ext32u_i64 1
93	#define TCG_TARGET_HAS_andc_i64 0
94	#define TCG_TARGET_HAS_eqv_i64 0
95	#define TCG_TARGET_HAS_nand_i64 0
96	#define TCG_TARGET_HAS_nor_i64 0
97	#define TCG_TARGET_HAS_neg_i64 1
98	#define TCG_TARGET_HAS_not_i64 1
99	#define TCG_TARGET_HAS_orc_i64 0
100	#define TCG_TARGET_HAS_rot_i64 1
101	#endif /* TCG_TARGET_REG_BITS == 64 */
102
103	/* Offset to user memory in user mode. */
104	#define TCG_TARGET_HAS_GUEST_BASE
105
106	/* Number of registers available.
107	For 32 bit hosts, we need more than 8 registers (call arguments). */
108	/* #define TCG_TARGET_NB_REGS 8 */
109	#define TCG_TARGET_NB_REGS 16
110	/* #define TCG_TARGET_NB_REGS 32 */
111
112	/* List of registers which are used by TCG. */
113	typedef enum {
114	TCG_REG_R0 = 0,
115	TCG_REG_R1,
116	TCG_REG_R2,
117	TCG_REG_R3,
118	TCG_REG_R4,
119	TCG_REG_R5,
120	TCG_REG_R6,
121	TCG_REG_R7,
122	TCG_AREG0 = TCG_REG_R7,
123	#if TCG_TARGET_NB_REGS >= 16
124	TCG_REG_R8,
125	TCG_REG_R9,
126	TCG_REG_R10,
127	TCG_REG_R11,
128	TCG_REG_R12,
129	TCG_REG_R13,
130	TCG_REG_R14,
131	TCG_REG_R15,
132	#if TCG_TARGET_NB_REGS >= 32
133	TCG_REG_R16,
134	TCG_REG_R17,
135	TCG_REG_R18,
136	TCG_REG_R19,
137	TCG_REG_R20,
138	TCG_REG_R21,
139	TCG_REG_R22,
140	TCG_REG_R23,
141	TCG_REG_R24,
142	TCG_REG_R25,
143	TCG_REG_R26,
144	TCG_REG_R27,
145	TCG_REG_R28,
146	TCG_REG_R29,
147	TCG_REG_R30,
148	TCG_REG_R31,
149	#endif
150	#endif
151	/* Special value UINT8_MAX is used by TCI to encode constant values. */
152	TCG_CONST = UINT8_MAX
771142c2	153	} TCGReg;
7316329a SW	154
	155	void tci_disas(uint8_t opc);
	156
69784eae	157	tcg_target_ulong tcg_qemu_tb_exec(CPUArchState env, uint8_t tb_ptr);
7316329a SW	158	#define tcg_qemu_tb_exec tcg_qemu_tb_exec
7316329a SW	159
f57a5160 SW	160	static inline void flush_icache_range(tcg_target_ulong start,
f57a5160 SW	161	tcg_target_ulong stop)
51711aee SW	162	{
	163	}
	164
7316329a	165	#endif /* TCG_TARGET_H */