[qemu.git] / target / hppa / int_helper.c

/*
 *  HPPA interrupt helper routines
 *
 *  Copyright (c) 2017 Richard Henderson
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu/main-loop.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "qom/cpu.h"

#ifndef CONFIG_USER_ONLY
static void eval_interrupt(HPPACPU *cpu)
{
    CPUState *cs = CPU(cpu);
    if (cpu->env.cr[CR_EIRR] & cpu->env.cr[CR_EIEM]) {
        cpu_interrupt(cs, CPU_INTERRUPT_HARD);
    } else {
        cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
    }
}

/* Each CPU has a word mapped into the GSC bus.  Anything on the GSC bus
 * can write to this word to raise an external interrupt on the target CPU.
 * This includes the system controler (DINO) for regular devices, or
 * another CPU for SMP interprocessor interrupts.
 */
static uint64_t io_eir_read(void *opaque, hwaddr addr, unsigned size)
{
    HPPACPU *cpu = opaque;

    /* ??? What does a read of this register over the GSC bus do?  */
    return cpu->env.cr[CR_EIRR];
}

static void io_eir_write(void *opaque, hwaddr addr,
                         uint64_t data, unsigned size)
{
    HPPACPU *cpu = opaque;
    int le_bit = ~data & (TARGET_REGISTER_BITS - 1);

    cpu->env.cr[CR_EIRR] |= (target_ureg)1 << le_bit;
    eval_interrupt(cpu);
}

const MemoryRegionOps hppa_io_eir_ops = {
    .read = io_eir_read,
    .write = io_eir_write,
    .valid.min_access_size = 4,
    .valid.max_access_size = 4,
    .impl.min_access_size = 4,
    .impl.max_access_size = 4,
};

void hppa_cpu_alarm_timer(void *opaque)
{
    /* Raise interrupt 0.  */
    io_eir_write(opaque, 0, 0, 4);
}

void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val)
{
    env->cr[CR_EIRR] &= ~val;
    qemu_mutex_lock_iothread();
    eval_interrupt(hppa_env_get_cpu(env));
    qemu_mutex_unlock_iothread();
}

void HELPER(write_eiem)(CPUHPPAState *env, target_ureg val)
{
    env->cr[CR_EIEM] = val;
    qemu_mutex_lock_iothread();
    eval_interrupt(hppa_env_get_cpu(env));
    qemu_mutex_unlock_iothread();
}
#endif /* !CONFIG_USER_ONLY */

void hppa_cpu_do_interrupt(CPUState *cs)
{
    HPPACPU *cpu = HPPA_CPU(cs);
    CPUHPPAState *env = &cpu->env;
    int i = cs->exception_index;
    target_ureg iaoq_f = env->iaoq_f;
    target_ureg iaoq_b = env->iaoq_b;
    uint64_t iasq_f = env->iasq_f;
    uint64_t iasq_b = env->iasq_b;

#ifndef CONFIG_USER_ONLY
    target_ureg old_psw;

    /* As documented in pa2.0 -- interruption handling.  */
    /* step 1 */
    env->cr[CR_IPSW] = old_psw = cpu_hppa_get_psw(env);

    /* step 2 -- note PSW_W == 0 for !HPPA64.  */
    cpu_hppa_put_psw(env, PSW_W | (i == EXCP_HPMC ? PSW_M : 0));

    /* step 3 */
    env->cr[CR_IIASQ] = iasq_f >> 32;
    env->cr_back[0] = iasq_b >> 32;
    env->cr[CR_IIAOQ] = iaoq_f;
    env->cr_back[1] = iaoq_b;

    if (old_psw & PSW_Q) {
        /* step 5 */
        /* ISR and IOR will be set elsewhere.  */
        switch (i) {
        case EXCP_ILL:
        case EXCP_BREAK:
        case EXCP_PRIV_REG:
        case EXCP_PRIV_OPR:
            /* IIR set via translate.c.  */
            break;

        case EXCP_OVERFLOW:
        case EXCP_COND:
        case EXCP_ASSIST:
        case EXCP_DTLB_MISS:
        case EXCP_NA_ITLB_MISS:
        case EXCP_NA_DTLB_MISS:
        case EXCP_DMAR:
        case EXCP_DMPI:
        case EXCP_UNALIGN:
        case EXCP_DMP:
        case EXCP_DMB:
        case EXCP_TLB_DIRTY:
        case EXCP_PAGE_REF:
        case EXCP_ASSIST_EMU:
            {
                /* Avoid reading directly from the virtual address, lest we
                   raise another exception from some sort of TLB issue.  */
                /* ??? An alternate fool-proof method would be to store the
                   instruction data into the unwind info.  That's probably
                   a bit too much in the way of extra storage required.  */
                vaddr vaddr;
                hwaddr paddr;

                paddr = vaddr = iaoq_f & -4;
                if (old_psw & PSW_C) {
                    int prot, t;

                    vaddr = hppa_form_gva_psw(old_psw, iasq_f, vaddr);
                    t = hppa_get_physical_address(env, vaddr, MMU_KERNEL_IDX,
                                                  0, &paddr, &prot);
                    if (t >= 0) {
                        /* We can't re-load the instruction.  */
                        env->cr[CR_IIR] = 0;
                        break;
                    }
                }
                env->cr[CR_IIR] = ldl_phys(cs->as, paddr);
            }
            break;

        default:
            /* Other exceptions do not set IIR.  */
            break;
        }

        /* step 6 */
        env->shadow[0] = env->gr[1];
        env->shadow[1] = env->gr[8];
        env->shadow[2] = env->gr[9];
        env->shadow[3] = env->gr[16];
        env->shadow[4] = env->gr[17];
        env->shadow[5] = env->gr[24];
        env->shadow[6] = env->gr[25];
    }

    /* step 7 */
    env->iaoq_f = env->cr[CR_IVA] + 32 * i;
    env->iaoq_b = env->iaoq_f + 4;
    env->iasq_f = 0;
    env->iasq_b = 0;
#endif

    if (qemu_loglevel_mask(CPU_LOG_INT)) {
        static const char * const names[] = {
            [EXCP_HPMC]          = "high priority machine check",
            [EXCP_POWER_FAIL]    = "power fail interrupt",
            [EXCP_RC]            = "recovery counter trap",
            [EXCP_EXT_INTERRUPT] = "external interrupt",
            [EXCP_LPMC]          = "low priority machine check",
            [EXCP_ITLB_MISS]     = "instruction tlb miss fault",
            [EXCP_IMP]           = "instruction memory protection trap",
            [EXCP_ILL]           = "illegal instruction trap",
            [EXCP_BREAK]         = "break instruction trap",
            [EXCP_PRIV_OPR]      = "privileged operation trap",
            [EXCP_PRIV_REG]      = "privileged register trap",
            [EXCP_OVERFLOW]      = "overflow trap",
            [EXCP_COND]          = "conditional trap",
            [EXCP_ASSIST]        = "assist exception trap",
            [EXCP_DTLB_MISS]     = "data tlb miss fault",
            [EXCP_NA_ITLB_MISS]  = "non-access instruction tlb miss",
            [EXCP_NA_DTLB_MISS]  = "non-access data tlb miss",
            [EXCP_DMP]           = "data memory protection trap",
            [EXCP_DMB]           = "data memory break trap",
            [EXCP_TLB_DIRTY]     = "tlb dirty bit trap",
            [EXCP_PAGE_REF]      = "page reference trap",
            [EXCP_ASSIST_EMU]    = "assist emulation trap",
            [EXCP_HPT]           = "high-privilege transfer trap",
            [EXCP_LPT]           = "low-privilege transfer trap",
            [EXCP_TB]            = "taken branch trap",
            [EXCP_DMAR]          = "data memory access rights trap",
            [EXCP_DMPI]          = "data memory protection id trap",
            [EXCP_UNALIGN]       = "unaligned data reference trap",
            [EXCP_PER_INTERRUPT] = "performance monitor interrupt",
            [EXCP_SYSCALL]       = "syscall",
            [EXCP_SYSCALL_LWS]   = "syscall-lws",
        };
        static int count;
        const char *name = NULL;
        char unknown[16];

        if (i >= 0 && i < ARRAY_SIZE(names)) {
            name = names[i];
        }
        if (!name) {
            snprintf(unknown, sizeof(unknown), "unknown %d", i);
            name = unknown;
        }
        qemu_log("INT %6d: %s @ " TARGET_FMT_lx "," TARGET_FMT_lx
                 " -> " TREG_FMT_lx " " TARGET_FMT_lx "\n",
                 ++count, name,
                 hppa_form_gva(env, iasq_f, iaoq_f),
                 hppa_form_gva(env, iasq_b, iaoq_b),
                 env->iaoq_f,
                 hppa_form_gva(env, (uint64_t)env->cr[CR_ISR] << 32,
                               env->cr[CR_IOR]));
    }
    cs->exception_index = -1;
}

bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
#ifndef CONFIG_USER_ONLY
    HPPACPU *cpu = HPPA_CPU(cs);
    CPUHPPAState *env = &cpu->env;

    /* If interrupts are requested and enabled, raise them.  */
    if ((env->psw & PSW_I) && (interrupt_request & CPU_INTERRUPT_HARD)) {
        cs->exception_index = EXCP_EXT_INTERRUPT;
        hppa_cpu_do_interrupt(cs);
        return true;
    }
#endif
    return false;
}
Commit	Line	Data
1a19da0d RH	1	/*
	2	* HPPA interrupt helper routines
	3	*
	4	* Copyright (c) 2017 Richard Henderson
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "qemu/osdep.h"
	21	#include "qemu/main-loop.h"
	22	#include "cpu.h"
	23	#include "exec/exec-all.h"
	24	#include "exec/helper-proto.h"
	25	#include "qom/cpu.h"
	26
4f5f2548 RH	27	#ifndef CONFIG_USER_ONLY
	28	static void eval_interrupt(HPPACPU *cpu)
	29	{
	30	CPUState *cs = CPU(cpu);
	31	if (cpu->env.cr[CR_EIRR] & cpu->env.cr[CR_EIEM]) {
	32	cpu_interrupt(cs, CPU_INTERRUPT_HARD);
	33	} else {
	34	cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
	35	}
	36	}
	37
	38	/* Each CPU has a word mapped into the GSC bus. Anything on the GSC bus
	39	* can write to this word to raise an external interrupt on the target CPU.
	40	* This includes the system controler (DINO) for regular devices, or
	41	* another CPU for SMP interprocessor interrupts.
	42	*/
	43	static uint64_t io_eir_read(void *opaque, hwaddr addr, unsigned size)
	44	{
	45	HPPACPU *cpu = opaque;
	46
	47	/* ??? What does a read of this register over the GSC bus do? */
	48	return cpu->env.cr[CR_EIRR];
	49	}
	50
	51	static void io_eir_write(void *opaque, hwaddr addr,
	52	uint64_t data, unsigned size)
	53	{
	54	HPPACPU *cpu = opaque;
	55	int le_bit = ~data & (TARGET_REGISTER_BITS - 1);
	56
	57	cpu->env.cr[CR_EIRR] \|= (target_ureg)1 << le_bit;
	58	eval_interrupt(cpu);
	59	}
	60
	61	const MemoryRegionOps hppa_io_eir_ops = {
	62	.read = io_eir_read,
	63	.write = io_eir_write,
	64	.valid.min_access_size = 4,
	65	.valid.max_access_size = 4,
	66	.impl.min_access_size = 4,
	67	.impl.max_access_size = 4,
	68	};
	69
49c29d6c RH	70	void hppa_cpu_alarm_timer(void *opaque)
	71	{
	72	/* Raise interrupt 0. */
	73	io_eir_write(opaque, 0, 0, 4);
	74	}
	75
4f5f2548 RH	76	void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val)
	77	{
	78	env->cr[CR_EIRR] &= ~val;
	79	qemu_mutex_lock_iothread();
	80	eval_interrupt(hppa_env_get_cpu(env));
	81	qemu_mutex_unlock_iothread();
	82	}
	83
	84	void HELPER(write_eiem)(CPUHPPAState *env, target_ureg val)
	85	{
	86	env->cr[CR_EIEM] = val;
	87	qemu_mutex_lock_iothread();
	88	eval_interrupt(hppa_env_get_cpu(env));
	89	qemu_mutex_unlock_iothread();
	90	}
	91	#endif /* !CONFIG_USER_ONLY */
1a19da0d RH	92
	93	void hppa_cpu_do_interrupt(CPUState *cs)
	94	{
	95	HPPACPU *cpu = HPPA_CPU(cs);
	96	CPUHPPAState *env = &cpu->env;
	97	int i = cs->exception_index;
	98	target_ureg iaoq_f = env->iaoq_f;
	99	target_ureg iaoq_b = env->iaoq_b;
c301f34e RH	100	uint64_t iasq_f = env->iasq_f;
c301f34e RH	101	uint64_t iasq_b = env->iasq_b;
1a19da0d RH	102
	103	#ifndef CONFIG_USER_ONLY
	104	target_ureg old_psw;
	105
	106	/* As documented in pa2.0 -- interruption handling. */
	107	/* step 1 */
	108	env->cr[CR_IPSW] = old_psw = cpu_hppa_get_psw(env);
	109
	110	/* step 2 -- note PSW_W == 0 for !HPPA64. */
	111	cpu_hppa_put_psw(env, PSW_W \| (i == EXCP_HPMC ? PSW_M : 0));
	112
	113	/* step 3 */
c301f34e RH	114	env->cr[CR_IIASQ] = iasq_f >> 32;
c301f34e RH	115	env->cr_back[0] = iasq_b >> 32;
1a19da0d RH	116	env->cr[CR_IIAOQ] = iaoq_f;
	117	env->cr_back[1] = iaoq_b;
	118
	119	if (old_psw & PSW_Q) {
	120	/* step 5 */
	121	/* ISR and IOR will be set elsewhere. */
	122	switch (i) {
	123	case EXCP_ILL:
	124	case EXCP_BREAK:
	125	case EXCP_PRIV_REG:
	126	case EXCP_PRIV_OPR:
	127	/* IIR set via translate.c. */
	128	break;
	129
	130	case EXCP_OVERFLOW:
	131	case EXCP_COND:
	132	case EXCP_ASSIST:
	133	case EXCP_DTLB_MISS:
	134	case EXCP_NA_ITLB_MISS:
	135	case EXCP_NA_DTLB_MISS:
	136	case EXCP_DMAR:
	137	case EXCP_DMPI:
	138	case EXCP_UNALIGN:
	139	case EXCP_DMP:
	140	case EXCP_DMB:
	141	case EXCP_TLB_DIRTY:
	142	case EXCP_PAGE_REF:
	143	case EXCP_ASSIST_EMU:
	144	{
	145	/* Avoid reading directly from the virtual address, lest we
	146	raise another exception from some sort of TLB issue. */
650cdb2a RH	147	/* ??? An alternate fool-proof method would be to store the
	148	instruction data into the unwind info. That's probably
	149	a bit too much in the way of extra storage required. */
1a19da0d RH	150	vaddr vaddr;
	151	hwaddr paddr;
	152
	153	paddr = vaddr = iaoq_f & -4;
c301f34e	154	if (old_psw & PSW_C) {
650cdb2a RH	155	int prot, t;
	156
	157	vaddr = hppa_form_gva_psw(old_psw, iasq_f, vaddr);
	158	t = hppa_get_physical_address(env, vaddr, MMU_KERNEL_IDX,
	159	0, &paddr, &prot);
	160	if (t >= 0) {
	161	/* We can't re-load the instruction. */
	162	env->cr[CR_IIR] = 0;
	163	break;
	164	}
c301f34e	165	}
1a19da0d RH	166	env->cr[CR_IIR] = ldl_phys(cs->as, paddr);
	167	}
	168	break;
	169
	170	default:
	171	/* Other exceptions do not set IIR. */
	172	break;
	173	}
	174
	175	/* step 6 */
	176	env->shadow[0] = env->gr[1];
	177	env->shadow[1] = env->gr[8];
	178	env->shadow[2] = env->gr[9];
	179	env->shadow[3] = env->gr[16];
	180	env->shadow[4] = env->gr[17];
	181	env->shadow[5] = env->gr[24];
	182	env->shadow[6] = env->gr[25];
	183	}
	184
	185	/* step 7 */
	186	env->iaoq_f = env->cr[CR_IVA] + 32 * i;
	187	env->iaoq_b = env->iaoq_f + 4;
c301f34e RH	188	env->iasq_f = 0;
c301f34e RH	189	env->iasq_b = 0;
1a19da0d RH	190	#endif
	191
	192	if (qemu_loglevel_mask(CPU_LOG_INT)) {
	193	static const char * const names[] = {
	194	[EXCP_HPMC] = "high priority machine check",
	195	[EXCP_POWER_FAIL] = "power fail interrupt",
	196	[EXCP_RC] = "recovery counter trap",
	197	[EXCP_EXT_INTERRUPT] = "external interrupt",
	198	[EXCP_LPMC] = "low priority machine check",
	199	[EXCP_ITLB_MISS] = "instruction tlb miss fault",
	200	[EXCP_IMP] = "instruction memory protection trap",
	201	[EXCP_ILL] = "illegal instruction trap",
	202	[EXCP_BREAK] = "break instruction trap",
	203	[EXCP_PRIV_OPR] = "privileged operation trap",
	204	[EXCP_PRIV_REG] = "privileged register trap",
	205	[EXCP_OVERFLOW] = "overflow trap",
	206	[EXCP_COND] = "conditional trap",
	207	[EXCP_ASSIST] = "assist exception trap",
	208	[EXCP_DTLB_MISS] = "data tlb miss fault",
	209	[EXCP_NA_ITLB_MISS] = "non-access instruction tlb miss",
	210	[EXCP_NA_DTLB_MISS] = "non-access data tlb miss",
	211	[EXCP_DMP] = "data memory protection trap",
	212	[EXCP_DMB] = "data memory break trap",
	213	[EXCP_TLB_DIRTY] = "tlb dirty bit trap",
	214	[EXCP_PAGE_REF] = "page reference trap",
	215	[EXCP_ASSIST_EMU] = "assist emulation trap",
	216	[EXCP_HPT] = "high-privilege transfer trap",
	217	[EXCP_LPT] = "low-privilege transfer trap",
	218	[EXCP_TB] = "taken branch trap",
	219	[EXCP_DMAR] = "data memory access rights trap",
	220	[EXCP_DMPI] = "data memory protection id trap",
	221	[EXCP_UNALIGN] = "unaligned data reference trap",
	222	[EXCP_PER_INTERRUPT] = "performance monitor interrupt",
	223	[EXCP_SYSCALL] = "syscall",
	224	[EXCP_SYSCALL_LWS] = "syscall-lws",
	225	};
	226	static int count;
	227	const char *name = NULL;
	228	char unknown[16];
	229
	230	if (i >= 0 && i < ARRAY_SIZE(names)) {
	231	name = names[i];
	232	}
	233	if (!name) {
	234	snprintf(unknown, sizeof(unknown), "unknown %d", i);
	235	name = unknown;
	236	}
	237	qemu_log("INT %6d: %s @ " TARGET_FMT_lx "," TARGET_FMT_lx
	238	" -> " TREG_FMT_lx " " TARGET_FMT_lx "\n",
	239	++count, name,
c301f34e RH	240	hppa_form_gva(env, iasq_f, iaoq_f),
c301f34e RH	241	hppa_form_gva(env, iasq_b, iaoq_b),
1a19da0d	242	env->iaoq_f,
c301f34e RH	243	hppa_form_gva(env, (uint64_t)env->cr[CR_ISR] << 32,
c301f34e RH	244	env->cr[CR_IOR]));
1a19da0d RH	245	}
	246	cs->exception_index = -1;
	247	}
	248
	249	bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
	250	{
	251	#ifndef CONFIG_USER_ONLY
	252	HPPACPU *cpu = HPPA_CPU(cs);
	253	CPUHPPAState *env = &cpu->env;
	254
	255	/* If interrupts are requested and enabled, raise them. */
	256	if ((env->psw & PSW_I) && (interrupt_request & CPU_INTERRUPT_HARD)) {
	257	cs->exception_index = EXCP_EXT_INTERRUPT;
	258	hppa_cpu_do_interrupt(cs);
	259	return true;
	260	}
	261	#endif
	262	return false;
	263	}