[qemu.git] / target-xtensa / cpu.h

/*
 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of the Open Source and Linux Lab nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef CPU_XTENSA_H
#define CPU_XTENSA_H

#define TARGET_LONG_BITS 32
#define ELF_MACHINE EM_XTENSA

#define CPUArchState struct CPUXtensaState

#include "config.h"
#include "qemu-common.h"
#include "cpu-defs.h"

#define TARGET_HAS_ICE 1

#define NB_MMU_MODES 4

#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define TARGET_PAGE_BITS 12

enum {
    /* Additional instructions */
    XTENSA_OPTION_CODE_DENSITY,
    XTENSA_OPTION_LOOP,
    XTENSA_OPTION_EXTENDED_L32R,
    XTENSA_OPTION_16_BIT_IMUL,
    XTENSA_OPTION_32_BIT_IMUL,
    XTENSA_OPTION_32_BIT_IMUL_HIGH,
    XTENSA_OPTION_32_BIT_IDIV,
    XTENSA_OPTION_MAC16,
    XTENSA_OPTION_MISC_OP_NSA,
    XTENSA_OPTION_MISC_OP_MINMAX,
    XTENSA_OPTION_MISC_OP_SEXT,
    XTENSA_OPTION_MISC_OP_CLAMPS,
    XTENSA_OPTION_COPROCESSOR,
    XTENSA_OPTION_BOOLEAN,
    XTENSA_OPTION_FP_COPROCESSOR,
    XTENSA_OPTION_MP_SYNCHRO,
    XTENSA_OPTION_CONDITIONAL_STORE,

    /* Interrupts and exceptions */
    XTENSA_OPTION_EXCEPTION,
    XTENSA_OPTION_RELOCATABLE_VECTOR,
    XTENSA_OPTION_UNALIGNED_EXCEPTION,
    XTENSA_OPTION_INTERRUPT,
    XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
    XTENSA_OPTION_TIMER_INTERRUPT,

    /* Local memory */
    XTENSA_OPTION_ICACHE,
    XTENSA_OPTION_ICACHE_TEST,
    XTENSA_OPTION_ICACHE_INDEX_LOCK,
    XTENSA_OPTION_DCACHE,
    XTENSA_OPTION_DCACHE_TEST,
    XTENSA_OPTION_DCACHE_INDEX_LOCK,
    XTENSA_OPTION_IRAM,
    XTENSA_OPTION_IROM,
    XTENSA_OPTION_DRAM,
    XTENSA_OPTION_DROM,
    XTENSA_OPTION_XLMI,
    XTENSA_OPTION_HW_ALIGNMENT,
    XTENSA_OPTION_MEMORY_ECC_PARITY,

    /* Memory protection and translation */
    XTENSA_OPTION_REGION_PROTECTION,
    XTENSA_OPTION_REGION_TRANSLATION,
    XTENSA_OPTION_MMU,

    /* Other */
    XTENSA_OPTION_WINDOWED_REGISTER,
    XTENSA_OPTION_PROCESSOR_INTERFACE,
    XTENSA_OPTION_MISC_SR,
    XTENSA_OPTION_THREAD_POINTER,
    XTENSA_OPTION_PROCESSOR_ID,
    XTENSA_OPTION_DEBUG,
    XTENSA_OPTION_TRACE_PORT,
};

enum {
    THREADPTR = 231,
    FCR = 232,
    FSR = 233,
};

enum {
    LBEG = 0,
    LEND = 1,
    LCOUNT = 2,
    SAR = 3,
    BR = 4,
    LITBASE = 5,
    SCOMPARE1 = 12,
    ACCLO = 16,
    ACCHI = 17,
    MR = 32,
    WINDOW_BASE = 72,
    WINDOW_START = 73,
    PTEVADDR = 83,
    RASID = 90,
    ITLBCFG = 91,
    DTLBCFG = 92,
    IBREAKENABLE = 96,
    IBREAKA = 128,
    DBREAKA = 144,
    DBREAKC = 160,
    EPC1 = 177,
    DEPC = 192,
    EPS2 = 194,
    EXCSAVE1 = 209,
    CPENABLE = 224,
    INTSET = 226,
    INTCLEAR = 227,
    INTENABLE = 228,
    PS = 230,
    VECBASE = 231,
    EXCCAUSE = 232,
    DEBUGCAUSE = 233,
    CCOUNT = 234,
    PRID = 235,
    ICOUNT = 236,
    ICOUNTLEVEL = 237,
    EXCVADDR = 238,
    CCOMPARE = 240,
};

#define PS_INTLEVEL 0xf
#define PS_INTLEVEL_SHIFT 0

#define PS_EXCM 0x10
#define PS_UM 0x20

#define PS_RING 0xc0
#define PS_RING_SHIFT 6

#define PS_OWB 0xf00
#define PS_OWB_SHIFT 8

#define PS_CALLINC 0x30000
#define PS_CALLINC_SHIFT 16
#define PS_CALLINC_LEN 2

#define PS_WOE 0x40000

#define DEBUGCAUSE_IC 0x1
#define DEBUGCAUSE_IB 0x2
#define DEBUGCAUSE_DB 0x4
#define DEBUGCAUSE_BI 0x8
#define DEBUGCAUSE_BN 0x10
#define DEBUGCAUSE_DI 0x20
#define DEBUGCAUSE_DBNUM 0xf00
#define DEBUGCAUSE_DBNUM_SHIFT 8

#define DBREAKC_SB 0x80000000
#define DBREAKC_LB 0x40000000
#define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
#define DBREAKC_MASK 0x3f

#define MAX_NAREG 64
#define MAX_NINTERRUPT 32
#define MAX_NLEVEL 6
#define MAX_NNMI 1
#define MAX_NCCOMPARE 3
#define MAX_TLB_WAY_SIZE 8
#define MAX_NDBREAK 2

#define REGION_PAGE_MASK 0xe0000000

enum {
    /* Static vectors */
    EXC_RESET,
    EXC_MEMORY_ERROR,

    /* Dynamic vectors */
    EXC_WINDOW_OVERFLOW4,
    EXC_WINDOW_UNDERFLOW4,
    EXC_WINDOW_OVERFLOW8,
    EXC_WINDOW_UNDERFLOW8,
    EXC_WINDOW_OVERFLOW12,
    EXC_WINDOW_UNDERFLOW12,
    EXC_IRQ,
    EXC_KERNEL,
    EXC_USER,
    EXC_DOUBLE,
    EXC_DEBUG,
    EXC_MAX
};

enum {
    ILLEGAL_INSTRUCTION_CAUSE = 0,
    SYSCALL_CAUSE,
    INSTRUCTION_FETCH_ERROR_CAUSE,
    LOAD_STORE_ERROR_CAUSE,
    LEVEL1_INTERRUPT_CAUSE,
    ALLOCA_CAUSE,
    INTEGER_DIVIDE_BY_ZERO_CAUSE,
    PRIVILEGED_CAUSE = 8,
    LOAD_STORE_ALIGNMENT_CAUSE,

    INSTR_PIF_DATA_ERROR_CAUSE = 12,
    LOAD_STORE_PIF_DATA_ERROR_CAUSE,
    INSTR_PIF_ADDR_ERROR_CAUSE,
    LOAD_STORE_PIF_ADDR_ERROR_CAUSE,

    INST_TLB_MISS_CAUSE,
    INST_TLB_MULTI_HIT_CAUSE,
    INST_FETCH_PRIVILEGE_CAUSE,
    INST_FETCH_PROHIBITED_CAUSE = 20,
    LOAD_STORE_TLB_MISS_CAUSE = 24,
    LOAD_STORE_TLB_MULTI_HIT_CAUSE,
    LOAD_STORE_PRIVILEGE_CAUSE,
    LOAD_PROHIBITED_CAUSE = 28,
    STORE_PROHIBITED_CAUSE,

    COPROCESSOR0_DISABLED = 32,
};

typedef enum {
    INTTYPE_LEVEL,
    INTTYPE_EDGE,
    INTTYPE_NMI,
    INTTYPE_SOFTWARE,
    INTTYPE_TIMER,
    INTTYPE_DEBUG,
    INTTYPE_WRITE_ERR,
    INTTYPE_MAX
} interrupt_type;

typedef struct xtensa_tlb_entry {
    uint32_t vaddr;
    uint32_t paddr;
    uint8_t asid;
    uint8_t attr;
    bool variable;
} xtensa_tlb_entry;

typedef struct xtensa_tlb {
    unsigned nways;
    const unsigned way_size[10];
    bool varway56;
    unsigned nrefillentries;
} xtensa_tlb;

typedef struct XtensaGdbReg {
    int targno;
    int type;
    int group;
} XtensaGdbReg;

typedef struct XtensaGdbRegmap {
    int num_regs;
    int num_core_regs;
    /* PC + a + ar + sr + ur */
    XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
} XtensaGdbRegmap;

typedef struct XtensaConfig {
    const char *name;
    uint64_t options;
    XtensaGdbRegmap gdb_regmap;
    unsigned nareg;
    int excm_level;
    int ndepc;
    uint32_t vecbase;
    uint32_t exception_vector[EXC_MAX];
    unsigned ninterrupt;
    unsigned nlevel;
    uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
    uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
    uint32_t inttype_mask[INTTYPE_MAX];
    struct {
        uint32_t level;
        interrupt_type inttype;
    } interrupt[MAX_NINTERRUPT];
    unsigned nccompare;
    uint32_t timerint[MAX_NCCOMPARE];
    unsigned nextint;
    unsigned extint[MAX_NINTERRUPT];

    unsigned debug_level;
    unsigned nibreak;
    unsigned ndbreak;

    uint32_t clock_freq_khz;

    xtensa_tlb itlb;
    xtensa_tlb dtlb;
} XtensaConfig;

typedef struct XtensaConfigList {
    const XtensaConfig *config;
    struct XtensaConfigList *next;
} XtensaConfigList;

typedef struct CPUXtensaState {
    const XtensaConfig *config;
    uint32_t regs[16];
    uint32_t pc;
    uint32_t sregs[256];
    uint32_t uregs[256];
    uint32_t phys_regs[MAX_NAREG];

    xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
    xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
    unsigned autorefill_idx;

    int pending_irq_level; /* level of last raised IRQ */
    void **irq_inputs;
    QEMUTimer *ccompare_timer;
    uint32_t wake_ccount;
    int64_t halt_clock;

    int exception_taken;

    /* Watchpoints for DBREAK registers */
    CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];

    CPU_COMMON
} CPUXtensaState;

#include "cpu-qom.h"

#define cpu_exec cpu_xtensa_exec
#define cpu_gen_code cpu_xtensa_gen_code
#define cpu_signal_handler cpu_xtensa_signal_handler
#define cpu_list xtensa_cpu_list

XtensaCPU *cpu_xtensa_init(const char *cpu_model);

static inline CPUXtensaState *cpu_init(const char *cpu_model)
{
    XtensaCPU *cpu = cpu_xtensa_init(cpu_model);
    if (cpu == NULL) {
        return NULL;
    }
    return &cpu->env;
}

void xtensa_translate_init(void);
int cpu_xtensa_exec(CPUXtensaState *s);
void xtensa_register_core(XtensaConfigList *node);
void do_interrupt(CPUXtensaState *s);
void check_interrupts(CPUXtensaState *s);
void xtensa_irq_init(CPUXtensaState *env);
void *xtensa_get_extint(CPUXtensaState *env, unsigned extint);
void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d);
void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
void xtensa_rearm_ccompare_timer(CPUXtensaState *env);
int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
void xtensa_sync_window_from_phys(CPUXtensaState *env);
void xtensa_sync_phys_from_window(CPUXtensaState *env);
uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
        uint32_t *vpn, uint32_t wi, uint32_t *ei);
int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
        uint32_t *pwi, uint32_t *pei, uint8_t *pring);
void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
        xtensa_tlb_entry *entry, bool dtlb,
        unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
        unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
        uint32_t vaddr, int is_write, int mmu_idx,
        uint32_t *paddr, uint32_t *page_size, unsigned *access);
void reset_mmu(CPUXtensaState *env);
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);


#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))

static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
        uint64_t opt)
{
    return (config->options & opt) != 0;
}

static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
{
    return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
}

static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
{
    int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
    if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
        level = env->config->excm_level;
    }
    return level;
}

static inline int xtensa_get_ring(const CPUXtensaState *env)
{
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
        return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
    } else {
        return 0;
    }
}

static inline int xtensa_get_cring(const CPUXtensaState *env)
{
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
            (env->sregs[PS] & PS_EXCM) == 0) {
        return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
    } else {
        return 0;
    }
}

static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
        bool dtlb, unsigned wi, unsigned ei)
{
    return dtlb ?
        env->dtlb[wi] + ei :
        env->itlb[wi] + ei;
}

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _ring0
#define MMU_MODE1_SUFFIX _ring1
#define MMU_MODE2_SUFFIX _ring2
#define MMU_MODE3_SUFFIX _ring3

static inline int cpu_mmu_index(CPUXtensaState *env)
{
    return xtensa_get_cring(env);
}

#define XTENSA_TBFLAG_RING_MASK 0x3
#define XTENSA_TBFLAG_EXCM 0x4
#define XTENSA_TBFLAG_LITBASE 0x8
#define XTENSA_TBFLAG_DEBUG 0x10
#define XTENSA_TBFLAG_ICOUNT 0x20

static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
        target_ulong *cs_base, int *flags)
{
    *pc = env->pc;
    *cs_base = 0;
    *flags = 0;
    *flags |= xtensa_get_ring(env);
    if (env->sregs[PS] & PS_EXCM) {
        *flags |= XTENSA_TBFLAG_EXCM;
    }
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
            (env->sregs[LITBASE] & 1)) {
        *flags |= XTENSA_TBFLAG_LITBASE;
    }
    if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
        if (xtensa_get_cintlevel(env) < env->config->debug_level) {
            *flags |= XTENSA_TBFLAG_DEBUG;
        }
        if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
            *flags |= XTENSA_TBFLAG_ICOUNT;
        }
    }
}

#include "cpu-all.h"
#include "exec-all.h"

static inline int cpu_has_work(CPUXtensaState *env)
{
    return env->pending_irq_level;
}

static inline void cpu_pc_from_tb(CPUXtensaState *env, TranslationBlock *tb)
{
    env->pc = tb->pc;
}

#endif
Commit	Line	Data
2328826b MF	1	/*
	2	* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
	3	* All rights reserved.
	4	*
	5	* Redistribution and use in source and binary forms, with or without
	6	* modification, are permitted provided that the following conditions are met:
	7	* * Redistributions of source code must retain the above copyright
	8	* notice, this list of conditions and the following disclaimer.
	9	* * Redistributions in binary form must reproduce the above copyright
	10	* notice, this list of conditions and the following disclaimer in the
	11	* documentation and/or other materials provided with the distribution.
	12	* * Neither the name of the Open Source and Linux Lab nor the
	13	* names of its contributors may be used to endorse or promote products
	14	* derived from this software without specific prior written permission.
	15	*
	16	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	17	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	18	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	19	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	20	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	21	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	22	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	23	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	24	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	25	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	26	*/
	27
	28	#ifndef CPU_XTENSA_H
	29	#define CPU_XTENSA_H
	30
	31	#define TARGET_LONG_BITS 32
	32	#define ELF_MACHINE EM_XTENSA
	33
9349b4f9	34	#define CPUArchState struct CPUXtensaState
2328826b MF	35
	36	#include "config.h"
	37	#include "qemu-common.h"
	38	#include "cpu-defs.h"
	39
	40	#define TARGET_HAS_ICE 1
	41
	42	#define NB_MMU_MODES 4
	43
	44	#define TARGET_PHYS_ADDR_SPACE_BITS 32
	45	#define TARGET_VIRT_ADDR_SPACE_BITS 32
	46	#define TARGET_PAGE_BITS 12
	47
dedc5eae MF	48	enum {
	49	/* Additional instructions */
	50	XTENSA_OPTION_CODE_DENSITY,
	51	XTENSA_OPTION_LOOP,
	52	XTENSA_OPTION_EXTENDED_L32R,
	53	XTENSA_OPTION_16_BIT_IMUL,
	54	XTENSA_OPTION_32_BIT_IMUL,
7f65f4b0	55	XTENSA_OPTION_32_BIT_IMUL_HIGH,
dedc5eae MF	56	XTENSA_OPTION_32_BIT_IDIV,
dedc5eae MF	57	XTENSA_OPTION_MAC16,
7f65f4b0 MF	58	XTENSA_OPTION_MISC_OP_NSA,
	59	XTENSA_OPTION_MISC_OP_MINMAX,
	60	XTENSA_OPTION_MISC_OP_SEXT,
	61	XTENSA_OPTION_MISC_OP_CLAMPS,
dedc5eae MF	62	XTENSA_OPTION_COPROCESSOR,
	63	XTENSA_OPTION_BOOLEAN,
	64	XTENSA_OPTION_FP_COPROCESSOR,
	65	XTENSA_OPTION_MP_SYNCHRO,
	66	XTENSA_OPTION_CONDITIONAL_STORE,
	67
	68	/* Interrupts and exceptions */
	69	XTENSA_OPTION_EXCEPTION,
	70	XTENSA_OPTION_RELOCATABLE_VECTOR,
	71	XTENSA_OPTION_UNALIGNED_EXCEPTION,
	72	XTENSA_OPTION_INTERRUPT,
	73	XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
	74	XTENSA_OPTION_TIMER_INTERRUPT,
	75
	76	/* Local memory */
	77	XTENSA_OPTION_ICACHE,
	78	XTENSA_OPTION_ICACHE_TEST,
	79	XTENSA_OPTION_ICACHE_INDEX_LOCK,
	80	XTENSA_OPTION_DCACHE,
	81	XTENSA_OPTION_DCACHE_TEST,
	82	XTENSA_OPTION_DCACHE_INDEX_LOCK,
	83	XTENSA_OPTION_IRAM,
	84	XTENSA_OPTION_IROM,
	85	XTENSA_OPTION_DRAM,
	86	XTENSA_OPTION_DROM,
	87	XTENSA_OPTION_XLMI,
	88	XTENSA_OPTION_HW_ALIGNMENT,
	89	XTENSA_OPTION_MEMORY_ECC_PARITY,
	90
	91	/* Memory protection and translation */
	92	XTENSA_OPTION_REGION_PROTECTION,
	93	XTENSA_OPTION_REGION_TRANSLATION,
	94	XTENSA_OPTION_MMU,
	95
	96	/* Other */
	97	XTENSA_OPTION_WINDOWED_REGISTER,
	98	XTENSA_OPTION_PROCESSOR_INTERFACE,
	99	XTENSA_OPTION_MISC_SR,
	100	XTENSA_OPTION_THREAD_POINTER,
	101	XTENSA_OPTION_PROCESSOR_ID,
	102	XTENSA_OPTION_DEBUG,
	103	XTENSA_OPTION_TRACE_PORT,
	104	};
	105
2af3da91 MF	106	enum {
	107	THREADPTR = 231,
	108	FCR = 232,
	109	FSR = 233,
	110	};
	111
3580ecad	112	enum {
797d780b MF	113	LBEG = 0,
	114	LEND = 1,
	115	LCOUNT = 2,
3580ecad	116	SAR = 3,
4dd85b6b	117	BR = 4,
6ad6dbf7	118	LITBASE = 5,
809377aa	119	SCOMPARE1 = 12,
6825b6c3 MF	120	ACCLO = 16,
	121	ACCHI = 17,
	122	MR = 32,
553e44f9 MF	123	WINDOW_BASE = 72,
553e44f9 MF	124	WINDOW_START = 73,
b67ea0cd MF	125	PTEVADDR = 83,
	126	RASID = 90,
	127	ITLBCFG = 91,
	128	DTLBCFG = 92,
e61dc8f7 MF	129	IBREAKENABLE = 96,
e61dc8f7 MF	130	IBREAKA = 128,
f14c4b5f MF	131	DBREAKA = 144,
f14c4b5f MF	132	DBREAKC = 160,
40643d7c MF	133	EPC1 = 177,
40643d7c MF	134	DEPC = 192,
b994e91b	135	EPS2 = 194,
40643d7c	136	EXCSAVE1 = 209,
f3df4c04	137	CPENABLE = 224,
b994e91b MF	138	INTSET = 226,
	139	INTCLEAR = 227,
	140	INTENABLE = 228,
f0a548b9	141	PS = 230,
97836cee	142	VECBASE = 231,
40643d7c	143	EXCCAUSE = 232,
ab58c5b4	144	DEBUGCAUSE = 233,
b994e91b	145	CCOUNT = 234,
f3df4c04	146	PRID = 235,
35b5c044 MF	147	ICOUNT = 236,
35b5c044 MF	148	ICOUNTLEVEL = 237,
40643d7c	149	EXCVADDR = 238,
b994e91b	150	CCOMPARE = 240,
3580ecad MF	151	};
3580ecad MF	152
f0a548b9 MF	153	#define PS_INTLEVEL 0xf
	154	#define PS_INTLEVEL_SHIFT 0
	155
	156	#define PS_EXCM 0x10
	157	#define PS_UM 0x20
	158
	159	#define PS_RING 0xc0
	160	#define PS_RING_SHIFT 6
	161
	162	#define PS_OWB 0xf00
	163	#define PS_OWB_SHIFT 8
	164
	165	#define PS_CALLINC 0x30000
	166	#define PS_CALLINC_SHIFT 16
	167	#define PS_CALLINC_LEN 2
	168
	169	#define PS_WOE 0x40000
	170
ab58c5b4 MF	171	#define DEBUGCAUSE_IC 0x1
	172	#define DEBUGCAUSE_IB 0x2
	173	#define DEBUGCAUSE_DB 0x4
	174	#define DEBUGCAUSE_BI 0x8
	175	#define DEBUGCAUSE_BN 0x10
	176	#define DEBUGCAUSE_DI 0x20
	177	#define DEBUGCAUSE_DBNUM 0xf00
	178	#define DEBUGCAUSE_DBNUM_SHIFT 8
	179
f14c4b5f MF	180	#define DBREAKC_SB 0x80000000
	181	#define DBREAKC_LB 0x40000000
	182	#define DBREAKC_SB_LB (DBREAKC_SB \| DBREAKC_LB)
	183	#define DBREAKC_MASK 0x3f
	184
553e44f9	185	#define MAX_NAREG 64
b994e91b MF	186	#define MAX_NINTERRUPT 32
	187	#define MAX_NLEVEL 6
	188	#define MAX_NNMI 1
	189	#define MAX_NCCOMPARE 3
b67ea0cd	190	#define MAX_TLB_WAY_SIZE 8
f14c4b5f	191	#define MAX_NDBREAK 2
b67ea0cd MF	192
b67ea0cd MF	193	#define REGION_PAGE_MASK 0xe0000000
553e44f9	194
40643d7c MF	195	enum {
	196	/* Static vectors */
	197	EXC_RESET,
	198	EXC_MEMORY_ERROR,
	199
	200	/* Dynamic vectors */
	201	EXC_WINDOW_OVERFLOW4,
	202	EXC_WINDOW_UNDERFLOW4,
	203	EXC_WINDOW_OVERFLOW8,
	204	EXC_WINDOW_UNDERFLOW8,
	205	EXC_WINDOW_OVERFLOW12,
	206	EXC_WINDOW_UNDERFLOW12,
	207	EXC_IRQ,
	208	EXC_KERNEL,
	209	EXC_USER,
	210	EXC_DOUBLE,
e61dc8f7	211	EXC_DEBUG,
40643d7c MF	212	EXC_MAX
	213	};
	214
	215	enum {
	216	ILLEGAL_INSTRUCTION_CAUSE = 0,
	217	SYSCALL_CAUSE,
	218	INSTRUCTION_FETCH_ERROR_CAUSE,
	219	LOAD_STORE_ERROR_CAUSE,
	220	LEVEL1_INTERRUPT_CAUSE,
	221	ALLOCA_CAUSE,
	222	INTEGER_DIVIDE_BY_ZERO_CAUSE,
	223	PRIVILEGED_CAUSE = 8,
	224	LOAD_STORE_ALIGNMENT_CAUSE,
	225
	226	INSTR_PIF_DATA_ERROR_CAUSE = 12,
	227	LOAD_STORE_PIF_DATA_ERROR_CAUSE,
	228	INSTR_PIF_ADDR_ERROR_CAUSE,
	229	LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
	230
	231	INST_TLB_MISS_CAUSE,
	232	INST_TLB_MULTI_HIT_CAUSE,
	233	INST_FETCH_PRIVILEGE_CAUSE,
	234	INST_FETCH_PROHIBITED_CAUSE = 20,
	235	LOAD_STORE_TLB_MISS_CAUSE = 24,
	236	LOAD_STORE_TLB_MULTI_HIT_CAUSE,
	237	LOAD_STORE_PRIVILEGE_CAUSE,
	238	LOAD_PROHIBITED_CAUSE = 28,
	239	STORE_PROHIBITED_CAUSE,
	240
	241	COPROCESSOR0_DISABLED = 32,
	242	};
	243
b994e91b MF	244	typedef enum {
	245	INTTYPE_LEVEL,
	246	INTTYPE_EDGE,
	247	INTTYPE_NMI,
	248	INTTYPE_SOFTWARE,
	249	INTTYPE_TIMER,
	250	INTTYPE_DEBUG,
	251	INTTYPE_WRITE_ERR,
	252	INTTYPE_MAX
	253	} interrupt_type;
	254
b67ea0cd MF	255	typedef struct xtensa_tlb_entry {
	256	uint32_t vaddr;
	257	uint32_t paddr;
	258	uint8_t asid;
	259	uint8_t attr;
	260	bool variable;
	261	} xtensa_tlb_entry;
	262
	263	typedef struct xtensa_tlb {
	264	unsigned nways;
	265	const unsigned way_size[10];
	266	bool varway56;
	267	unsigned nrefillentries;
	268	} xtensa_tlb;
	269
ccfcaba6 MF	270	typedef struct XtensaGdbReg {
	271	int targno;
	272	int type;
	273	int group;
	274	} XtensaGdbReg;
	275
	276	typedef struct XtensaGdbRegmap {
	277	int num_regs;
	278	int num_core_regs;
	279	/* PC + a + ar + sr + ur */
	280	XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
	281	} XtensaGdbRegmap;
	282
dedc5eae MF	283	typedef struct XtensaConfig {
	284	const char *name;
	285	uint64_t options;
ccfcaba6	286	XtensaGdbRegmap gdb_regmap;
553e44f9	287	unsigned nareg;
40643d7c MF	288	int excm_level;
40643d7c MF	289	int ndepc;
97836cee	290	uint32_t vecbase;
40643d7c	291	uint32_t exception_vector[EXC_MAX];
b994e91b MF	292	unsigned ninterrupt;
	293	unsigned nlevel;
	294	uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
	295	uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
	296	uint32_t inttype_mask[INTTYPE_MAX];
	297	struct {
	298	uint32_t level;
	299	interrupt_type inttype;
	300	} interrupt[MAX_NINTERRUPT];
	301	unsigned nccompare;
	302	uint32_t timerint[MAX_NCCOMPARE];
b8929a54 MF	303	unsigned nextint;
b8929a54 MF	304	unsigned extint[MAX_NINTERRUPT];
ab58c5b4 MF	305
	306	unsigned debug_level;
	307	unsigned nibreak;
	308	unsigned ndbreak;
	309
b994e91b	310	uint32_t clock_freq_khz;
b67ea0cd MF	311
	312	xtensa_tlb itlb;
	313	xtensa_tlb dtlb;
dedc5eae MF	314	} XtensaConfig;
dedc5eae MF	315
ac8b7db4 MF	316	typedef struct XtensaConfigList {
	317	const XtensaConfig *config;
	318	struct XtensaConfigList *next;
	319	} XtensaConfigList;
	320
2328826b	321	typedef struct CPUXtensaState {
dedc5eae	322	const XtensaConfig *config;
2328826b MF	323	uint32_t regs[16];
	324	uint32_t pc;
	325	uint32_t sregs[256];
2af3da91	326	uint32_t uregs[256];
553e44f9	327	uint32_t phys_regs[MAX_NAREG];
2328826b	328
b67ea0cd MF	329	xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
	330	xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
	331	unsigned autorefill_idx;
	332
b994e91b MF	333	int pending_irq_level; /* level of last raised IRQ */
	334	void **irq_inputs;
	335	QEMUTimer *ccompare_timer;
	336	uint32_t wake_ccount;
	337	int64_t halt_clock;
	338
40643d7c MF	339	int exception_taken;
40643d7c MF	340
f14c4b5f MF	341	/* Watchpoints for DBREAK registers */
	342	CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
	343
2328826b MF	344	CPU_COMMON
	345	} CPUXtensaState;
	346
15be3171 AF	347	#include "cpu-qom.h"
15be3171 AF	348
2328826b MF	349	#define cpu_exec cpu_xtensa_exec
	350	#define cpu_gen_code cpu_xtensa_gen_code
	351	#define cpu_signal_handler cpu_xtensa_signal_handler
	352	#define cpu_list xtensa_cpu_list
	353
15be3171 AF	354	XtensaCPU cpu_xtensa_init(const char cpu_model);
	355
	356	static inline CPUXtensaState cpu_init(const char cpu_model)
	357	{
	358	XtensaCPU *cpu = cpu_xtensa_init(cpu_model);
	359	if (cpu == NULL) {
	360	return NULL;
	361	}
	362	return &cpu->env;
	363	}
	364
2328826b MF	365	void xtensa_translate_init(void);
2328826b MF	366	int cpu_xtensa_exec(CPUXtensaState *s);
ac8b7db4	367	void xtensa_register_core(XtensaConfigList *node);
2328826b	368	void do_interrupt(CPUXtensaState *s);
b994e91b	369	void check_interrupts(CPUXtensaState *s);
97129ac8 AF	370	void xtensa_irq_init(CPUXtensaState *env);
	371	void xtensa_get_extint(CPUXtensaState env, unsigned extint);
	372	void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d);
	373	void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
	374	void xtensa_rearm_ccompare_timer(CPUXtensaState *env);
2328826b MF	375	int cpu_xtensa_signal_handler(int host_signum, void pinfo, void puc);
2328826b MF	376	void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
97129ac8 AF	377	void xtensa_sync_window_from_phys(CPUXtensaState *env);
	378	void xtensa_sync_phys_from_window(CPUXtensaState *env);
	379	uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
	380	void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
b67ea0cd	381	uint32_t vpn, uint32_t wi, uint32_t ei);
97129ac8	382	int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
b67ea0cd	383	uint32_t pwi, uint32_t pei, uint8_t *pring);
16bde77a MF	384	void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
	385	xtensa_tlb_entry *entry, bool dtlb,
	386	unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
97129ac8	387	void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
b67ea0cd	388	unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
ae4e7982	389	int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
b67ea0cd MF	390	uint32_t vaddr, int is_write, int mmu_idx,
b67ea0cd MF	391	uint32_t paddr, uint32_t page_size, unsigned *access);
5087a72c	392	void reset_mmu(CPUXtensaState *env);
97129ac8 AF	393	void dump_mmu(FILE f, fprintf_function cpu_fprintf, CPUXtensaState env);
97129ac8 AF	394	void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
b67ea0cd	395
2328826b	396
dedc5eae MF	397	#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
dedc5eae MF	398
b67ea0cd MF	399	static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
	400	uint64_t opt)
	401	{
	402	return (config->options & opt) != 0;
	403	}
	404
dedc5eae MF	405	static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
dedc5eae MF	406	{
b67ea0cd	407	return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
dedc5eae MF	408	}
dedc5eae MF	409
97129ac8	410	static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
40643d7c MF	411	{
	412	int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
	413	if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
	414	level = env->config->excm_level;
	415	}
	416	return level;
	417	}
	418
97129ac8	419	static inline int xtensa_get_ring(const CPUXtensaState *env)
f0a548b9 MF	420	{
	421	if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
	422	return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
	423	} else {
	424	return 0;
	425	}
	426	}
	427
97129ac8	428	static inline int xtensa_get_cring(const CPUXtensaState *env)
f0a548b9 MF	429	{
	430	if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
	431	(env->sregs[PS] & PS_EXCM) == 0) {
	432	return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
	433	} else {
	434	return 0;
	435	}
	436	}
	437
97129ac8	438	static inline xtensa_tlb_entry xtensa_tlb_get_entry(CPUXtensaState env,
b67ea0cd MF	439	bool dtlb, unsigned wi, unsigned ei)
	440	{
	441	return dtlb ?
	442	env->dtlb[wi] + ei :
	443	env->itlb[wi] + ei;
	444	}
	445
f0a548b9 MF	446	/* MMU modes definitions */
	447	#define MMU_MODE0_SUFFIX _ring0
	448	#define MMU_MODE1_SUFFIX _ring1
	449	#define MMU_MODE2_SUFFIX _ring2
	450	#define MMU_MODE3_SUFFIX _ring3
	451
97129ac8	452	static inline int cpu_mmu_index(CPUXtensaState *env)
2328826b	453	{
f0a548b9	454	return xtensa_get_cring(env);
2328826b MF	455	}
2328826b MF	456
f0a548b9 MF	457	#define XTENSA_TBFLAG_RING_MASK 0x3
f0a548b9 MF	458	#define XTENSA_TBFLAG_EXCM 0x4
6ad6dbf7	459	#define XTENSA_TBFLAG_LITBASE 0x8
e61dc8f7	460	#define XTENSA_TBFLAG_DEBUG 0x10
35b5c044	461	#define XTENSA_TBFLAG_ICOUNT 0x20
f0a548b9	462
97129ac8	463	static inline void cpu_get_tb_cpu_state(CPUXtensaState env, target_ulong pc,
2328826b MF	464	target_ulong cs_base, int flags)
	465	{
	466	*pc = env->pc;
	467	*cs_base = 0;
	468	*flags = 0;
f0a548b9 MF	469	*flags \|= xtensa_get_ring(env);
	470	if (env->sregs[PS] & PS_EXCM) {
	471	*flags \|= XTENSA_TBFLAG_EXCM;
	472	}
6ad6dbf7 MF	473	if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
	474	(env->sregs[LITBASE] & 1)) {
	475	*flags \|= XTENSA_TBFLAG_LITBASE;
	476	}
e61dc8f7 MF	477	if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
	478	if (xtensa_get_cintlevel(env) < env->config->debug_level) {
	479	*flags \|= XTENSA_TBFLAG_DEBUG;
	480	}
35b5c044 MF	481	if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
	482	*flags \|= XTENSA_TBFLAG_ICOUNT;
	483	}
e61dc8f7	484	}
2328826b MF	485	}
	486
	487	#include "cpu-all.h"
	488	#include "exec-all.h"
	489
97129ac8	490	static inline int cpu_has_work(CPUXtensaState *env)
2328826b	491	{
b994e91b	492	return env->pending_irq_level;
2328826b MF	493	}
2328826b MF	494
97129ac8	495	static inline void cpu_pc_from_tb(CPUXtensaState env, TranslationBlock tb)
2328826b MF	496	{
	497	env->pc = tb->pc;
	498	}
	499
	500	#endif