[qemu.git] / hw / ne2000.c

/*
 * QEMU NE2000 emulation
 * 
 * Copyright (c) 2003-2004 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

/* debug NE2000 card */
//#define DEBUG_NE2000

#define MAX_ETH_FRAME_SIZE 1514

#define E8390_CMD	0x00  /* The command register (for all pages) */
/* Page 0 register offsets. */
#define EN0_CLDALO	0x01	/* Low byte of current local dma addr  RD */
#define EN0_STARTPG	0x01	/* Starting page of ring bfr WR */
#define EN0_CLDAHI	0x02	/* High byte of current local dma addr  RD */
#define EN0_STOPPG	0x02	/* Ending page +1 of ring bfr WR */
#define EN0_BOUNDARY	0x03	/* Boundary page of ring bfr RD WR */
#define EN0_TSR		0x04	/* Transmit status reg RD */
#define EN0_TPSR	0x04	/* Transmit starting page WR */
#define EN0_NCR		0x05	/* Number of collision reg RD */
#define EN0_TCNTLO	0x05	/* Low  byte of tx byte count WR */
#define EN0_FIFO	0x06	/* FIFO RD */
#define EN0_TCNTHI	0x06	/* High byte of tx byte count WR */
#define EN0_ISR		0x07	/* Interrupt status reg RD WR */
#define EN0_CRDALO	0x08	/* low byte of current remote dma address RD */
#define EN0_RSARLO	0x08	/* Remote start address reg 0 */
#define EN0_CRDAHI	0x09	/* high byte, current remote dma address RD */
#define EN0_RSARHI	0x09	/* Remote start address reg 1 */
#define EN0_RCNTLO	0x0a	/* Remote byte count reg WR */
#define EN0_RCNTHI	0x0b	/* Remote byte count reg WR */
#define EN0_RSR		0x0c	/* rx status reg RD */
#define EN0_RXCR	0x0c	/* RX configuration reg WR */
#define EN0_TXCR	0x0d	/* TX configuration reg WR */
#define EN0_COUNTER0	0x0d	/* Rcv alignment error counter RD */
#define EN0_DCFG	0x0e	/* Data configuration reg WR */
#define EN0_COUNTER1	0x0e	/* Rcv CRC error counter RD */
#define EN0_IMR		0x0f	/* Interrupt mask reg WR */
#define EN0_COUNTER2	0x0f	/* Rcv missed frame error counter RD */

#define EN1_PHYS        0x11
#define EN1_CURPAG      0x17
#define EN1_MULT        0x18

/*  Register accessed at EN_CMD, the 8390 base addr.  */
#define E8390_STOP	0x01	/* Stop and reset the chip */
#define E8390_START	0x02	/* Start the chip, clear reset */
#define E8390_TRANS	0x04	/* Transmit a frame */
#define E8390_RREAD	0x08	/* Remote read */
#define E8390_RWRITE	0x10	/* Remote write  */
#define E8390_NODMA	0x20	/* Remote DMA */
#define E8390_PAGE0	0x00	/* Select page chip registers */
#define E8390_PAGE1	0x40	/* using the two high-order bits */
#define E8390_PAGE2	0x80	/* Page 3 is invalid. */

/* Bits in EN0_ISR - Interrupt status register */
#define ENISR_RX	0x01	/* Receiver, no error */
#define ENISR_TX	0x02	/* Transmitter, no error */
#define ENISR_RX_ERR	0x04	/* Receiver, with error */
#define ENISR_TX_ERR	0x08	/* Transmitter, with error */
#define ENISR_OVER	0x10	/* Receiver overwrote the ring */
#define ENISR_COUNTERS	0x20	/* Counters need emptying */
#define ENISR_RDC	0x40	/* remote dma complete */
#define ENISR_RESET	0x80	/* Reset completed */
#define ENISR_ALL	0x3f	/* Interrupts we will enable */

/* Bits in received packet status byte and EN0_RSR*/
#define ENRSR_RXOK	0x01	/* Received a good packet */
#define ENRSR_CRC	0x02	/* CRC error */
#define ENRSR_FAE	0x04	/* frame alignment error */
#define ENRSR_FO	0x08	/* FIFO overrun */
#define ENRSR_MPA	0x10	/* missed pkt */
#define ENRSR_PHY	0x20	/* physical/multicast address */
#define ENRSR_DIS	0x40	/* receiver disable. set in monitor mode */
#define ENRSR_DEF	0x80	/* deferring */

/* Transmitted packet status, EN0_TSR. */
#define ENTSR_PTX 0x01	/* Packet transmitted without error */
#define ENTSR_ND  0x02	/* The transmit wasn't deferred. */
#define ENTSR_COL 0x04	/* The transmit collided at least once. */
#define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
#define ENTSR_CRS 0x10	/* The carrier sense was lost. */
#define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
#define ENTSR_CDH 0x40	/* The collision detect "heartbeat" signal was lost. */
#define ENTSR_OWC 0x80  /* There was an out-of-window collision. */

#define NE2000_MEM_SIZE 32768

typedef struct NE2000State {
    uint8_t cmd;
    uint32_t start;
    uint32_t stop;
    uint8_t boundary;
    uint8_t tsr;
    uint8_t tpsr;
    uint16_t tcnt;
    uint16_t rcnt;
    uint32_t rsar;
    uint8_t isr;
    uint8_t dcfg;
    uint8_t imr;
    uint8_t phys[6]; /* mac address */
    uint8_t curpag;
    uint8_t mult[8]; /* multicast mask array */
    int irq;
    NetDriverState *nd;
    uint8_t mem[NE2000_MEM_SIZE];
} NE2000State;

static void ne2000_reset(NE2000State *s)
{
    int i;

    s->isr = ENISR_RESET;
    memcpy(s->mem, s->nd->macaddr, 6);
    s->mem[14] = 0x57;
    s->mem[15] = 0x57;

    /* duplicate prom data */
    for(i = 15;i >= 0; i--) {
        s->mem[2 * i] = s->mem[i];
        s->mem[2 * i + 1] = s->mem[i];
    }
}

static void ne2000_update_irq(NE2000State *s)
{
    int isr;
    isr = s->isr & s->imr;
    if (isr)
        pic_set_irq(s->irq, 1);
    else
        pic_set_irq(s->irq, 0);
}

/* return the max buffer size if the NE2000 can receive more data */
static int ne2000_can_receive(void *opaque)
{
    NE2000State *s = opaque;
    int avail, index, boundary;
    
    if (s->cmd & E8390_STOP)
        return 0;
    index = s->curpag << 8;
    boundary = s->boundary << 8;
    if (index < boundary)
        avail = boundary - index;
    else
        avail = (s->stop - s->start) - (index - boundary);
    if (avail < (MAX_ETH_FRAME_SIZE + 4))
        return 0;
    return MAX_ETH_FRAME_SIZE;
}

#define MIN_BUF_SIZE 60

static void ne2000_receive(void *opaque, const uint8_t *buf, int size)
{
    NE2000State *s = opaque;
    uint8_t *p;
    int total_len, next, avail, len, index;
    uint8_t buf1[60];
    
#if defined(DEBUG_NE2000)
    printf("NE2000: received len=%d\n", size);
#endif

    /* if too small buffer, then expand it */
    if (size < MIN_BUF_SIZE) {
        memcpy(buf1, buf, size);
        memset(buf1 + size, 0, MIN_BUF_SIZE - size);
        buf = buf1;
        size = MIN_BUF_SIZE;
    }

    index = s->curpag << 8;
    /* 4 bytes for header */
    total_len = size + 4;
    /* address for next packet (4 bytes for CRC) */
    next = index + ((total_len + 4 + 255) & ~0xff);
    if (next >= s->stop)
        next -= (s->stop - s->start);
    /* prepare packet header */
    p = s->mem + index;
    p[0] = ENRSR_RXOK; /* receive status */
    p[1] = next >> 8;
    p[2] = total_len;
    p[3] = total_len >> 8;
    index += 4;

    /* write packet data */
    while (size > 0) {
        avail = s->stop - index;
        len = size;
        if (len > avail)
            len = avail;
        memcpy(s->mem + index, buf, len);
        buf += len;
        index += len;
        if (index == s->stop)
            index = s->start;
        size -= len;
    }
    s->curpag = next >> 8;
    
    /* now we can signal we have receive something */
    s->isr |= ENISR_RX;
    ne2000_update_irq(s);
}

static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
    NE2000State *s = opaque;
    int offset, page;

    addr &= 0xf;
#ifdef DEBUG_NE2000
    printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
#endif
    if (addr == E8390_CMD) {
        /* control register */
        s->cmd = val;
        if (val & E8390_START) {
            /* test specific case: zero length transfert */
            if ((val & (E8390_RREAD | E8390_RWRITE)) &&
                s->rcnt == 0) {
                s->isr |= ENISR_RDC;
                ne2000_update_irq(s);
            }
            if (val & E8390_TRANS) {
                net_send_packet(s->nd, s->mem + (s->tpsr << 8), s->tcnt);
                /* signal end of transfert */
                s->tsr = ENTSR_PTX;
                s->isr |= ENISR_TX;
                ne2000_update_irq(s);
            }
        }
    } else {
        page = s->cmd >> 6;
        offset = addr | (page << 4);
        switch(offset) {
        case EN0_STARTPG:
            s->start = val << 8;
            break;
        case EN0_STOPPG:
            s->stop = val << 8;
            break;
        case EN0_BOUNDARY:
            s->boundary = val;
            break;
        case EN0_IMR:
            s->imr = val;
            ne2000_update_irq(s);
            break;
        case EN0_TPSR:
            s->tpsr = val;
            break;
        case EN0_TCNTLO:
            s->tcnt = (s->tcnt & 0xff00) | val;
            break;
        case EN0_TCNTHI:
            s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
            break;
        case EN0_RSARLO:
            s->rsar = (s->rsar & 0xff00) | val;
            break;
        case EN0_RSARHI:
            s->rsar = (s->rsar & 0x00ff) | (val << 8);
            break;
        case EN0_RCNTLO:
            s->rcnt = (s->rcnt & 0xff00) | val;
            break;
        case EN0_RCNTHI:
            s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
            break;
        case EN0_DCFG:
            s->dcfg = val;
            break;
        case EN0_ISR:
            s->isr &= ~val;
            ne2000_update_irq(s);
            break;
        case EN1_PHYS ... EN1_PHYS + 5:
            s->phys[offset - EN1_PHYS] = val;
            break;
        case EN1_CURPAG:
            s->curpag = val;
            break;
        case EN1_MULT ... EN1_MULT + 7:
            s->mult[offset - EN1_MULT] = val;
            break;
        }
    }
}

static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
{
    NE2000State *s = opaque;
    int offset, page, ret;

    addr &= 0xf;
    if (addr == E8390_CMD) {
        ret = s->cmd;
    } else {
        page = s->cmd >> 6;
        offset = addr | (page << 4);
        switch(offset) {
        case EN0_TSR:
            ret = s->tsr;
            break;
        case EN0_BOUNDARY:
            ret = s->boundary;
            break;
        case EN0_ISR:
            ret = s->isr;
            break;
        case EN1_PHYS ... EN1_PHYS + 5:
            ret = s->phys[offset - EN1_PHYS];
            break;
        case EN1_CURPAG:
            ret = s->curpag;
            break;
        case EN1_MULT ... EN1_MULT + 7:
            ret = s->mult[offset - EN1_MULT];
            break;
        default:
            ret = 0x00;
            break;
        }
    }
#ifdef DEBUG_NE2000
    printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
#endif
    return ret;
}

static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
    NE2000State *s = opaque;
    uint8_t *p;

#ifdef DEBUG_NE2000
    printf("NE2000: asic write val=0x%04x\n", val);
#endif
    p = s->mem + s->rsar;
    if (s->dcfg & 0x01) {
        /* 16 bit access */
        p[0] = val;
        p[1] = val >> 8;
        s->rsar += 2;
        s->rcnt -= 2;
    } else {
        /* 8 bit access */
        p[0] = val;
        s->rsar++;
        s->rcnt--;
    }
    /* wrap */
    if (s->rsar == s->stop)
        s->rsar = s->start;
    if (s->rcnt == 0) {
        /* signal end of transfert */
        s->isr |= ENISR_RDC;
        ne2000_update_irq(s);
    }
}

static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
{
    NE2000State *s = opaque;
    uint8_t *p;
    int ret;

    p = s->mem + s->rsar;
    if (s->dcfg & 0x01) {
        /* 16 bit access */
        ret = p[0] | (p[1] << 8);
        s->rsar += 2;
        s->rcnt -= 2;
    } else {
        /* 8 bit access */
        ret = p[0];
        s->rsar++;
        s->rcnt--;
    }
    /* wrap */
    if (s->rsar == s->stop)
        s->rsar = s->start;
    if (s->rcnt == 0) {
        /* signal end of transfert */
        s->isr |= ENISR_RDC;
        ne2000_update_irq(s);
    }
#ifdef DEBUG_NE2000
    printf("NE2000: asic read val=0x%04x\n", ret);
#endif
    return ret;
}

static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
    /* nothing to do (end of reset pulse) */
}

static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
{
    NE2000State *s = opaque;
    ne2000_reset(s);
    return 0;
}

void ne2000_init(int base, int irq, NetDriverState *nd)
{
    NE2000State *s;

    s = qemu_mallocz(sizeof(NE2000State));
    if (!s)
        return;
    
    register_ioport_write(base, 16, 1, ne2000_ioport_write, s);
    register_ioport_read(base, 16, 1, ne2000_ioport_read, s);

    register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s);
    register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s);
    register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s);
    register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s);

    register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
    register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
    s->irq = irq;
    s->nd = nd;

    ne2000_reset(s);

    qemu_add_fd_read_handler(nd->fd, ne2000_can_receive, ne2000_receive, s);
}
Commit	Line	Data
80cabfad FB	1	/*
	2	* QEMU NE2000 emulation
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
80cabfad FB	24	#include "vl.h"
	25
	26	/* debug NE2000 card */
	27	//#define DEBUG_NE2000
	28
b41a2cd1	29	#define MAX_ETH_FRAME_SIZE 1514
80cabfad FB	30
	31	#define E8390_CMD 0x00 /* The command register (for all pages) */
	32	/* Page 0 register offsets. */
	33	#define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
	34	#define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
	35	#define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
	36	#define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
	37	#define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
	38	#define EN0_TSR 0x04 /* Transmit status reg RD */
	39	#define EN0_TPSR 0x04 /* Transmit starting page WR */
	40	#define EN0_NCR 0x05 /* Number of collision reg RD */
	41	#define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
	42	#define EN0_FIFO 0x06 /* FIFO RD */
	43	#define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
	44	#define EN0_ISR 0x07 /* Interrupt status reg RD WR */
	45	#define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
	46	#define EN0_RSARLO 0x08 /* Remote start address reg 0 */
	47	#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
	48	#define EN0_RSARHI 0x09 /* Remote start address reg 1 */
	49	#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
	50	#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
	51	#define EN0_RSR 0x0c /* rx status reg RD */
	52	#define EN0_RXCR 0x0c /* RX configuration reg WR */
	53	#define EN0_TXCR 0x0d /* TX configuration reg WR */
	54	#define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
	55	#define EN0_DCFG 0x0e /* Data configuration reg WR */
	56	#define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
	57	#define EN0_IMR 0x0f /* Interrupt mask reg WR */
	58	#define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
	59
	60	#define EN1_PHYS 0x11
	61	#define EN1_CURPAG 0x17
	62	#define EN1_MULT 0x18
	63
	64	/* Register accessed at EN_CMD, the 8390 base addr. */
	65	#define E8390_STOP 0x01 /* Stop and reset the chip */
	66	#define E8390_START 0x02 /* Start the chip, clear reset */
	67	#define E8390_TRANS 0x04 /* Transmit a frame */
	68	#define E8390_RREAD 0x08 /* Remote read */
	69	#define E8390_RWRITE 0x10 /* Remote write */
	70	#define E8390_NODMA 0x20 /* Remote DMA */
	71	#define E8390_PAGE0 0x00 /* Select page chip registers */
	72	#define E8390_PAGE1 0x40 /* using the two high-order bits */
	73	#define E8390_PAGE2 0x80 /* Page 3 is invalid. */
	74
	75	/* Bits in EN0_ISR - Interrupt status register */
	76	#define ENISR_RX 0x01 /* Receiver, no error */
	77	#define ENISR_TX 0x02 /* Transmitter, no error */
	78	#define ENISR_RX_ERR 0x04 /* Receiver, with error */
	79	#define ENISR_TX_ERR 0x08 /* Transmitter, with error */
	80	#define ENISR_OVER 0x10 /* Receiver overwrote the ring */
	81	#define ENISR_COUNTERS 0x20 /* Counters need emptying */
	82	#define ENISR_RDC 0x40 /* remote dma complete */
	83	#define ENISR_RESET 0x80 /* Reset completed */
	84	#define ENISR_ALL 0x3f /* Interrupts we will enable */
	85
	86	/* Bits in received packet status byte and EN0_RSR*/
	87	#define ENRSR_RXOK 0x01 /* Received a good packet */
	88	#define ENRSR_CRC 0x02 /* CRC error */
	89	#define ENRSR_FAE 0x04 /* frame alignment error */
	90	#define ENRSR_FO 0x08 /* FIFO overrun */
	91	#define ENRSR_MPA 0x10 /* missed pkt */
	92	#define ENRSR_PHY 0x20 /* physical/multicast address */
	93	#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
94	#define ENRSR_DEF 0x80 /* deferring */
95
96	/* Transmitted packet status, EN0_TSR. */
97	#define ENTSR_PTX 0x01 /* Packet transmitted without error */
98	#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
99	#define ENTSR_COL 0x04 /* The transmit collided at least once. */
100	#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
101	#define ENTSR_CRS 0x10 /* The carrier sense was lost. */
102	#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
103	#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
104	#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
105
106	#define NE2000_MEM_SIZE 32768
107
108	typedef struct NE2000State {
109	uint8_t cmd;
110	uint32_t start;
111	uint32_t stop;
112	uint8_t boundary;
113	uint8_t tsr;
114	uint8_t tpsr;
115	uint16_t tcnt;
116	uint16_t rcnt;
117	uint32_t rsar;
118	uint8_t isr;
119	uint8_t dcfg;
120	uint8_t imr;
121	uint8_t phys[6]; /* mac address */
122	uint8_t curpag;
123	uint8_t mult[8]; /* multicast mask array */
124	int irq;
b41a2cd1	125	NetDriverState *nd;
80cabfad FB	126	uint8_t mem[NE2000_MEM_SIZE];
	127	} NE2000State;
	128
80cabfad FB	129	static void ne2000_reset(NE2000State *s)
	130	{
	131	int i;
	132
	133	s->isr = ENISR_RESET;
b41a2cd1	134	memcpy(s->mem, s->nd->macaddr, 6);
80cabfad FB	135	s->mem[14] = 0x57;
	136	s->mem[15] = 0x57;
	137
	138	/* duplicate prom data */
	139	for(i = 15;i >= 0; i--) {
	140	s->mem[2 * i] = s->mem[i];
	141	s->mem[2 * i + 1] = s->mem[i];
	142	}
	143	}
	144
	145	static void ne2000_update_irq(NE2000State *s)
	146	{
	147	int isr;
	148	isr = s->isr & s->imr;
	149	if (isr)
	150	pic_set_irq(s->irq, 1);
	151	else
	152	pic_set_irq(s->irq, 0);
	153	}
	154
b41a2cd1 FB	155	/* return the max buffer size if the NE2000 can receive more data */
b41a2cd1 FB	156	static int ne2000_can_receive(void *opaque)
80cabfad	157	{
b41a2cd1	158	NE2000State *s = opaque;
80cabfad FB	159	int avail, index, boundary;
	160
	161	if (s->cmd & E8390_STOP)
	162	return 0;
	163	index = s->curpag << 8;
	164	boundary = s->boundary << 8;
	165	if (index < boundary)
	166	avail = boundary - index;
	167	else
	168	avail = (s->stop - s->start) - (index - boundary);
	169	if (avail < (MAX_ETH_FRAME_SIZE + 4))
	170	return 0;
b41a2cd1	171	return MAX_ETH_FRAME_SIZE;
80cabfad FB	172	}
80cabfad FB	173
b41a2cd1 FB	174	#define MIN_BUF_SIZE 60
	175
	176	static void ne2000_receive(void opaque, const uint8_t buf, int size)
80cabfad	177	{
b41a2cd1	178	NE2000State *s = opaque;
80cabfad FB	179	uint8_t *p;
80cabfad FB	180	int total_len, next, avail, len, index;
b41a2cd1 FB	181	uint8_t buf1[60];
b41a2cd1 FB	182
80cabfad FB	183	#if defined(DEBUG_NE2000)
	184	printf("NE2000: received len=%d\n", size);
	185	#endif
	186
b41a2cd1 FB	187	/* if too small buffer, then expand it */
	188	if (size < MIN_BUF_SIZE) {
	189	memcpy(buf1, buf, size);
	190	memset(buf1 + size, 0, MIN_BUF_SIZE - size);
	191	buf = buf1;
	192	size = MIN_BUF_SIZE;
	193	}
	194
80cabfad FB	195	index = s->curpag << 8;
	196	/* 4 bytes for header */
	197	total_len = size + 4;
	198	/* address for next packet (4 bytes for CRC) */
	199	next = index + ((total_len + 4 + 255) & ~0xff);
	200	if (next >= s->stop)
	201	next -= (s->stop - s->start);
	202	/* prepare packet header */
	203	p = s->mem + index;
	204	p[0] = ENRSR_RXOK; /* receive status */
	205	p[1] = next >> 8;
	206	p[2] = total_len;
	207	p[3] = total_len >> 8;
	208	index += 4;
	209
	210	/* write packet data */
	211	while (size > 0) {
	212	avail = s->stop - index;
	213	len = size;
	214	if (len > avail)
	215	len = avail;
	216	memcpy(s->mem + index, buf, len);
	217	buf += len;
	218	index += len;
	219	if (index == s->stop)
	220	index = s->start;
	221	size -= len;
	222	}
	223	s->curpag = next >> 8;
	224
	225	/* now we can signal we have receive something */
	226	s->isr \|= ENISR_RX;
	227	ne2000_update_irq(s);
	228	}
	229
b41a2cd1	230	static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
80cabfad	231	{
b41a2cd1	232	NE2000State *s = opaque;
80cabfad FB	233	int offset, page;
	234
	235	addr &= 0xf;
	236	#ifdef DEBUG_NE2000
	237	printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
	238	#endif
	239	if (addr == E8390_CMD) {
	240	/* control register */
	241	s->cmd = val;
	242	if (val & E8390_START) {
	243	/* test specific case: zero length transfert */
	244	if ((val & (E8390_RREAD \| E8390_RWRITE)) &&
	245	s->rcnt == 0) {
	246	s->isr \|= ENISR_RDC;
	247	ne2000_update_irq(s);
	248	}
	249	if (val & E8390_TRANS) {
b41a2cd1	250	net_send_packet(s->nd, s->mem + (s->tpsr << 8), s->tcnt);
80cabfad FB	251	/* signal end of transfert */
	252	s->tsr = ENTSR_PTX;
	253	s->isr \|= ENISR_TX;
	254	ne2000_update_irq(s);
	255	}
	256	}
	257	} else {
	258	page = s->cmd >> 6;
	259	offset = addr \| (page << 4);
	260	switch(offset) {
	261	case EN0_STARTPG:
	262	s->start = val << 8;
	263	break;
	264	case EN0_STOPPG:
	265	s->stop = val << 8;
	266	break;
	267	case EN0_BOUNDARY:
	268	s->boundary = val;
	269	break;
	270	case EN0_IMR:
	271	s->imr = val;
	272	ne2000_update_irq(s);
	273	break;
	274	case EN0_TPSR:
	275	s->tpsr = val;
	276	break;
	277	case EN0_TCNTLO:
	278	s->tcnt = (s->tcnt & 0xff00) \| val;
	279	break;
	280	case EN0_TCNTHI:
	281	s->tcnt = (s->tcnt & 0x00ff) \| (val << 8);
	282	break;
	283	case EN0_RSARLO:
	284	s->rsar = (s->rsar & 0xff00) \| val;
	285	break;
	286	case EN0_RSARHI:
	287	s->rsar = (s->rsar & 0x00ff) \| (val << 8);
	288	break;
	289	case EN0_RCNTLO:
	290	s->rcnt = (s->rcnt & 0xff00) \| val;
	291	break;
	292	case EN0_RCNTHI:
	293	s->rcnt = (s->rcnt & 0x00ff) \| (val << 8);
	294	break;
	295	case EN0_DCFG:
	296	s->dcfg = val;
	297	break;
	298	case EN0_ISR:
	299	s->isr &= ~val;
	300	ne2000_update_irq(s);
	301	break;
	302	case EN1_PHYS ... EN1_PHYS + 5:
	303	s->phys[offset - EN1_PHYS] = val;
	304	break;
	305	case EN1_CURPAG:
	306	s->curpag = val;
	307	break;
	308	case EN1_MULT ... EN1_MULT + 7:
	309	s->mult[offset - EN1_MULT] = val;
	310	break;
	311	}
	312	}
	313	}
	314
b41a2cd1	315	static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
80cabfad	316	{
b41a2cd1	317	NE2000State *s = opaque;
80cabfad FB	318	int offset, page, ret;
	319
	320	addr &= 0xf;
	321	if (addr == E8390_CMD) {
	322	ret = s->cmd;
	323	} else {
	324	page = s->cmd >> 6;
	325	offset = addr \| (page << 4);
	326	switch(offset) {
	327	case EN0_TSR:
	328	ret = s->tsr;
	329	break;
	330	case EN0_BOUNDARY:
	331	ret = s->boundary;
	332	break;
	333	case EN0_ISR:
	334	ret = s->isr;
	335	break;
	336	case EN1_PHYS ... EN1_PHYS + 5:
	337	ret = s->phys[offset - EN1_PHYS];
	338	break;
	339	case EN1_CURPAG:
	340	ret = s->curpag;
	341	break;
	342	case EN1_MULT ... EN1_MULT + 7:
	343	ret = s->mult[offset - EN1_MULT];
	344	break;
	345	default:
	346	ret = 0x00;
	347	break;
	348	}
	349	}
	350	#ifdef DEBUG_NE2000
	351	printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
	352	#endif
	353	return ret;
	354	}
	355
b41a2cd1	356	static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
80cabfad	357	{
b41a2cd1	358	NE2000State *s = opaque;
80cabfad FB	359	uint8_t *p;
	360
	361	#ifdef DEBUG_NE2000
	362	printf("NE2000: asic write val=0x%04x\n", val);
	363	#endif
	364	p = s->mem + s->rsar;
	365	if (s->dcfg & 0x01) {
	366	/* 16 bit access */
	367	p[0] = val;
	368	p[1] = val >> 8;
	369	s->rsar += 2;
	370	s->rcnt -= 2;
	371	} else {
	372	/* 8 bit access */
	373	p[0] = val;
	374	s->rsar++;
	375	s->rcnt--;
	376	}
	377	/* wrap */
	378	if (s->rsar == s->stop)
	379	s->rsar = s->start;
	380	if (s->rcnt == 0) {
	381	/* signal end of transfert */
	382	s->isr \|= ENISR_RDC;
	383	ne2000_update_irq(s);
	384	}
	385	}
	386
b41a2cd1	387	static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
80cabfad	388	{
b41a2cd1	389	NE2000State *s = opaque;
80cabfad FB	390	uint8_t *p;
	391	int ret;
	392
	393	p = s->mem + s->rsar;
	394	if (s->dcfg & 0x01) {
	395	/* 16 bit access */
	396	ret = p[0] \| (p[1] << 8);
	397	s->rsar += 2;
	398	s->rcnt -= 2;
	399	} else {
	400	/* 8 bit access */
	401	ret = p[0];
	402	s->rsar++;
	403	s->rcnt--;
	404	}
	405	/* wrap */
	406	if (s->rsar == s->stop)
	407	s->rsar = s->start;
	408	if (s->rcnt == 0) {
	409	/* signal end of transfert */
	410	s->isr \|= ENISR_RDC;
	411	ne2000_update_irq(s);
	412	}
	413	#ifdef DEBUG_NE2000
	414	printf("NE2000: asic read val=0x%04x\n", ret);
	415	#endif
	416	return ret;
	417	}
	418
b41a2cd1	419	static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
80cabfad FB	420	{
	421	/* nothing to do (end of reset pulse) */
	422	}
	423
b41a2cd1	424	static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
80cabfad	425	{
b41a2cd1	426	NE2000State *s = opaque;
80cabfad FB	427	ne2000_reset(s);
	428	return 0;
	429	}
	430
b41a2cd1	431	void ne2000_init(int base, int irq, NetDriverState *nd)
80cabfad	432	{
b41a2cd1	433	NE2000State *s;
80cabfad	434
b41a2cd1 FB	435	s = qemu_mallocz(sizeof(NE2000State));
	436	if (!s)
	437	return;
	438
	439	register_ioport_write(base, 16, 1, ne2000_ioport_write, s);
	440	register_ioport_read(base, 16, 1, ne2000_ioport_read, s);
80cabfad	441
b41a2cd1 FB	442	register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s);
	443	register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s);
	444	register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s);
	445	register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s);
80cabfad	446
b41a2cd1 FB	447	register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
b41a2cd1 FB	448	register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
80cabfad	449	s->irq = irq;
b41a2cd1	450	s->nd = nd;
80cabfad FB	451
80cabfad FB	452	ne2000_reset(s);
b41a2cd1	453
b0a21b53	454	qemu_add_fd_read_handler(nd->fd, ne2000_can_receive, ne2000_receive, s);
80cabfad	455	}