[qemu.git] / hw / omap_i2c.c

/*
 * TI OMAP on-chip I2C controller.  Only "new I2C" mode supported.
 *
 * Copyright (C) 2007 Andrzej Zaborowski  <[email protected]>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */
#include "hw.h"
#include "i2c.h"
#include "omap.h"
#include "sysbus.h"


typedef struct OMAPI2CState {
    SysBusDevice busdev;
    MemoryRegion iomem;
    qemu_irq irq;
    qemu_irq drq[2];
    i2c_bus *bus;

    uint8_t revision;
    void *iclk;
    void *fclk;

    uint8_t mask;
    uint16_t stat;
    uint16_t dma;
    uint16_t count;
    int count_cur;
    uint32_t fifo;
    int rxlen;
    int txlen;
    uint16_t control;
    uint16_t addr[2];
    uint8_t divider;
    uint8_t times[2];
    uint16_t test;
} OMAPI2CState;

#define OMAP2_INTR_REV	0x34
#define OMAP2_GC_REV	0x34

static void omap_i2c_interrupts_update(OMAPI2CState *s)
{
    qemu_set_irq(s->irq, s->stat & s->mask);
    if ((s->dma >> 15) & 1)					/* RDMA_EN */
        qemu_set_irq(s->drq[0], (s->stat >> 3) & 1);		/* RRDY */
    if ((s->dma >> 7) & 1)					/* XDMA_EN */
        qemu_set_irq(s->drq[1], (s->stat >> 4) & 1);		/* XRDY */
}

static void omap_i2c_fifo_run(OMAPI2CState *s)
{
    int ack = 1;

    if (!i2c_bus_busy(s->bus))
        return;

    if ((s->control >> 2) & 1) {				/* RM */
        if ((s->control >> 1) & 1) {				/* STP */
            i2c_end_transfer(s->bus);
            s->control &= ~(1 << 1);				/* STP */
            s->count_cur = s->count;
            s->txlen = 0;
        } else if ((s->control >> 9) & 1) {			/* TRX */
            while (ack && s->txlen)
                ack = (i2c_send(s->bus,
                                        (s->fifo >> ((-- s->txlen) << 3)) &
                                        0xff) >= 0);
            s->stat |= 1 << 4;					/* XRDY */
        } else {
            while (s->rxlen < 4)
                s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
            s->stat |= 1 << 3;					/* RRDY */
        }
    } else {
        if ((s->control >> 9) & 1) {				/* TRX */
            while (ack && s->count_cur && s->txlen) {
                ack = (i2c_send(s->bus,
                                        (s->fifo >> ((-- s->txlen) << 3)) &
                                        0xff) >= 0);
                s->count_cur --;
            }
            if (ack && s->count_cur)
                s->stat |= 1 << 4;				/* XRDY */
            else
                s->stat &= ~(1 << 4);				/* XRDY */
            if (!s->count_cur) {
                s->stat |= 1 << 2;				/* ARDY */
                s->control &= ~(1 << 10);			/* MST */
            }
        } else {
            while (s->count_cur && s->rxlen < 4) {
                s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
                s->count_cur --;
            }
            if (s->rxlen)
                s->stat |= 1 << 3;				/* RRDY */
            else
                s->stat &= ~(1 << 3);				/* RRDY */
        }
        if (!s->count_cur) {
            if ((s->control >> 1) & 1) {			/* STP */
                i2c_end_transfer(s->bus);
                s->control &= ~(1 << 1);			/* STP */
                s->count_cur = s->count;
                s->txlen = 0;
            } else {
                s->stat |= 1 << 2;				/* ARDY */
                s->control &= ~(1 << 10);			/* MST */
            }
        }
    }

    s->stat |= (!ack) << 1;					/* NACK */
    if (!ack)
        s->control &= ~(1 << 1);				/* STP */
}

static void omap_i2c_reset(DeviceState *dev)
{
    OMAPI2CState *s = FROM_SYSBUS(OMAPI2CState,
                                  sysbus_from_qdev(dev));
    s->mask = 0;
    s->stat = 0;
    s->dma = 0;
    s->count = 0;
    s->count_cur = 0;
    s->fifo = 0;
    s->rxlen = 0;
    s->txlen = 0;
    s->control = 0;
    s->addr[0] = 0;
    s->addr[1] = 0;
    s->divider = 0;
    s->times[0] = 0;
    s->times[1] = 0;
    s->test = 0;
}

static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
{
    OMAPI2CState *s = opaque;
    int offset = addr & OMAP_MPUI_REG_MASK;
    uint16_t ret;

    switch (offset) {
    case 0x00:	/* I2C_REV */
        return s->revision;					/* REV */

    case 0x04:	/* I2C_IE */
        return s->mask;

    case 0x08:	/* I2C_STAT */
        return s->stat | (i2c_bus_busy(s->bus) << 12);

    case 0x0c:	/* I2C_IV */
        if (s->revision >= OMAP2_INTR_REV)
            break;
        ret = ffs(s->stat & s->mask);
        if (ret)
            s->stat ^= 1 << (ret - 1);
        omap_i2c_interrupts_update(s);
        return ret;

    case 0x10:	/* I2C_SYSS */
        return (s->control >> 15) & 1;				/* I2C_EN */

    case 0x14:	/* I2C_BUF */
        return s->dma;

    case 0x18:	/* I2C_CNT */
        return s->count_cur;					/* DCOUNT */

    case 0x1c:	/* I2C_DATA */
        ret = 0;
        if (s->control & (1 << 14)) {				/* BE */
            ret |= ((s->fifo >> 0) & 0xff) << 8;
            ret |= ((s->fifo >> 8) & 0xff) << 0;
        } else {
            ret |= ((s->fifo >> 8) & 0xff) << 8;
            ret |= ((s->fifo >> 0) & 0xff) << 0;
        }
        if (s->rxlen == 1) {
            s->stat |= 1 << 15;					/* SBD */
            s->rxlen = 0;
        } else if (s->rxlen > 1) {
            if (s->rxlen > 2)
                s->fifo >>= 16;
            s->rxlen -= 2;
        } else {
            /* XXX: remote access (qualifier) error - what's that?  */
        }
        if (!s->rxlen) {
            s->stat &= ~(1 << 3);				/* RRDY */
            if (((s->control >> 10) & 1) &&			/* MST */
                            ((~s->control >> 9) & 1)) {		/* TRX */
                s->stat |= 1 << 2;				/* ARDY */
                s->control &= ~(1 << 10);			/* MST */
            }
        }
        s->stat &= ~(1 << 11);					/* ROVR */
        omap_i2c_fifo_run(s);
        omap_i2c_interrupts_update(s);
        return ret;

    case 0x20:	/* I2C_SYSC */
        return 0;

    case 0x24:	/* I2C_CON */
        return s->control;

    case 0x28:	/* I2C_OA */
        return s->addr[0];

    case 0x2c:	/* I2C_SA */
        return s->addr[1];

    case 0x30:	/* I2C_PSC */
        return s->divider;

    case 0x34:	/* I2C_SCLL */
        return s->times[0];

    case 0x38:	/* I2C_SCLH */
        return s->times[1];

    case 0x3c:	/* I2C_SYSTEST */
        if (s->test & (1 << 15)) {				/* ST_EN */
            s->test ^= 0xa;
            return s->test;
        } else
            return s->test & ~0x300f;
    }

    OMAP_BAD_REG(addr);
    return 0;
}

static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
                uint32_t value)
{
    OMAPI2CState *s = opaque;
    int offset = addr & OMAP_MPUI_REG_MASK;
    int nack;

    switch (offset) {
    case 0x00:	/* I2C_REV */
    case 0x0c:	/* I2C_IV */
    case 0x10:	/* I2C_SYSS */
        OMAP_RO_REG(addr);
        return;

    case 0x04:	/* I2C_IE */
        s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f);
        break;

    case 0x08:	/* I2C_STAT */
        if (s->revision < OMAP2_INTR_REV) {
            OMAP_RO_REG(addr);
            return;
        }

        /* RRDY and XRDY are reset by hardware. (in all versions???) */
        s->stat &= ~(value & 0x27);
        omap_i2c_interrupts_update(s);
        break;

    case 0x14:	/* I2C_BUF */
        s->dma = value & 0x8080;
        if (value & (1 << 15))					/* RDMA_EN */
            s->mask &= ~(1 << 3);				/* RRDY_IE */
        if (value & (1 << 7))					/* XDMA_EN */
            s->mask &= ~(1 << 4);				/* XRDY_IE */
        break;

    case 0x18:	/* I2C_CNT */
        s->count = value;					/* DCOUNT */
        break;

    case 0x1c:	/* I2C_DATA */
        if (s->txlen > 2) {
            /* XXX: remote access (qualifier) error - what's that?  */
            break;
        }
        s->fifo <<= 16;
        s->txlen += 2;
        if (s->control & (1 << 14)) {				/* BE */
            s->fifo |= ((value >> 8) & 0xff) << 8;
            s->fifo |= ((value >> 0) & 0xff) << 0;
        } else {
            s->fifo |= ((value >> 0) & 0xff) << 8;
            s->fifo |= ((value >> 8) & 0xff) << 0;
        }
        s->stat &= ~(1 << 10);					/* XUDF */
        if (s->txlen > 2)
            s->stat &= ~(1 << 4);				/* XRDY */
        omap_i2c_fifo_run(s);
        omap_i2c_interrupts_update(s);
        break;

    case 0x20:	/* I2C_SYSC */
        if (s->revision < OMAP2_INTR_REV) {
            OMAP_BAD_REG(addr);
            return;
        }

        if (value & 2)
            omap_i2c_reset(&s->busdev.qdev);
        break;

    case 0x24:	/* I2C_CON */
        s->control = value & 0xcf87;
        if (~value & (1 << 15)) {				/* I2C_EN */
            if (s->revision < OMAP2_INTR_REV)
                omap_i2c_reset(&s->busdev.qdev);
            break;
        }
        if ((value & (1 << 15)) && !(value & (1 << 10))) {	/* MST */
            fprintf(stderr, "%s: I^2C slave mode not supported\n",
                            __FUNCTION__);
            break;
        }
        if ((value & (1 << 15)) && value & (1 << 8)) {		/* XA */
            fprintf(stderr, "%s: 10-bit addressing mode not supported\n",
                            __FUNCTION__);
            break;
        }
        if ((value & (1 << 15)) && value & (1 << 0)) {		/* STT */
            nack = !!i2c_start_transfer(s->bus, s->addr[1],	/* SA */
                            (~value >> 9) & 1);			/* TRX */
            s->stat |= nack << 1;				/* NACK */
            s->control &= ~(1 << 0);				/* STT */
            s->fifo = 0;
            if (nack)
                s->control &= ~(1 << 1);			/* STP */
            else {
                s->count_cur = s->count;
                omap_i2c_fifo_run(s);
            }
            omap_i2c_interrupts_update(s);
        }
        break;

    case 0x28:	/* I2C_OA */
        s->addr[0] = value & 0x3ff;
        break;

    case 0x2c:	/* I2C_SA */
        s->addr[1] = value & 0x3ff;
        break;

    case 0x30:	/* I2C_PSC */
        s->divider = value;
        break;

    case 0x34:	/* I2C_SCLL */
        s->times[0] = value;
        break;

    case 0x38:	/* I2C_SCLH */
        s->times[1] = value;
        break;

    case 0x3c:	/* I2C_SYSTEST */
        s->test = value & 0xf80f;
        if (value & (1 << 11))					/* SBB */
            if (s->revision >= OMAP2_INTR_REV) {
                s->stat |= 0x3f;
                omap_i2c_interrupts_update(s);
            }
        if (value & (1 << 15))					/* ST_EN */
            fprintf(stderr, "%s: System Test not supported\n", __FUNCTION__);
        break;

    default:
        OMAP_BAD_REG(addr);
        return;
    }
}

static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr,
                uint32_t value)
{
    OMAPI2CState *s = opaque;
    int offset = addr & OMAP_MPUI_REG_MASK;

    switch (offset) {
    case 0x1c:	/* I2C_DATA */
        if (s->txlen > 2) {
            /* XXX: remote access (qualifier) error - what's that?  */
            break;
        }
        s->fifo <<= 8;
        s->txlen += 1;
        s->fifo |= value & 0xff;
        s->stat &= ~(1 << 10);					/* XUDF */
        if (s->txlen > 2)
            s->stat &= ~(1 << 4);				/* XRDY */
        omap_i2c_fifo_run(s);
        omap_i2c_interrupts_update(s);
        break;

    default:
        OMAP_BAD_REG(addr);
        return;
    }
}

static const MemoryRegionOps omap_i2c_ops = {
    .old_mmio = {
        .read = {
            omap_badwidth_read16,
            omap_i2c_read,
            omap_badwidth_read16,
        },
        .write = {
            omap_i2c_writeb, /* Only the last fifo write can be 8 bit.  */
            omap_i2c_write,
            omap_badwidth_write16,
        },
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static int omap_i2c_init(SysBusDevice *dev)
{
    OMAPI2CState *s = FROM_SYSBUS(OMAPI2CState, dev);

    if (!s->fclk) {
        hw_error("omap_i2c: fclk not connected\n");
    }
    if (s->revision >= OMAP2_INTR_REV && !s->iclk) {
        /* Note that OMAP1 doesn't have a separate interface clock */
        hw_error("omap_i2c: iclk not connected\n");
    }
    sysbus_init_irq(dev, &s->irq);
    sysbus_init_irq(dev, &s->drq[0]);
    sysbus_init_irq(dev, &s->drq[1]);
    memory_region_init_io(&s->iomem, &omap_i2c_ops, s, "omap.i2c",
                          (s->revision < OMAP2_INTR_REV) ? 0x800 : 0x1000);
    sysbus_init_mmio(dev, &s->iomem);
    s->bus = i2c_init_bus(&dev->qdev, NULL);
    return 0;
}

static Property omap_i2c_properties[] = {
    DEFINE_PROP_UINT8("revision", OMAPI2CState, revision, 0),
    DEFINE_PROP_PTR("iclk", OMAPI2CState, iclk),
    DEFINE_PROP_PTR("fclk", OMAPI2CState, fclk),
    DEFINE_PROP_END_OF_LIST(),
};

static void omap_i2c_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
    k->init = omap_i2c_init;
    dc->props = omap_i2c_properties;
    dc->reset = omap_i2c_reset;
}

static TypeInfo omap_i2c_info = {
    .name = "omap_i2c",
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(OMAPI2CState),
    .class_init = omap_i2c_class_init,
};

static void omap_i2c_register_types(void)
{
    type_register_static(&omap_i2c_info);
}

i2c_bus *omap_i2c_bus(DeviceState *omap_i2c)
{
    OMAPI2CState *s = FROM_SYSBUS(OMAPI2CState, sysbus_from_qdev(omap_i2c));
    return s->bus;
}

type_init(omap_i2c_register_types)
Commit	Line	Data
02645926 AZ	1	/*
	2	* TI OMAP on-chip I2C controller. Only "new I2C" mode supported.
	3	*
	4	* Copyright (C) 2007 Andrzej Zaborowski <[email protected]>
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
fad6cb1a	16	* You should have received a copy of the GNU General Public License along
8167ee88	17	* with this program; if not, see <http://www.gnu.org/licenses/>.
02645926	18	*/
87ecb68b PB	19	#include "hw.h"
	20	#include "i2c.h"
	21	#include "omap.h"
54e17933	22	#include "sysbus.h"
02645926	23
54e17933 JR	24
	25	typedef struct OMAPI2CState {
	26	SysBusDevice busdev;
74878139	27	MemoryRegion iomem;
02645926 AZ	28	qemu_irq irq;
02645926 AZ	29	qemu_irq drq[2];
02645926 AZ	30	i2c_bus *bus;
02645926 AZ	31
29885477	32	uint8_t revision;
54e17933 JR	33	void *iclk;
	34	void *fclk;
	35
02645926 AZ	36	uint8_t mask;
	37	uint16_t stat;
	38	uint16_t dma;
	39	uint16_t count;
	40	int count_cur;
	41	uint32_t fifo;
	42	int rxlen;
	43	int txlen;
	44	uint16_t control;
	45	uint16_t addr[2];
	46	uint8_t divider;
	47	uint8_t times[2];
	48	uint16_t test;
54e17933	49	} OMAPI2CState;
02645926	50
29885477 AZ	51	#define OMAP2_INTR_REV 0x34
	52	#define OMAP2_GC_REV 0x34
	53
54e17933	54	static void omap_i2c_interrupts_update(OMAPI2CState *s)
02645926 AZ	55	{
	56	qemu_set_irq(s->irq, s->stat & s->mask);
	57	if ((s->dma >> 15) & 1) /* RDMA_EN */
	58	qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */
	59	if ((s->dma >> 7) & 1) /* XDMA_EN */
	60	qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */
	61	}
	62
54e17933	63	static void omap_i2c_fifo_run(OMAPI2CState *s)
02645926 AZ	64	{
	65	int ack = 1;
	66
	67	if (!i2c_bus_busy(s->bus))
	68	return;
	69
	70	if ((s->control >> 2) & 1) { /* RM */
	71	if ((s->control >> 1) & 1) { /* STP */
	72	i2c_end_transfer(s->bus);
	73	s->control &= ~(1 << 1); /* STP */
	74	s->count_cur = s->count;
29885477	75	s->txlen = 0;
02645926 AZ	76	} else if ((s->control >> 9) & 1) { /* TRX */
	77	while (ack && s->txlen)
	78	ack = (i2c_send(s->bus,
	79	(s->fifo >> ((-- s->txlen) << 3)) &
	80	0xff) >= 0);
	81	s->stat \|= 1 << 4; /* XRDY */
	82	} else {
	83	while (s->rxlen < 4)
	84	s->fifo \|= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
	85	s->stat \|= 1 << 3; /* RRDY */
	86	}
	87	} else {
	88	if ((s->control >> 9) & 1) { /* TRX */
	89	while (ack && s->count_cur && s->txlen) {
	90	ack = (i2c_send(s->bus,
	91	(s->fifo >> ((-- s->txlen) << 3)) &
	92	0xff) >= 0);
	93	s->count_cur --;
	94	}
	95	if (ack && s->count_cur)
	96	s->stat \|= 1 << 4; /* XRDY */
827df9f3 AZ	97	else
827df9f3 AZ	98	s->stat &= ~(1 << 4); /* XRDY */
02645926 AZ	99	if (!s->count_cur) {
	100	s->stat \|= 1 << 2; /* ARDY */
	101	s->control &= ~(1 << 10); /* MST */
	102	}
	103	} else {
	104	while (s->count_cur && s->rxlen < 4) {
	105	s->fifo \|= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
	106	s->count_cur --;
	107	}
	108	if (s->rxlen)
	109	s->stat \|= 1 << 3; /* RRDY */
827df9f3 AZ	110	else
827df9f3 AZ	111	s->stat &= ~(1 << 3); /* RRDY */
02645926 AZ	112	}
	113	if (!s->count_cur) {
	114	if ((s->control >> 1) & 1) { /* STP */
	115	i2c_end_transfer(s->bus);
	116	s->control &= ~(1 << 1); /* STP */
	117	s->count_cur = s->count;
29885477	118	s->txlen = 0;
02645926 AZ	119	} else {
	120	s->stat \|= 1 << 2; /* ARDY */
	121	s->control &= ~(1 << 10); /* MST */
	122	}
	123	}
	124	}
	125
	126	s->stat \|= (!ack) << 1; /* NACK */
	127	if (!ack)
	128	s->control &= ~(1 << 1); /* STP */
	129	}
	130
54e17933	131	static void omap_i2c_reset(DeviceState *dev)
02645926	132	{
54e17933 JR	133	OMAPI2CState *s = FROM_SYSBUS(OMAPI2CState,
54e17933 JR	134	sysbus_from_qdev(dev));
02645926 AZ	135	s->mask = 0;
	136	s->stat = 0;
	137	s->dma = 0;
	138	s->count = 0;
	139	s->count_cur = 0;
	140	s->fifo = 0;
	141	s->rxlen = 0;
	142	s->txlen = 0;
	143	s->control = 0;
	144	s->addr[0] = 0;
	145	s->addr[1] = 0;
	146	s->divider = 0;
	147	s->times[0] = 0;
	148	s->times[1] = 0;
	149	s->test = 0;
	150	}
	151
c227f099	152	static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
02645926	153	{
54e17933	154	OMAPI2CState *s = opaque;
cf965d24	155	int offset = addr & OMAP_MPUI_REG_MASK;
02645926 AZ	156	uint16_t ret;
	157
	158	switch (offset) {
	159	case 0x00: /* I2C_REV */
29885477	160	return s->revision; /* REV */
02645926 AZ	161
	162	case 0x04: /* I2C_IE */
	163	return s->mask;
	164
	165	case 0x08: /* I2C_STAT */
	166	return s->stat \| (i2c_bus_busy(s->bus) << 12);
	167
	168	case 0x0c: /* I2C_IV */
29885477 AZ	169	if (s->revision >= OMAP2_INTR_REV)
29885477 AZ	170	break;
02645926 AZ	171	ret = ffs(s->stat & s->mask);
	172	if (ret)
	173	s->stat ^= 1 << (ret - 1);
	174	omap_i2c_interrupts_update(s);
	175	return ret;
	176
29885477 AZ	177	case 0x10: /* I2C_SYSS */
	178	return (s->control >> 15) & 1; /* I2C_EN */
	179
02645926 AZ	180	case 0x14: /* I2C_BUF */
	181	return s->dma;
	182
	183	case 0x18: /* I2C_CNT */
	184	return s->count_cur; /* DCOUNT */
	185
	186	case 0x1c: /* I2C_DATA */
	187	ret = 0;
	188	if (s->control & (1 << 14)) { /* BE */
	189	ret \|= ((s->fifo >> 0) & 0xff) << 8;
	190	ret \|= ((s->fifo >> 8) & 0xff) << 0;
	191	} else {
	192	ret \|= ((s->fifo >> 8) & 0xff) << 8;
	193	ret \|= ((s->fifo >> 0) & 0xff) << 0;
	194	}
	195	if (s->rxlen == 1) {
	196	s->stat \|= 1 << 15; /* SBD */
	197	s->rxlen = 0;
	198	} else if (s->rxlen > 1) {
	199	if (s->rxlen > 2)
	200	s->fifo >>= 16;
	201	s->rxlen -= 2;
3ffd710e BS	202	} else {
	203	/* XXX: remote access (qualifier) error - what's that? */
	204	}
02645926	205	if (!s->rxlen) {
29885477	206	s->stat &= ~(1 << 3); /* RRDY */
02645926 AZ	207	if (((s->control >> 10) & 1) && /* MST */
	208	((~s->control >> 9) & 1)) { /* TRX */
	209	s->stat \|= 1 << 2; /* ARDY */
	210	s->control &= ~(1 << 10); /* MST */
	211	}
	212	}
	213	s->stat &= ~(1 << 11); /* ROVR */
	214	omap_i2c_fifo_run(s);
	215	omap_i2c_interrupts_update(s);
	216	return ret;
	217
29885477 AZ	218	case 0x20: /* I2C_SYSC */
	219	return 0;
	220
02645926 AZ	221	case 0x24: /* I2C_CON */
	222	return s->control;
	223
	224	case 0x28: /* I2C_OA */
	225	return s->addr[0];
	226
	227	case 0x2c: /* I2C_SA */
	228	return s->addr[1];
	229
	230	case 0x30: /* I2C_PSC */
	231	return s->divider;
	232
	233	case 0x34: /* I2C_SCLL */
	234	return s->times[0];
	235
	236	case 0x38: /* I2C_SCLH */
	237	return s->times[1];
	238
	239	case 0x3c: /* I2C_SYSTEST */
	240	if (s->test & (1 << 15)) { /* ST_EN */
	241	s->test ^= 0xa;
	242	return s->test;
	243	} else
	244	return s->test & ~0x300f;
	245	}
	246
	247	OMAP_BAD_REG(addr);
	248	return 0;
	249	}
	250
c227f099	251	static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
02645926 AZ	252	uint32_t value)
02645926 AZ	253	{
54e17933	254	OMAPI2CState *s = opaque;
cf965d24	255	int offset = addr & OMAP_MPUI_REG_MASK;
02645926 AZ	256	int nack;
	257
	258	switch (offset) {
	259	case 0x00: /* I2C_REV */
02645926	260	case 0x0c: /* I2C_IV */
29885477 AZ	261	case 0x10: /* I2C_SYSS */
29885477 AZ	262	OMAP_RO_REG(addr);
02645926 AZ	263	return;
	264
	265	case 0x04: /* I2C_IE */
29885477 AZ	266	s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f);
	267	break;
	268
	269	case 0x08: /* I2C_STAT */
	270	if (s->revision < OMAP2_INTR_REV) {
	271	OMAP_RO_REG(addr);
	272	return;
	273	}
	274
827df9f3 AZ	275	/* RRDY and XRDY are reset by hardware. (in all versions???) */
827df9f3 AZ	276	s->stat &= ~(value & 0x27);
29885477	277	omap_i2c_interrupts_update(s);
02645926 AZ	278	break;
	279
	280	case 0x14: /* I2C_BUF */
	281	s->dma = value & 0x8080;
	282	if (value & (1 << 15)) /* RDMA_EN */
	283	s->mask &= ~(1 << 3); /* RRDY_IE */
	284	if (value & (1 << 7)) /* XDMA_EN */
	285	s->mask &= ~(1 << 4); /* XRDY_IE */
	286	break;
	287
	288	case 0x18: /* I2C_CNT */
	289	s->count = value; /* DCOUNT */
	290	break;
	291
	292	case 0x1c: /* I2C_DATA */
	293	if (s->txlen > 2) {
	294	/* XXX: remote access (qualifier) error - what's that? */
	295	break;
	296	}
	297	s->fifo <<= 16;
	298	s->txlen += 2;
	299	if (s->control & (1 << 14)) { /* BE */
	300	s->fifo \|= ((value >> 8) & 0xff) << 8;
	301	s->fifo \|= ((value >> 0) & 0xff) << 0;
	302	} else {
	303	s->fifo \|= ((value >> 0) & 0xff) << 8;
	304	s->fifo \|= ((value >> 8) & 0xff) << 0;
	305	}
	306	s->stat &= ~(1 << 10); /* XUDF */
	307	if (s->txlen > 2)
	308	s->stat &= ~(1 << 4); /* XRDY */
	309	omap_i2c_fifo_run(s);
	310	omap_i2c_interrupts_update(s);
	311	break;
	312
29885477 AZ	313	case 0x20: /* I2C_SYSC */
	314	if (s->revision < OMAP2_INTR_REV) {
	315	OMAP_BAD_REG(addr);
	316	return;
	317	}
	318
	319	if (value & 2)
54e17933	320	omap_i2c_reset(&s->busdev.qdev);
29885477 AZ	321	break;
29885477 AZ	322
02645926	323	case 0x24: /* I2C_CON */
29885477	324	s->control = value & 0xcf87;
02645926	325	if (~value & (1 << 15)) { /* I2C_EN */
29885477	326	if (s->revision < OMAP2_INTR_REV)
54e17933	327	omap_i2c_reset(&s->busdev.qdev);
02645926 AZ	328	break;
02645926 AZ	329	}
29885477	330	if ((value & (1 << 15)) && !(value & (1 << 10))) { /* MST */
827df9f3 AZ	331	fprintf(stderr, "%s: I^2C slave mode not supported\n",
827df9f3 AZ	332	__FUNCTION__);
02645926 AZ	333	break;
02645926 AZ	334	}
29885477	335	if ((value & (1 << 15)) && value & (1 << 8)) { /* XA */
827df9f3 AZ	336	fprintf(stderr, "%s: 10-bit addressing mode not supported\n",
827df9f3 AZ	337	__FUNCTION__);
02645926 AZ	338	break;
02645926 AZ	339	}
29885477	340	if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */
02645926 AZ	341	nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */
	342	(~value >> 9) & 1); /* TRX */
	343	s->stat \|= nack << 1; /* NACK */
	344	s->control &= ~(1 << 0); /* STT */
51fec3cc	345	s->fifo = 0;
02645926 AZ	346	if (nack)
02645926 AZ	347	s->control &= ~(1 << 1); /* STP */
29885477 AZ	348	else {
29885477 AZ	349	s->count_cur = s->count;
02645926	350	omap_i2c_fifo_run(s);
29885477	351	}
02645926 AZ	352	omap_i2c_interrupts_update(s);
	353	}
	354	break;
	355
	356	case 0x28: /* I2C_OA */
	357	s->addr[0] = value & 0x3ff;
02645926 AZ	358	break;
	359
	360	case 0x2c: /* I2C_SA */
	361	s->addr[1] = value & 0x3ff;
	362	break;
	363
	364	case 0x30: /* I2C_PSC */
	365	s->divider = value;
	366	break;
	367
	368	case 0x34: /* I2C_SCLL */
	369	s->times[0] = value;
	370	break;
	371
	372	case 0x38: /* I2C_SCLH */
	373	s->times[1] = value;
	374	break;
	375
	376	case 0x3c: /* I2C_SYSTEST */
29885477 AZ	377	s->test = value & 0xf80f;
	378	if (value & (1 << 11)) /* SBB */
	379	if (s->revision >= OMAP2_INTR_REV) {
	380	s->stat \|= 0x3f;
	381	omap_i2c_interrupts_update(s);
	382	}
02645926	383	if (value & (1 << 15)) /* ST_EN */
827df9f3	384	fprintf(stderr, "%s: System Test not supported\n", __FUNCTION__);
02645926 AZ	385	break;
	386
	387	default:
	388	OMAP_BAD_REG(addr);
	389	return;
	390	}
	391	}
	392
c227f099	393	static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr,
29885477 AZ	394	uint32_t value)
29885477 AZ	395	{
54e17933	396	OMAPI2CState *s = opaque;
29885477 AZ	397	int offset = addr & OMAP_MPUI_REG_MASK;
	398
	399	switch (offset) {
	400	case 0x1c: /* I2C_DATA */
	401	if (s->txlen > 2) {
	402	/* XXX: remote access (qualifier) error - what's that? */
	403	break;
	404	}
	405	s->fifo <<= 8;
	406	s->txlen += 1;
	407	s->fifo \|= value & 0xff;
	408	s->stat &= ~(1 << 10); /* XUDF */
	409	if (s->txlen > 2)
	410	s->stat &= ~(1 << 4); /* XRDY */
	411	omap_i2c_fifo_run(s);
	412	omap_i2c_interrupts_update(s);
	413	break;
	414
	415	default:
	416	OMAP_BAD_REG(addr);
	417	return;
	418	}
	419	}
	420
74878139 BC	421	static const MemoryRegionOps omap_i2c_ops = {
	422	.old_mmio = {
	423	.read = {
	424	omap_badwidth_read16,
	425	omap_i2c_read,
	426	omap_badwidth_read16,
	427	},
	428	.write = {
	429	omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */
	430	omap_i2c_write,
	431	omap_badwidth_write16,
	432	},
	433	},
	434	.endianness = DEVICE_NATIVE_ENDIAN,
02645926 AZ	435	};
02645926 AZ	436
54e17933	437	static int omap_i2c_init(SysBusDevice *dev)
02645926	438	{
54e17933	439	OMAPI2CState *s = FROM_SYSBUS(OMAPI2CState, dev);
02645926	440
54e17933 JR	441	if (!s->fclk) {
	442	hw_error("omap_i2c: fclk not connected\n");
	443	}
	444	if (s->revision >= OMAP2_INTR_REV && !s->iclk) {
	445	/* Note that OMAP1 doesn't have a separate interface clock */
	446	hw_error("omap_i2c: iclk not connected\n");
	447	}
	448	sysbus_init_irq(dev, &s->irq);
	449	sysbus_init_irq(dev, &s->drq[0]);
	450	sysbus_init_irq(dev, &s->drq[1]);
	451	memory_region_init_io(&s->iomem, &omap_i2c_ops, s, "omap.i2c",
	452	(s->revision < OMAP2_INTR_REV) ? 0x800 : 0x1000);
	453	sysbus_init_mmio(dev, &s->iomem);
	454	s->bus = i2c_init_bus(&dev->qdev, NULL);
	455	return 0;
02645926 AZ	456	}
02645926 AZ	457
54e17933 JR	458	static Property omap_i2c_properties[] = {
	459	DEFINE_PROP_UINT8("revision", OMAPI2CState, revision, 0),
	460	DEFINE_PROP_PTR("iclk", OMAPI2CState, iclk),
	461	DEFINE_PROP_PTR("fclk", OMAPI2CState, fclk),
	462	DEFINE_PROP_END_OF_LIST(),
	463	};
29885477	464
54e17933 JR	465	static void omap_i2c_class_init(ObjectClass klass, void data)
	466	{
	467	DeviceClass *dc = DEVICE_CLASS(klass);
	468	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	469	k->init = omap_i2c_init;
	470	dc->props = omap_i2c_properties;
	471	dc->reset = omap_i2c_reset;
	472	}
29885477	473
54e17933 JR	474	static TypeInfo omap_i2c_info = {
	475	.name = "omap_i2c",
	476	.parent = TYPE_SYS_BUS_DEVICE,
	477	.instance_size = sizeof(OMAPI2CState),
	478	.class_init = omap_i2c_class_init,
	479	};
29885477	480
54e17933 JR	481	static void omap_i2c_register_types(void)
	482	{
	483	type_register_static(&omap_i2c_info);
29885477 AZ	484	}
29885477 AZ	485
54e17933	486	i2c_bus omap_i2c_bus(DeviceState omap_i2c)
02645926	487	{
54e17933	488	OMAPI2CState *s = FROM_SYSBUS(OMAPI2CState, sysbus_from_qdev(omap_i2c));
02645926 AZ	489	return s->bus;
02645926 AZ	490	}
54e17933 JR	491
54e17933 JR	492	type_init(omap_i2c_register_types)