[qemu.git] / hw / sd / omap_mmc.c

/*
 * OMAP on-chip MMC/SD host emulation.
 *
 * Copyright (C) 2006-2007 Andrzej Zaborowski  <[email protected]>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 or
 * (at your option) version 3 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "hw/hw.h"
#include "hw/arm/omap.h"
#include "hw/sd/sd.h"

struct omap_mmc_s {
    qemu_irq irq;
    qemu_irq *dma;
    qemu_irq coverswitch;
    MemoryRegion iomem;
    omap_clk clk;
    SDState *card;
    uint16_t last_cmd;
    uint16_t sdio;
    uint16_t rsp[8];
    uint32_t arg;
    int lines;
    int dw;
    int mode;
    int enable;
    int be;
    int rev;
    uint16_t status;
    uint16_t mask;
    uint8_t cto;
    uint16_t dto;
    int clkdiv;
    uint16_t fifo[32];
    int fifo_start;
    int fifo_len;
    uint16_t blen;
    uint16_t blen_counter;
    uint16_t nblk;
    uint16_t nblk_counter;
    int tx_dma;
    int rx_dma;
    int af_level;
    int ae_level;

    int ddir;
    int transfer;

    int cdet_wakeup;
    int cdet_enable;
    int cdet_state;
    qemu_irq cdet;
};

static void omap_mmc_interrupts_update(struct omap_mmc_s *s)
{
    qemu_set_irq(s->irq, !!(s->status & s->mask));
}

static void omap_mmc_fifolevel_update(struct omap_mmc_s *host)
{
    if (!host->transfer && !host->fifo_len) {
        host->status &= 0xf3ff;
        return;
    }

    if (host->fifo_len > host->af_level && host->ddir) {
        if (host->rx_dma) {
            host->status &= 0xfbff;
            qemu_irq_raise(host->dma[1]);
        } else
            host->status |= 0x0400;
    } else {
        host->status &= 0xfbff;
        qemu_irq_lower(host->dma[1]);
    }

    if (host->fifo_len < host->ae_level && !host->ddir) {
        if (host->tx_dma) {
            host->status &= 0xf7ff;
            qemu_irq_raise(host->dma[0]);
        } else
            host->status |= 0x0800;
    } else {
        qemu_irq_lower(host->dma[0]);
        host->status &= 0xf7ff;
    }
}

typedef enum {
    sd_nore = 0,	/* no response */
    sd_r1,		/* normal response command */
    sd_r2,		/* CID, CSD registers */
    sd_r3,		/* OCR register */
    sd_r6 = 6,		/* Published RCA response */
    sd_r1b = -1,
} sd_rsp_type_t;

static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
                sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
{
    uint32_t rspstatus, mask;
    int rsplen, timeout;
    SDRequest request;
    uint8_t response[16];

    if (init && cmd == 0) {
        host->status |= 0x0001;
        return;
    }

    if (resptype == sd_r1 && busy)
        resptype = sd_r1b;

    if (type == sd_adtc) {
        host->fifo_start = 0;
        host->fifo_len = 0;
        host->transfer = 1;
        host->ddir = dir;
    } else
        host->transfer = 0;
    timeout = 0;
    mask = 0;
    rspstatus = 0;

    request.cmd = cmd;
    request.arg = host->arg;
    request.crc = 0; /* FIXME */

    rsplen = sd_do_command(host->card, &request, response);

    /* TODO: validate CRCs */
    switch (resptype) {
    case sd_nore:
        rsplen = 0;
        break;

    case sd_r1:
    case sd_r1b:
        if (rsplen < 4) {
            timeout = 1;
            break;
        }
        rsplen = 4;

        mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR |
                ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION |
                LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND |
                CARD_ECC_FAILED | CC_ERROR | SD_ERROR |
                CID_CSD_OVERWRITE;
        if (host->sdio & (1 << 13))
            mask |= AKE_SEQ_ERROR;
        rspstatus = (response[0] << 24) | (response[1] << 16) |
                (response[2] << 8) | (response[3] << 0);
        break;

    case sd_r2:
        if (rsplen < 16) {
            timeout = 1;
            break;
        }
        rsplen = 16;
        break;

    case sd_r3:
        if (rsplen < 4) {
            timeout = 1;
            break;
        }
        rsplen = 4;

        rspstatus = (response[0] << 24) | (response[1] << 16) |
                (response[2] << 8) | (response[3] << 0);
        if (rspstatus & 0x80000000)
            host->status &= 0xe000;
        else
            host->status |= 0x1000;
        break;

    case sd_r6:
        if (rsplen < 4) {
            timeout = 1;
            break;
        }
        rsplen = 4;

        mask = 0xe000 | AKE_SEQ_ERROR;
        rspstatus = (response[2] << 8) | (response[3] << 0);
    }

    if (rspstatus & mask)
        host->status |= 0x4000;
    else
        host->status &= 0xb000;

    if (rsplen)
        for (rsplen = 0; rsplen < 8; rsplen ++)
            host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] |
                    (response[(rsplen << 1) | 0] << 8);

    if (timeout)
        host->status |= 0x0080;
    else if (cmd == 12)
        host->status |= 0x0005;	/* Makes it more real */
    else
        host->status |= 0x0001;
}

static void omap_mmc_transfer(struct omap_mmc_s *host)
{
    uint8_t value;

    if (!host->transfer)
        return;

    while (1) {
        if (host->ddir) {
            if (host->fifo_len > host->af_level)
                break;

            value = sd_read_data(host->card);
            host->fifo[(host->fifo_start + host->fifo_len) & 31] = value;
            if (-- host->blen_counter) {
                value = sd_read_data(host->card);
                host->fifo[(host->fifo_start + host->fifo_len) & 31] |=
                        value << 8;
                host->blen_counter --;
            }

            host->fifo_len ++;
        } else {
            if (!host->fifo_len)
                break;

            value = host->fifo[host->fifo_start] & 0xff;
            sd_write_data(host->card, value);
            if (-- host->blen_counter) {
                value = host->fifo[host->fifo_start] >> 8;
                sd_write_data(host->card, value);
                host->blen_counter --;
            }

            host->fifo_start ++;
            host->fifo_len --;
            host->fifo_start &= 31;
        }

        if (host->blen_counter == 0) {
            host->nblk_counter --;
            host->blen_counter = host->blen;

            if (host->nblk_counter == 0) {
                host->nblk_counter = host->nblk;
                host->transfer = 0;
                host->status |= 0x0008;
                break;
            }
        }
    }
}

static void omap_mmc_update(void *opaque)
{
    struct omap_mmc_s *s = opaque;
    omap_mmc_transfer(s);
    omap_mmc_fifolevel_update(s);
    omap_mmc_interrupts_update(s);
}

void omap_mmc_reset(struct omap_mmc_s *host)
{
    host->last_cmd = 0;
    memset(host->rsp, 0, sizeof(host->rsp));
    host->arg = 0;
    host->dw = 0;
    host->mode = 0;
    host->enable = 0;
    host->status = 0;
    host->mask = 0;
    host->cto = 0;
    host->dto = 0;
    host->fifo_len = 0;
    host->blen = 0;
    host->blen_counter = 0;
    host->nblk = 0;
    host->nblk_counter = 0;
    host->tx_dma = 0;
    host->rx_dma = 0;
    host->ae_level = 0x00;
    host->af_level = 0x1f;
    host->transfer = 0;
    host->cdet_wakeup = 0;
    host->cdet_enable = 0;
    qemu_set_irq(host->coverswitch, host->cdet_state);
    host->clkdiv = 0;

    /* Since we're still using the legacy SD API the card is not plugged
     * into any bus, and we must reset it manually. When omap_mmc is
     * QOMified this must move into the QOM reset function.
     */
    device_reset(DEVICE(host->card));
}

static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
                              unsigned size)
{
    uint16_t i;
    struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;

    if (size != 2) {
        return omap_badwidth_read16(opaque, offset);
    }

    switch (offset) {
    case 0x00:	/* MMC_CMD */
        return s->last_cmd;

    case 0x04:	/* MMC_ARGL */
        return s->arg & 0x0000ffff;

    case 0x08:	/* MMC_ARGH */
        return s->arg >> 16;

    case 0x0c:	/* MMC_CON */
        return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) | 
                (s->be << 10) | s->clkdiv;

    case 0x10:	/* MMC_STAT */
        return s->status;

    case 0x14:	/* MMC_IE */
        return s->mask;

    case 0x18:	/* MMC_CTO */
        return s->cto;

    case 0x1c:	/* MMC_DTO */
        return s->dto;

    case 0x20:	/* MMC_DATA */
        /* TODO: support 8-bit access */
        i = s->fifo[s->fifo_start];
        if (s->fifo_len == 0) {
            printf("MMC: FIFO underrun\n");
            return i;
        }
        s->fifo_start ++;
        s->fifo_len --;
        s->fifo_start &= 31;
        omap_mmc_transfer(s);
        omap_mmc_fifolevel_update(s);
        omap_mmc_interrupts_update(s);
        return i;

    case 0x24:	/* MMC_BLEN */
        return s->blen_counter;

    case 0x28:	/* MMC_NBLK */
        return s->nblk_counter;

    case 0x2c:	/* MMC_BUF */
        return (s->rx_dma << 15) | (s->af_level << 8) |
            (s->tx_dma << 7) | s->ae_level;

    case 0x30:	/* MMC_SPI */
        return 0x0000;
    case 0x34:	/* MMC_SDIO */
        return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio;
    case 0x38:	/* MMC_SYST */
        return 0x0000;

    case 0x3c:	/* MMC_REV */
        return s->rev;

    case 0x40:	/* MMC_RSP0 */
    case 0x44:	/* MMC_RSP1 */
    case 0x48:	/* MMC_RSP2 */
    case 0x4c:	/* MMC_RSP3 */
    case 0x50:	/* MMC_RSP4 */
    case 0x54:	/* MMC_RSP5 */
    case 0x58:	/* MMC_RSP6 */
    case 0x5c:	/* MMC_RSP7 */
        return s->rsp[(offset - 0x40) >> 2];

    /* OMAP2-specific */
    case 0x60:	/* MMC_IOSR */
    case 0x64:	/* MMC_SYSC */
        return 0;
    case 0x68:	/* MMC_SYSS */
        return 1;						/* RSTD */
    }

    OMAP_BAD_REG(offset);
    return 0;
}

static void omap_mmc_write(void *opaque, hwaddr offset,
                           uint64_t value, unsigned size)
{
    int i;
    struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;

    if (size != 2) {
        omap_badwidth_write16(opaque, offset, value);
        return;
    }

    switch (offset) {
    case 0x00:	/* MMC_CMD */
        if (!s->enable)
            break;

        s->last_cmd = value;
        for (i = 0; i < 8; i ++)
            s->rsp[i] = 0x0000;
        omap_mmc_command(s, value & 63, (value >> 15) & 1,
                (sd_cmd_type_t) ((value >> 12) & 3),
                (value >> 11) & 1,
                (sd_rsp_type_t) ((value >> 8) & 7),
                (value >> 7) & 1);
        omap_mmc_update(s);
        break;

    case 0x04:	/* MMC_ARGL */
        s->arg &= 0xffff0000;
        s->arg |= 0x0000ffff & value;
        break;

    case 0x08:	/* MMC_ARGH */
        s->arg &= 0x0000ffff;
        s->arg |= value << 16;
        break;

    case 0x0c:	/* MMC_CON */
        s->dw = (value >> 15) & 1;
        s->mode = (value >> 12) & 3;
        s->enable = (value >> 11) & 1;
        s->be = (value >> 10) & 1;
        s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff);
        if (s->mode != 0) {
            qemu_log_mask(LOG_UNIMP,
                          "omap_mmc_wr: mode #%i unimplemented\n", s->mode);
        }
        if (s->be != 0) {
            qemu_log_mask(LOG_UNIMP,
                          "omap_mmc_wr: Big Endian not implemented\n");
        }
        if (s->dw != 0 && s->lines < 4)
            printf("4-bit SD bus enabled\n");
        if (!s->enable)
            omap_mmc_reset(s);
        break;

    case 0x10:	/* MMC_STAT */
        s->status &= ~value;
        omap_mmc_interrupts_update(s);
        break;

    case 0x14:	/* MMC_IE */
        s->mask = value & 0x7fff;
        omap_mmc_interrupts_update(s);
        break;

    case 0x18:	/* MMC_CTO */
        s->cto = value & 0xff;
        if (s->cto > 0xfd && s->rev <= 1)
            printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
        break;

    case 0x1c:	/* MMC_DTO */
        s->dto = value & 0xffff;
        break;

    case 0x20:	/* MMC_DATA */
        /* TODO: support 8-bit access */
        if (s->fifo_len == 32)
            break;
        s->fifo[(s->fifo_start + s->fifo_len) & 31] = value;
        s->fifo_len ++;
        omap_mmc_transfer(s);
        omap_mmc_fifolevel_update(s);
        omap_mmc_interrupts_update(s);
        break;

    case 0x24:	/* MMC_BLEN */
        s->blen = (value & 0x07ff) + 1;
        s->blen_counter = s->blen;
        break;

    case 0x28:	/* MMC_NBLK */
        s->nblk = (value & 0x07ff) + 1;
        s->nblk_counter = s->nblk;
        s->blen_counter = s->blen;
        break;

    case 0x2c:	/* MMC_BUF */
        s->rx_dma = (value >> 15) & 1;
        s->af_level = (value >> 8) & 0x1f;
        s->tx_dma = (value >> 7) & 1;
        s->ae_level = value & 0x1f;

        if (s->rx_dma)
            s->status &= 0xfbff;
        if (s->tx_dma)
            s->status &= 0xf7ff;
        omap_mmc_fifolevel_update(s);
        omap_mmc_interrupts_update(s);
        break;

    /* SPI, SDIO and TEST modes unimplemented */
    case 0x30:	/* MMC_SPI (OMAP1 only) */
        break;
    case 0x34:	/* MMC_SDIO */
        s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020);
        s->cdet_wakeup = (value >> 9) & 1;
        s->cdet_enable = (value >> 2) & 1;
        break;
    case 0x38:	/* MMC_SYST */
        break;

    case 0x3c:	/* MMC_REV */
    case 0x40:	/* MMC_RSP0 */
    case 0x44:	/* MMC_RSP1 */
    case 0x48:	/* MMC_RSP2 */
    case 0x4c:	/* MMC_RSP3 */
    case 0x50:	/* MMC_RSP4 */
    case 0x54:	/* MMC_RSP5 */
    case 0x58:	/* MMC_RSP6 */
    case 0x5c:	/* MMC_RSP7 */
        OMAP_RO_REG(offset);
        break;

    /* OMAP2-specific */
    case 0x60:	/* MMC_IOSR */
        if (value & 0xf)
            printf("MMC: SDIO bits used!\n");
        break;
    case 0x64:	/* MMC_SYSC */
        if (value & (1 << 2))					/* SRTS */
            omap_mmc_reset(s);
        break;
    case 0x68:	/* MMC_SYSS */
        OMAP_RO_REG(offset);
        break;

    default:
        OMAP_BAD_REG(offset);
    }
}

static const MemoryRegionOps omap_mmc_ops = {
    .read = omap_mmc_read,
    .write = omap_mmc_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void omap_mmc_cover_cb(void *opaque, int line, int level)
{
    struct omap_mmc_s *host = (struct omap_mmc_s *) opaque;

    if (!host->cdet_state && level) {
        host->status |= 0x0002;
        omap_mmc_interrupts_update(host);
        if (host->cdet_wakeup) {
            /* TODO: Assert wake-up */
        }
    }

    if (host->cdet_state != level) {
        qemu_set_irq(host->coverswitch, level);
        host->cdet_state = level;
    }
}

struct omap_mmc_s *omap_mmc_init(hwaddr base,
                MemoryRegion *sysmem,
                BlockBackend *blk,
                qemu_irq irq, qemu_irq dma[], omap_clk clk)
{
    struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);

    s->irq = irq;
    s->dma = dma;
    s->clk = clk;
    s->lines = 1;	/* TODO: needs to be settable per-board */
    s->rev = 1;

    memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 0x800);
    memory_region_add_subregion(sysmem, base, &s->iomem);

    /* Instantiate the storage */
    s->card = sd_init(blk, false);
    if (s->card == NULL) {
        exit(1);
    }

    omap_mmc_reset(s);

    return s;
}

struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
                BlockBackend *blk, qemu_irq irq, qemu_irq dma[],
                omap_clk fclk, omap_clk iclk)
{
    struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);

    s->irq = irq;
    s->dma = dma;
    s->clk = fclk;
    s->lines = 4;
    s->rev = 2;

    memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc",
                          omap_l4_region_size(ta, 0));
    omap_l4_attach(ta, 0, &s->iomem);

    /* Instantiate the storage */
    s->card = sd_init(blk, false);
    if (s->card == NULL) {
        exit(1);
    }

    s->cdet = qemu_allocate_irq(omap_mmc_cover_cb, s, 0);
    sd_set_cb(s->card, NULL, s->cdet);

    omap_mmc_reset(s);

    return s;
}

void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover)
{
    if (s->cdet) {
        sd_set_cb(s->card, ro, s->cdet);
        s->coverswitch = cover;
        qemu_set_irq(cover, s->cdet_state);
    } else
        sd_set_cb(s->card, ro, cover);
}

void omap_mmc_enable(struct omap_mmc_s *s, int enable)
{
    sd_enable(s->card, enable);
}
Commit	Line	Data
b30bb3a2 AZ	1	/*
	2	* OMAP on-chip MMC/SD host emulation.
	3	*
	4	* Copyright (C) 2006-2007 Andrzej Zaborowski <[email protected]>
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
827df9f3 AZ	8	* published by the Free Software Foundation; either version 2 or
827df9f3 AZ	9	* (at your option) version 3 of the License.
b30bb3a2 AZ	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
fad6cb1a	16	* You should have received a copy of the GNU General Public License along
8167ee88	17	* with this program; if not, see <http://www.gnu.org/licenses/>.
b30bb3a2	18	*/
17b7f2db	19	#include "qemu/osdep.h"
25b98b96	20	#include "qemu/log.h"
83c9f4ca	21	#include "hw/hw.h"
0d09e41a	22	#include "hw/arm/omap.h"
e3382ef0	23	#include "hw/sd/sd.h"
b30bb3a2 AZ	24
b30bb3a2 AZ	25	struct omap_mmc_s {
b30bb3a2 AZ	26	qemu_irq irq;
b30bb3a2 AZ	27	qemu_irq *dma;
827df9f3	28	qemu_irq coverswitch;
c304fed7	29	MemoryRegion iomem;
b30bb3a2 AZ	30	omap_clk clk;
	31	SDState *card;
	32	uint16_t last_cmd;
	33	uint16_t sdio;
	34	uint16_t rsp[8];
	35	uint32_t arg;
827df9f3	36	int lines;
b30bb3a2 AZ	37	int dw;
	38	int mode;
	39	int enable;
827df9f3 AZ	40	int be;
827df9f3 AZ	41	int rev;
b30bb3a2 AZ	42	uint16_t status;
	43	uint16_t mask;
	44	uint8_t cto;
	45	uint16_t dto;
827df9f3	46	int clkdiv;
b30bb3a2 AZ	47	uint16_t fifo[32];
	48	int fifo_start;
	49	int fifo_len;
	50	uint16_t blen;
	51	uint16_t blen_counter;
	52	uint16_t nblk;
	53	uint16_t nblk_counter;
	54	int tx_dma;
	55	int rx_dma;
	56	int af_level;
	57	int ae_level;
	58
	59	int ddir;
	60	int transfer;
827df9f3 AZ	61
	62	int cdet_wakeup;
	63	int cdet_enable;
	64	int cdet_state;
	65	qemu_irq cdet;
b30bb3a2 AZ	66	};
	67
	68	static void omap_mmc_interrupts_update(struct omap_mmc_s *s)
	69	{
	70	qemu_set_irq(s->irq, !!(s->status & s->mask));
	71	}
	72
	73	static void omap_mmc_fifolevel_update(struct omap_mmc_s *host)
	74	{
	75	if (!host->transfer && !host->fifo_len) {
	76	host->status &= 0xf3ff;
	77	return;
	78	}
	79
	80	if (host->fifo_len > host->af_level && host->ddir) {
	81	if (host->rx_dma) {
	82	host->status &= 0xfbff;
	83	qemu_irq_raise(host->dma[1]);
	84	} else
	85	host->status \|= 0x0400;
	86	} else {
	87	host->status &= 0xfbff;
	88	qemu_irq_lower(host->dma[1]);
	89	}
	90
	91	if (host->fifo_len < host->ae_level && !host->ddir) {
	92	if (host->tx_dma) {
	93	host->status &= 0xf7ff;
	94	qemu_irq_raise(host->dma[0]);
	95	} else
	96	host->status \|= 0x0800;
	97	} else {
	98	qemu_irq_lower(host->dma[0]);
	99	host->status &= 0xf7ff;
	100	}
	101	}
	102
	103	typedef enum {
	104	sd_nore = 0, /* no response */
	105	sd_r1, /* normal response command */
	106	sd_r2, /* CID, CSD registers */
	107	sd_r3, /* OCR register */
	108	sd_r6 = 6, /* Published RCA response */
	109	sd_r1b = -1,
c227f099	110	} sd_rsp_type_t;
b30bb3a2 AZ	111
b30bb3a2 AZ	112	static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
c227f099	113	sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
b30bb3a2 AZ	114	{
	115	uint32_t rspstatus, mask;
	116	int rsplen, timeout;
bc24a225	117	SDRequest request;
b30bb3a2 AZ	118	uint8_t response[16];
b30bb3a2 AZ	119
827df9f3 AZ	120	if (init && cmd == 0) {
	121	host->status \|= 0x0001;
	122	return;
	123	}
	124
b30bb3a2 AZ	125	if (resptype == sd_r1 && busy)
	126	resptype = sd_r1b;
	127
	128	if (type == sd_adtc) {
	129	host->fifo_start = 0;
	130	host->fifo_len = 0;
	131	host->transfer = 1;
	132	host->ddir = dir;
	133	} else
	134	host->transfer = 0;
	135	timeout = 0;
	136	mask = 0;
	137	rspstatus = 0;
	138
	139	request.cmd = cmd;
	140	request.arg = host->arg;
	141	request.crc = 0; /* FIXME */
	142
	143	rsplen = sd_do_command(host->card, &request, response);
	144
	145	/* TODO: validate CRCs */
	146	switch (resptype) {
	147	case sd_nore:
	148	rsplen = 0;
	149	break;
	150
	151	case sd_r1:
	152	case sd_r1b:
	153	if (rsplen < 4) {
	154	timeout = 1;
	155	break;
	156	}
	157	rsplen = 4;
	158
	159	mask = OUT_OF_RANGE \| ADDRESS_ERROR \| BLOCK_LEN_ERROR \|
	160	ERASE_SEQ_ERROR \| ERASE_PARAM \| WP_VIOLATION \|
	161	LOCK_UNLOCK_FAILED \| COM_CRC_ERROR \| ILLEGAL_COMMAND \|
	162	CARD_ECC_FAILED \| CC_ERROR \| SD_ERROR \|
	163	CID_CSD_OVERWRITE;
	164	if (host->sdio & (1 << 13))
	165	mask \|= AKE_SEQ_ERROR;
	166	rspstatus = (response[0] << 24) \| (response[1] << 16) \|
	167	(response[2] << 8) \| (response[3] << 0);
	168	break;
	169
	170	case sd_r2:
	171	if (rsplen < 16) {
	172	timeout = 1;
	173	break;
	174	}
	175	rsplen = 16;
	176	break;
	177
	178	case sd_r3:
	179	if (rsplen < 4) {
	180	timeout = 1;
	181	break;
	182	}
	183	rsplen = 4;
	184
	185	rspstatus = (response[0] << 24) \| (response[1] << 16) \|
	186	(response[2] << 8) \| (response[3] << 0);
	187	if (rspstatus & 0x80000000)
	188	host->status &= 0xe000;
189	else
190	host->status \|= 0x1000;
191	break;
192
193	case sd_r6:
194	if (rsplen < 4) {
195	timeout = 1;
196	break;
197	}
198	rsplen = 4;
199
200	mask = 0xe000 \| AKE_SEQ_ERROR;
201	rspstatus = (response[2] << 8) \| (response[3] << 0);
202	}
203
204	if (rspstatus & mask)
205	host->status \|= 0x4000;
206	else
207	host->status &= 0xb000;
208
209	if (rsplen)
210	for (rsplen = 0; rsplen < 8; rsplen ++)
211	host->rsp[~rsplen & 7] = response[(rsplen << 1) \| 1] \|
212	(response[(rsplen << 1) \| 0] << 8);
213
214	if (timeout)
215	host->status \|= 0x0080;
216	else if (cmd == 12)
217	host->status \|= 0x0005; /* Makes it more real */
218	else
219	host->status \|= 0x0001;
220	}
221
222	static void omap_mmc_transfer(struct omap_mmc_s *host)
223	{
224	uint8_t value;
225
226	if (!host->transfer)
227	return;
228
229	while (1) {
230	if (host->ddir) {
231	if (host->fifo_len > host->af_level)
232	break;
233
234	value = sd_read_data(host->card);
235	host->fifo[(host->fifo_start + host->fifo_len) & 31] = value;
236	if (-- host->blen_counter) {
237	value = sd_read_data(host->card);
238	host->fifo[(host->fifo_start + host->fifo_len) & 31] \|=
239	value << 8;
240	host->blen_counter --;
241	}
242
243	host->fifo_len ++;
244	} else {
245	if (!host->fifo_len)
246	break;
247
248	value = host->fifo[host->fifo_start] & 0xff;
249	sd_write_data(host->card, value);
250	if (-- host->blen_counter) {
251	value = host->fifo[host->fifo_start] >> 8;
252	sd_write_data(host->card, value);
253	host->blen_counter --;
254	}
255
256	host->fifo_start ++;
257	host->fifo_len --;
258	host->fifo_start &= 31;
259	}
260
261	if (host->blen_counter == 0) {
262	host->nblk_counter --;
263	host->blen_counter = host->blen;
264
265	if (host->nblk_counter == 0) {
266	host->nblk_counter = host->nblk;
267	host->transfer = 0;
268	host->status \|= 0x0008;
269	break;
270	}
271	}
272	}
273	}
274
275	static void omap_mmc_update(void *opaque)
276	{
277	struct omap_mmc_s *s = opaque;
278	omap_mmc_transfer(s);
279	omap_mmc_fifolevel_update(s);
280	omap_mmc_interrupts_update(s);
281	}
282
827df9f3 AZ	283	void omap_mmc_reset(struct omap_mmc_s *host)
	284	{
	285	host->last_cmd = 0;
	286	memset(host->rsp, 0, sizeof(host->rsp));
	287	host->arg = 0;
	288	host->dw = 0;
	289	host->mode = 0;
	290	host->enable = 0;
	291	host->status = 0;
	292	host->mask = 0;
	293	host->cto = 0;
	294	host->dto = 0;
	295	host->fifo_len = 0;
	296	host->blen = 0;
	297	host->blen_counter = 0;
	298	host->nblk = 0;
	299	host->nblk_counter = 0;
	300	host->tx_dma = 0;
	301	host->rx_dma = 0;
	302	host->ae_level = 0x00;
	303	host->af_level = 0x1f;
	304	host->transfer = 0;
	305	host->cdet_wakeup = 0;
	306	host->cdet_enable = 0;
	307	qemu_set_irq(host->coverswitch, host->cdet_state);
	308	host->clkdiv = 0;
ecd219f7 PM	309
	310	/* Since we're still using the legacy SD API the card is not plugged
	311	* into any bus, and we must reset it manually. When omap_mmc is
	312	* QOMified this must move into the QOM reset function.
	313	*/
	314	device_reset(DEVICE(host->card));
827df9f3 AZ	315	}
827df9f3 AZ	316
a8170e5e	317	static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
c304fed7	318	unsigned size)
b30bb3a2 AZ	319	{
	320	uint16_t i;
	321	struct omap_mmc_s s = (struct omap_mmc_s ) opaque;
c304fed7 AK	322
	323	if (size != 2) {
	324	return omap_badwidth_read16(opaque, offset);
	325	}
b30bb3a2 AZ	326
	327	switch (offset) {
	328	case 0x00: /* MMC_CMD */
	329	return s->last_cmd;
	330
	331	case 0x04: /* MMC_ARGL */
	332	return s->arg & 0x0000ffff;
	333
	334	case 0x08: /* MMC_ARGH */
	335	return s->arg >> 16;
	336
	337	case 0x0c: /* MMC_CON */
827df9f3 AZ	338	return (s->dw << 15) \| (s->mode << 12) \| (s->enable << 11) \|
827df9f3 AZ	339	(s->be << 10) \| s->clkdiv;
b30bb3a2 AZ	340
	341	case 0x10: /* MMC_STAT */
	342	return s->status;
	343
	344	case 0x14: /* MMC_IE */
	345	return s->mask;
	346
	347	case 0x18: /* MMC_CTO */
	348	return s->cto;
	349
	350	case 0x1c: /* MMC_DTO */
	351	return s->dto;
	352
	353	case 0x20: /* MMC_DATA */
	354	/* TODO: support 8-bit access */
	355	i = s->fifo[s->fifo_start];
	356	if (s->fifo_len == 0) {
	357	printf("MMC: FIFO underrun\n");
	358	return i;
	359	}
	360	s->fifo_start ++;
	361	s->fifo_len --;
	362	s->fifo_start &= 31;
	363	omap_mmc_transfer(s);
	364	omap_mmc_fifolevel_update(s);
	365	omap_mmc_interrupts_update(s);
	366	return i;
	367
	368	case 0x24: /* MMC_BLEN */
	369	return s->blen_counter;
	370
	371	case 0x28: /* MMC_NBLK */
	372	return s->nblk_counter;
	373
	374	case 0x2c: /* MMC_BUF */
	375	return (s->rx_dma << 15) \| (s->af_level << 8) \|
	376	(s->tx_dma << 7) \| s->ae_level;
	377
	378	case 0x30: /* MMC_SPI */
	379	return 0x0000;
	380	case 0x34: /* MMC_SDIO */
827df9f3	381	return (s->cdet_wakeup << 2) \| (s->cdet_enable) \| s->sdio;
b30bb3a2 AZ	382	case 0x38: /* MMC_SYST */
	383	return 0x0000;
	384
	385	case 0x3c: /* MMC_REV */
827df9f3	386	return s->rev;
b30bb3a2 AZ	387
	388	case 0x40: /* MMC_RSP0 */
	389	case 0x44: /* MMC_RSP1 */
	390	case 0x48: /* MMC_RSP2 */
	391	case 0x4c: /* MMC_RSP3 */
	392	case 0x50: /* MMC_RSP4 */
	393	case 0x54: /* MMC_RSP5 */
	394	case 0x58: /* MMC_RSP6 */
	395	case 0x5c: /* MMC_RSP7 */
	396	return s->rsp[(offset - 0x40) >> 2];
827df9f3 AZ	397
	398	/* OMAP2-specific */
	399	case 0x60: /* MMC_IOSR */
	400	case 0x64: /* MMC_SYSC */
	401	return 0;
	402	case 0x68: /* MMC_SYSS */
	403	return 1; /* RSTD */
b30bb3a2 AZ	404	}
	405
	406	OMAP_BAD_REG(offset);
	407	return 0;
	408	}
	409
a8170e5e	410	static void omap_mmc_write(void *opaque, hwaddr offset,
c304fed7	411	uint64_t value, unsigned size)
b30bb3a2 AZ	412	{
	413	int i;
	414	struct omap_mmc_s s = (struct omap_mmc_s ) opaque;
c304fed7 AK	415
c304fed7 AK	416	if (size != 2) {
77a8257e SW	417	omap_badwidth_write16(opaque, offset, value);
77a8257e SW	418	return;
c304fed7	419	}
b30bb3a2 AZ	420
	421	switch (offset) {
	422	case 0x00: /* MMC_CMD */
	423	if (!s->enable)
	424	break;
	425
	426	s->last_cmd = value;
	427	for (i = 0; i < 8; i ++)
	428	s->rsp[i] = 0x0000;
	429	omap_mmc_command(s, value & 63, (value >> 15) & 1,
c227f099	430	(sd_cmd_type_t) ((value >> 12) & 3),
b30bb3a2	431	(value >> 11) & 1,
c227f099	432	(sd_rsp_type_t) ((value >> 8) & 7),
b30bb3a2 AZ	433	(value >> 7) & 1);
	434	omap_mmc_update(s);
	435	break;
	436
	437	case 0x04: /* MMC_ARGL */
	438	s->arg &= 0xffff0000;
	439	s->arg \|= 0x0000ffff & value;
	440	break;
	441
	442	case 0x08: /* MMC_ARGH */
	443	s->arg &= 0x0000ffff;
	444	s->arg \|= value << 16;
	445	break;
	446
	447	case 0x0c: /* MMC_CON */
	448	s->dw = (value >> 15) & 1;
	449	s->mode = (value >> 12) & 3;
	450	s->enable = (value >> 11) & 1;
827df9f3 AZ	451	s->be = (value >> 10) & 1;
827df9f3 AZ	452	s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff);
25b98b96 PMD	453	if (s->mode != 0) {
	454	qemu_log_mask(LOG_UNIMP,
	455	"omap_mmc_wr: mode #%i unimplemented\n", s->mode);
	456	}
	457	if (s->be != 0) {
	458	qemu_log_mask(LOG_UNIMP,
	459	"omap_mmc_wr: Big Endian not implemented\n");
	460	}
827df9f3	461	if (s->dw != 0 && s->lines < 4)
b30bb3a2	462	printf("4-bit SD bus enabled\n");
827df9f3 AZ	463	if (!s->enable)
827df9f3 AZ	464	omap_mmc_reset(s);
b30bb3a2 AZ	465	break;
	466
	467	case 0x10: /* MMC_STAT */
	468	s->status &= ~value;
	469	omap_mmc_interrupts_update(s);
	470	break;
	471
	472	case 0x14: /* MMC_IE */
827df9f3	473	s->mask = value & 0x7fff;
b30bb3a2 AZ	474	omap_mmc_interrupts_update(s);
	475	break;
	476
	477	case 0x18: /* MMC_CTO */
	478	s->cto = value & 0xff;
827df9f3	479	if (s->cto > 0xfd && s->rev <= 1)
b30bb3a2 AZ	480	printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
	481	break;
	482
	483	case 0x1c: /* MMC_DTO */
	484	s->dto = value & 0xffff;
	485	break;
	486
	487	case 0x20: /* MMC_DATA */
	488	/* TODO: support 8-bit access */
	489	if (s->fifo_len == 32)
	490	break;
	491	s->fifo[(s->fifo_start + s->fifo_len) & 31] = value;
	492	s->fifo_len ++;
	493	omap_mmc_transfer(s);
	494	omap_mmc_fifolevel_update(s);
	495	omap_mmc_interrupts_update(s);
	496	break;
	497
	498	case 0x24: /* MMC_BLEN */
	499	s->blen = (value & 0x07ff) + 1;
	500	s->blen_counter = s->blen;
	501	break;
	502
	503	case 0x28: /* MMC_NBLK */
	504	s->nblk = (value & 0x07ff) + 1;
	505	s->nblk_counter = s->nblk;
	506	s->blen_counter = s->blen;
	507	break;
	508
	509	case 0x2c: /* MMC_BUF */
	510	s->rx_dma = (value >> 15) & 1;
	511	s->af_level = (value >> 8) & 0x1f;
	512	s->tx_dma = (value >> 7) & 1;
	513	s->ae_level = value & 0x1f;
	514
	515	if (s->rx_dma)
	516	s->status &= 0xfbff;
	517	if (s->tx_dma)
	518	s->status &= 0xf7ff;
	519	omap_mmc_fifolevel_update(s);
	520	omap_mmc_interrupts_update(s);
	521	break;
	522
	523	/* SPI, SDIO and TEST modes unimplemented */
827df9f3	524	case 0x30: /* MMC_SPI (OMAP1 only) */
b30bb3a2 AZ	525	break;
b30bb3a2 AZ	526	case 0x34: /* MMC_SDIO */
827df9f3 AZ	527	s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020);
	528	s->cdet_wakeup = (value >> 9) & 1;
	529	s->cdet_enable = (value >> 2) & 1;
b30bb3a2 AZ	530	break;
	531	case 0x38: /* MMC_SYST */
	532	break;
	533
	534	case 0x3c: /* MMC_REV */
	535	case 0x40: /* MMC_RSP0 */
	536	case 0x44: /* MMC_RSP1 */
	537	case 0x48: /* MMC_RSP2 */
	538	case 0x4c: /* MMC_RSP3 */
	539	case 0x50: /* MMC_RSP4 */
	540	case 0x54: /* MMC_RSP5 */
	541	case 0x58: /* MMC_RSP6 */
	542	case 0x5c: /* MMC_RSP7 */
	543	OMAP_RO_REG(offset);
	544	break;
	545
827df9f3 AZ	546	/* OMAP2-specific */
	547	case 0x60: /* MMC_IOSR */
	548	if (value & 0xf)
	549	printf("MMC: SDIO bits used!\n");
	550	break;
	551	case 0x64: /* MMC_SYSC */
	552	if (value & (1 << 2)) /* SRTS */
	553	omap_mmc_reset(s);
	554	break;
	555	case 0x68: /* MMC_SYSS */
	556	OMAP_RO_REG(offset);
	557	break;
	558
b30bb3a2 AZ	559	default:
	560	OMAP_BAD_REG(offset);
	561	}
	562	}
	563
c304fed7 AK	564	static const MemoryRegionOps omap_mmc_ops = {
	565	.read = omap_mmc_read,
	566	.write = omap_mmc_write,
	567	.endianness = DEVICE_NATIVE_ENDIAN,
b30bb3a2 AZ	568	};
b30bb3a2 AZ	569
827df9f3	570	static void omap_mmc_cover_cb(void *opaque, int line, int level)
b30bb3a2	571	{
827df9f3 AZ	572	struct omap_mmc_s host = (struct omap_mmc_s ) opaque;
	573
	574	if (!host->cdet_state && level) {
	575	host->status \|= 0x0002;
	576	omap_mmc_interrupts_update(host);
3ffd710e BS	577	if (host->cdet_wakeup) {
	578	/* TODO: Assert wake-up */
	579	}
827df9f3 AZ	580	}
	581
	582	if (host->cdet_state != level) {
	583	qemu_set_irq(host->coverswitch, level);
	584	host->cdet_state = level;
	585	}
b30bb3a2 AZ	586	}
b30bb3a2 AZ	587
a8170e5e	588	struct omap_mmc_s *omap_mmc_init(hwaddr base,
c304fed7	589	MemoryRegion *sysmem,
4be74634	590	BlockBackend *blk,
b30bb3a2 AZ	591	qemu_irq irq, qemu_irq dma[], omap_clk clk)
b30bb3a2 AZ	592	{
b45c03f5	593	struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);
b30bb3a2 AZ	594
b30bb3a2 AZ	595	s->irq = irq;
b30bb3a2 AZ	596	s->dma = dma;
b30bb3a2 AZ	597	s->clk = clk;
827df9f3 AZ	598	s->lines = 1; /* TODO: needs to be settable per-board */
	599	s->rev = 1;
	600
2c9b15ca	601	memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 0x800);
c304fed7	602	memory_region_add_subregion(sysmem, base, &s->iomem);
b30bb3a2 AZ	603
b30bb3a2 AZ	604	/* Instantiate the storage */
4be74634	605	s->card = sd_init(blk, false);
4f8a066b KW	606	if (s->card == NULL) {
	607	exit(1);
	608	}
b30bb3a2	609
ecd219f7 PM	610	omap_mmc_reset(s);
ecd219f7 PM	611
b30bb3a2 AZ	612	return s;
	613	}
	614
827df9f3	615	struct omap_mmc_s omap2_mmc_init(struct omap_target_agent_s ta,
4be74634	616	BlockBackend *blk, qemu_irq irq, qemu_irq dma[],
827df9f3 AZ	617	omap_clk fclk, omap_clk iclk)
827df9f3 AZ	618	{
b45c03f5	619	struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);
827df9f3 AZ	620
	621	s->irq = irq;
	622	s->dma = dma;
	623	s->clk = fclk;
	624	s->lines = 4;
	625	s->rev = 2;
	626
2c9b15ca	627	memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc",
c304fed7	628	omap_l4_region_size(ta, 0));
f44336c5	629	omap_l4_attach(ta, 0, &s->iomem);
827df9f3 AZ	630
827df9f3 AZ	631	/* Instantiate the storage */
4be74634	632	s->card = sd_init(blk, false);
4f8a066b KW	633	if (s->card == NULL) {
	634	exit(1);
	635	}
827df9f3	636
f3c7d038	637	s->cdet = qemu_allocate_irq(omap_mmc_cover_cb, s, 0);
b9d38e95	638	sd_set_cb(s->card, NULL, s->cdet);
827df9f3	639
ecd219f7 PM	640	omap_mmc_reset(s);
ecd219f7 PM	641
827df9f3 AZ	642	return s;
	643	}
	644
8e129e07 AZ	645	void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover)
8e129e07 AZ	646	{
827df9f3 AZ	647	if (s->cdet) {
	648	sd_set_cb(s->card, ro, s->cdet);
	649	s->coverswitch = cover;
	650	qemu_set_irq(cover, s->cdet_state);
	651	} else
	652	sd_set_cb(s->card, ro, cover);
	653	}
	654
	655	void omap_mmc_enable(struct omap_mmc_s *s, int enable)
	656	{
	657	sd_enable(s->card, enable);
8e129e07	658	}