[qemu.git] / hw / arm / nrf51_soc.c

/*
 * Nordic Semiconductor nRF51 SoC
 * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
 *
 * Copyright 2018 Joel Stanley <[email protected]>
 *
 * This code is licensed under the GPL version 2 or later.  See
 * the COPYING file in the top-level directory.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/arm/boot.h"
#include "hw/sysbus.h"
#include "hw/boards.h"
#include "hw/misc/unimp.h"
#include "exec/address-spaces.h"
#include "sysemu/sysemu.h"
#include "qemu/log.h"
#include "cpu.h"

#include "hw/arm/nrf51.h"
#include "hw/arm/nrf51_soc.h"

/*
 * The size and base is for the NRF51822 part. If other parts
 * are supported in the future, add a sub-class of NRF51SoC for
 * the specific variants
 */
#define NRF51822_FLASH_PAGES    256
#define NRF51822_SRAM_PAGES     16
#define NRF51822_FLASH_SIZE     (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE)
#define NRF51822_SRAM_SIZE      (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE)

#define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)

static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size)
{
    qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
                  __func__, addr, size);
    return 1;
}

static void clock_write(void *opaque, hwaddr addr, uint64_t data,
                        unsigned int size)
{
    qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
                  __func__, addr, data, size);
}

static const MemoryRegionOps clock_ops = {
    .read = clock_read,
    .write = clock_write
};


static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
{
    NRF51State *s = NRF51_SOC(dev_soc);
    MemoryRegion *mr;
    Error *err = NULL;
    uint8_t i = 0;
    hwaddr base_addr = 0;

    if (!s->board_memory) {
        error_setg(errp, "memory property was not set");
        return;
    }

    object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory",
            &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);

    memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size,
                           &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram);

    /* UART */
    object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
    memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
                       qdev_get_gpio_in(DEVICE(&s->cpu),
                       BASE_TO_IRQ(NRF51_UART_BASE)));

    /* RNG */
    object_property_set_bool(OBJECT(&s->rng), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0);
    memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0,
                       qdev_get_gpio_in(DEVICE(&s->cpu),
                       BASE_TO_IRQ(NRF51_RNG_BASE)));

    /* UICR, FICR, NVMC, FLASH */
    object_property_set_uint(OBJECT(&s->nvm), s->flash_size, "flash-size",
                             &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    object_property_set_bool(OBJECT(&s->nvm), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0);
    memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr, 0);
    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1);
    memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr, 0);
    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2);
    memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr, 0);
    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3);
    memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0);

    /* GPIO */
    object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0);
    memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0);

    /* Pass all GPIOs to the SOC layer so they are available to the board */
    qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL);

    /* TIMER */
    for (i = 0; i < NRF51_NUM_TIMERS; i++) {
        object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }

        base_addr = NRF51_TIMER_BASE + i * NRF51_TIMER_SIZE;

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->cpu),
                                            BASE_TO_IRQ(base_addr)));
    }

    /* STUB Peripherals */
    memory_region_init_io(&s->clock, NULL, &clock_ops, NULL,
                          "nrf51_soc.clock", 0x1000);
    memory_region_add_subregion_overlap(&s->container,
                                        NRF51_IOMEM_BASE, &s->clock, -1);

    create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE,
                                NRF51_IOMEM_SIZE);
    create_unimplemented_device("nrf51_soc.private",
                                NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE);
}

static void nrf51_soc_init(Object *obj)
{
    uint8_t i = 0;

    NRF51State *s = NRF51_SOC(obj);

    memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);

    sysbus_init_child_obj(OBJECT(s), "armv6m", OBJECT(&s->cpu), sizeof(s->cpu),
                          TYPE_ARMV7M);
    qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
                         ARM_CPU_TYPE_NAME("cortex-m0"));
    qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);

    sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),
                           TYPE_NRF51_UART);
    object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev",
                              &error_abort);

    sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng),
                           TYPE_NRF51_RNG);

    sysbus_init_child_obj(obj, "nvm", &s->nvm, sizeof(s->nvm), TYPE_NRF51_NVM);

    sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio),
                          TYPE_NRF51_GPIO);

    for (i = 0; i < NRF51_NUM_TIMERS; i++) {
        sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
                              sizeof(s->timer[i]), TYPE_NRF51_TIMER);

    }
}

static Property nrf51_soc_properties[] = {
    DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION,
                     MemoryRegion *),
    DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE),
    DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size,
                       NRF51822_FLASH_SIZE),
    DEFINE_PROP_END_OF_LIST(),
};

static void nrf51_soc_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = nrf51_soc_realize;
    dc->props = nrf51_soc_properties;
}

static const TypeInfo nrf51_soc_info = {
    .name          = TYPE_NRF51_SOC,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(NRF51State),
    .instance_init = nrf51_soc_init,
    .class_init    = nrf51_soc_class_init,
};

static void nrf51_soc_types(void)
{
    type_register_static(&nrf51_soc_info);
}
type_init(nrf51_soc_types)
Commit	Line	Data
673b2d42 JS	1	/*
	2	* Nordic Semiconductor nRF51 SoC
	3	* http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
	4	*
	5	* Copyright 2018 Joel Stanley <[email protected]>
	6	*
	7	* This code is licensed under the GPL version 2 or later. See
	8	* the COPYING file in the top-level directory.
	9	*/
	10
	11	#include "qemu/osdep.h"
	12	#include "qapi/error.h"
12ec8bd5	13	#include "hw/arm/boot.h"
673b2d42 JS	14	#include "hw/sysbus.h"
673b2d42 JS	15	#include "hw/boards.h"
673b2d42 JS	16	#include "hw/misc/unimp.h"
	17	#include "exec/address-spaces.h"
	18	#include "sysemu/sysemu.h"
	19	#include "qemu/log.h"
	20	#include "cpu.h"
	21
659b85e4	22	#include "hw/arm/nrf51.h"
673b2d42 JS	23	#include "hw/arm/nrf51_soc.h"
673b2d42 JS	24
673b2d42 JS	25	/*
	26	* The size and base is for the NRF51822 part. If other parts
	27	* are supported in the future, add a sub-class of NRF51SoC for
	28	* the specific variants
	29	*/
4d744b25 SG	30	#define NRF51822_FLASH_PAGES 256
	31	#define NRF51822_SRAM_PAGES 16
	32	#define NRF51822_FLASH_SIZE (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE)
	33	#define NRF51822_SRAM_SIZE (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE)
673b2d42	34
b0014913 JS	35	#define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)
b0014913 JS	36
b39dced6 SG	37	static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size)
	38	{
	39	qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
	40	__func__, addr, size);
	41	return 1;
	42	}
	43
	44	static void clock_write(void *opaque, hwaddr addr, uint64_t data,
	45	unsigned int size)
	46	{
	47	qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
	48	__func__, addr, data, size);
	49	}
	50
	51	static const MemoryRegionOps clock_ops = {
	52	.read = clock_read,
	53	.write = clock_write
	54	};
	55
	56
673b2d42 JS	57	static void nrf51_soc_realize(DeviceState dev_soc, Error *errp)
	58	{
	59	NRF51State *s = NRF51_SOC(dev_soc);
b0014913	60	MemoryRegion *mr;
673b2d42	61	Error *err = NULL;
60facd90 SG	62	uint8_t i = 0;
60facd90 SG	63	hwaddr base_addr = 0;
673b2d42 JS	64
	65	if (!s->board_memory) {
	66	error_setg(errp, "memory property was not set");
	67	return;
	68	}
	69
	70	object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory",
	71	&err);
	72	if (err) {
	73	error_propagate(errp, err);
	74	return;
	75	}
	76	object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
	77	if (err) {
	78	error_propagate(errp, err);
	79	return;
	80	}
	81
	82	memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
	83
287a7f6e	84	memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size,
287a7f6e	85	&err);
673b2d42 JS	86	if (err) {
	87	error_propagate(errp, err);
	88	return;
	89	}
659b85e4	90	memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram);
673b2d42	91
b0014913 JS	92	/* UART */
	93	object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
	94	if (err) {
	95	error_propagate(errp, err);
	96	return;
	97	}
	98	mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
659b85e4	99	memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0);
b0014913 JS	100	sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
b0014913 JS	101	qdev_get_gpio_in(DEVICE(&s->cpu),
659b85e4	102	BASE_TO_IRQ(NRF51_UART_BASE)));
b0014913	103
f30890de SG	104	/* RNG */
	105	object_property_set_bool(OBJECT(&s->rng), true, "realized", &err);
	106	if (err) {
	107	error_propagate(errp, err);
	108	return;
	109	}
	110
	111	mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0);
	112	memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0);
	113	sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0,
	114	qdev_get_gpio_in(DEVICE(&s->cpu),
	115	BASE_TO_IRQ(NRF51_RNG_BASE)));
	116
4d744b25 SG	117	/* UICR, FICR, NVMC, FLASH */
	118	object_property_set_uint(OBJECT(&s->nvm), s->flash_size, "flash-size",
	119	&err);
	120	if (err) {
	121	error_propagate(errp, err);
	122	return;
	123	}
	124
	125	object_property_set_bool(OBJECT(&s->nvm), true, "realized", &err);
	126	if (err) {
	127	error_propagate(errp, err);
	128	return;
	129	}
	130
	131	mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0);
	132	memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr, 0);
	133	mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1);
	134	memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr, 0);
	135	mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2);
	136	memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr, 0);
	137	mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3);
	138	memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0);
	139
bb42c4cb SG	140	/* GPIO */
	141	object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
	142	if (err) {
	143	error_propagate(errp, err);
	144	return;
	145	}
	146
	147	mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0);
	148	memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0);
	149
	150	/* Pass all GPIOs to the SOC layer so they are available to the board */
	151	qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL);
	152
60facd90 SG	153	/* TIMER */
	154	for (i = 0; i < NRF51_NUM_TIMERS; i++) {
	155	object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
	156	if (err) {
	157	error_propagate(errp, err);
	158	return;
	159	}
	160
	161	base_addr = NRF51_TIMER_BASE + i * NRF51_TIMER_SIZE;
	162
	163	sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);
	164	sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,
	165	qdev_get_gpio_in(DEVICE(&s->cpu),
	166	BASE_TO_IRQ(base_addr)));
	167	}
	168
b39dced6 SG	169	/* STUB Peripherals */
	170	memory_region_init_io(&s->clock, NULL, &clock_ops, NULL,
	171	"nrf51_soc.clock", 0x1000);
	172	memory_region_add_subregion_overlap(&s->container,
	173	NRF51_IOMEM_BASE, &s->clock, -1);
	174
659b85e4 SG	175	create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE,
659b85e4 SG	176	NRF51_IOMEM_SIZE);
673b2d42	177	create_unimplemented_device("nrf51_soc.private",
659b85e4	178	NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE);
673b2d42 JS	179	}
	180
	181	static void nrf51_soc_init(Object *obj)
	182	{
60facd90 SG	183	uint8_t i = 0;
60facd90 SG	184
673b2d42 JS	185	NRF51State *s = NRF51_SOC(obj);
	186
	187	memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
	188
	189	sysbus_init_child_obj(OBJECT(s), "armv6m", OBJECT(&s->cpu), sizeof(s->cpu),
	190	TYPE_ARMV7M);
	191	qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
	192	ARM_CPU_TYPE_NAME("cortex-m0"));
	193	qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
b0014913 JS	194
	195	sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),
	196	TYPE_NRF51_UART);
	197	object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev",
	198	&error_abort);
f30890de SG	199
	200	sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng),
	201	TYPE_NRF51_RNG);
bb42c4cb	202
4d744b25 SG	203	sysbus_init_child_obj(obj, "nvm", &s->nvm, sizeof(s->nvm), TYPE_NRF51_NVM);
4d744b25 SG	204
bb42c4cb SG	205	sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio),
bb42c4cb SG	206	TYPE_NRF51_GPIO);
60facd90 SG	207
	208	for (i = 0; i < NRF51_NUM_TIMERS; i++) {
	209	sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
	210	sizeof(s->timer[i]), TYPE_NRF51_TIMER);
	211
	212	}
673b2d42 JS	213	}
	214
	215	static Property nrf51_soc_properties[] = {
	216	DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION,
	217	MemoryRegion *),
	218	DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE),
	219	DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size,
	220	NRF51822_FLASH_SIZE),
	221	DEFINE_PROP_END_OF_LIST(),
	222	};
	223
	224	static void nrf51_soc_class_init(ObjectClass klass, void data)
	225	{
	226	DeviceClass *dc = DEVICE_CLASS(klass);
	227
	228	dc->realize = nrf51_soc_realize;
	229	dc->props = nrf51_soc_properties;
	230	}
	231
	232	static const TypeInfo nrf51_soc_info = {
	233	.name = TYPE_NRF51_SOC,
	234	.parent = TYPE_SYS_BUS_DEVICE,
	235	.instance_size = sizeof(NRF51State),
	236	.instance_init = nrf51_soc_init,
	237	.class_init = nrf51_soc_class_init,
	238	};
	239
	240	static void nrf51_soc_types(void)
	241	{
	242	type_register_static(&nrf51_soc_info);
	243	}
	244	type_init(nrf51_soc_types)