]> Git Repo - qemu.git/blame - hw/microblaze/petalogix_s3adsp1800_mmu.c
xlnx-zynqmp: Add support for high DDR memory regions
[qemu.git] / hw / microblaze / petalogix_s3adsp1800_mmu.c
CommitLineData
6a8b1ae2
EI
1/*
2 * Model of Petalogix linux reference design targeting Xilinx Spartan 3ADSP-1800
3 * boards.
4 *
5 * Copyright (c) 2009 Edgar E. Iglesias.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
83c9f4ca
PB
26#include "hw/sysbus.h"
27#include "hw/hw.h"
1422e32d 28#include "net/net.h"
0d09e41a 29#include "hw/block/flash.h"
9c17d615 30#include "sysemu/sysemu.h"
bd2be150 31#include "hw/devices.h"
83c9f4ca 32#include "hw/boards.h"
fa1d36df 33#include "sysemu/block-backend.h"
022c62cb 34#include "exec/address-spaces.h"
6a8b1ae2 35
47b43a1f 36#include "boot.h"
b861b741 37
6a8b1ae2
EI
38#define LMB_BRAM_SIZE (128 * 1024)
39#define FLASH_SIZE (16 * 1024 * 1024)
40
6a8b1ae2 41#define BINARY_DEVICE_TREE_FILE "petalogix-s3adsp1800.dtb"
409dbce5 42
cba1fd36
PC
43#define MEMORY_BASEADDR 0x90000000
44#define FLASH_BASEADDR 0xa0000000
45#define INTC_BASEADDR 0x81800000
46#define TIMER_BASEADDR 0x83c00000
47#define UARTLITE_BASEADDR 0x84000000
48#define ETHLITE_BASEADDR 0x81000000
49
05a738c4
PC
50#define TIMER_IRQ 0
51#define ETHLITE_IRQ 1
52#define UARTLITE_IRQ 3
53
6a8b1ae2 54static void
3ef96221 55petalogix_s3adsp1800_init(MachineState *machine)
6a8b1ae2 56{
3ef96221 57 ram_addr_t ram_size = machine->ram_size;
6a8b1ae2 58 DeviceState *dev;
3ed60733 59 MicroBlazeCPU *cpu;
751c6a17 60 DriveInfo *dinfo;
6a8b1ae2 61 int i;
a8170e5e 62 hwaddr ddr_base = MEMORY_BASEADDR;
589f0aad
AK
63 MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
64 MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
73c69456 65 qemu_irq irq[32];
589f0aad 66 MemoryRegion *sysmem = get_system_memory();
6a8b1ae2 67
d87636b1 68 cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
ad24f947 69 object_property_set_str(OBJECT(cpu), "7.10.d", "version", &error_abort);
d87636b1 70 object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
6a8b1ae2 71
6a8b1ae2 72 /* Attach emulated BRAM through the LMB. */
2c9b15ca 73 memory_region_init_ram(phys_lmb_bram, NULL,
49946538 74 "petalogix_s3adsp1800.lmb_bram", LMB_BRAM_SIZE,
f8ed85ac 75 &error_fatal);
c5705a77 76 vmstate_register_ram_global(phys_lmb_bram);
589f0aad 77 memory_region_add_subregion(sysmem, 0x00000000, phys_lmb_bram);
6a8b1ae2 78
49946538 79 memory_region_init_ram(phys_ram, NULL, "petalogix_s3adsp1800.ram",
f8ed85ac 80 ram_size, &error_fatal);
c5705a77 81 vmstate_register_ram_global(phys_ram);
589f0aad 82 memory_region_add_subregion(sysmem, ddr_base, phys_ram);
6a8b1ae2 83
751c6a17 84 dinfo = drive_get(IF_PFLASH, 0, 0);
cba1fd36 85 pflash_cfi01_register(FLASH_BASEADDR,
cfe5f011 86 NULL, "petalogix_s3adsp1800.flash", FLASH_SIZE,
4be74634 87 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
fa1d36df 88 (64 * 1024), FLASH_SIZE >> 16,
01e0451a 89 1, 0x89, 0x18, 0x0000, 0x0, 1);
6a8b1ae2 90
13c9bfbf
PC
91 dev = qdev_create(NULL, "xlnx.xps-intc");
92 qdev_prop_set_uint32(dev, "kind-of-intr",
93 1 << ETHLITE_IRQ | 1 << UARTLITE_IRQ);
94 qdev_init_nofail(dev);
95 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
96 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
97 qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ));
6a8b1ae2
EI
98 for (i = 0; i < 32; i++) {
99 irq[i] = qdev_get_gpio_in(dev, i);
100 }
101
05a738c4
PC
102 sysbus_create_simple("xlnx.xps-uartlite", UARTLITE_BASEADDR,
103 irq[UARTLITE_IRQ]);
29873712 104
6a8b1ae2 105 /* 2 timers at irq 2 @ 62 Mhz. */
29873712
PC
106 dev = qdev_create(NULL, "xlnx.xps-timer");
107 qdev_prop_set_uint32(dev, "one-timer-only", 0);
108 qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
109 qdev_init_nofail(dev);
110 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
111 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
112
b8d4e1c4
PC
113 qemu_check_nic_model(&nd_table[0], "xlnx.xps-ethernetlite");
114 dev = qdev_create(NULL, "xlnx.xps-ethernetlite");
115 qdev_set_nic_properties(dev, &nd_table[0]);
116 qdev_prop_set_uint32(dev, "tx-ping-pong", 0);
117 qdev_prop_set_uint32(dev, "rx-ping-pong", 0);
118 qdev_init_nofail(dev);
119 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR);
120 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]);
6a8b1ae2 121
bf494367 122 microblaze_load_kernel(cpu, ddr_base, ram_size,
3ef96221 123 machine->initrd_filename,
ec426ff8 124 BINARY_DEVICE_TREE_FILE,
033af8e9 125 NULL);
6a8b1ae2
EI
126}
127
e264d29d 128static void petalogix_s3adsp1800_machine_init(MachineClass *mc)
6a8b1ae2 129{
e264d29d
EH
130 mc->desc = "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800";
131 mc->init = petalogix_s3adsp1800_init;
132 mc->is_default = 1;
6a8b1ae2
EI
133}
134
e264d29d 135DEFINE_MACHINE("petalogix-s3adsp1800", petalogix_s3adsp1800_machine_init)
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