[qemu.git] / hw / arm / xilinx_zynq.c

/*
 * Xilinx Zynq Baseboard System emulation.
 *
 * Copyright (c) 2010 Xilinx.
 * Copyright (c) 2012 Peter A.G. Crosthwaite ([email protected])
 * Copyright (c) 2012 Petalogix Pty Ltd.
 * Written by Haibing Ma
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "hw/sysbus.h"
#include "hw/arm/arm.h"
#include "net/net.h"
#include "exec/address-spaces.h"
#include "sysemu/sysemu.h"
#include "hw/boards.h"
#include "hw/block/flash.h"
#include "sysemu/block-backend.h"
#include "hw/loader.h"
#include "hw/misc/zynq-xadc.h"
#include "hw/ssi.h"
#include "qemu/error-report.h"

#define NUM_SPI_FLASHES 4
#define NUM_QSPI_FLASHES 2
#define NUM_QSPI_BUSSES 2

#define FLASH_SIZE (64 * 1024 * 1024)
#define FLASH_SECTOR_SIZE (128 * 1024)

#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */

#define MPCORE_PERIPHBASE 0xF8F00000
#define ZYNQ_BOARD_MIDR 0x413FC090

static const int dma_irqs[8] = {
    46, 47, 48, 49, 72, 73, 74, 75
};

#define BOARD_SETUP_ADDR        0x100

#define SLCR_LOCK_OFFSET        0x004
#define SLCR_UNLOCK_OFFSET      0x008
#define SLCR_ARM_PLL_OFFSET     0x100

#define SLCR_XILINX_UNLOCK_KEY  0xdf0d
#define SLCR_XILINX_LOCK_KEY    0x767b

#define ARMV7_IMM16(x) (extract32((x),  0, 12) | \
                        extract32((x), 12,  4) << 16)

/* Write immediate val to address r0 + addr. r0 should contain base offset
 * of the SLCR block. Clobbers r1.
 */

#define SLCR_WRITE(addr, val) \
    0xe3001000 + ARMV7_IMM16(extract32((val),  0, 16)), /* movw r1 ... */ \
    0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
    0xe5801000 + (addr)

static void zynq_write_board_setup(ARMCPU *cpu,
                                   const struct arm_boot_info *info)
{
    int n;
    uint32_t board_setup_blob[] = {
        0xe3a004f8, /* mov r0, #0xf8000000 */
        SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY),
        SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008),
        SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY),
        0xe12fff1e, /* bx lr */
    };
    for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
        board_setup_blob[n] = tswap32(board_setup_blob[n]);
    }
    rom_add_blob_fixed("board-setup", board_setup_blob,
                       sizeof(board_setup_blob), BOARD_SETUP_ADDR);
}

static struct arm_boot_info zynq_binfo = {};

static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
{
    DeviceState *dev;
    SysBusDevice *s;

    dev = qdev_create(NULL, "cadence_gem");
    if (nd->used) {
        qemu_check_nic_model(nd, "cadence_gem");
        qdev_set_nic_properties(dev, nd);
    }
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(s, 0, base);
    sysbus_connect_irq(s, 0, irq);
}

static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
                                         bool is_qspi)
{
    DeviceState *dev;
    SysBusDevice *busdev;
    SSIBus *spi;
    DeviceState *flash_dev;
    int i, j;
    int num_busses =  is_qspi ? NUM_QSPI_BUSSES : 1;
    int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;

    dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
    qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
    qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
    qdev_prop_set_uint8(dev, "num-busses", num_busses);
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, base_addr);
    if (is_qspi) {
        sysbus_mmio_map(busdev, 1, 0xFC000000);
    }
    sysbus_connect_irq(busdev, 0, irq);

    for (i = 0; i < num_busses; ++i) {
        char bus_name[16];
        qemu_irq cs_line;

        snprintf(bus_name, 16, "spi%d", i);
        spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);

        for (j = 0; j < num_ss; ++j) {
            flash_dev = ssi_create_slave(spi, "n25q128");

            cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
            sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
        }
    }

}

static void zynq_init(MachineState *machine)
{
    ram_addr_t ram_size = machine->ram_size;
    const char *cpu_model = machine->cpu_model;
    const char *kernel_filename = machine->kernel_filename;
    const char *kernel_cmdline = machine->kernel_cmdline;
    const char *initrd_filename = machine->initrd_filename;
    ObjectClass *cpu_oc;
    ARMCPU *cpu;
    MemoryRegion *address_space_mem = get_system_memory();
    MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
    MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
    DeviceState *dev;
    SysBusDevice *busdev;
    qemu_irq pic[64];
    int n;

    if (!cpu_model) {
        cpu_model = "cortex-a9";
    }
    cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);

    cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc)));

    /* By default A9 CPUs have EL3 enabled.  This board does not
     * currently support EL3 so the CPU EL3 property is disabled before
     * realization.
     */
    if (object_property_find(OBJECT(cpu), "has_el3", NULL)) {
        object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal);
    }

    object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr",
                            &error_fatal);
    object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
                            &error_fatal);
    object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal);

    /* max 2GB ram */
    if (ram_size > 0x80000000) {
        ram_size = 0x80000000;
    }

    /* DDR remapped to address zero.  */
    memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram",
                                         ram_size);
    memory_region_add_subregion(address_space_mem, 0, ext_ram);

    /* 256K of on-chip memory */
    memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10,
                           &error_fatal);
    vmstate_register_ram_global(ocm_ram);
    memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);

    DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);

    /* AMD */
    pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE,
                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                          FLASH_SECTOR_SIZE,
                          FLASH_SIZE/FLASH_SECTOR_SIZE, 1,
                          1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
                              0);

    dev = qdev_create(NULL, "xilinx,zynq_slcr");
    qdev_init_nofail(dev);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);

    dev = qdev_create(NULL, "a9mpcore_priv");
    qdev_prop_set_uint32(dev, "num-cpu", 1);
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
    sysbus_connect_irq(busdev, 0,
                       qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));

    for (n = 0; n < 64; n++) {
        pic[n] = qdev_get_gpio_in(dev, n);
    }

    zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);
    zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
    zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);

    sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]);
    sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]);

    sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]);
    sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);

    sysbus_create_varargs("cadence_ttc", 0xF8001000,
            pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
    sysbus_create_varargs("cadence_ttc", 0xF8002000,
            pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);

    gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
    gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);

    dev = qdev_create(NULL, "generic-sdhci");
    qdev_init_nofail(dev);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0100000);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[56-IRQ_OFFSET]);

    dev = qdev_create(NULL, "generic-sdhci");
    qdev_init_nofail(dev);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]);

    dev = qdev_create(NULL, TYPE_ZYNQ_XADC);
    qdev_init_nofail(dev);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);

    dev = qdev_create(NULL, "pl330");
    qdev_prop_set_uint8(dev, "num_chnls",  8);
    qdev_prop_set_uint8(dev, "num_periph_req",  4);
    qdev_prop_set_uint8(dev, "num_events",  16);

    qdev_prop_set_uint8(dev, "data_width",  64);
    qdev_prop_set_uint8(dev, "wr_cap",  8);
    qdev_prop_set_uint8(dev, "wr_q_dep",  16);
    qdev_prop_set_uint8(dev, "rd_cap",  8);
    qdev_prop_set_uint8(dev, "rd_q_dep",  16);
    qdev_prop_set_uint16(dev, "data_buffer_dep",  256);

    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, 0xF8003000);
    sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
    for (n = 0; n < 8; ++n) { /* event irqs */
        sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
    }

    zynq_binfo.ram_size = ram_size;
    zynq_binfo.kernel_filename = kernel_filename;
    zynq_binfo.kernel_cmdline = kernel_cmdline;
    zynq_binfo.initrd_filename = initrd_filename;
    zynq_binfo.nb_cpus = 1;
    zynq_binfo.board_id = 0xd32;
    zynq_binfo.loader_start = 0;
    zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
    zynq_binfo.write_board_setup = zynq_write_board_setup;

    arm_load_kernel(ARM_CPU(first_cpu), &zynq_binfo);
}

static void zynq_machine_init(MachineClass *mc)
{
    mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
    mc->init = zynq_init;
    mc->block_default_type = IF_SCSI;
    mc->max_cpus = 1;
    mc->no_sdcard = 1;
}

DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)
Commit	Line	Data
e3260506 PC	1	/*
	2	* Xilinx Zynq Baseboard System emulation.
	3	*
	4	* Copyright (c) 2010 Xilinx.
	5	* Copyright (c) 2012 Peter A.G. Crosthwaite ([email protected])
	6	* Copyright (c) 2012 Petalogix Pty Ltd.
	7	* Written by Haibing Ma
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version
	12	* 2 of the License, or (at your option) any later version.
	13	*
	14	* You should have received a copy of the GNU General Public License along
	15	* with this program; if not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
83c9f4ca	18	#include "hw/sysbus.h"
bd2be150	19	#include "hw/arm/arm.h"
1422e32d	20	#include "net/net.h"
022c62cb	21	#include "exec/address-spaces.h"
9c17d615	22	#include "sysemu/sysemu.h"
83c9f4ca	23	#include "hw/boards.h"
0d09e41a	24	#include "hw/block/flash.h"
fa1d36df	25	#include "sysemu/block-backend.h"
83c9f4ca	26	#include "hw/loader.h"
74fcbd22	27	#include "hw/misc/zynq-xadc.h"
83c9f4ca	28	#include "hw/ssi.h"
d8bbdcf8	29	#include "qemu/error-report.h"
559d489f PC	30
559d489f PC	31	#define NUM_SPI_FLASHES 4
7b482bcf PC	32	#define NUM_QSPI_FLASHES 2
7b482bcf PC	33	#define NUM_QSPI_BUSSES 2
e3260506 PC	34
	35	#define FLASH_SIZE (64 * 1024 * 1024)
	36	#define FLASH_SECTOR_SIZE (128 * 1024)
	37
	38	#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
	39
c2577128	40	#define MPCORE_PERIPHBASE 0xF8F00000
b48adc0d	41	#define ZYNQ_BOARD_MIDR 0x413FC090
c2577128	42
7451afb6 PC	43	static const int dma_irqs[8] = {
	44	46, 47, 48, 49, 72, 73, 74, 75
	45	};
	46
c3a9a689 PC	47	#define BOARD_SETUP_ADDR 0x100
	48
	49	#define SLCR_LOCK_OFFSET 0x004
	50	#define SLCR_UNLOCK_OFFSET 0x008
	51	#define SLCR_ARM_PLL_OFFSET 0x100
	52
	53	#define SLCR_XILINX_UNLOCK_KEY 0xdf0d
	54	#define SLCR_XILINX_LOCK_KEY 0x767b
	55
	56	#define ARMV7_IMM16(x) (extract32((x), 0, 12) \| \
	57	extract32((x), 12, 4) << 16)
	58
	59	/* Write immediate val to address r0 + addr. r0 should contain base offset
	60	* of the SLCR block. Clobbers r1.
	61	*/
	62
	63	#define SLCR_WRITE(addr, val) \
	64	0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \
	65	0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
	66	0xe5801000 + (addr)
	67
	68	static void zynq_write_board_setup(ARMCPU *cpu,
	69	const struct arm_boot_info *info)
	70	{
	71	int n;
	72	uint32_t board_setup_blob[] = {
	73	0xe3a004f8, /* mov r0, #0xf8000000 */
	74	SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY),
	75	SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008),
	76	SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY),
	77	0xe12fff1e, /* bx lr */
	78	};
	79	for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
	80	board_setup_blob[n] = tswap32(board_setup_blob[n]);
	81	}
	82	rom_add_blob_fixed("board-setup", board_setup_blob,
	83	sizeof(board_setup_blob), BOARD_SETUP_ADDR);
	84	}
	85
e3260506 PC	86	static struct arm_boot_info zynq_binfo = {};
	87
	88	static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
	89	{
	90	DeviceState *dev;
	91	SysBusDevice *s;
	92
e3260506	93	dev = qdev_create(NULL, "cadence_gem");
7fcd57e8 PC	94	if (nd->used) {
	95	qemu_check_nic_model(nd, "cadence_gem");
	96	qdev_set_nic_properties(dev, nd);
	97	}
e3260506	98	qdev_init_nofail(dev);
1356b98d	99	s = SYS_BUS_DEVICE(dev);
e3260506 PC	100	sysbus_mmio_map(s, 0, base);
	101	sysbus_connect_irq(s, 0, irq);
	102	}
	103
7b482bcf PC	104	static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
7b482bcf PC	105	bool is_qspi)
559d489f PC	106	{
	107	DeviceState *dev;
	108	SysBusDevice *busdev;
	109	SSIBus *spi;
79f5d67e	110	DeviceState *flash_dev;
7b482bcf PC	111	int i, j;
	112	int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1;
	113	int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
559d489f	114
6b91f015	115	dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
7b482bcf PC	116	qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
	117	qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
	118	qdev_prop_set_uint8(dev, "num-busses", num_busses);
559d489f	119	qdev_init_nofail(dev);
1356b98d	120	busdev = SYS_BUS_DEVICE(dev);
559d489f	121	sysbus_mmio_map(busdev, 0, base_addr);
7b482bcf PC	122	if (is_qspi) {
	123	sysbus_mmio_map(busdev, 1, 0xFC000000);
	124	}
559d489f PC	125	sysbus_connect_irq(busdev, 0, irq);
559d489f PC	126
7b482bcf PC	127	for (i = 0; i < num_busses; ++i) {
7b482bcf PC	128	char bus_name[16];
559d489f PC	129	qemu_irq cs_line;
559d489f PC	130
7b482bcf PC	131	snprintf(bus_name, 16, "spi%d", i);
	132	spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);
	133
	134	for (j = 0; j < num_ss; ++j) {
f1922e36	135	flash_dev = ssi_create_slave(spi, "n25q128");
559d489f	136
de77914e	137	cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
7b482bcf PC	138	sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
7b482bcf PC	139	}
559d489f PC	140	}
	141
	142	}
	143
3ef96221	144	static void zynq_init(MachineState *machine)
e3260506	145	{
3ef96221 MA	146	ram_addr_t ram_size = machine->ram_size;
	147	const char *cpu_model = machine->cpu_model;
	148	const char *kernel_filename = machine->kernel_filename;
	149	const char *kernel_cmdline = machine->kernel_cmdline;
	150	const char *initrd_filename = machine->initrd_filename;
d8bbdcf8	151	ObjectClass *cpu_oc;
17c2f0bf	152	ARMCPU *cpu;
e3260506 PC	153	MemoryRegion *address_space_mem = get_system_memory();
	154	MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
	155	MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
	156	DeviceState *dev;
	157	SysBusDevice *busdev;
e3260506	158	qemu_irq pic[64];
e3260506	159	int n;
e3260506 PC	160
	161	if (!cpu_model) {
	162	cpu_model = "cortex-a9";
	163	}
d8bbdcf8	164	cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
e3260506	165
d8bbdcf8 PC	166	cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc)));
d8bbdcf8 PC	167
61e2f352 GB	168	/* By default A9 CPUs have EL3 enabled. This board does not
	169	* currently support EL3 so the CPU EL3 property is disabled before
	170	* realization.
	171	*/
	172	if (object_property_find(OBJECT(cpu), "has_el3", NULL)) {
007b0657	173	object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal);
b48adc0d AF	174	}
b48adc0d AF	175
007b0657 MA	176	object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr",
	177	&error_fatal);
	178	object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
	179	&error_fatal);
	180	object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal);
e3260506 PC	181
	182	/* max 2GB ram */
	183	if (ram_size > 0x80000000) {
	184	ram_size = 0x80000000;
	185	}
	186
	187	/* DDR remapped to address zero. */
c8623c02 DM	188	memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram",
c8623c02 DM	189	ram_size);
e3260506 PC	190	memory_region_add_subregion(address_space_mem, 0, ext_ram);
	191
	192	/* 256K of on-chip memory */
49946538	193	memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10,
f8ed85ac	194	&error_fatal);
e3260506 PC	195	vmstate_register_ram_global(ocm_ram);
	196	memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
	197
	198	DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
	199
	200	/* AMD */
	201	pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE,
4be74634	202	dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
fa1d36df	203	FLASH_SECTOR_SIZE,
e3260506 PC	204	FLASH_SIZE/FLASH_SECTOR_SIZE, 1,
	205	1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
	206	0);
	207
	208	dev = qdev_create(NULL, "xilinx,zynq_slcr");
	209	qdev_init_nofail(dev);
1356b98d	210	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);
e3260506 PC	211
	212	dev = qdev_create(NULL, "a9mpcore_priv");
	213	qdev_prop_set_uint32(dev, "num-cpu", 1);
	214	qdev_init_nofail(dev);
1356b98d	215	busdev = SYS_BUS_DEVICE(dev);
c2577128	216	sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
e4a6540d PM	217	sysbus_connect_irq(busdev, 0,
e4a6540d PM	218	qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
e3260506 PC	219
	220	for (n = 0; n < 64; n++) {
	221	pic[n] = qdev_get_gpio_in(dev, n);
	222	}
	223
7b482bcf PC	224	zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);
	225	zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
	226	zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);
559d489f	227
892776ce	228	sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]);
70ef6a5b	229	sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]);
892776ce	230
e3260506 PC	231	sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]);
	232	sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);
	233
	234	sysbus_create_varargs("cadence_ttc", 0xF8001000,
	235	pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
	236	sysbus_create_varargs("cadence_ttc", 0xF8002000,
	237	pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
	238
7fcd57e8 PC	239	gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
7fcd57e8 PC	240	gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);
e3260506	241
b972b4e2 PC	242	dev = qdev_create(NULL, "generic-sdhci");
	243	qdev_init_nofail(dev);
	244	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0100000);
	245	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[56-IRQ_OFFSET]);
	246
	247	dev = qdev_create(NULL, "generic-sdhci");
	248	qdev_init_nofail(dev);
	249	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000);
	250	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]);
	251
74fcbd22 GR	252	dev = qdev_create(NULL, TYPE_ZYNQ_XADC);
	253	qdev_init_nofail(dev);
	254	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
	255	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
	256
7451afb6 PC	257	dev = qdev_create(NULL, "pl330");
	258	qdev_prop_set_uint8(dev, "num_chnls", 8);
	259	qdev_prop_set_uint8(dev, "num_periph_req", 4);
	260	qdev_prop_set_uint8(dev, "num_events", 16);
	261
	262	qdev_prop_set_uint8(dev, "data_width", 64);
	263	qdev_prop_set_uint8(dev, "wr_cap", 8);
	264	qdev_prop_set_uint8(dev, "wr_q_dep", 16);
	265	qdev_prop_set_uint8(dev, "rd_cap", 8);
	266	qdev_prop_set_uint8(dev, "rd_q_dep", 16);
	267	qdev_prop_set_uint16(dev, "data_buffer_dep", 256);
	268
	269	qdev_init_nofail(dev);
	270	busdev = SYS_BUS_DEVICE(dev);
	271	sysbus_mmio_map(busdev, 0, 0xF8003000);
	272	sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
	273	for (n = 0; n < 8; ++n) { /* event irqs */
	274	sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
	275	}
	276
e3260506 PC	277	zynq_binfo.ram_size = ram_size;
	278	zynq_binfo.kernel_filename = kernel_filename;
	279	zynq_binfo.kernel_cmdline = kernel_cmdline;
	280	zynq_binfo.initrd_filename = initrd_filename;
	281	zynq_binfo.nb_cpus = 1;
	282	zynq_binfo.board_id = 0xd32;
	283	zynq_binfo.loader_start = 0;
c3a9a689 PC	284	zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
	285	zynq_binfo.write_board_setup = zynq_write_board_setup;
	286
182735ef	287	arm_load_kernel(ARM_CPU(first_cpu), &zynq_binfo);
e3260506 PC	288	}
e3260506 PC	289
e264d29d	290	static void zynq_machine_init(MachineClass *mc)
e3260506	291	{
e264d29d EH	292	mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
	293	mc->init = zynq_init;
	294	mc->block_default_type = IF_SCSI;
	295	mc->max_cpus = 1;
	296	mc->no_sdcard = 1;
e3260506 PC	297	}
e3260506 PC	298
e264d29d	299	DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)