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fixed 16 bit segment optimisations
[qemu.git] / target-i386 / translate.c
CommitLineData
2c0262af
FB		 1/*
2 * i386 translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25#include <signal.h>
26#include <assert.h>
2c0262af
FB		 27
28#include "cpu.h"
29#include "exec-all.h"
30#include "disas.h"
31
32/* XXX: move that elsewhere */
33static uint16_t *gen_opc_ptr;
34static uint32_t *gen_opparam_ptr;
35
36#define PREFIX_REPZ 0x01
37#define PREFIX_REPNZ 0x02
38#define PREFIX_LOCK 0x04
39#define PREFIX_DATA 0x08
40#define PREFIX_ADR 0x10
41
42typedef struct DisasContext {
43 /* current insn context */
44 int override; /* -1 if no override */
45 int prefix;
46 int aflag, dflag;
47 uint8_t *pc; /* pc = eip + cs_base */
48 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
49 static state change (stop translation) */
50 /* current block context */
51 uint8_t *cs_base; /* base of CS segment */
52 int pe; /* protected mode */
53 int code32; /* 32 bit code segment */
54 int ss32; /* 32 bit stack segment */
55 int cc_op; /* current CC operation */
56 int addseg; /* non zero if either DS/ES/SS have a non zero base */
57 int f_st; /* currently unused */
58 int vm86; /* vm86 mode */
59 int cpl;
60 int iopl;
61 int tf; /* TF cpu flag */
34865134 62 int singlestep_enabled; /* "hardware" single step enabled */
2c0262af
FB		 63 int jmp_opt; /* use direct block chaining for direct jumps */
64 int mem_index; /* select memory access functions */
7eee2a50 65 int flags; /* all execution flags */
2c0262af
FB		 66 struct TranslationBlock *tb;
67 int popl_esp_hack; /* for correct popl with esp base handling */
68} DisasContext;
69
70static void gen_eob(DisasContext *s);
71static void gen_jmp(DisasContext *s, unsigned int eip);
72
73/* i386 arith/logic operations */
74enum {
75 OP_ADDL,
76 OP_ORL,
77 OP_ADCL,
78 OP_SBBL,
79 OP_ANDL,
80 OP_SUBL,
81 OP_XORL,
82 OP_CMPL,
83};
84
85/* i386 shift ops */
86enum {
87 OP_ROL,
88 OP_ROR,
89 OP_RCL,
90 OP_RCR,
91 OP_SHL,
92 OP_SHR,
93 OP_SHL1, /* undocumented */
94 OP_SAR = 7,
95};
96
97enum {
98#define DEF(s, n, copy_size) INDEX_op_ ## s,
99#include "opc.h"
100#undef DEF
101 NB_OPS,
102};
103
104#include "gen-op.h"
105
106/* operand size */
107enum {
108 OT_BYTE = 0,
109 OT_WORD,
110 OT_LONG,
111 OT_QUAD,
112};
113
114enum {
115 /* I386 int registers */
116 OR_EAX, /* MUST be even numbered */
117 OR_ECX,
118 OR_EDX,
119 OR_EBX,
120 OR_ESP,
121 OR_EBP,
122 OR_ESI,
123 OR_EDI,
124 OR_TMP0, /* temporary operand register */
125 OR_TMP1,
126 OR_A0, /* temporary register used when doing address evaluation */
127 OR_ZERO, /* fixed zero register */
128 NB_OREGS,
129};
130
2c0262af
FB		 131static GenOpFunc *gen_op_mov_reg_T0[3][8] = {
132 [OT_BYTE] = {
133 gen_op_movb_EAX_T0,
134 gen_op_movb_ECX_T0,
135 gen_op_movb_EDX_T0,
136 gen_op_movb_EBX_T0,
137 gen_op_movh_EAX_T0,
138 gen_op_movh_ECX_T0,
139 gen_op_movh_EDX_T0,
140 gen_op_movh_EBX_T0,
141 },
142 [OT_WORD] = {
143 gen_op_movw_EAX_T0,
144 gen_op_movw_ECX_T0,
145 gen_op_movw_EDX_T0,
146 gen_op_movw_EBX_T0,
147 gen_op_movw_ESP_T0,
148 gen_op_movw_EBP_T0,
149 gen_op_movw_ESI_T0,
150 gen_op_movw_EDI_T0,
151 },
152 [OT_LONG] = {
153 gen_op_movl_EAX_T0,
154 gen_op_movl_ECX_T0,
155 gen_op_movl_EDX_T0,
156 gen_op_movl_EBX_T0,
157 gen_op_movl_ESP_T0,
158 gen_op_movl_EBP_T0,
159 gen_op_movl_ESI_T0,
160 gen_op_movl_EDI_T0,
161 },
162};
163
164static GenOpFunc *gen_op_mov_reg_T1[3][8] = {
165 [OT_BYTE] = {
166 gen_op_movb_EAX_T1,
167 gen_op_movb_ECX_T1,
168 gen_op_movb_EDX_T1,
169 gen_op_movb_EBX_T1,
170 gen_op_movh_EAX_T1,
171 gen_op_movh_ECX_T1,
172 gen_op_movh_EDX_T1,
173 gen_op_movh_EBX_T1,
174 },
175 [OT_WORD] = {
176 gen_op_movw_EAX_T1,
177 gen_op_movw_ECX_T1,
178 gen_op_movw_EDX_T1,
179 gen_op_movw_EBX_T1,
180 gen_op_movw_ESP_T1,
181 gen_op_movw_EBP_T1,
182 gen_op_movw_ESI_T1,
183 gen_op_movw_EDI_T1,
184 },
185 [OT_LONG] = {
186 gen_op_movl_EAX_T1,
187 gen_op_movl_ECX_T1,
188 gen_op_movl_EDX_T1,
189 gen_op_movl_EBX_T1,
190 gen_op_movl_ESP_T1,
191 gen_op_movl_EBP_T1,
192 gen_op_movl_ESI_T1,
193 gen_op_movl_EDI_T1,
194 },
195};
196
197static GenOpFunc *gen_op_mov_reg_A0[2][8] = {
198 [0] = {
199 gen_op_movw_EAX_A0,
200 gen_op_movw_ECX_A0,
201 gen_op_movw_EDX_A0,
202 gen_op_movw_EBX_A0,
203 gen_op_movw_ESP_A0,
204 gen_op_movw_EBP_A0,
205 gen_op_movw_ESI_A0,
206 gen_op_movw_EDI_A0,
207 },
208 [1] = {
209 gen_op_movl_EAX_A0,
210 gen_op_movl_ECX_A0,
211 gen_op_movl_EDX_A0,
212 gen_op_movl_EBX_A0,
213 gen_op_movl_ESP_A0,
214 gen_op_movl_EBP_A0,
215 gen_op_movl_ESI_A0,
216 gen_op_movl_EDI_A0,
217 },
218};
219
220static GenOpFunc *gen_op_mov_TN_reg[3][2][8] =
221{
222 [OT_BYTE] = {
223 {
224 gen_op_movl_T0_EAX,
225 gen_op_movl_T0_ECX,
226 gen_op_movl_T0_EDX,
227 gen_op_movl_T0_EBX,
228 gen_op_movh_T0_EAX,
229 gen_op_movh_T0_ECX,
230 gen_op_movh_T0_EDX,
231 gen_op_movh_T0_EBX,
232 },
233 {
234 gen_op_movl_T1_EAX,
235 gen_op_movl_T1_ECX,
236 gen_op_movl_T1_EDX,
237 gen_op_movl_T1_EBX,
238 gen_op_movh_T1_EAX,
239 gen_op_movh_T1_ECX,
240 gen_op_movh_T1_EDX,
241 gen_op_movh_T1_EBX,
242 },
243 },
244 [OT_WORD] = {
245 {
246 gen_op_movl_T0_EAX,
247 gen_op_movl_T0_ECX,
248 gen_op_movl_T0_EDX,
249 gen_op_movl_T0_EBX,
250 gen_op_movl_T0_ESP,
251 gen_op_movl_T0_EBP,
252 gen_op_movl_T0_ESI,
253 gen_op_movl_T0_EDI,
254 },
255 {
256 gen_op_movl_T1_EAX,
257 gen_op_movl_T1_ECX,
258 gen_op_movl_T1_EDX,
259 gen_op_movl_T1_EBX,
260 gen_op_movl_T1_ESP,
261 gen_op_movl_T1_EBP,
262 gen_op_movl_T1_ESI,
263 gen_op_movl_T1_EDI,
264 },
265 },
266 [OT_LONG] = {
267 {
268 gen_op_movl_T0_EAX,
269 gen_op_movl_T0_ECX,
270 gen_op_movl_T0_EDX,
271 gen_op_movl_T0_EBX,
272 gen_op_movl_T0_ESP,
273 gen_op_movl_T0_EBP,
274 gen_op_movl_T0_ESI,
275 gen_op_movl_T0_EDI,
276 },
277 {
278 gen_op_movl_T1_EAX,
279 gen_op_movl_T1_ECX,
280 gen_op_movl_T1_EDX,
281 gen_op_movl_T1_EBX,
282 gen_op_movl_T1_ESP,
283 gen_op_movl_T1_EBP,
284 gen_op_movl_T1_ESI,
285 gen_op_movl_T1_EDI,
286 },
287 },
288};
289
290static GenOpFunc *gen_op_movl_A0_reg[8] = {
291 gen_op_movl_A0_EAX,
292 gen_op_movl_A0_ECX,
293 gen_op_movl_A0_EDX,
294 gen_op_movl_A0_EBX,
295 gen_op_movl_A0_ESP,
296 gen_op_movl_A0_EBP,
297 gen_op_movl_A0_ESI,
298 gen_op_movl_A0_EDI,
299};
300
301static GenOpFunc *gen_op_addl_A0_reg_sN[4][8] = {
302 [0] = {
303 gen_op_addl_A0_EAX,
304 gen_op_addl_A0_ECX,
305 gen_op_addl_A0_EDX,
306 gen_op_addl_A0_EBX,
307 gen_op_addl_A0_ESP,
308 gen_op_addl_A0_EBP,
309 gen_op_addl_A0_ESI,
310 gen_op_addl_A0_EDI,
311 },
312 [1] = {
313 gen_op_addl_A0_EAX_s1,
314 gen_op_addl_A0_ECX_s1,
315 gen_op_addl_A0_EDX_s1,
316 gen_op_addl_A0_EBX_s1,
317 gen_op_addl_A0_ESP_s1,
318 gen_op_addl_A0_EBP_s1,
319 gen_op_addl_A0_ESI_s1,
320 gen_op_addl_A0_EDI_s1,
321 },
322 [2] = {
323 gen_op_addl_A0_EAX_s2,
324 gen_op_addl_A0_ECX_s2,
325 gen_op_addl_A0_EDX_s2,
326 gen_op_addl_A0_EBX_s2,
327 gen_op_addl_A0_ESP_s2,
328 gen_op_addl_A0_EBP_s2,
329 gen_op_addl_A0_ESI_s2,
330 gen_op_addl_A0_EDI_s2,
331 },
332 [3] = {
333 gen_op_addl_A0_EAX_s3,
334 gen_op_addl_A0_ECX_s3,
335 gen_op_addl_A0_EDX_s3,
336 gen_op_addl_A0_EBX_s3,
337 gen_op_addl_A0_ESP_s3,
338 gen_op_addl_A0_EBP_s3,
339 gen_op_addl_A0_ESI_s3,
340 gen_op_addl_A0_EDI_s3,
341 },
342};
343
344static GenOpFunc *gen_op_cmov_reg_T1_T0[2][8] = {
345 [0] = {
346 gen_op_cmovw_EAX_T1_T0,
347 gen_op_cmovw_ECX_T1_T0,
348 gen_op_cmovw_EDX_T1_T0,
349 gen_op_cmovw_EBX_T1_T0,
350 gen_op_cmovw_ESP_T1_T0,
351 gen_op_cmovw_EBP_T1_T0,
352 gen_op_cmovw_ESI_T1_T0,
353 gen_op_cmovw_EDI_T1_T0,
354 },
355 [1] = {
356 gen_op_cmovl_EAX_T1_T0,
357 gen_op_cmovl_ECX_T1_T0,
358 gen_op_cmovl_EDX_T1_T0,
359 gen_op_cmovl_EBX_T1_T0,
360 gen_op_cmovl_ESP_T1_T0,
361 gen_op_cmovl_EBP_T1_T0,
362 gen_op_cmovl_ESI_T1_T0,
363 gen_op_cmovl_EDI_T1_T0,
364 },
365};
366
367static GenOpFunc *gen_op_arith_T0_T1_cc[8] = {
368 NULL,
369 gen_op_orl_T0_T1,
370 NULL,
371 NULL,
372 gen_op_andl_T0_T1,
373 NULL,
374 gen_op_xorl_T0_T1,
375 NULL,
376};
377
4f31916f
FB		 378#define DEF_ARITHC(SUFFIX)\
379 {\
380 gen_op_adcb ## SUFFIX ## _T0_T1_cc,\
381 gen_op_sbbb ## SUFFIX ## _T0_T1_cc,\
382 },\
383 {\
384 gen_op_adcw ## SUFFIX ## _T0_T1_cc,\
385 gen_op_sbbw ## SUFFIX ## _T0_T1_cc,\
386 },\
387 {\
388 gen_op_adcl ## SUFFIX ## _T0_T1_cc,\
389 gen_op_sbbl ## SUFFIX ## _T0_T1_cc,\
2c0262af 390 },
4f31916f
FB		 391
392static GenOpFunc *gen_op_arithc_T0_T1_cc[3][2] = {
4bb2fcc7 393 DEF_ARITHC( )
2c0262af
FB		 394};
395
4f31916f
FB		 396static GenOpFunc *gen_op_arithc_mem_T0_T1_cc[9][2] = {
397 DEF_ARITHC(_raw)
398#ifndef CONFIG_USER_ONLY
399 DEF_ARITHC(_kernel)
400 DEF_ARITHC(_user)
401#endif
2c0262af
FB		 402};
403
404static const int cc_op_arithb[8] = {
405 CC_OP_ADDB,
406 CC_OP_LOGICB,
407 CC_OP_ADDB,
408 CC_OP_SUBB,
409 CC_OP_LOGICB,
410 CC_OP_SUBB,
411 CC_OP_LOGICB,
412 CC_OP_SUBB,
413};
414
4f31916f
FB		 415#define DEF_CMPXCHG(SUFFIX)\
416 gen_op_cmpxchgb ## SUFFIX ## _T0_T1_EAX_cc,\
417 gen_op_cmpxchgw ## SUFFIX ## _T0_T1_EAX_cc,\
418 gen_op_cmpxchgl ## SUFFIX ## _T0_T1_EAX_cc,
419
420
2c0262af 421static GenOpFunc *gen_op_cmpxchg_T0_T1_EAX_cc[3] = {
4bb2fcc7 422 DEF_CMPXCHG( )
2c0262af
FB		 423};
424
4f31916f
FB		 425static GenOpFunc *gen_op_cmpxchg_mem_T0_T1_EAX_cc[9] = {
426 DEF_CMPXCHG(_raw)
427#ifndef CONFIG_USER_ONLY
428 DEF_CMPXCHG(_kernel)
429 DEF_CMPXCHG(_user)
430#endif
2c0262af
FB		 431};
432
4f31916f
FB		 433#define DEF_SHIFT(SUFFIX)\
434 {\
435 gen_op_rolb ## SUFFIX ## _T0_T1_cc,\
436 gen_op_rorb ## SUFFIX ## _T0_T1_cc,\
437 gen_op_rclb ## SUFFIX ## _T0_T1_cc,\
438 gen_op_rcrb ## SUFFIX ## _T0_T1_cc,\
439 gen_op_shlb ## SUFFIX ## _T0_T1_cc,\
440 gen_op_shrb ## SUFFIX ## _T0_T1_cc,\
441 gen_op_shlb ## SUFFIX ## _T0_T1_cc,\
442 gen_op_sarb ## SUFFIX ## _T0_T1_cc,\
443 },\
444 {\
445 gen_op_rolw ## SUFFIX ## _T0_T1_cc,\
446 gen_op_rorw ## SUFFIX ## _T0_T1_cc,\
447 gen_op_rclw ## SUFFIX ## _T0_T1_cc,\
448 gen_op_rcrw ## SUFFIX ## _T0_T1_cc,\
449 gen_op_shlw ## SUFFIX ## _T0_T1_cc,\
450 gen_op_shrw ## SUFFIX ## _T0_T1_cc,\
451 gen_op_shlw ## SUFFIX ## _T0_T1_cc,\
452 gen_op_sarw ## SUFFIX ## _T0_T1_cc,\
453 },\
454 {\
455 gen_op_roll ## SUFFIX ## _T0_T1_cc,\
456 gen_op_rorl ## SUFFIX ## _T0_T1_cc,\
457 gen_op_rcll ## SUFFIX ## _T0_T1_cc,\
458 gen_op_rcrl ## SUFFIX ## _T0_T1_cc,\
459 gen_op_shll ## SUFFIX ## _T0_T1_cc,\
460 gen_op_shrl ## SUFFIX ## _T0_T1_cc,\
461 gen_op_shll ## SUFFIX ## _T0_T1_cc,\
462 gen_op_sarl ## SUFFIX ## _T0_T1_cc,\
2c0262af 463 },
4f31916f
FB		 464
465static GenOpFunc *gen_op_shift_T0_T1_cc[3][8] = {
4bb2fcc7 466 DEF_SHIFT( )
2c0262af
FB		 467};
468
4f31916f
FB		 469static GenOpFunc *gen_op_shift_mem_T0_T1_cc[9][8] = {
470 DEF_SHIFT(_raw)
471#ifndef CONFIG_USER_ONLY
472 DEF_SHIFT(_kernel)
473 DEF_SHIFT(_user)
474#endif
2c0262af
FB		 475};
476
4f31916f
FB		 477#define DEF_SHIFTD(SUFFIX, op)\
478 {\
479 NULL,\
480 NULL,\
481 },\
482 {\
483 gen_op_shldw ## SUFFIX ## _T0_T1_ ## op ## _cc,\
484 gen_op_shrdw ## SUFFIX ## _T0_T1_ ## op ## _cc,\
485 },\
486 {\
487 gen_op_shldl ## SUFFIX ## _T0_T1_ ## op ## _cc,\
488 gen_op_shrdl ## SUFFIX ## _T0_T1_ ## op ## _cc,\
2c0262af 489 },
4f31916f
FB		 490
491
492static GenOpFunc1 *gen_op_shiftd_T0_T1_im_cc[3][2] = {
493 DEF_SHIFTD(, im)
2c0262af
FB		 494};
495
4f31916f
FB		 496static GenOpFunc *gen_op_shiftd_T0_T1_ECX_cc[3][2] = {
497 DEF_SHIFTD(, ECX)
2c0262af
FB		 498};
499
4f31916f
FB		 500static GenOpFunc1 *gen_op_shiftd_mem_T0_T1_im_cc[9][2] = {
501 DEF_SHIFTD(_raw, im)
502#ifndef CONFIG_USER_ONLY
503 DEF_SHIFTD(_kernel, im)
504 DEF_SHIFTD(_user, im)
505#endif
2c0262af
FB		 506};
507
4f31916f
FB		 508static GenOpFunc *gen_op_shiftd_mem_T0_T1_ECX_cc[9][2] = {
509 DEF_SHIFTD(_raw, ECX)
510#ifndef CONFIG_USER_ONLY
511 DEF_SHIFTD(_kernel, ECX)
512 DEF_SHIFTD(_user, ECX)
513#endif
2c0262af
FB		 514};
515
516static GenOpFunc *gen_op_btx_T0_T1_cc[2][4] = {
517 [0] = {
518 gen_op_btw_T0_T1_cc,
519 gen_op_btsw_T0_T1_cc,
520 gen_op_btrw_T0_T1_cc,
521 gen_op_btcw_T0_T1_cc,
522 },
523 [1] = {
524 gen_op_btl_T0_T1_cc,
525 gen_op_btsl_T0_T1_cc,
526 gen_op_btrl_T0_T1_cc,
527 gen_op_btcl_T0_T1_cc,
528 },
529};
530
531static GenOpFunc *gen_op_bsx_T0_cc[2][2] = {
532 [0] = {
533 gen_op_bsfw_T0_cc,
534 gen_op_bsrw_T0_cc,
535 },
536 [1] = {
537 gen_op_bsfl_T0_cc,
538 gen_op_bsrl_T0_cc,
539 },
540};
541
542static GenOpFunc *gen_op_lds_T0_A0[3 * 3] = {
61382a50
FB		 543 gen_op_ldsb_raw_T0_A0,
544 gen_op_ldsw_raw_T0_A0,
2c0262af 545 NULL,
61382a50 546#ifndef CONFIG_USER_ONLY
2c0262af
FB		 547 gen_op_ldsb_kernel_T0_A0,
548 gen_op_ldsw_kernel_T0_A0,
549 NULL,
550
551 gen_op_ldsb_user_T0_A0,
552 gen_op_ldsw_user_T0_A0,
553 NULL,
61382a50 554#endif
2c0262af
FB		 555};
556
557static GenOpFunc *gen_op_ldu_T0_A0[3 * 3] = {
61382a50
FB		 558 gen_op_ldub_raw_T0_A0,
559 gen_op_lduw_raw_T0_A0,
2c0262af
FB		 560 NULL,
561
61382a50 562#ifndef CONFIG_USER_ONLY
2c0262af
FB		 563 gen_op_ldub_kernel_T0_A0,
564 gen_op_lduw_kernel_T0_A0,
565 NULL,
566
567 gen_op_ldub_user_T0_A0,
568 gen_op_lduw_user_T0_A0,
569 NULL,
61382a50 570#endif
2c0262af
FB		 571};
572
573/* sign does not matter, except for lidt/lgdt call (TODO: fix it) */
574static GenOpFunc *gen_op_ld_T0_A0[3 * 3] = {
61382a50
FB		 575 gen_op_ldub_raw_T0_A0,
576 gen_op_lduw_raw_T0_A0,
577 gen_op_ldl_raw_T0_A0,
2c0262af 578
61382a50 579#ifndef CONFIG_USER_ONLY
2c0262af
FB		 580 gen_op_ldub_kernel_T0_A0,
581 gen_op_lduw_kernel_T0_A0,
582 gen_op_ldl_kernel_T0_A0,
583
584 gen_op_ldub_user_T0_A0,
585 gen_op_lduw_user_T0_A0,
586 gen_op_ldl_user_T0_A0,
61382a50 587#endif
2c0262af
FB		 588};
589
590static GenOpFunc *gen_op_ld_T1_A0[3 * 3] = {
61382a50
FB		 591 gen_op_ldub_raw_T1_A0,
592 gen_op_lduw_raw_T1_A0,
593 gen_op_ldl_raw_T1_A0,
2c0262af 594
61382a50 595#ifndef CONFIG_USER_ONLY
2c0262af
FB		 596 gen_op_ldub_kernel_T1_A0,
597 gen_op_lduw_kernel_T1_A0,
598 gen_op_ldl_kernel_T1_A0,
599
600 gen_op_ldub_user_T1_A0,
601 gen_op_lduw_user_T1_A0,
602 gen_op_ldl_user_T1_A0,
61382a50 603#endif
2c0262af
FB		 604};
605
606static GenOpFunc *gen_op_st_T0_A0[3 * 3] = {
61382a50
FB		 607 gen_op_stb_raw_T0_A0,
608 gen_op_stw_raw_T0_A0,
609 gen_op_stl_raw_T0_A0,
2c0262af 610
61382a50 611#ifndef CONFIG_USER_ONLY
2c0262af
FB		 612 gen_op_stb_kernel_T0_A0,
613 gen_op_stw_kernel_T0_A0,
614 gen_op_stl_kernel_T0_A0,
615
616 gen_op_stb_user_T0_A0,
617 gen_op_stw_user_T0_A0,
618 gen_op_stl_user_T0_A0,
61382a50 619#endif
2c0262af
FB		 620};
621
4f31916f
FB		 622static GenOpFunc *gen_op_st_T1_A0[3 * 3] = {
623 NULL,
624 gen_op_stw_raw_T1_A0,
625 gen_op_stl_raw_T1_A0,
626
627#ifndef CONFIG_USER_ONLY
628 NULL,
629 gen_op_stw_kernel_T1_A0,
630 gen_op_stl_kernel_T1_A0,
631
632 NULL,
633 gen_op_stw_user_T1_A0,
634 gen_op_stl_user_T1_A0,
635#endif
636};
637
2c0262af
FB		 638static inline void gen_string_movl_A0_ESI(DisasContext *s)
639{
640 int override;
641
642 override = s->override;
643 if (s->aflag) {
644 /* 32 bit address */
645 if (s->addseg && override < 0)
646 override = R_DS;
647 if (override >= 0) {
648 gen_op_movl_A0_seg(offsetof(CPUX86State,segs[override].base));
649 gen_op_addl_A0_reg_sN[0][R_ESI]();
650 } else {
651 gen_op_movl_A0_reg[R_ESI]();
652 }
653 } else {
654 /* 16 address, always override */
655 if (override < 0)
656 override = R_DS;
657 gen_op_movl_A0_reg[R_ESI]();
658 gen_op_andl_A0_ffff();
659 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
660 }
661}
662
663static inline void gen_string_movl_A0_EDI(DisasContext *s)
664{
665 if (s->aflag) {
666 if (s->addseg) {
667 gen_op_movl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
668 gen_op_addl_A0_reg_sN[0][R_EDI]();
669 } else {
670 gen_op_movl_A0_reg[R_EDI]();
671 }
672 } else {
673 gen_op_movl_A0_reg[R_EDI]();
674 gen_op_andl_A0_ffff();
675 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
676 }
677}
678
679static GenOpFunc *gen_op_movl_T0_Dshift[3] = {
680 gen_op_movl_T0_Dshiftb,
681 gen_op_movl_T0_Dshiftw,
682 gen_op_movl_T0_Dshiftl,
683};
684
685static GenOpFunc2 *gen_op_jz_ecx[2] = {
686 gen_op_jz_ecxw,
687 gen_op_jz_ecxl,
688};
689
690static GenOpFunc1 *gen_op_jz_ecx_im[2] = {
691 gen_op_jz_ecxw_im,
692 gen_op_jz_ecxl_im,
693};
694
695static GenOpFunc *gen_op_dec_ECX[2] = {
696 gen_op_decw_ECX,
697 gen_op_decl_ECX,
698};
699
7399c5a9
FB		 700#ifdef USE_DIRECT_JUMP
701typedef GenOpFunc GenOpFuncTB2;
702#define gen_op_string_jnz_sub(nz, ot, tb) gen_op_string_jnz_sub2[nz][ot]()
703#else
704typedef GenOpFunc1 GenOpFuncTB2;
705#define gen_op_string_jnz_sub(nz, ot, tb) gen_op_string_jnz_sub2[nz][ot](tb)
706#endif
707
708static GenOpFuncTB2 *gen_op_string_jnz_sub2[2][3] = {
2c0262af
FB		 709 {
710 gen_op_string_jnz_subb,
711 gen_op_string_jnz_subw,
712 gen_op_string_jnz_subl,
713 },
714 {
715 gen_op_string_jz_subb,
716 gen_op_string_jz_subw,
717 gen_op_string_jz_subl,
718 },
719};
720
721static GenOpFunc1 *gen_op_string_jnz_sub_im[2][3] = {
722 {
723 gen_op_string_jnz_subb_im,
724 gen_op_string_jnz_subw_im,
725 gen_op_string_jnz_subl_im,
726 },
727 {
728 gen_op_string_jz_subb_im,
729 gen_op_string_jz_subw_im,
730 gen_op_string_jz_subl_im,
731 },
732};
733
734static GenOpFunc *gen_op_in_DX_T0[3] = {
735 gen_op_inb_DX_T0,
736 gen_op_inw_DX_T0,
737 gen_op_inl_DX_T0,
738};
739
740static GenOpFunc *gen_op_out_DX_T0[3] = {
741 gen_op_outb_DX_T0,
742 gen_op_outw_DX_T0,
743 gen_op_outl_DX_T0,
744};
745
f115e911
FB		 746static GenOpFunc *gen_op_in[3] = {
747 gen_op_inb_T0_T1,
748 gen_op_inw_T0_T1,
749 gen_op_inl_T0_T1,
750};
751
752static GenOpFunc *gen_op_out[3] = {
753 gen_op_outb_T0_T1,
754 gen_op_outw_T0_T1,
755 gen_op_outl_T0_T1,
756};
757
758static GenOpFunc *gen_check_io_T0[3] = {
759 gen_op_check_iob_T0,
760 gen_op_check_iow_T0,
761 gen_op_check_iol_T0,
762};
763
764static GenOpFunc *gen_check_io_DX[3] = {
765 gen_op_check_iob_DX,
766 gen_op_check_iow_DX,
767 gen_op_check_iol_DX,
768};
769
770static void gen_check_io(DisasContext *s, int ot, int use_dx, int cur_eip)
771{
772 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
773 if (s->cc_op != CC_OP_DYNAMIC)
774 gen_op_set_cc_op(s->cc_op);
775 gen_op_jmp_im(cur_eip);
776 if (use_dx)
777 gen_check_io_DX[ot]();
778 else
779 gen_check_io_T0[ot]();
780 }
781}
782
2c0262af
FB		 783static inline void gen_movs(DisasContext *s, int ot)
784{
785 gen_string_movl_A0_ESI(s);
786 gen_op_ld_T0_A0[ot + s->mem_index]();
787 gen_string_movl_A0_EDI(s);
788 gen_op_st_T0_A0[ot + s->mem_index]();
789 gen_op_movl_T0_Dshift[ot]();
790 if (s->aflag) {
791 gen_op_addl_ESI_T0();
792 gen_op_addl_EDI_T0();
793 } else {
794 gen_op_addw_ESI_T0();
795 gen_op_addw_EDI_T0();
796 }
797}
798
799static inline void gen_update_cc_op(DisasContext *s)
800{
801 if (s->cc_op != CC_OP_DYNAMIC) {
802 gen_op_set_cc_op(s->cc_op);
803 s->cc_op = CC_OP_DYNAMIC;
804 }
805}
806
807static inline void gen_jz_ecx_string(DisasContext *s, unsigned int next_eip)
808{
809 if (s->jmp_opt) {
810 gen_op_jz_ecx[s->aflag]((long)s->tb, next_eip);
811 } else {
812 /* XXX: does not work with gdbstub "ice" single step - not a
813 serious problem */
814 gen_op_jz_ecx_im[s->aflag](next_eip);
815 }
816}
817
818static inline void gen_stos(DisasContext *s, int ot)
819{
820 gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
821 gen_string_movl_A0_EDI(s);
822 gen_op_st_T0_A0[ot + s->mem_index]();
823 gen_op_movl_T0_Dshift[ot]();
824 if (s->aflag) {
825 gen_op_addl_EDI_T0();
826 } else {
827 gen_op_addw_EDI_T0();
828 }
829}
830
831static inline void gen_lods(DisasContext *s, int ot)
832{
833 gen_string_movl_A0_ESI(s);
834 gen_op_ld_T0_A0[ot + s->mem_index]();
835 gen_op_mov_reg_T0[ot][R_EAX]();
836 gen_op_movl_T0_Dshift[ot]();
837 if (s->aflag) {
838 gen_op_addl_ESI_T0();
839 } else {
840 gen_op_addw_ESI_T0();
841 }
842}
843
844static inline void gen_scas(DisasContext *s, int ot)
845{
846 gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
847 gen_string_movl_A0_EDI(s);
848 gen_op_ld_T1_A0[ot + s->mem_index]();
849 gen_op_cmpl_T0_T1_cc();
850 gen_op_movl_T0_Dshift[ot]();
851 if (s->aflag) {
852 gen_op_addl_EDI_T0();
853 } else {
854 gen_op_addw_EDI_T0();
855 }
856}
857
858static inline void gen_cmps(DisasContext *s, int ot)
859{
860 gen_string_movl_A0_ESI(s);
861 gen_op_ld_T0_A0[ot + s->mem_index]();
862 gen_string_movl_A0_EDI(s);
863 gen_op_ld_T1_A0[ot + s->mem_index]();
864 gen_op_cmpl_T0_T1_cc();
865 gen_op_movl_T0_Dshift[ot]();
866 if (s->aflag) {
867 gen_op_addl_ESI_T0();
868 gen_op_addl_EDI_T0();
869 } else {
870 gen_op_addw_ESI_T0();
871 gen_op_addw_EDI_T0();
872 }
873}
874
875static inline void gen_ins(DisasContext *s, int ot)
876{
877 gen_op_in_DX_T0[ot]();
878 gen_string_movl_A0_EDI(s);
879 gen_op_st_T0_A0[ot + s->mem_index]();
880 gen_op_movl_T0_Dshift[ot]();
881 if (s->aflag) {
882 gen_op_addl_EDI_T0();
883 } else {
884 gen_op_addw_EDI_T0();
885 }
886}
887
888static inline void gen_outs(DisasContext *s, int ot)
889{
890 gen_string_movl_A0_ESI(s);
891 gen_op_ld_T0_A0[ot + s->mem_index]();
892 gen_op_out_DX_T0[ot]();
893 gen_op_movl_T0_Dshift[ot]();
894 if (s->aflag) {
895 gen_op_addl_ESI_T0();
896 } else {
897 gen_op_addw_ESI_T0();
898 }
899}
900
901/* same method as Valgrind : we generate jumps to current or next
902 instruction */
903#define GEN_REPZ(op) \
904static inline void gen_repz_ ## op(DisasContext *s, int ot, \
905 unsigned int cur_eip, unsigned int next_eip) \
906{ \
907 gen_update_cc_op(s); \
908 gen_jz_ecx_string(s, next_eip); \
909 gen_ ## op(s, ot); \
910 gen_op_dec_ECX[s->aflag](); \
911 /* a loop would cause two single step exceptions if ECX = 1 \
912 before rep string_insn */ \
913 if (!s->jmp_opt) \
914 gen_op_jz_ecx_im[s->aflag](next_eip); \
915 gen_jmp(s, cur_eip); \
916}
917
918#define GEN_REPZ2(op) \
919static inline void gen_repz_ ## op(DisasContext *s, int ot, \
920 unsigned int cur_eip, \
921 unsigned int next_eip, \
922 int nz) \
923{ \
924 gen_update_cc_op(s); \
925 gen_jz_ecx_string(s, next_eip); \
926 gen_ ## op(s, ot); \
927 gen_op_dec_ECX[s->aflag](); \
928 gen_op_set_cc_op(CC_OP_SUBB + ot); \
929 if (!s->jmp_opt) \
930 gen_op_string_jnz_sub_im[nz][ot](next_eip); \
931 else \
7399c5a9 932 gen_op_string_jnz_sub(nz, ot, (long)s->tb); \
2c0262af
FB		 933 if (!s->jmp_opt) \
934 gen_op_jz_ecx_im[s->aflag](next_eip); \
935 gen_jmp(s, cur_eip); \
936}
937
938GEN_REPZ(movs)
939GEN_REPZ(stos)
940GEN_REPZ(lods)
941GEN_REPZ(ins)
942GEN_REPZ(outs)
943GEN_REPZ2(scas)
944GEN_REPZ2(cmps)
945
2c0262af
FB		 946enum {
947 JCC_O,
948 JCC_B,
949 JCC_Z,
950 JCC_BE,
951 JCC_S,
952 JCC_P,
953 JCC_L,
954 JCC_LE,
955};
956
957static GenOpFunc3 *gen_jcc_sub[3][8] = {
958 [OT_BYTE] = {
959 NULL,
960 gen_op_jb_subb,
961 gen_op_jz_subb,
962 gen_op_jbe_subb,
963 gen_op_js_subb,
964 NULL,
965 gen_op_jl_subb,
966 gen_op_jle_subb,
967 },
968 [OT_WORD] = {
969 NULL,
970 gen_op_jb_subw,
971 gen_op_jz_subw,
972 gen_op_jbe_subw,
973 gen_op_js_subw,
974 NULL,
975 gen_op_jl_subw,
976 gen_op_jle_subw,
977 },
978 [OT_LONG] = {
979 NULL,
980 gen_op_jb_subl,
981 gen_op_jz_subl,
982 gen_op_jbe_subl,
983 gen_op_js_subl,
984 NULL,
985 gen_op_jl_subl,
986 gen_op_jle_subl,
987 },
988};
989static GenOpFunc2 *gen_op_loop[2][4] = {
990 [0] = {
991 gen_op_loopnzw,
992 gen_op_loopzw,
993 gen_op_loopw,
994 gen_op_jecxzw,
995 },
996 [1] = {
997 gen_op_loopnzl,
998 gen_op_loopzl,
999 gen_op_loopl,
1000 gen_op_jecxzl,
1001 },
1002};
1003
1004static GenOpFunc *gen_setcc_slow[8] = {
1005 gen_op_seto_T0_cc,
1006 gen_op_setb_T0_cc,
1007 gen_op_setz_T0_cc,
1008 gen_op_setbe_T0_cc,
1009 gen_op_sets_T0_cc,
1010 gen_op_setp_T0_cc,
1011 gen_op_setl_T0_cc,
1012 gen_op_setle_T0_cc,
1013};
1014
1015static GenOpFunc *gen_setcc_sub[3][8] = {
1016 [OT_BYTE] = {
1017 NULL,
1018 gen_op_setb_T0_subb,
1019 gen_op_setz_T0_subb,
1020 gen_op_setbe_T0_subb,
1021 gen_op_sets_T0_subb,
1022 NULL,
1023 gen_op_setl_T0_subb,
1024 gen_op_setle_T0_subb,
1025 },
1026 [OT_WORD] = {
1027 NULL,
1028 gen_op_setb_T0_subw,
1029 gen_op_setz_T0_subw,
1030 gen_op_setbe_T0_subw,
1031 gen_op_sets_T0_subw,
1032 NULL,
1033 gen_op_setl_T0_subw,
1034 gen_op_setle_T0_subw,
1035 },
1036 [OT_LONG] = {
1037 NULL,
1038 gen_op_setb_T0_subl,
1039 gen_op_setz_T0_subl,
1040 gen_op_setbe_T0_subl,
1041 gen_op_sets_T0_subl,
1042 NULL,
1043 gen_op_setl_T0_subl,
1044 gen_op_setle_T0_subl,
1045 },
1046};
1047
1048static GenOpFunc *gen_op_fp_arith_ST0_FT0[8] = {
1049 gen_op_fadd_ST0_FT0,
1050 gen_op_fmul_ST0_FT0,
1051 gen_op_fcom_ST0_FT0,
1052 gen_op_fcom_ST0_FT0,
1053 gen_op_fsub_ST0_FT0,
1054 gen_op_fsubr_ST0_FT0,
1055 gen_op_fdiv_ST0_FT0,
1056 gen_op_fdivr_ST0_FT0,
1057};
1058
1059/* NOTE the exception in "r" op ordering */
1060static GenOpFunc1 *gen_op_fp_arith_STN_ST0[8] = {
1061 gen_op_fadd_STN_ST0,
1062 gen_op_fmul_STN_ST0,
1063 NULL,
1064 NULL,
1065 gen_op_fsubr_STN_ST0,
1066 gen_op_fsub_STN_ST0,
1067 gen_op_fdivr_STN_ST0,
1068 gen_op_fdiv_STN_ST0,
1069};
1070
1071/* if d == OR_TMP0, it means memory operand (address in A0) */
1072static void gen_op(DisasContext *s1, int op, int ot, int d)
1073{
1074 GenOpFunc *gen_update_cc;
1075
1076 if (d != OR_TMP0) {
1077 gen_op_mov_TN_reg[ot][0][d]();
1078 } else {
1079 gen_op_ld_T0_A0[ot + s1->mem_index]();
1080 }
1081 switch(op) {
1082 case OP_ADCL:
1083 case OP_SBBL:
1084 if (s1->cc_op != CC_OP_DYNAMIC)
1085 gen_op_set_cc_op(s1->cc_op);
1086 if (d != OR_TMP0) {
1087 gen_op_arithc_T0_T1_cc[ot][op - OP_ADCL]();
1088 gen_op_mov_reg_T0[ot][d]();
1089 } else {
4f31916f 1090 gen_op_arithc_mem_T0_T1_cc[ot + s1->mem_index][op - OP_ADCL]();
2c0262af
FB		 1091 }
1092 s1->cc_op = CC_OP_DYNAMIC;
1093 goto the_end;
1094 case OP_ADDL:
1095 gen_op_addl_T0_T1();
1096 s1->cc_op = CC_OP_ADDB + ot;
1097 gen_update_cc = gen_op_update2_cc;
1098 break;
1099 case OP_SUBL:
1100 gen_op_subl_T0_T1();
1101 s1->cc_op = CC_OP_SUBB + ot;
1102 gen_update_cc = gen_op_update2_cc;
1103 break;
1104 default:
1105 case OP_ANDL:
1106 case OP_ORL:
1107 case OP_XORL:
1108 gen_op_arith_T0_T1_cc[op]();
1109 s1->cc_op = CC_OP_LOGICB + ot;
1110 gen_update_cc = gen_op_update1_cc;
1111 break;
1112 case OP_CMPL:
1113 gen_op_cmpl_T0_T1_cc();
1114 s1->cc_op = CC_OP_SUBB + ot;
1115 gen_update_cc = NULL;
1116 break;
1117 }
1118 if (op != OP_CMPL) {
1119 if (d != OR_TMP0)
1120 gen_op_mov_reg_T0[ot][d]();
1121 else
1122 gen_op_st_T0_A0[ot + s1->mem_index]();
1123 }
1124 /* the flags update must happen after the memory write (precise
1125 exception support) */
1126 if (gen_update_cc)
1127 gen_update_cc();
1128 the_end: ;
1129}
1130
1131/* if d == OR_TMP0, it means memory operand (address in A0) */
1132static void gen_inc(DisasContext *s1, int ot, int d, int c)
1133{
1134 if (d != OR_TMP0)
1135 gen_op_mov_TN_reg[ot][0][d]();
1136 else
1137 gen_op_ld_T0_A0[ot + s1->mem_index]();
1138 if (s1->cc_op != CC_OP_DYNAMIC)
1139 gen_op_set_cc_op(s1->cc_op);
1140 if (c > 0) {
1141 gen_op_incl_T0();
1142 s1->cc_op = CC_OP_INCB + ot;
1143 } else {
1144 gen_op_decl_T0();
1145 s1->cc_op = CC_OP_DECB + ot;
1146 }
1147 if (d != OR_TMP0)
1148 gen_op_mov_reg_T0[ot][d]();
1149 else
1150 gen_op_st_T0_A0[ot + s1->mem_index]();
1151 gen_op_update_inc_cc();
1152}
1153
1154static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1155{
1156 if (d != OR_TMP0)
1157 gen_op_mov_TN_reg[ot][0][d]();
1158 else
1159 gen_op_ld_T0_A0[ot + s1->mem_index]();
1160 if (s != OR_TMP1)
1161 gen_op_mov_TN_reg[ot][1][s]();
1162 /* for zero counts, flags are not updated, so must do it dynamically */
1163 if (s1->cc_op != CC_OP_DYNAMIC)
1164 gen_op_set_cc_op(s1->cc_op);
1165
1166 if (d != OR_TMP0)
1167 gen_op_shift_T0_T1_cc[ot][op]();
1168 else
4f31916f 1169 gen_op_shift_mem_T0_T1_cc[ot + s1->mem_index][op]();
2c0262af
FB		 1170 if (d != OR_TMP0)
1171 gen_op_mov_reg_T0[ot][d]();
1172 s1->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1173}
1174
1175static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1176{
1177 /* currently not optimized */
1178 gen_op_movl_T1_im(c);
1179 gen_shift(s1, op, ot, d, OR_TMP1);
1180}
1181
1182static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1183{
1184 int havesib;
1185 int base, disp;
1186 int index;
1187 int scale;
1188 int opreg;
1189 int mod, rm, code, override, must_add_seg;
1190
1191 override = s->override;
1192 must_add_seg = s->addseg;
1193 if (override >= 0)
1194 must_add_seg = 1;
1195 mod = (modrm >> 6) & 3;
1196 rm = modrm & 7;
1197
1198 if (s->aflag) {
1199
1200 havesib = 0;
1201 base = rm;
1202 index = 0;
1203 scale = 0;
1204
1205 if (base == 4) {
1206 havesib = 1;
61382a50 1207 code = ldub_code(s->pc++);
2c0262af
FB		 1208 scale = (code >> 6) & 3;
1209 index = (code >> 3) & 7;
1210 base = code & 7;
1211 }
1212
1213 switch (mod) {
1214 case 0:
1215 if (base == 5) {
1216 base = -1;
61382a50 1217 disp = ldl_code(s->pc);
2c0262af
FB		 1218 s->pc += 4;
1219 } else {
1220 disp = 0;
1221 }
1222 break;
1223 case 1:
61382a50 1224 disp = (int8_t)ldub_code(s->pc++);
2c0262af
FB		 1225 break;
1226 default:
1227 case 2:
61382a50 1228 disp = ldl_code(s->pc);
2c0262af
FB		 1229 s->pc += 4;
1230 break;
1231 }
1232
1233 if (base >= 0) {
1234 /* for correct popl handling with esp */
1235 if (base == 4 && s->popl_esp_hack)
1236 disp += s->popl_esp_hack;
1237 gen_op_movl_A0_reg[base]();
1238 if (disp != 0)
1239 gen_op_addl_A0_im(disp);
1240 } else {
1241 gen_op_movl_A0_im(disp);
1242 }
1243 /* XXX: index == 4 is always invalid */
1244 if (havesib && (index != 4 || scale != 0)) {
1245 gen_op_addl_A0_reg_sN[scale][index]();
1246 }
1247 if (must_add_seg) {
1248 if (override < 0) {
1249 if (base == R_EBP || base == R_ESP)
1250 override = R_SS;
1251 else
1252 override = R_DS;
1253 }
1254 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1255 }
1256 } else {
1257 switch (mod) {
1258 case 0:
1259 if (rm == 6) {
61382a50 1260 disp = lduw_code(s->pc);
2c0262af
FB		 1261 s->pc += 2;
1262 gen_op_movl_A0_im(disp);
1263 rm = 0; /* avoid SS override */
1264 goto no_rm;
1265 } else {
1266 disp = 0;
1267 }
1268 break;
1269 case 1:
61382a50 1270 disp = (int8_t)ldub_code(s->pc++);
2c0262af
FB		 1271 break;
1272 default:
1273 case 2:
61382a50 1274 disp = lduw_code(s->pc);
2c0262af
FB		 1275 s->pc += 2;
1276 break;
1277 }
1278 switch(rm) {
1279 case 0:
1280 gen_op_movl_A0_reg[R_EBX]();
1281 gen_op_addl_A0_reg_sN[0][R_ESI]();
1282 break;
1283 case 1:
1284 gen_op_movl_A0_reg[R_EBX]();
1285 gen_op_addl_A0_reg_sN[0][R_EDI]();
1286 break;
1287 case 2:
1288 gen_op_movl_A0_reg[R_EBP]();
1289 gen_op_addl_A0_reg_sN[0][R_ESI]();
1290 break;
1291 case 3:
1292 gen_op_movl_A0_reg[R_EBP]();
1293 gen_op_addl_A0_reg_sN[0][R_EDI]();
1294 break;
1295 case 4:
1296 gen_op_movl_A0_reg[R_ESI]();
1297 break;
1298 case 5:
1299 gen_op_movl_A0_reg[R_EDI]();
1300 break;
1301 case 6:
1302 gen_op_movl_A0_reg[R_EBP]();
1303 break;
1304 default:
1305 case 7:
1306 gen_op_movl_A0_reg[R_EBX]();
1307 break;
1308 }
1309 if (disp != 0)
1310 gen_op_addl_A0_im(disp);
1311 gen_op_andl_A0_ffff();
1312 no_rm:
1313 if (must_add_seg) {
1314 if (override < 0) {
1315 if (rm == 2 || rm == 3 || rm == 6)
1316 override = R_SS;
1317 else
1318 override = R_DS;
1319 }
1320 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1321 }
1322 }
1323
1324 opreg = OR_A0;
1325 disp = 0;
1326 *reg_ptr = opreg;
1327 *offset_ptr = disp;
1328}
1329
1330/* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
1331 OR_TMP0 */
1332static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
1333{
1334 int mod, rm, opreg, disp;
1335
1336 mod = (modrm >> 6) & 3;
1337 rm = modrm & 7;
1338 if (mod == 3) {
1339 if (is_store) {
1340 if (reg != OR_TMP0)
1341 gen_op_mov_TN_reg[ot][0][reg]();
1342 gen_op_mov_reg_T0[ot][rm]();
1343 } else {
1344 gen_op_mov_TN_reg[ot][0][rm]();
1345 if (reg != OR_TMP0)
1346 gen_op_mov_reg_T0[ot][reg]();
1347 }
1348 } else {
1349 gen_lea_modrm(s, modrm, &opreg, &disp);
1350 if (is_store) {
1351 if (reg != OR_TMP0)
1352 gen_op_mov_TN_reg[ot][0][reg]();
1353 gen_op_st_T0_A0[ot + s->mem_index]();
1354 } else {
1355 gen_op_ld_T0_A0[ot + s->mem_index]();
1356 if (reg != OR_TMP0)
1357 gen_op_mov_reg_T0[ot][reg]();
1358 }
1359 }
1360}
1361
1362static inline uint32_t insn_get(DisasContext *s, int ot)
1363{
1364 uint32_t ret;
1365
1366 switch(ot) {
1367 case OT_BYTE:
61382a50 1368 ret = ldub_code(s->pc);
2c0262af
FB		 1369 s->pc++;
1370 break;
1371 case OT_WORD:
61382a50 1372 ret = lduw_code(s->pc);
2c0262af
FB		 1373 s->pc += 2;
1374 break;
1375 default:
1376 case OT_LONG:
61382a50 1377 ret = ldl_code(s->pc);
2c0262af
FB		 1378 s->pc += 4;
1379 break;
1380 }
1381 return ret;
1382}
1383
1384static inline void gen_jcc(DisasContext *s, int b, int val, int next_eip)
1385{
1386 TranslationBlock *tb;
1387 int inv, jcc_op;
1388 GenOpFunc3 *func;
1389
1390 inv = b & 1;
1391 jcc_op = (b >> 1) & 7;
1392
1393 if (s->jmp_opt) {
1394 switch(s->cc_op) {
1395 /* we optimize the cmp/jcc case */
1396 case CC_OP_SUBB:
1397 case CC_OP_SUBW:
1398 case CC_OP_SUBL:
1399 func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1400 break;
1401
1402 /* some jumps are easy to compute */
1403 case CC_OP_ADDB:
1404 case CC_OP_ADDW:
1405 case CC_OP_ADDL:
1406 case CC_OP_ADCB:
1407 case CC_OP_ADCW:
1408 case CC_OP_ADCL:
1409 case CC_OP_SBBB:
1410 case CC_OP_SBBW:
1411 case CC_OP_SBBL:
1412 case CC_OP_LOGICB:
1413 case CC_OP_LOGICW:
1414 case CC_OP_LOGICL:
1415 case CC_OP_INCB:
1416 case CC_OP_INCW:
1417 case CC_OP_INCL:
1418 case CC_OP_DECB:
1419 case CC_OP_DECW:
1420 case CC_OP_DECL:
1421 case CC_OP_SHLB:
1422 case CC_OP_SHLW:
1423 case CC_OP_SHLL:
1424 case CC_OP_SARB:
1425 case CC_OP_SARW:
1426 case CC_OP_SARL:
1427 switch(jcc_op) {
1428 case JCC_Z:
1429 func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1430 break;
1431 case JCC_S:
1432 func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1433 break;
1434 default:
1435 func = NULL;
1436 break;
1437 }
1438 break;
1439 default:
1440 func = NULL;
1441 break;
1442 }
1443
1444 if (s->cc_op != CC_OP_DYNAMIC)
1445 gen_op_set_cc_op(s->cc_op);
1446
1447 if (!func) {
1448 gen_setcc_slow[jcc_op]();
1449 func = gen_op_jcc;
1450 }
1451
1452 tb = s->tb;
1453 if (!inv) {
1454 func((long)tb, val, next_eip);
1455 } else {
1456 func((long)tb, next_eip, val);
1457 }
1458 s->is_jmp = 3;
1459 } else {
1460 if (s->cc_op != CC_OP_DYNAMIC) {
1461 gen_op_set_cc_op(s->cc_op);
1462 s->cc_op = CC_OP_DYNAMIC;
1463 }
1464 gen_setcc_slow[jcc_op]();
1465 if (!inv) {
1466 gen_op_jcc_im(val, next_eip);
1467 } else {
1468 gen_op_jcc_im(next_eip, val);
1469 }
1470 gen_eob(s);
1471 }
1472}
1473
1474static void gen_setcc(DisasContext *s, int b)
1475{
1476 int inv, jcc_op;
1477 GenOpFunc *func;
1478
1479 inv = b & 1;
1480 jcc_op = (b >> 1) & 7;
1481 switch(s->cc_op) {
1482 /* we optimize the cmp/jcc case */
1483 case CC_OP_SUBB:
1484 case CC_OP_SUBW:
1485 case CC_OP_SUBL:
1486 func = gen_setcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1487 if (!func)
1488 goto slow_jcc;
1489 break;
1490
1491 /* some jumps are easy to compute */
1492 case CC_OP_ADDB:
1493 case CC_OP_ADDW:
1494 case CC_OP_ADDL:
1495 case CC_OP_LOGICB:
1496 case CC_OP_LOGICW:
1497 case CC_OP_LOGICL:
1498 case CC_OP_INCB:
1499 case CC_OP_INCW:
1500 case CC_OP_INCL:
1501 case CC_OP_DECB:
1502 case CC_OP_DECW:
1503 case CC_OP_DECL:
1504 case CC_OP_SHLB:
1505 case CC_OP_SHLW:
1506 case CC_OP_SHLL:
1507 switch(jcc_op) {
1508 case JCC_Z:
1509 func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1510 break;
1511 case JCC_S:
1512 func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1513 break;
1514 default:
1515 goto slow_jcc;
1516 }
1517 break;
1518 default:
1519 slow_jcc:
1520 if (s->cc_op != CC_OP_DYNAMIC)
1521 gen_op_set_cc_op(s->cc_op);
1522 func = gen_setcc_slow[jcc_op];
1523 break;
1524 }
1525 func();
1526 if (inv) {
1527 gen_op_xor_T0_1();
1528 }
1529}
1530
1531/* move T0 to seg_reg and compute if the CPU state may change. Never
1532 call this function with seg_reg == R_CS */
1533static void gen_movl_seg_T0(DisasContext *s, int seg_reg, unsigned int cur_eip)
1534{
3415a4dd
FB		 1535 if (s->pe && !s->vm86) {
1536 /* XXX: optimize by finding processor state dynamically */
1537 if (s->cc_op != CC_OP_DYNAMIC)
1538 gen_op_set_cc_op(s->cc_op);
1539 gen_op_jmp_im(cur_eip);
1540 gen_op_movl_seg_T0(seg_reg);
dc196a57
FB		 1541 /* abort translation because the addseg value may change or
1542 because ss32 may change. For R_SS, translation must always
1543 stop as a special handling must be done to disable hardware
1544 interrupts for the next instruction */
1545 if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
1546 s->is_jmp = 3;
3415a4dd 1547 } else {
2c0262af 1548 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg]));
dc196a57
FB		 1549 if (seg_reg == R_SS)
1550 s->is_jmp = 3;
3415a4dd 1551 }
2c0262af
FB		 1552}
1553
4f31916f
FB		 1554static inline void gen_stack_update(DisasContext *s, int addend)
1555{
1556 if (s->ss32) {
1557 if (addend == 2)
1558 gen_op_addl_ESP_2();
1559 else if (addend == 4)
1560 gen_op_addl_ESP_4();
1561 else
1562 gen_op_addl_ESP_im(addend);
1563 } else {
1564 if (addend == 2)
1565 gen_op_addw_ESP_2();
1566 else if (addend == 4)
1567 gen_op_addw_ESP_4();
1568 else
1569 gen_op_addw_ESP_im(addend);
1570 }
1571}
1572
2c0262af
FB		 1573/* generate a push. It depends on ss32, addseg and dflag */
1574static void gen_push_T0(DisasContext *s)
1575{
4f31916f
FB		 1576 gen_op_movl_A0_reg[R_ESP]();
1577 if (!s->dflag)
1578 gen_op_subl_A0_2();
1579 else
1580 gen_op_subl_A0_4();
2c0262af 1581 if (s->ss32) {
4f31916f
FB		 1582 if (s->addseg) {
1583 gen_op_movl_T1_A0();
1584 gen_op_addl_A0_SS();
2c0262af
FB		 1585 }
1586 } else {
4f31916f
FB		 1587 gen_op_andl_A0_ffff();
1588 gen_op_movl_T1_A0();
1589 gen_op_addl_A0_SS();
2c0262af 1590 }
4f31916f
FB		 1591 gen_op_st_T0_A0[s->dflag + 1 + s->mem_index]();
1592 if (s->ss32 && !s->addseg)
1593 gen_op_movl_ESP_A0();
1594 else
1595 gen_op_mov_reg_T1[s->ss32 + 1][R_ESP]();
2c0262af
FB		 1596}
1597
4f31916f
FB		 1598/* generate a push. It depends on ss32, addseg and dflag */
1599/* slower version for T1, only used for call Ev */
1600static void gen_push_T1(DisasContext *s)
2c0262af 1601{
4f31916f
FB		 1602 gen_op_movl_A0_reg[R_ESP]();
1603 if (!s->dflag)
1604 gen_op_subl_A0_2();
1605 else
1606 gen_op_subl_A0_4();
2c0262af 1607 if (s->ss32) {
4f31916f
FB		 1608 if (s->addseg) {
1609 gen_op_addl_A0_SS();
2c0262af
FB		 1610 }
1611 } else {
4f31916f
FB		 1612 gen_op_andl_A0_ffff();
1613 gen_op_addl_A0_SS();
2c0262af 1614 }
4f31916f
FB		 1615 gen_op_st_T1_A0[s->dflag + 1 + s->mem_index]();
1616
1617 if (s->ss32 && !s->addseg)
1618 gen_op_movl_ESP_A0();
1619 else
1620 gen_stack_update(s, (-2) << s->dflag);
2c0262af
FB		 1621}
1622
4f31916f
FB		 1623/* two step pop is necessary for precise exceptions */
1624static void gen_pop_T0(DisasContext *s)
2c0262af 1625{
4f31916f 1626 gen_op_movl_A0_reg[R_ESP]();
2c0262af 1627 if (s->ss32) {
4f31916f
FB		 1628 if (s->addseg)
1629 gen_op_addl_A0_SS();
2c0262af 1630 } else {
4f31916f
FB		 1631 gen_op_andl_A0_ffff();
1632 gen_op_addl_A0_SS();
2c0262af 1633 }
4f31916f 1634 gen_op_ld_T0_A0[s->dflag + 1 + s->mem_index]();
2c0262af
FB		 1635}
1636
1637static void gen_pop_update(DisasContext *s)
1638{
1639 gen_stack_update(s, 2 << s->dflag);
1640}
1641
1642static void gen_stack_A0(DisasContext *s)
1643{
1644 gen_op_movl_A0_ESP();
1645 if (!s->ss32)
1646 gen_op_andl_A0_ffff();
1647 gen_op_movl_T1_A0();
1648 if (s->addseg)
1649 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1650}
1651
1652/* NOTE: wrap around in 16 bit not fully handled */
1653static void gen_pusha(DisasContext *s)
1654{
1655 int i;
1656 gen_op_movl_A0_ESP();
1657 gen_op_addl_A0_im(-16 << s->dflag);
1658 if (!s->ss32)
1659 gen_op_andl_A0_ffff();
1660 gen_op_movl_T1_A0();
1661 if (s->addseg)
1662 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1663 for(i = 0;i < 8; i++) {
1664 gen_op_mov_TN_reg[OT_LONG][0][7 - i]();
1665 gen_op_st_T0_A0[OT_WORD + s->dflag + s->mem_index]();
1666 gen_op_addl_A0_im(2 << s->dflag);
1667 }
1668 gen_op_mov_reg_T1[OT_WORD + s->dflag][R_ESP]();
1669}
1670
1671/* NOTE: wrap around in 16 bit not fully handled */
1672static void gen_popa(DisasContext *s)
1673{
1674 int i;
1675 gen_op_movl_A0_ESP();
1676 if (!s->ss32)
1677 gen_op_andl_A0_ffff();
1678 gen_op_movl_T1_A0();
1679 gen_op_addl_T1_im(16 << s->dflag);
1680 if (s->addseg)
1681 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1682 for(i = 0;i < 8; i++) {
1683 /* ESP is not reloaded */
1684 if (i != 3) {
1685 gen_op_ld_T0_A0[OT_WORD + s->dflag + s->mem_index]();
1686 gen_op_mov_reg_T0[OT_WORD + s->dflag][7 - i]();
1687 }
1688 gen_op_addl_A0_im(2 << s->dflag);
1689 }
1690 gen_op_mov_reg_T1[OT_WORD + s->dflag][R_ESP]();
1691}
1692
1693/* NOTE: wrap around in 16 bit not fully handled */
1694/* XXX: check this */
1695static void gen_enter(DisasContext *s, int esp_addend, int level)
1696{
1697 int ot, level1, addend, opsize;
1698
1699 ot = s->dflag + OT_WORD;
1700 level &= 0x1f;
1701 level1 = level;
1702 opsize = 2 << s->dflag;
1703
1704 gen_op_movl_A0_ESP();
1705 gen_op_addl_A0_im(-opsize);
1706 if (!s->ss32)
1707 gen_op_andl_A0_ffff();
1708 gen_op_movl_T1_A0();
1709 if (s->addseg)
1710 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1711 /* push bp */
1712 gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
1713 gen_op_st_T0_A0[ot + s->mem_index]();
1714 if (level) {
1715 while (level--) {
1716 gen_op_addl_A0_im(-opsize);
1717 gen_op_addl_T0_im(-opsize);
1718 gen_op_st_T0_A0[ot + s->mem_index]();
1719 }
1720 gen_op_addl_A0_im(-opsize);
4f31916f 1721 gen_op_st_T1_A0[ot + s->mem_index]();
2c0262af
FB		 1722 }
1723 gen_op_mov_reg_T1[ot][R_EBP]();
1724 addend = -esp_addend;
1725 if (level1)
1726 addend -= opsize * (level1 + 1);
1727 gen_op_addl_T1_im(addend);
1728 gen_op_mov_reg_T1[ot][R_ESP]();
1729}
1730
1731static void gen_exception(DisasContext *s, int trapno, unsigned int cur_eip)
1732{
1733 if (s->cc_op != CC_OP_DYNAMIC)
1734 gen_op_set_cc_op(s->cc_op);
1735 gen_op_jmp_im(cur_eip);
1736 gen_op_raise_exception(trapno);
1737 s->is_jmp = 3;
1738}
1739
1740/* an interrupt is different from an exception because of the
1741 priviledge checks */
1742static void gen_interrupt(DisasContext *s, int intno,
1743 unsigned int cur_eip, unsigned int next_eip)
1744{
1745 if (s->cc_op != CC_OP_DYNAMIC)
1746 gen_op_set_cc_op(s->cc_op);
1747 gen_op_jmp_im(cur_eip);
1748 gen_op_raise_interrupt(intno, next_eip);
1749 s->is_jmp = 3;
1750}
1751
1752static void gen_debug(DisasContext *s, unsigned int cur_eip)
1753{
1754 if (s->cc_op != CC_OP_DYNAMIC)
1755 gen_op_set_cc_op(s->cc_op);
1756 gen_op_jmp_im(cur_eip);
1757 gen_op_debug();
1758 s->is_jmp = 3;
1759}
1760
1761/* generate a generic end of block. Trace exception is also generated
1762 if needed */
1763static void gen_eob(DisasContext *s)
1764{
1765 if (s->cc_op != CC_OP_DYNAMIC)
1766 gen_op_set_cc_op(s->cc_op);
a2cc3b24
FB		 1767 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
1768 gen_op_reset_inhibit_irq();
1769 }
34865134
FB		 1770 if (s->singlestep_enabled) {
1771 gen_op_debug();
1772 } else if (s->tf) {
2c0262af
FB		 1773 gen_op_raise_exception(EXCP01_SSTP);
1774 } else {
1775 gen_op_movl_T0_0();
1776 gen_op_exit_tb();
1777 }
1778 s->is_jmp = 3;
1779}
1780
1781/* generate a jump to eip. No segment change must happen before as a
1782 direct call to the next block may occur */
1783static void gen_jmp(DisasContext *s, unsigned int eip)
1784{
1785 TranslationBlock *tb = s->tb;
1786
1787 if (s->jmp_opt) {
1788 if (s->cc_op != CC_OP_DYNAMIC)
1789 gen_op_set_cc_op(s->cc_op);
1790 gen_op_jmp((long)tb, eip);
1791 s->is_jmp = 3;
1792 } else {
1793 gen_op_jmp_im(eip);
1794 gen_eob(s);
1795 }
1796}
1797
1798/* convert one instruction. s->is_jmp is set if the translation must
1799 be stopped. Return the next pc value */
1800static uint8_t *disas_insn(DisasContext *s, uint8_t *pc_start)
1801{
1802 int b, prefixes, aflag, dflag;
1803 int shift, ot;
1804 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
1805 unsigned int next_eip;
1806
1807 s->pc = pc_start;
1808 prefixes = 0;
1809 aflag = s->code32;
1810 dflag = s->code32;
1811 s->override = -1;
1812 next_byte:
61382a50 1813 b = ldub_code(s->pc);
2c0262af
FB		 1814 s->pc++;
1815 /* check prefixes */
1816 switch (b) {
1817 case 0xf3:
1818 prefixes |= PREFIX_REPZ;
1819 goto next_byte;
1820 case 0xf2:
1821 prefixes |= PREFIX_REPNZ;
1822 goto next_byte;
1823 case 0xf0:
1824 prefixes |= PREFIX_LOCK;
1825 goto next_byte;
1826 case 0x2e:
1827 s->override = R_CS;
1828 goto next_byte;
1829 case 0x36:
1830 s->override = R_SS;
1831 goto next_byte;
1832 case 0x3e:
1833 s->override = R_DS;
1834 goto next_byte;
1835 case 0x26:
1836 s->override = R_ES;
1837 goto next_byte;
1838 case 0x64:
1839 s->override = R_FS;
1840 goto next_byte;
1841 case 0x65:
1842 s->override = R_GS;
1843 goto next_byte;
1844 case 0x66:
1845 prefixes |= PREFIX_DATA;
1846 goto next_byte;
1847 case 0x67:
1848 prefixes |= PREFIX_ADR;
1849 goto next_byte;
1850 }
1851
1852 if (prefixes & PREFIX_DATA)
1853 dflag ^= 1;
1854 if (prefixes & PREFIX_ADR)
1855 aflag ^= 1;
1856
1857 s->prefix = prefixes;
1858 s->aflag = aflag;
1859 s->dflag = dflag;
1860
1861 /* lock generation */
1862 if (prefixes & PREFIX_LOCK)
1863 gen_op_lock();
1864
1865 /* now check op code */
1866 reswitch:
1867 switch(b) {
1868 case 0x0f:
1869 /**************************/
1870 /* extended op code */
61382a50 1871 b = ldub_code(s->pc++) | 0x100;
2c0262af
FB		 1872 goto reswitch;
1873
1874 /**************************/
1875 /* arith & logic */
1876 case 0x00 ... 0x05:
1877 case 0x08 ... 0x0d:
1878 case 0x10 ... 0x15:
1879 case 0x18 ... 0x1d:
1880 case 0x20 ... 0x25:
1881 case 0x28 ... 0x2d:
1882 case 0x30 ... 0x35:
1883 case 0x38 ... 0x3d:
1884 {
1885 int op, f, val;
1886 op = (b >> 3) & 7;
1887 f = (b >> 1) & 3;
1888
1889 if ((b & 1) == 0)
1890 ot = OT_BYTE;
1891 else
1892 ot = dflag ? OT_LONG : OT_WORD;
1893
1894 switch(f) {
1895 case 0: /* OP Ev, Gv */
61382a50 1896 modrm = ldub_code(s->pc++);
2c0262af
FB		 1897 reg = ((modrm >> 3) & 7);
1898 mod = (modrm >> 6) & 3;
1899 rm = modrm & 7;
1900 if (mod != 3) {
1901 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1902 opreg = OR_TMP0;
1903 } else if (op == OP_XORL && rm == reg) {
1904 xor_zero:
1905 /* xor reg, reg optimisation */
1906 gen_op_movl_T0_0();
1907 s->cc_op = CC_OP_LOGICB + ot;
1908 gen_op_mov_reg_T0[ot][reg]();
1909 gen_op_update1_cc();
1910 break;
1911 } else {
1912 opreg = rm;
1913 }
1914 gen_op_mov_TN_reg[ot][1][reg]();
1915 gen_op(s, op, ot, opreg);
1916 break;
1917 case 1: /* OP Gv, Ev */
61382a50 1918 modrm = ldub_code(s->pc++);
2c0262af
FB		 1919 mod = (modrm >> 6) & 3;
1920 reg = ((modrm >> 3) & 7);
1921 rm = modrm & 7;
1922 if (mod != 3) {
1923 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1924 gen_op_ld_T1_A0[ot + s->mem_index]();
1925 } else if (op == OP_XORL && rm == reg) {
1926 goto xor_zero;
1927 } else {
1928 gen_op_mov_TN_reg[ot][1][rm]();
1929 }
1930 gen_op(s, op, ot, reg);
1931 break;
1932 case 2: /* OP A, Iv */
1933 val = insn_get(s, ot);
1934 gen_op_movl_T1_im(val);
1935 gen_op(s, op, ot, OR_EAX);
1936 break;
1937 }
1938 }
1939 break;
1940
1941 case 0x80: /* GRP1 */
1942 case 0x81:
d64477af 1943 case 0x82:
2c0262af
FB		 1944 case 0x83:
1945 {
1946 int val;
1947
1948 if ((b & 1) == 0)
1949 ot = OT_BYTE;
1950 else
1951 ot = dflag ? OT_LONG : OT_WORD;
1952
61382a50 1953 modrm = ldub_code(s->pc++);
2c0262af
FB		 1954 mod = (modrm >> 6) & 3;
1955 rm = modrm & 7;
1956 op = (modrm >> 3) & 7;
1957
1958 if (mod != 3) {
1959 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1960 opreg = OR_TMP0;
1961 } else {
1962 opreg = rm + OR_EAX;
1963 }
1964
1965 switch(b) {
1966 default:
1967 case 0x80:
1968 case 0x81:
d64477af 1969 case 0x82:
2c0262af
FB		 1970 val = insn_get(s, ot);
1971 break;
1972 case 0x83:
1973 val = (int8_t)insn_get(s, OT_BYTE);
1974 break;
1975 }
1976 gen_op_movl_T1_im(val);
1977 gen_op(s, op, ot, opreg);
1978 }
1979 break;
1980
1981 /**************************/
1982 /* inc, dec, and other misc arith */
1983 case 0x40 ... 0x47: /* inc Gv */
1984 ot = dflag ? OT_LONG : OT_WORD;
1985 gen_inc(s, ot, OR_EAX + (b & 7), 1);
1986 break;
1987 case 0x48 ... 0x4f: /* dec Gv */
1988 ot = dflag ? OT_LONG : OT_WORD;
1989 gen_inc(s, ot, OR_EAX + (b & 7), -1);
1990 break;
1991 case 0xf6: /* GRP3 */
1992 case 0xf7:
1993 if ((b & 1) == 0)
1994 ot = OT_BYTE;
1995 else
1996 ot = dflag ? OT_LONG : OT_WORD;
1997
61382a50 1998 modrm = ldub_code(s->pc++);
2c0262af
FB		 1999 mod = (modrm >> 6) & 3;
2000 rm = modrm & 7;
2001 op = (modrm >> 3) & 7;
2002 if (mod != 3) {
2003 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2004 gen_op_ld_T0_A0[ot + s->mem_index]();
2005 } else {
2006 gen_op_mov_TN_reg[ot][0][rm]();
2007 }
2008
2009 switch(op) {
2010 case 0: /* test */
2011 val = insn_get(s, ot);
2012 gen_op_movl_T1_im(val);
2013 gen_op_testl_T0_T1_cc();
2014 s->cc_op = CC_OP_LOGICB + ot;
2015 break;
2016 case 2: /* not */
2017 gen_op_notl_T0();
2018 if (mod != 3) {
2019 gen_op_st_T0_A0[ot + s->mem_index]();
2020 } else {
2021 gen_op_mov_reg_T0[ot][rm]();
2022 }
2023 break;
2024 case 3: /* neg */
2025 gen_op_negl_T0();
2026 if (mod != 3) {
2027 gen_op_st_T0_A0[ot + s->mem_index]();
2028 } else {
2029 gen_op_mov_reg_T0[ot][rm]();
2030 }
2031 gen_op_update_neg_cc();
2032 s->cc_op = CC_OP_SUBB + ot;
2033 break;
2034 case 4: /* mul */
2035 switch(ot) {
2036 case OT_BYTE:
2037 gen_op_mulb_AL_T0();
d36cd60e 2038 s->cc_op = CC_OP_MULB;
2c0262af
FB		 2039 break;
2040 case OT_WORD:
2041 gen_op_mulw_AX_T0();
d36cd60e 2042 s->cc_op = CC_OP_MULW;
2c0262af
FB		 2043 break;
2044 default:
2045 case OT_LONG:
2046 gen_op_mull_EAX_T0();
d36cd60e 2047 s->cc_op = CC_OP_MULL;
2c0262af
FB		 2048 break;
2049 }
2c0262af
FB		 2050 break;
2051 case 5: /* imul */
2052 switch(ot) {
2053 case OT_BYTE:
2054 gen_op_imulb_AL_T0();
d36cd60e 2055 s->cc_op = CC_OP_MULB;
2c0262af
FB		 2056 break;
2057 case OT_WORD:
2058 gen_op_imulw_AX_T0();
d36cd60e 2059 s->cc_op = CC_OP_MULW;
2c0262af
FB		 2060 break;
2061 default:
2062 case OT_LONG:
2063 gen_op_imull_EAX_T0();
d36cd60e 2064 s->cc_op = CC_OP_MULL;
2c0262af
FB		 2065 break;
2066 }
2c0262af
FB		 2067 break;
2068 case 6: /* div */
2069 switch(ot) {
2070 case OT_BYTE:
2071 gen_op_divb_AL_T0(pc_start - s->cs_base);
2072 break;
2073 case OT_WORD:
2074 gen_op_divw_AX_T0(pc_start - s->cs_base);
2075 break;
2076 default:
2077 case OT_LONG:
2078 gen_op_divl_EAX_T0(pc_start - s->cs_base);
2079 break;
2080 }
2081 break;
2082 case 7: /* idiv */
2083 switch(ot) {
2084 case OT_BYTE:
2085 gen_op_idivb_AL_T0(pc_start - s->cs_base);
2086 break;
2087 case OT_WORD:
2088 gen_op_idivw_AX_T0(pc_start - s->cs_base);
2089 break;
2090 default:
2091 case OT_LONG:
2092 gen_op_idivl_EAX_T0(pc_start - s->cs_base);
2093 break;
2094 }
2095 break;
2096 default:
2097 goto illegal_op;
2098 }
2099 break;
2100
2101 case 0xfe: /* GRP4 */
2102 case 0xff: /* GRP5 */
2103 if ((b & 1) == 0)
2104 ot = OT_BYTE;
2105 else
2106 ot = dflag ? OT_LONG : OT_WORD;
2107
61382a50 2108 modrm = ldub_code(s->pc++);
2c0262af
FB		 2109 mod = (modrm >> 6) & 3;
2110 rm = modrm & 7;
2111 op = (modrm >> 3) & 7;
2112 if (op >= 2 && b == 0xfe) {
2113 goto illegal_op;
2114 }
2115 if (mod != 3) {
2116 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2117 if (op >= 2 && op != 3 && op != 5)
2118 gen_op_ld_T0_A0[ot + s->mem_index]();
2119 } else {
2120 gen_op_mov_TN_reg[ot][0][rm]();
2121 }
2122
2123 switch(op) {
2124 case 0: /* inc Ev */
2125 if (mod != 3)
2126 opreg = OR_TMP0;
2127 else
2128 opreg = rm;
2129 gen_inc(s, ot, opreg, 1);
2130 break;
2131 case 1: /* dec Ev */
2132 if (mod != 3)
2133 opreg = OR_TMP0;
2134 else
2135 opreg = rm;
2136 gen_inc(s, ot, opreg, -1);
2137 break;
2138 case 2: /* call Ev */
4f31916f 2139 /* XXX: optimize if memory (no 'and' is necessary) */
2c0262af
FB		 2140 if (s->dflag == 0)
2141 gen_op_andl_T0_ffff();
2c0262af 2142 next_eip = s->pc - s->cs_base;
4f31916f
FB		 2143 gen_op_movl_T1_im(next_eip);
2144 gen_push_T1(s);
2145 gen_op_jmp_T0();
2c0262af
FB		 2146 gen_eob(s);
2147 break;
61382a50 2148 case 3: /* lcall Ev */
2c0262af
FB		 2149 gen_op_ld_T1_A0[ot + s->mem_index]();
2150 gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
61382a50 2151 gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
2c0262af
FB		 2152 do_lcall:
2153 if (s->pe && !s->vm86) {
2154 if (s->cc_op != CC_OP_DYNAMIC)
2155 gen_op_set_cc_op(s->cc_op);
2156 gen_op_jmp_im(pc_start - s->cs_base);
2157 gen_op_lcall_protected_T0_T1(dflag, s->pc - s->cs_base);
2158 } else {
2159 gen_op_lcall_real_T0_T1(dflag, s->pc - s->cs_base);
2160 }
2161 gen_eob(s);
2162 break;
2163 case 4: /* jmp Ev */
2164 if (s->dflag == 0)
2165 gen_op_andl_T0_ffff();
2166 gen_op_jmp_T0();
2167 gen_eob(s);
2168 break;
2169 case 5: /* ljmp Ev */
2170 gen_op_ld_T1_A0[ot + s->mem_index]();
2171 gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
61382a50 2172 gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
2c0262af
FB		 2173 do_ljmp:
2174 if (s->pe && !s->vm86) {
2175 if (s->cc_op != CC_OP_DYNAMIC)
2176 gen_op_set_cc_op(s->cc_op);
2177 gen_op_jmp_im(pc_start - s->cs_base);
08cea4ee 2178 gen_op_ljmp_protected_T0_T1(s->pc - s->cs_base);
2c0262af
FB		 2179 } else {
2180 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
2181 gen_op_movl_T0_T1();
2182 gen_op_jmp_T0();
2183 }
2184 gen_eob(s);
2185 break;
2186 case 6: /* push Ev */
2187 gen_push_T0(s);
2188 break;
2189 default:
2190 goto illegal_op;
2191 }
2192 break;
2193
2194 case 0x84: /* test Ev, Gv */
2195 case 0x85:
2196 if ((b & 1) == 0)
2197 ot = OT_BYTE;
2198 else
2199 ot = dflag ? OT_LONG : OT_WORD;
2200
61382a50 2201 modrm = ldub_code(s->pc++);
2c0262af
FB		 2202 mod = (modrm >> 6) & 3;
2203 rm = modrm & 7;
2204 reg = (modrm >> 3) & 7;
2205
2206 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2207 gen_op_mov_TN_reg[ot][1][reg + OR_EAX]();
2208 gen_op_testl_T0_T1_cc();
2209 s->cc_op = CC_OP_LOGICB + ot;
2210 break;
2211
2212 case 0xa8: /* test eAX, Iv */
2213 case 0xa9:
2214 if ((b & 1) == 0)
2215 ot = OT_BYTE;
2216 else
2217 ot = dflag ? OT_LONG : OT_WORD;
2218 val = insn_get(s, ot);
2219
2220 gen_op_mov_TN_reg[ot][0][OR_EAX]();
2221 gen_op_movl_T1_im(val);
2222 gen_op_testl_T0_T1_cc();
2223 s->cc_op = CC_OP_LOGICB + ot;
2224 break;
2225
2226 case 0x98: /* CWDE/CBW */
2227 if (dflag)
2228 gen_op_movswl_EAX_AX();
2229 else
2230 gen_op_movsbw_AX_AL();
2231 break;
2232 case 0x99: /* CDQ/CWD */
2233 if (dflag)
2234 gen_op_movslq_EDX_EAX();
2235 else
2236 gen_op_movswl_DX_AX();
2237 break;
2238 case 0x1af: /* imul Gv, Ev */
2239 case 0x69: /* imul Gv, Ev, I */
2240 case 0x6b:
2241 ot = dflag ? OT_LONG : OT_WORD;
61382a50 2242 modrm = ldub_code(s->pc++);
2c0262af
FB		 2243 reg = ((modrm >> 3) & 7) + OR_EAX;
2244 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2245 if (b == 0x69) {
2246 val = insn_get(s, ot);
2247 gen_op_movl_T1_im(val);
2248 } else if (b == 0x6b) {
d64477af 2249 val = (int8_t)insn_get(s, OT_BYTE);
2c0262af
FB		 2250 gen_op_movl_T1_im(val);
2251 } else {
2252 gen_op_mov_TN_reg[ot][1][reg]();
2253 }
2254
2255 if (ot == OT_LONG) {
2256 gen_op_imull_T0_T1();
2257 } else {
2258 gen_op_imulw_T0_T1();
2259 }
2260 gen_op_mov_reg_T0[ot][reg]();
d36cd60e 2261 s->cc_op = CC_OP_MULB + ot;
2c0262af
FB		 2262 break;
2263 case 0x1c0:
2264 case 0x1c1: /* xadd Ev, Gv */
2265 if ((b & 1) == 0)
2266 ot = OT_BYTE;
2267 else
2268 ot = dflag ? OT_LONG : OT_WORD;
61382a50 2269 modrm = ldub_code(s->pc++);
2c0262af
FB		 2270 reg = (modrm >> 3) & 7;
2271 mod = (modrm >> 6) & 3;
2272 if (mod == 3) {
2273 rm = modrm & 7;
2274 gen_op_mov_TN_reg[ot][0][reg]();
2275 gen_op_mov_TN_reg[ot][1][rm]();
2276 gen_op_addl_T0_T1();
2c0262af 2277 gen_op_mov_reg_T1[ot][reg]();
5a1388b6 2278 gen_op_mov_reg_T0[ot][rm]();
2c0262af
FB		 2279 } else {
2280 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2281 gen_op_mov_TN_reg[ot][0][reg]();
2282 gen_op_ld_T1_A0[ot + s->mem_index]();
2283 gen_op_addl_T0_T1();
2284 gen_op_st_T0_A0[ot + s->mem_index]();
2285 gen_op_mov_reg_T1[ot][reg]();
2286 }
2287 gen_op_update2_cc();
2288 s->cc_op = CC_OP_ADDB + ot;
2289 break;
2290 case 0x1b0:
2291 case 0x1b1: /* cmpxchg Ev, Gv */
2292 if ((b & 1) == 0)
2293 ot = OT_BYTE;
2294 else
2295 ot = dflag ? OT_LONG : OT_WORD;
61382a50 2296 modrm = ldub_code(s->pc++);
2c0262af
FB		 2297 reg = (modrm >> 3) & 7;
2298 mod = (modrm >> 6) & 3;
2299 gen_op_mov_TN_reg[ot][1][reg]();
2300 if (mod == 3) {
2301 rm = modrm & 7;
2302 gen_op_mov_TN_reg[ot][0][rm]();
2303 gen_op_cmpxchg_T0_T1_EAX_cc[ot]();
2304 gen_op_mov_reg_T0[ot][rm]();
2305 } else {
2306 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2307 gen_op_ld_T0_A0[ot + s->mem_index]();
4f31916f 2308 gen_op_cmpxchg_mem_T0_T1_EAX_cc[ot + s->mem_index]();
2c0262af
FB		 2309 }
2310 s->cc_op = CC_OP_SUBB + ot;
2311 break;
2312 case 0x1c7: /* cmpxchg8b */
61382a50 2313 modrm = ldub_code(s->pc++);
2c0262af
FB		 2314 mod = (modrm >> 6) & 3;
2315 if (mod == 3)
2316 goto illegal_op;
2317 if (s->cc_op != CC_OP_DYNAMIC)
2318 gen_op_set_cc_op(s->cc_op);
2319 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2320 gen_op_cmpxchg8b();
2321 s->cc_op = CC_OP_EFLAGS;
2322 break;
2323
2324 /**************************/
2325 /* push/pop */
2326 case 0x50 ... 0x57: /* push */
2327 gen_op_mov_TN_reg[OT_LONG][0][b & 7]();
2328 gen_push_T0(s);
2329 break;
2330 case 0x58 ... 0x5f: /* pop */
2331 ot = dflag ? OT_LONG : OT_WORD;
2332 gen_pop_T0(s);
77729c24 2333 /* NOTE: order is important for pop %sp */
2c0262af 2334 gen_pop_update(s);
77729c24 2335 gen_op_mov_reg_T0[ot][b & 7]();
2c0262af
FB		 2336 break;
2337 case 0x60: /* pusha */
2338 gen_pusha(s);
2339 break;
2340 case 0x61: /* popa */
2341 gen_popa(s);
2342 break;
2343 case 0x68: /* push Iv */
2344 case 0x6a:
2345 ot = dflag ? OT_LONG : OT_WORD;
2346 if (b == 0x68)
2347 val = insn_get(s, ot);
2348 else
2349 val = (int8_t)insn_get(s, OT_BYTE);
2350 gen_op_movl_T0_im(val);
2351 gen_push_T0(s);
2352 break;
2353 case 0x8f: /* pop Ev */
2354 ot = dflag ? OT_LONG : OT_WORD;
61382a50 2355 modrm = ldub_code(s->pc++);
77729c24 2356 mod = (modrm >> 6) & 3;
2c0262af 2357 gen_pop_T0(s);
77729c24
FB		 2358 if (mod == 3) {
2359 /* NOTE: order is important for pop %sp */
2360 gen_pop_update(s);
2361 rm = modrm & 7;
2362 gen_op_mov_reg_T0[ot][rm]();
2363 } else {
2364 /* NOTE: order is important too for MMU exceptions */
2365 s->popl_esp_hack = 2 << dflag;
2366 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
2367 s->popl_esp_hack = 0;
2368 gen_pop_update(s);
2369 }
2c0262af
FB		 2370 break;
2371 case 0xc8: /* enter */
2372 {
2373 int level;
61382a50 2374 val = lduw_code(s->pc);
2c0262af 2375 s->pc += 2;
61382a50 2376 level = ldub_code(s->pc++);
2c0262af
FB		 2377 gen_enter(s, val, level);
2378 }
2379 break;
2380 case 0xc9: /* leave */
2381 /* XXX: exception not precise (ESP is updated before potential exception) */
2382 if (s->ss32) {
2383 gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
2384 gen_op_mov_reg_T0[OT_LONG][R_ESP]();
2385 } else {
2386 gen_op_mov_TN_reg[OT_WORD][0][R_EBP]();
2387 gen_op_mov_reg_T0[OT_WORD][R_ESP]();
2388 }
2389 gen_pop_T0(s);
2390 ot = dflag ? OT_LONG : OT_WORD;
2391 gen_op_mov_reg_T0[ot][R_EBP]();
2392 gen_pop_update(s);
2393 break;
2394 case 0x06: /* push es */
2395 case 0x0e: /* push cs */
2396 case 0x16: /* push ss */
2397 case 0x1e: /* push ds */
2398 gen_op_movl_T0_seg(b >> 3);
2399 gen_push_T0(s);
2400 break;
2401 case 0x1a0: /* push fs */
2402 case 0x1a8: /* push gs */
2403 gen_op_movl_T0_seg((b >> 3) & 7);
2404 gen_push_T0(s);
2405 break;
2406 case 0x07: /* pop es */
2407 case 0x17: /* pop ss */
2408 case 0x1f: /* pop ds */
2409 reg = b >> 3;
2410 gen_pop_T0(s);
2411 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
2412 gen_pop_update(s);
2413 if (reg == R_SS) {
a2cc3b24
FB		 2414 /* if reg == SS, inhibit interrupts/trace. */
2415 /* If several instructions disable interrupts, only the
2416 _first_ does it */
2417 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
2418 gen_op_set_inhibit_irq();
2c0262af
FB		 2419 s->tf = 0;
2420 }
2421 if (s->is_jmp) {
2422 gen_op_jmp_im(s->pc - s->cs_base);
2423 gen_eob(s);
2424 }
2425 break;
2426 case 0x1a1: /* pop fs */
2427 case 0x1a9: /* pop gs */
2428 gen_pop_T0(s);
2429 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
2430 gen_pop_update(s);
2431 if (s->is_jmp) {
2432 gen_op_jmp_im(s->pc - s->cs_base);
2433 gen_eob(s);
2434 }
2435 break;
2436
2437 /**************************/
2438 /* mov */
2439 case 0x88:
2440 case 0x89: /* mov Gv, Ev */
2441 if ((b & 1) == 0)
2442 ot = OT_BYTE;
2443 else
2444 ot = dflag ? OT_LONG : OT_WORD;
61382a50 2445 modrm = ldub_code(s->pc++);
2c0262af
FB		 2446 reg = (modrm >> 3) & 7;
2447
2448 /* generate a generic store */
2449 gen_ldst_modrm(s, modrm, ot, OR_EAX + reg, 1);
2450 break;
2451 case 0xc6:
2452 case 0xc7: /* mov Ev, Iv */
2453 if ((b & 1) == 0)
2454 ot = OT_BYTE;
2455 else
2456 ot = dflag ? OT_LONG : OT_WORD;
61382a50 2457 modrm = ldub_code(s->pc++);
2c0262af
FB		 2458 mod = (modrm >> 6) & 3;
2459 if (mod != 3)
2460 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2461 val = insn_get(s, ot);
2462 gen_op_movl_T0_im(val);
2463 if (mod != 3)
2464 gen_op_st_T0_A0[ot + s->mem_index]();
2465 else
2466 gen_op_mov_reg_T0[ot][modrm & 7]();
2467 break;
2468 case 0x8a:
2469 case 0x8b: /* mov Ev, Gv */
2470 if ((b & 1) == 0)
2471 ot = OT_BYTE;
2472 else
2473 ot = dflag ? OT_LONG : OT_WORD;
61382a50 2474 modrm = ldub_code(s->pc++);
2c0262af
FB		 2475 reg = (modrm >> 3) & 7;
2476
2477 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2478 gen_op_mov_reg_T0[ot][reg]();
2479 break;
2480 case 0x8e: /* mov seg, Gv */
61382a50 2481 modrm = ldub_code(s->pc++);
2c0262af
FB		 2482 reg = (modrm >> 3) & 7;
2483 if (reg >= 6 || reg == R_CS)
2484 goto illegal_op;
2485 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
2486 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
2487 if (reg == R_SS) {
2488 /* if reg == SS, inhibit interrupts/trace */
a2cc3b24
FB		 2489 /* If several instructions disable interrupts, only the
2490 _first_ does it */
2491 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
2492 gen_op_set_inhibit_irq();
2c0262af
FB		 2493 s->tf = 0;
2494 }
2495 if (s->is_jmp) {
2496 gen_op_jmp_im(s->pc - s->cs_base);
2497 gen_eob(s);
2498 }
2499 break;
2500 case 0x8c: /* mov Gv, seg */
61382a50 2501 modrm = ldub_code(s->pc++);
2c0262af
FB		 2502 reg = (modrm >> 3) & 7;
2503 mod = (modrm >> 6) & 3;
2504 if (reg >= 6)
2505 goto illegal_op;
2506 gen_op_movl_T0_seg(reg);
2507 ot = OT_WORD;
2508 if (mod == 3 && dflag)
2509 ot = OT_LONG;
2510 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
2511 break;
2512
2513 case 0x1b6: /* movzbS Gv, Eb */
2514 case 0x1b7: /* movzwS Gv, Eb */
2515 case 0x1be: /* movsbS Gv, Eb */
2516 case 0x1bf: /* movswS Gv, Eb */
2517 {
2518 int d_ot;
2519 /* d_ot is the size of destination */
2520 d_ot = dflag + OT_WORD;
2521 /* ot is the size of source */
2522 ot = (b & 1) + OT_BYTE;
61382a50 2523 modrm = ldub_code(s->pc++);
2c0262af
FB		 2524 reg = ((modrm >> 3) & 7) + OR_EAX;
2525 mod = (modrm >> 6) & 3;
2526 rm = modrm & 7;
2527
2528 if (mod == 3) {
2529 gen_op_mov_TN_reg[ot][0][rm]();
2530 switch(ot | (b & 8)) {
2531 case OT_BYTE:
2532 gen_op_movzbl_T0_T0();
2533 break;
2534 case OT_BYTE | 8:
2535 gen_op_movsbl_T0_T0();
2536 break;
2537 case OT_WORD:
2538 gen_op_movzwl_T0_T0();
2539 break;
2540 default:
2541 case OT_WORD | 8:
2542 gen_op_movswl_T0_T0();
2543 break;
2544 }
2545 gen_op_mov_reg_T0[d_ot][reg]();
2546 } else {
2547 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2548 if (b & 8) {
2549 gen_op_lds_T0_A0[ot + s->mem_index]();
2550 } else {
2551 gen_op_ldu_T0_A0[ot + s->mem_index]();
2552 }
2553 gen_op_mov_reg_T0[d_ot][reg]();
2554 }
2555 }
2556 break;
2557
2558 case 0x8d: /* lea */
2559 ot = dflag ? OT_LONG : OT_WORD;
61382a50 2560 modrm = ldub_code(s->pc++);
3a1d9b8b
FB		 2561 mod = (modrm >> 6) & 3;
2562 if (mod == 3)
2563 goto illegal_op;
2c0262af
FB		 2564 reg = (modrm >> 3) & 7;
2565 /* we must ensure that no segment is added */
2566 s->override = -1;
2567 val = s->addseg;
2568 s->addseg = 0;
2569 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2570 s->addseg = val;
2571 gen_op_mov_reg_A0[ot - OT_WORD][reg]();
2572 break;
2573
2574 case 0xa0: /* mov EAX, Ov */
2575 case 0xa1:
2576 case 0xa2: /* mov Ov, EAX */
2577 case 0xa3:
2578 if ((b & 1) == 0)
2579 ot = OT_BYTE;
2580 else
2581 ot = dflag ? OT_LONG : OT_WORD;
2582 if (s->aflag)
2583 offset_addr = insn_get(s, OT_LONG);
2584 else
2585 offset_addr = insn_get(s, OT_WORD);
2586 gen_op_movl_A0_im(offset_addr);
2587 /* handle override */
2588 {
2589 int override, must_add_seg;
2590 must_add_seg = s->addseg;
2591 if (s->override >= 0) {
2592 override = s->override;
2593 must_add_seg = 1;
2594 } else {
2595 override = R_DS;
2596 }
2597 if (must_add_seg) {
2598 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
2599 }
2600 }
2601 if ((b & 2) == 0) {
2602 gen_op_ld_T0_A0[ot + s->mem_index]();
2603 gen_op_mov_reg_T0[ot][R_EAX]();
2604 } else {
2605 gen_op_mov_TN_reg[ot][0][R_EAX]();
2606 gen_op_st_T0_A0[ot + s->mem_index]();
2607 }
2608 break;
2609 case 0xd7: /* xlat */
2610 gen_op_movl_A0_reg[R_EBX]();
2611 gen_op_addl_A0_AL();
2612 if (s->aflag == 0)
2613 gen_op_andl_A0_ffff();
2614 /* handle override */
2615 {
2616 int override, must_add_seg;
2617 must_add_seg = s->addseg;
2618 override = R_DS;
2619 if (s->override >= 0) {
2620 override = s->override;
2621 must_add_seg = 1;
2622 } else {
2623 override = R_DS;
2624 }
2625 if (must_add_seg) {
2626 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
2627 }
2628 }
2629 gen_op_ldu_T0_A0[OT_BYTE + s->mem_index]();
2630 gen_op_mov_reg_T0[OT_BYTE][R_EAX]();
2631 break;
2632 case 0xb0 ... 0xb7: /* mov R, Ib */
2633 val = insn_get(s, OT_BYTE);
2634 gen_op_movl_T0_im(val);
2635 gen_op_mov_reg_T0[OT_BYTE][b & 7]();
2636 break;
2637 case 0xb8 ... 0xbf: /* mov R, Iv */
2638 ot = dflag ? OT_LONG : OT_WORD;
2639 val = insn_get(s, ot);
2640 reg = OR_EAX + (b & 7);
2641 gen_op_movl_T0_im(val);
2642 gen_op_mov_reg_T0[ot][reg]();
2643 break;
2644
2645 case 0x91 ... 0x97: /* xchg R, EAX */
2646 ot = dflag ? OT_LONG : OT_WORD;
2647 reg = b & 7;
2648 rm = R_EAX;
2649 goto do_xchg_reg;
2650 case 0x86:
2651 case 0x87: /* xchg Ev, Gv */
2652 if ((b & 1) == 0)
2653 ot = OT_BYTE;
2654 else
2655 ot = dflag ? OT_LONG : OT_WORD;
61382a50 2656 modrm = ldub_code(s->pc++);
2c0262af
FB		 2657 reg = (modrm >> 3) & 7;
2658 mod = (modrm >> 6) & 3;
2659 if (mod == 3) {
2660 rm = modrm & 7;
2661 do_xchg_reg:
2662 gen_op_mov_TN_reg[ot][0][reg]();
2663 gen_op_mov_TN_reg[ot][1][rm]();
2664 gen_op_mov_reg_T0[ot][rm]();
2665 gen_op_mov_reg_T1[ot][reg]();
2666 } else {
2667 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2668 gen_op_mov_TN_reg[ot][0][reg]();
2669 /* for xchg, lock is implicit */
2670 if (!(prefixes & PREFIX_LOCK))
2671 gen_op_lock();
2672 gen_op_ld_T1_A0[ot + s->mem_index]();
2673 gen_op_st_T0_A0[ot + s->mem_index]();
2674 if (!(prefixes & PREFIX_LOCK))
2675 gen_op_unlock();
2676 gen_op_mov_reg_T1[ot][reg]();
2677 }
2678 break;
2679 case 0xc4: /* les Gv */
2680 op = R_ES;
2681 goto do_lxx;
2682 case 0xc5: /* lds Gv */
2683 op = R_DS;
2684 goto do_lxx;
2685 case 0x1b2: /* lss Gv */
2686 op = R_SS;
2687 goto do_lxx;
2688 case 0x1b4: /* lfs Gv */
2689 op = R_FS;
2690 goto do_lxx;
2691 case 0x1b5: /* lgs Gv */
2692 op = R_GS;
2693 do_lxx:
2694 ot = dflag ? OT_LONG : OT_WORD;
61382a50 2695 modrm = ldub_code(s->pc++);
2c0262af
FB		 2696 reg = (modrm >> 3) & 7;
2697 mod = (modrm >> 6) & 3;
2698 if (mod == 3)
2699 goto illegal_op;
2700 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2701 gen_op_ld_T1_A0[ot + s->mem_index]();
2702 gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
2703 /* load the segment first to handle exceptions properly */
61382a50 2704 gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
2c0262af
FB		 2705 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
2706 /* then put the data */
2707 gen_op_mov_reg_T1[ot][reg]();
2708 if (s->is_jmp) {
2709 gen_op_jmp_im(s->pc - s->cs_base);
2710 gen_eob(s);
2711 }
2712 break;
2713
2714 /************************/
2715 /* shifts */
2716 case 0xc0:
2717 case 0xc1:
2718 /* shift Ev,Ib */
2719 shift = 2;
2720 grp2:
2721 {
2722 if ((b & 1) == 0)
2723 ot = OT_BYTE;
2724 else
2725 ot = dflag ? OT_LONG : OT_WORD;
2726
61382a50 2727 modrm = ldub_code(s->pc++);
2c0262af
FB		 2728 mod = (modrm >> 6) & 3;
2729 rm = modrm & 7;
2730 op = (modrm >> 3) & 7;
2731
2732 if (mod != 3) {
2733 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2734 opreg = OR_TMP0;
2735 } else {
2736 opreg = rm + OR_EAX;
2737 }
2738
2739 /* simpler op */
2740 if (shift == 0) {
2741 gen_shift(s, op, ot, opreg, OR_ECX);
2742 } else {
2743 if (shift == 2) {
61382a50 2744 shift = ldub_code(s->pc++);
2c0262af
FB		 2745 }
2746 gen_shifti(s, op, ot, opreg, shift);
2747 }
2748 }
2749 break;
2750 case 0xd0:
2751 case 0xd1:
2752 /* shift Ev,1 */
2753 shift = 1;
2754 goto grp2;
2755 case 0xd2:
2756 case 0xd3:
2757 /* shift Ev,cl */
2758 shift = 0;
2759 goto grp2;
2760
2761 case 0x1a4: /* shld imm */
2762 op = 0;
2763 shift = 1;
2764 goto do_shiftd;
2765 case 0x1a5: /* shld cl */
2766 op = 0;
2767 shift = 0;
2768 goto do_shiftd;
2769 case 0x1ac: /* shrd imm */
2770 op = 1;
2771 shift = 1;
2772 goto do_shiftd;
2773 case 0x1ad: /* shrd cl */
2774 op = 1;
2775 shift = 0;
2776 do_shiftd:
2777 ot = dflag ? OT_LONG : OT_WORD;
61382a50 2778 modrm = ldub_code(s->pc++);
2c0262af
FB		 2779 mod = (modrm >> 6) & 3;
2780 rm = modrm & 7;
2781 reg = (modrm >> 3) & 7;
2782
2783 if (mod != 3) {
2784 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2785 gen_op_ld_T0_A0[ot + s->mem_index]();
2786 } else {
2787 gen_op_mov_TN_reg[ot][0][rm]();
2788 }
2789 gen_op_mov_TN_reg[ot][1][reg]();
2790
2791 if (shift) {
61382a50 2792 val = ldub_code(s->pc++);
2c0262af
FB		 2793 val &= 0x1f;
2794 if (val) {
2795 if (mod == 3)
4f31916f 2796 gen_op_shiftd_T0_T1_im_cc[ot][op](val);
2c0262af 2797 else
4f31916f 2798 gen_op_shiftd_mem_T0_T1_im_cc[ot + s->mem_index][op](val);
2c0262af
FB		 2799 if (op == 0 && ot != OT_WORD)
2800 s->cc_op = CC_OP_SHLB + ot;
2801 else
2802 s->cc_op = CC_OP_SARB + ot;
2803 }
2804 } else {
2805 if (s->cc_op != CC_OP_DYNAMIC)
2806 gen_op_set_cc_op(s->cc_op);
2807 if (mod == 3)
4f31916f 2808 gen_op_shiftd_T0_T1_ECX_cc[ot][op]();
2c0262af 2809 else
4f31916f 2810 gen_op_shiftd_mem_T0_T1_ECX_cc[ot + s->mem_index][op]();
2c0262af
FB		 2811 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
2812 }
2813 if (mod == 3) {
2814 gen_op_mov_reg_T0[ot][rm]();
2815 }
2816 break;
2817
2818 /************************/
2819 /* floats */
2820 case 0xd8 ... 0xdf:
7eee2a50
FB		 2821 if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
2822 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
2823 /* XXX: what to do if illegal op ? */
2824 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
2825 break;
2826 }
61382a50 2827 modrm = ldub_code(s->pc++);
2c0262af
FB		 2828 mod = (modrm >> 6) & 3;
2829 rm = modrm & 7;
2830 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
2c0262af
FB		 2831 if (mod != 3) {
2832 /* memory op */
2833 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2834 switch(op) {
2835 case 0x00 ... 0x07: /* fxxxs */
2836 case 0x10 ... 0x17: /* fixxxl */
2837 case 0x20 ... 0x27: /* fxxxl */
2838 case 0x30 ... 0x37: /* fixxx */
2839 {
2840 int op1;
2841 op1 = op & 7;
2842
2843 switch(op >> 4) {
2844 case 0:
2845 gen_op_flds_FT0_A0();
2846 break;
2847 case 1:
2848 gen_op_fildl_FT0_A0();
2849 break;
2850 case 2:
2851 gen_op_fldl_FT0_A0();
2852 break;
2853 case 3:
2854 default:
2855 gen_op_fild_FT0_A0();
2856 break;
2857 }
2858
2859 gen_op_fp_arith_ST0_FT0[op1]();
2860 if (op1 == 3) {
2861 /* fcomp needs pop */
2862 gen_op_fpop();
2863 }
2864 }
2865 break;
2866 case 0x08: /* flds */
2867 case 0x0a: /* fsts */
2868 case 0x0b: /* fstps */
2869 case 0x18: /* fildl */
2870 case 0x1a: /* fistl */
2871 case 0x1b: /* fistpl */
2872 case 0x28: /* fldl */
2873 case 0x2a: /* fstl */
2874 case 0x2b: /* fstpl */
2875 case 0x38: /* filds */
2876 case 0x3a: /* fists */
2877 case 0x3b: /* fistps */
2878
2879 switch(op & 7) {
2880 case 0:
2881 switch(op >> 4) {
2882 case 0:
2883 gen_op_flds_ST0_A0();
2884 break;
2885 case 1:
2886 gen_op_fildl_ST0_A0();
2887 break;
2888 case 2:
2889 gen_op_fldl_ST0_A0();
2890 break;
2891 case 3:
2892 default:
2893 gen_op_fild_ST0_A0();
2894 break;
2895 }
2896 break;
2897 default:
2898 switch(op >> 4) {
2899 case 0:
2900 gen_op_fsts_ST0_A0();
2901 break;
2902 case 1:
2903 gen_op_fistl_ST0_A0();
2904 break;
2905 case 2:
2906 gen_op_fstl_ST0_A0();
2907 break;
2908 case 3:
2909 default:
2910 gen_op_fist_ST0_A0();
2911 break;
2912 }
2913 if ((op & 7) == 3)
2914 gen_op_fpop();
2915 break;
2916 }
2917 break;
2918 case 0x0c: /* fldenv mem */
2919 gen_op_fldenv_A0(s->dflag);
2920 break;
2921 case 0x0d: /* fldcw mem */
2922 gen_op_fldcw_A0();
2923 break;
2924 case 0x0e: /* fnstenv mem */
2925 gen_op_fnstenv_A0(s->dflag);
2926 break;
2927 case 0x0f: /* fnstcw mem */
2928 gen_op_fnstcw_A0();
2929 break;
2930 case 0x1d: /* fldt mem */
2931 gen_op_fldt_ST0_A0();
2932 break;
2933 case 0x1f: /* fstpt mem */
2934 gen_op_fstt_ST0_A0();
2935 gen_op_fpop();
2936 break;
2937 case 0x2c: /* frstor mem */
2938 gen_op_frstor_A0(s->dflag);
2939 break;
2940 case 0x2e: /* fnsave mem */
2941 gen_op_fnsave_A0(s->dflag);
2942 break;
2943 case 0x2f: /* fnstsw mem */
2944 gen_op_fnstsw_A0();
2945 break;
2946 case 0x3c: /* fbld */
2947 gen_op_fbld_ST0_A0();
2948 break;
2949 case 0x3e: /* fbstp */
2950 gen_op_fbst_ST0_A0();
2951 gen_op_fpop();
2952 break;
2953 case 0x3d: /* fildll */
2954 gen_op_fildll_ST0_A0();
2955 break;
2956 case 0x3f: /* fistpll */
2957 gen_op_fistll_ST0_A0();
2958 gen_op_fpop();
2959 break;
2960 default:
2961 goto illegal_op;
2962 }
2963 } else {
2964 /* register float ops */
2965 opreg = rm;
2966
2967 switch(op) {
2968 case 0x08: /* fld sti */
2969 gen_op_fpush();
2970 gen_op_fmov_ST0_STN((opreg + 1) & 7);
2971 break;
2972 case 0x09: /* fxchg sti */
2973 gen_op_fxchg_ST0_STN(opreg);
2974 break;
2975 case 0x0a: /* grp d9/2 */
2976 switch(rm) {
2977 case 0: /* fnop */
023fe10d
FB		 2978 /* check exceptions (FreeBSD FPU probe) */
2979 if (s->cc_op != CC_OP_DYNAMIC)
2980 gen_op_set_cc_op(s->cc_op);
2981 gen_op_jmp_im(pc_start - s->cs_base);
2982 gen_op_fwait();
2c0262af
FB		 2983 break;
2984 default:
2985 goto illegal_op;
2986 }
2987 break;
2988 case 0x0c: /* grp d9/4 */
2989 switch(rm) {
2990 case 0: /* fchs */
2991 gen_op_fchs_ST0();
2992 break;
2993 case 1: /* fabs */
2994 gen_op_fabs_ST0();
2995 break;
2996 case 4: /* ftst */
2997 gen_op_fldz_FT0();
2998 gen_op_fcom_ST0_FT0();
2999 break;
3000 case 5: /* fxam */
3001 gen_op_fxam_ST0();
3002 break;
3003 default:
3004 goto illegal_op;
3005 }
3006 break;
3007 case 0x0d: /* grp d9/5 */
3008 {
3009 switch(rm) {
3010 case 0:
3011 gen_op_fpush();
3012 gen_op_fld1_ST0();
3013 break;
3014 case 1:
3015 gen_op_fpush();
3016 gen_op_fldl2t_ST0();
3017 break;
3018 case 2:
3019 gen_op_fpush();
3020 gen_op_fldl2e_ST0();
3021 break;
3022 case 3:
3023 gen_op_fpush();
3024 gen_op_fldpi_ST0();
3025 break;
3026 case 4:
3027 gen_op_fpush();
3028 gen_op_fldlg2_ST0();
3029 break;
3030 case 5:
3031 gen_op_fpush();
3032 gen_op_fldln2_ST0();
3033 break;
3034 case 6:
3035 gen_op_fpush();
3036 gen_op_fldz_ST0();
3037 break;
3038 default:
3039 goto illegal_op;
3040 }
3041 }
3042 break;
3043 case 0x0e: /* grp d9/6 */
3044 switch(rm) {
3045 case 0: /* f2xm1 */
3046 gen_op_f2xm1();
3047 break;
3048 case 1: /* fyl2x */
3049 gen_op_fyl2x();
3050 break;
3051 case 2: /* fptan */
3052 gen_op_fptan();
3053 break;
3054 case 3: /* fpatan */
3055 gen_op_fpatan();
3056 break;
3057 case 4: /* fxtract */
3058 gen_op_fxtract();
3059 break;
3060 case 5: /* fprem1 */
3061 gen_op_fprem1();
3062 break;
3063 case 6: /* fdecstp */
3064 gen_op_fdecstp();
3065 break;
3066 default:
3067 case 7: /* fincstp */
3068 gen_op_fincstp();
3069 break;
3070 }
3071 break;
3072 case 0x0f: /* grp d9/7 */
3073 switch(rm) {
3074 case 0: /* fprem */
3075 gen_op_fprem();
3076 break;
3077 case 1: /* fyl2xp1 */
3078 gen_op_fyl2xp1();
3079 break;
3080 case 2: /* fsqrt */
3081 gen_op_fsqrt();
3082 break;
3083 case 3: /* fsincos */
3084 gen_op_fsincos();
3085 break;
3086 case 5: /* fscale */
3087 gen_op_fscale();
3088 break;
3089 case 4: /* frndint */
3090 gen_op_frndint();
3091 break;
3092 case 6: /* fsin */
3093 gen_op_fsin();
3094 break;
3095 default:
3096 case 7: /* fcos */
3097 gen_op_fcos();
3098 break;
3099 }
3100 break;
3101 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
3102 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
3103 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
3104 {
3105 int op1;
3106
3107 op1 = op & 7;
3108 if (op >= 0x20) {
3109 gen_op_fp_arith_STN_ST0[op1](opreg);
3110 if (op >= 0x30)
3111 gen_op_fpop();
3112 } else {
3113 gen_op_fmov_FT0_STN(opreg);
3114 gen_op_fp_arith_ST0_FT0[op1]();
3115 }
3116 }
3117 break;
3118 case 0x02: /* fcom */
3119 gen_op_fmov_FT0_STN(opreg);
3120 gen_op_fcom_ST0_FT0();
3121 break;
3122 case 0x03: /* fcomp */
3123 gen_op_fmov_FT0_STN(opreg);
3124 gen_op_fcom_ST0_FT0();
3125 gen_op_fpop();
3126 break;
3127 case 0x15: /* da/5 */
3128 switch(rm) {
3129 case 1: /* fucompp */
3130 gen_op_fmov_FT0_STN(1);
3131 gen_op_fucom_ST0_FT0();
3132 gen_op_fpop();
3133 gen_op_fpop();
3134 break;
3135 default:
3136 goto illegal_op;
3137 }
3138 break;
3139 case 0x1c:
3140 switch(rm) {
3141 case 0: /* feni (287 only, just do nop here) */
3142 break;
3143 case 1: /* fdisi (287 only, just do nop here) */
3144 break;
3145 case 2: /* fclex */
3146 gen_op_fclex();
3147 break;
3148 case 3: /* fninit */
3149 gen_op_fninit();
3150 break;
3151 case 4: /* fsetpm (287 only, just do nop here) */
3152 break;
3153 default:
3154 goto illegal_op;
3155 }
3156 break;
3157 case 0x1d: /* fucomi */
3158 if (s->cc_op != CC_OP_DYNAMIC)
3159 gen_op_set_cc_op(s->cc_op);
3160 gen_op_fmov_FT0_STN(opreg);
3161 gen_op_fucomi_ST0_FT0();
3162 s->cc_op = CC_OP_EFLAGS;
3163 break;
3164 case 0x1e: /* fcomi */
3165 if (s->cc_op != CC_OP_DYNAMIC)
3166 gen_op_set_cc_op(s->cc_op);
3167 gen_op_fmov_FT0_STN(opreg);
3168 gen_op_fcomi_ST0_FT0();
3169 s->cc_op = CC_OP_EFLAGS;
3170 break;
658c8bda
FB		 3171 case 0x28: /* ffree sti */
3172 gen_op_ffree_STN(opreg);
3173 break;
2c0262af
FB		 3174 case 0x2a: /* fst sti */
3175 gen_op_fmov_STN_ST0(opreg);
3176 break;
3177 case 0x2b: /* fstp sti */
3178 gen_op_fmov_STN_ST0(opreg);
3179 gen_op_fpop();
3180 break;
3181 case 0x2c: /* fucom st(i) */
3182 gen_op_fmov_FT0_STN(opreg);
3183 gen_op_fucom_ST0_FT0();
3184 break;
3185 case 0x2d: /* fucomp st(i) */
3186 gen_op_fmov_FT0_STN(opreg);
3187 gen_op_fucom_ST0_FT0();
3188 gen_op_fpop();
3189 break;
3190 case 0x33: /* de/3 */
3191 switch(rm) {
3192 case 1: /* fcompp */
3193 gen_op_fmov_FT0_STN(1);
3194 gen_op_fcom_ST0_FT0();
3195 gen_op_fpop();
3196 gen_op_fpop();
3197 break;
3198 default:
3199 goto illegal_op;
3200 }
3201 break;
3202 case 0x3c: /* df/4 */
3203 switch(rm) {
3204 case 0:
3205 gen_op_fnstsw_EAX();
3206 break;
3207 default:
3208 goto illegal_op;
3209 }
3210 break;
3211 case 0x3d: /* fucomip */
3212 if (s->cc_op != CC_OP_DYNAMIC)
3213 gen_op_set_cc_op(s->cc_op);
3214 gen_op_fmov_FT0_STN(opreg);
3215 gen_op_fucomi_ST0_FT0();
3216 gen_op_fpop();
3217 s->cc_op = CC_OP_EFLAGS;
3218 break;
3219 case 0x3e: /* fcomip */
3220 if (s->cc_op != CC_OP_DYNAMIC)
3221 gen_op_set_cc_op(s->cc_op);
3222 gen_op_fmov_FT0_STN(opreg);
3223 gen_op_fcomi_ST0_FT0();
3224 gen_op_fpop();
3225 s->cc_op = CC_OP_EFLAGS;
3226 break;
a2cc3b24
FB		 3227 case 0x10 ... 0x13: /* fcmovxx */
3228 case 0x18 ... 0x1b:
3229 {
3230 int op1;
3231 const static uint8_t fcmov_cc[8] = {
3232 (JCC_B << 1),
3233 (JCC_Z << 1),
3234 (JCC_BE << 1),
3235 (JCC_P << 1),
3236 };
3237 op1 = fcmov_cc[op & 3] | ((op >> 3) & 1);
3238 gen_setcc(s, op1);
3239 gen_op_fcmov_ST0_STN_T0(opreg);
3240 }
3241 break;
2c0262af
FB		 3242 default:
3243 goto illegal_op;
3244 }
3245 }
7eee2a50
FB		 3246#ifdef USE_CODE_COPY
3247 s->tb->cflags |= CF_TB_FP_USED;
3248#endif
2c0262af
FB		 3249 break;
3250 /************************/
3251 /* string ops */
3252
3253 case 0xa4: /* movsS */
3254 case 0xa5:
3255 if ((b & 1) == 0)
3256 ot = OT_BYTE;
3257 else
3258 ot = dflag ? OT_LONG : OT_WORD;
3259
3260 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3261 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3262 } else {
3263 gen_movs(s, ot);
3264 }
3265 break;
3266
3267 case 0xaa: /* stosS */
3268 case 0xab:
3269 if ((b & 1) == 0)
3270 ot = OT_BYTE;
3271 else
3272 ot = dflag ? OT_LONG : OT_WORD;
3273
3274 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3275 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3276 } else {
3277 gen_stos(s, ot);
3278 }
3279 break;
3280 case 0xac: /* lodsS */
3281 case 0xad:
3282 if ((b & 1) == 0)
3283 ot = OT_BYTE;
3284 else
3285 ot = dflag ? OT_LONG : OT_WORD;
3286 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3287 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3288 } else {
3289 gen_lods(s, ot);
3290 }
3291 break;
3292 case 0xae: /* scasS */
3293 case 0xaf:
3294 if ((b & 1) == 0)
3295 ot = OT_BYTE;
3296 else
3297 ot = dflag ? OT_LONG : OT_WORD;
3298 if (prefixes & PREFIX_REPNZ) {
3299 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
3300 } else if (prefixes & PREFIX_REPZ) {
3301 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
3302 } else {
3303 gen_scas(s, ot);
3304 s->cc_op = CC_OP_SUBB + ot;
3305 }
3306 break;
3307
3308 case 0xa6: /* cmpsS */
3309 case 0xa7:
3310 if ((b & 1) == 0)
3311 ot = OT_BYTE;
3312 else
3313 ot = dflag ? OT_LONG : OT_WORD;
3314 if (prefixes & PREFIX_REPNZ) {
3315 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
3316 } else if (prefixes & PREFIX_REPZ) {
3317 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
3318 } else {
3319 gen_cmps(s, ot);
3320 s->cc_op = CC_OP_SUBB + ot;
3321 }
3322 break;
3323 case 0x6c: /* insS */
3324 case 0x6d:
f115e911
FB		 3325 if ((b & 1) == 0)
3326 ot = OT_BYTE;
3327 else
3328 ot = dflag ? OT_LONG : OT_WORD;
3329 gen_check_io(s, ot, 1, pc_start - s->cs_base);
3330 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3331 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
2c0262af 3332 } else {
f115e911 3333 gen_ins(s, ot);
2c0262af
FB		 3334 }
3335 break;
3336 case 0x6e: /* outsS */
3337 case 0x6f:
f115e911
FB		 3338 if ((b & 1) == 0)
3339 ot = OT_BYTE;
3340 else
3341 ot = dflag ? OT_LONG : OT_WORD;
3342 gen_check_io(s, ot, 1, pc_start - s->cs_base);
3343 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3344 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
2c0262af 3345 } else {
f115e911 3346 gen_outs(s, ot);
2c0262af
FB		 3347 }
3348 break;
3349
3350 /************************/
3351 /* port I/O */
3352 case 0xe4:
3353 case 0xe5:
f115e911
FB		 3354 if ((b & 1) == 0)
3355 ot = OT_BYTE;
3356 else
3357 ot = dflag ? OT_LONG : OT_WORD;
3358 val = ldub_code(s->pc++);
3359 gen_op_movl_T0_im(val);
3360 gen_check_io(s, ot, 0, pc_start - s->cs_base);
3361 gen_op_in[ot]();
3362 gen_op_mov_reg_T1[ot][R_EAX]();
2c0262af
FB		 3363 break;
3364 case 0xe6:
3365 case 0xe7:
f115e911
FB		 3366 if ((b & 1) == 0)
3367 ot = OT_BYTE;
3368 else
3369 ot = dflag ? OT_LONG : OT_WORD;
3370 val = ldub_code(s->pc++);
3371 gen_op_movl_T0_im(val);
3372 gen_check_io(s, ot, 0, pc_start - s->cs_base);
3373 gen_op_mov_TN_reg[ot][1][R_EAX]();
3374 gen_op_out[ot]();
2c0262af
FB		 3375 break;
3376 case 0xec:
3377 case 0xed:
f115e911
FB		 3378 if ((b & 1) == 0)
3379 ot = OT_BYTE;
3380 else
3381 ot = dflag ? OT_LONG : OT_WORD;
3382 gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
4f31916f 3383 gen_op_andl_T0_ffff();
f115e911
FB		 3384 gen_check_io(s, ot, 0, pc_start - s->cs_base);
3385 gen_op_in[ot]();
3386 gen_op_mov_reg_T1[ot][R_EAX]();
2c0262af
FB		 3387 break;
3388 case 0xee:
3389 case 0xef:
f115e911
FB		 3390 if ((b & 1) == 0)
3391 ot = OT_BYTE;
3392 else
3393 ot = dflag ? OT_LONG : OT_WORD;
3394 gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
4f31916f 3395 gen_op_andl_T0_ffff();
f115e911
FB		 3396 gen_check_io(s, ot, 0, pc_start - s->cs_base);
3397 gen_op_mov_TN_reg[ot][1][R_EAX]();
3398 gen_op_out[ot]();
2c0262af
FB		 3399 break;
3400
3401 /************************/
3402 /* control */
3403 case 0xc2: /* ret im */
61382a50 3404 val = ldsw_code(s->pc);
2c0262af
FB		 3405 s->pc += 2;
3406 gen_pop_T0(s);
3407 gen_stack_update(s, val + (2 << s->dflag));
3408 if (s->dflag == 0)
3409 gen_op_andl_T0_ffff();
3410 gen_op_jmp_T0();
3411 gen_eob(s);
3412 break;
3413 case 0xc3: /* ret */
3414 gen_pop_T0(s);
3415 gen_pop_update(s);
3416 if (s->dflag == 0)
3417 gen_op_andl_T0_ffff();
3418 gen_op_jmp_T0();
3419 gen_eob(s);
3420 break;
3421 case 0xca: /* lret im */
61382a50 3422 val = ldsw_code(s->pc);
2c0262af
FB		 3423 s->pc += 2;
3424 do_lret:
3425 if (s->pe && !s->vm86) {
3426 if (s->cc_op != CC_OP_DYNAMIC)
3427 gen_op_set_cc_op(s->cc_op);
3428 gen_op_jmp_im(pc_start - s->cs_base);
3429 gen_op_lret_protected(s->dflag, val);
3430 } else {
3431 gen_stack_A0(s);
3432 /* pop offset */
3433 gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
3434 if (s->dflag == 0)
3435 gen_op_andl_T0_ffff();
3436 /* NOTE: keeping EIP updated is not a problem in case of
3437 exception */
3438 gen_op_jmp_T0();
3439 /* pop selector */
3440 gen_op_addl_A0_im(2 << s->dflag);
3441 gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
3442 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
3443 /* add stack offset */
3444 gen_stack_update(s, val + (4 << s->dflag));
3445 }
3446 gen_eob(s);
3447 break;
3448 case 0xcb: /* lret */
3449 val = 0;
3450 goto do_lret;
3451 case 0xcf: /* iret */
3452 if (!s->pe) {
3453 /* real mode */
3454 gen_op_iret_real(s->dflag);
3455 s->cc_op = CC_OP_EFLAGS;
f115e911
FB		 3456 } else if (s->vm86) {
3457 if (s->iopl != 3) {
3458 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3459 } else {
3460 gen_op_iret_real(s->dflag);
3461 s->cc_op = CC_OP_EFLAGS;
3462 }
2c0262af
FB		 3463 } else {
3464 if (s->cc_op != CC_OP_DYNAMIC)
3465 gen_op_set_cc_op(s->cc_op);
3466 gen_op_jmp_im(pc_start - s->cs_base);
08cea4ee 3467 gen_op_iret_protected(s->dflag, s->pc - s->cs_base);
2c0262af
FB		 3468 s->cc_op = CC_OP_EFLAGS;
3469 }
3470 gen_eob(s);
3471 break;
3472 case 0xe8: /* call im */
3473 {
3474 unsigned int next_eip;
3475 ot = dflag ? OT_LONG : OT_WORD;
3476 val = insn_get(s, ot);
3477 next_eip = s->pc - s->cs_base;
3478 val += next_eip;
3479 if (s->dflag == 0)
3480 val &= 0xffff;
3481 gen_op_movl_T0_im(next_eip);
3482 gen_push_T0(s);
3483 gen_jmp(s, val);
3484 }
3485 break;
3486 case 0x9a: /* lcall im */
3487 {
3488 unsigned int selector, offset;
3489
3490 ot = dflag ? OT_LONG : OT_WORD;
3491 offset = insn_get(s, ot);
3492 selector = insn_get(s, OT_WORD);
3493
3494 gen_op_movl_T0_im(selector);
3495 gen_op_movl_T1_im(offset);
3496 }
3497 goto do_lcall;
3498 case 0xe9: /* jmp */
3499 ot = dflag ? OT_LONG : OT_WORD;
3500 val = insn_get(s, ot);
3501 val += s->pc - s->cs_base;
3502 if (s->dflag == 0)
3503 val = val & 0xffff;
3504 gen_jmp(s, val);
3505 break;
3506 case 0xea: /* ljmp im */
3507 {
3508 unsigned int selector, offset;
3509
3510 ot = dflag ? OT_LONG : OT_WORD;
3511 offset = insn_get(s, ot);
3512 selector = insn_get(s, OT_WORD);
3513
3514 gen_op_movl_T0_im(selector);
3515 gen_op_movl_T1_im(offset);
3516 }
3517 goto do_ljmp;
3518 case 0xeb: /* jmp Jb */
3519 val = (int8_t)insn_get(s, OT_BYTE);
3520 val += s->pc - s->cs_base;
3521 if (s->dflag == 0)
3522 val = val & 0xffff;
3523 gen_jmp(s, val);
3524 break;
3525 case 0x70 ... 0x7f: /* jcc Jb */
3526 val = (int8_t)insn_get(s, OT_BYTE);
3527 goto do_jcc;
3528 case 0x180 ... 0x18f: /* jcc Jv */
3529 if (dflag) {
3530 val = insn_get(s, OT_LONG);
3531 } else {
3532 val = (int16_t)insn_get(s, OT_WORD);
3533 }
3534 do_jcc:
3535 next_eip = s->pc - s->cs_base;
3536 val += next_eip;
3537 if (s->dflag == 0)
3538 val &= 0xffff;
3539 gen_jcc(s, b, val, next_eip);
3540 break;
3541
3542 case 0x190 ... 0x19f: /* setcc Gv */
61382a50 3543 modrm = ldub_code(s->pc++);
2c0262af
FB		 3544 gen_setcc(s, b);
3545 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
3546 break;
3547 case 0x140 ... 0x14f: /* cmov Gv, Ev */
3548 ot = dflag ? OT_LONG : OT_WORD;
61382a50 3549 modrm = ldub_code(s->pc++);
2c0262af
FB		 3550 reg = (modrm >> 3) & 7;
3551 mod = (modrm >> 6) & 3;
3552 gen_setcc(s, b);
3553 if (mod != 3) {
3554 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3555 gen_op_ld_T1_A0[ot + s->mem_index]();
3556 } else {
3557 rm = modrm & 7;
3558 gen_op_mov_TN_reg[ot][1][rm]();
3559 }
3560 gen_op_cmov_reg_T1_T0[ot - OT_WORD][reg]();
3561 break;
3562
3563 /************************/
3564 /* flags */
3565 case 0x9c: /* pushf */
3566 if (s->vm86 && s->iopl != 3) {
3567 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3568 } else {
3569 if (s->cc_op != CC_OP_DYNAMIC)
3570 gen_op_set_cc_op(s->cc_op);
3571 gen_op_movl_T0_eflags();
3572 gen_push_T0(s);
3573 }
3574 break;
3575 case 0x9d: /* popf */
3576 if (s->vm86 && s->iopl != 3) {
3577 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3578 } else {
3579 gen_pop_T0(s);
3580 if (s->cpl == 0) {
3581 if (s->dflag) {
3582 gen_op_movl_eflags_T0_cpl0();
3583 } else {
3584 gen_op_movw_eflags_T0_cpl0();
3585 }
3586 } else {
4136f33c
FB		 3587 if (s->cpl <= s->iopl) {
3588 if (s->dflag) {
3589 gen_op_movl_eflags_T0_io();
3590 } else {
3591 gen_op_movw_eflags_T0_io();
3592 }
2c0262af 3593 } else {
4136f33c
FB		 3594 if (s->dflag) {
3595 gen_op_movl_eflags_T0();
3596 } else {
3597 gen_op_movw_eflags_T0();
3598 }
2c0262af
FB		 3599 }
3600 }
3601 gen_pop_update(s);
3602 s->cc_op = CC_OP_EFLAGS;
3603 /* abort translation because TF flag may change */
3604 gen_op_jmp_im(s->pc - s->cs_base);
3605 gen_eob(s);
3606 }
3607 break;
3608 case 0x9e: /* sahf */
3609 gen_op_mov_TN_reg[OT_BYTE][0][R_AH]();
3610 if (s->cc_op != CC_OP_DYNAMIC)
3611 gen_op_set_cc_op(s->cc_op);
3612 gen_op_movb_eflags_T0();
3613 s->cc_op = CC_OP_EFLAGS;
3614 break;
3615 case 0x9f: /* lahf */
3616 if (s->cc_op != CC_OP_DYNAMIC)
3617 gen_op_set_cc_op(s->cc_op);
3618 gen_op_movl_T0_eflags();
3619 gen_op_mov_reg_T0[OT_BYTE][R_AH]();
3620 break;
3621 case 0xf5: /* cmc */
3622 if (s->cc_op != CC_OP_DYNAMIC)
3623 gen_op_set_cc_op(s->cc_op);
3624 gen_op_cmc();
3625 s->cc_op = CC_OP_EFLAGS;
3626 break;
3627 case 0xf8: /* clc */
3628 if (s->cc_op != CC_OP_DYNAMIC)
3629 gen_op_set_cc_op(s->cc_op);
3630 gen_op_clc();
3631 s->cc_op = CC_OP_EFLAGS;
3632 break;
3633 case 0xf9: /* stc */
3634 if (s->cc_op != CC_OP_DYNAMIC)
3635 gen_op_set_cc_op(s->cc_op);
3636 gen_op_stc();
3637 s->cc_op = CC_OP_EFLAGS;
3638 break;
3639 case 0xfc: /* cld */
3640 gen_op_cld();
3641 break;
3642 case 0xfd: /* std */
3643 gen_op_std();
3644 break;
3645
3646 /************************/
3647 /* bit operations */
3648 case 0x1ba: /* bt/bts/btr/btc Gv, im */
3649 ot = dflag ? OT_LONG : OT_WORD;
61382a50 3650 modrm = ldub_code(s->pc++);
2c0262af
FB		 3651 op = (modrm >> 3) & 7;
3652 mod = (modrm >> 6) & 3;
3653 rm = modrm & 7;
3654 if (mod != 3) {
3655 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3656 gen_op_ld_T0_A0[ot + s->mem_index]();
3657 } else {
3658 gen_op_mov_TN_reg[ot][0][rm]();
3659 }
3660 /* load shift */
61382a50 3661 val = ldub_code(s->pc++);
2c0262af
FB		 3662 gen_op_movl_T1_im(val);
3663 if (op < 4)
3664 goto illegal_op;
3665 op -= 4;
3666 gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
3667 s->cc_op = CC_OP_SARB + ot;
3668 if (op != 0) {
3669 if (mod != 3)
3670 gen_op_st_T0_A0[ot + s->mem_index]();
3671 else
3672 gen_op_mov_reg_T0[ot][rm]();
3673 gen_op_update_bt_cc();
3674 }
3675 break;
3676 case 0x1a3: /* bt Gv, Ev */
3677 op = 0;
3678 goto do_btx;
3679 case 0x1ab: /* bts */
3680 op = 1;
3681 goto do_btx;
3682 case 0x1b3: /* btr */
3683 op = 2;
3684 goto do_btx;
3685 case 0x1bb: /* btc */
3686 op = 3;
3687 do_btx:
3688 ot = dflag ? OT_LONG : OT_WORD;
61382a50 3689 modrm = ldub_code(s->pc++);
2c0262af
FB		 3690 reg = (modrm >> 3) & 7;
3691 mod = (modrm >> 6) & 3;
3692 rm = modrm & 7;
3693 gen_op_mov_TN_reg[OT_LONG][1][reg]();
3694 if (mod != 3) {
3695 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3696 /* specific case: we need to add a displacement */
3697 if (ot == OT_WORD)
3698 gen_op_add_bitw_A0_T1();
3699 else
3700 gen_op_add_bitl_A0_T1();
3701 gen_op_ld_T0_A0[ot + s->mem_index]();
3702 } else {
3703 gen_op_mov_TN_reg[ot][0][rm]();
3704 }
3705 gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
3706 s->cc_op = CC_OP_SARB + ot;
3707 if (op != 0) {
3708 if (mod != 3)
3709 gen_op_st_T0_A0[ot + s->mem_index]();
3710 else
3711 gen_op_mov_reg_T0[ot][rm]();
3712 gen_op_update_bt_cc();
3713 }
3714 break;
3715 case 0x1bc: /* bsf */
3716 case 0x1bd: /* bsr */
3717 ot = dflag ? OT_LONG : OT_WORD;
61382a50 3718 modrm = ldub_code(s->pc++);
2c0262af
FB		 3719 reg = (modrm >> 3) & 7;
3720 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
686f3f26
FB		 3721 /* NOTE: in order to handle the 0 case, we must load the
3722 result. It could be optimized with a generated jump */
3723 gen_op_mov_TN_reg[ot][1][reg]();
2c0262af 3724 gen_op_bsx_T0_cc[ot - OT_WORD][b & 1]();
686f3f26 3725 gen_op_mov_reg_T1[ot][reg]();
2c0262af
FB		 3726 s->cc_op = CC_OP_LOGICB + ot;
3727 break;
3728 /************************/
3729 /* bcd */
3730 case 0x27: /* daa */
3731 if (s->cc_op != CC_OP_DYNAMIC)
3732 gen_op_set_cc_op(s->cc_op);
3733 gen_op_daa();
3734 s->cc_op = CC_OP_EFLAGS;
3735 break;
3736 case 0x2f: /* das */
3737 if (s->cc_op != CC_OP_DYNAMIC)
3738 gen_op_set_cc_op(s->cc_op);
3739 gen_op_das();
3740 s->cc_op = CC_OP_EFLAGS;
3741 break;
3742 case 0x37: /* aaa */
3743 if (s->cc_op != CC_OP_DYNAMIC)
3744 gen_op_set_cc_op(s->cc_op);
3745 gen_op_aaa();
3746 s->cc_op = CC_OP_EFLAGS;
3747 break;
3748 case 0x3f: /* aas */
3749 if (s->cc_op != CC_OP_DYNAMIC)
3750 gen_op_set_cc_op(s->cc_op);
3751 gen_op_aas();
3752 s->cc_op = CC_OP_EFLAGS;
3753 break;
3754 case 0xd4: /* aam */
61382a50 3755 val = ldub_code(s->pc++);
2c0262af
FB		 3756 gen_op_aam(val);
3757 s->cc_op = CC_OP_LOGICB;
3758 break;
3759 case 0xd5: /* aad */
61382a50 3760 val = ldub_code(s->pc++);
2c0262af
FB		 3761 gen_op_aad(val);
3762 s->cc_op = CC_OP_LOGICB;
3763 break;
3764 /************************/
3765 /* misc */
3766 case 0x90: /* nop */
ab1f142b
FB		 3767 /* XXX: correct lock test for all insn */
3768 if (prefixes & PREFIX_LOCK)
3769 goto illegal_op;
2c0262af
FB		 3770 break;
3771 case 0x9b: /* fwait */
7eee2a50
FB		 3772 if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
3773 (HF_MP_MASK | HF_TS_MASK)) {
3774 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
2ee73ac3
FB		 3775 } else {
3776 if (s->cc_op != CC_OP_DYNAMIC)
3777 gen_op_set_cc_op(s->cc_op);
3778 gen_op_jmp_im(pc_start - s->cs_base);
3779 gen_op_fwait();
7eee2a50 3780 }
2c0262af
FB		 3781 break;
3782 case 0xcc: /* int3 */
3783 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
3784 break;
3785 case 0xcd: /* int N */
61382a50 3786 val = ldub_code(s->pc++);
f115e911 3787 if (s->vm86 && s->iopl != 3) {
2c0262af 3788 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
f115e911
FB		 3789 } else {
3790 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
3791 }
2c0262af
FB		 3792 break;
3793 case 0xce: /* into */
3794 if (s->cc_op != CC_OP_DYNAMIC)
3795 gen_op_set_cc_op(s->cc_op);
3796 gen_op_into(s->pc - s->cs_base);
3797 break;
3798 case 0xf1: /* icebp (undocumented, exits to external debugger) */
3799 gen_debug(s, pc_start - s->cs_base);
3800 break;
3801 case 0xfa: /* cli */
3802 if (!s->vm86) {
3803 if (s->cpl <= s->iopl) {
3804 gen_op_cli();
3805 } else {
3806 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3807 }
3808 } else {
3809 if (s->iopl == 3) {
3810 gen_op_cli();
3811 } else {
3812 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3813 }
3814 }
3815 break;
3816 case 0xfb: /* sti */
3817 if (!s->vm86) {
3818 if (s->cpl <= s->iopl) {
3819 gen_sti:
3820 gen_op_sti();
3821 /* interruptions are enabled only the first insn after sti */
a2cc3b24
FB		 3822 /* If several instructions disable interrupts, only the
3823 _first_ does it */
3824 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
3825 gen_op_set_inhibit_irq();
2c0262af
FB		 3826 /* give a chance to handle pending irqs */
3827 gen_op_jmp_im(s->pc - s->cs_base);
3828 gen_eob(s);
3829 } else {
3830 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3831 }
3832 } else {
3833 if (s->iopl == 3) {
3834 goto gen_sti;
3835 } else {
3836 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3837 }
3838 }
3839 break;
3840 case 0x62: /* bound */
3841 ot = dflag ? OT_LONG : OT_WORD;
61382a50 3842 modrm = ldub_code(s->pc++);
2c0262af
FB		 3843 reg = (modrm >> 3) & 7;
3844 mod = (modrm >> 6) & 3;
3845 if (mod == 3)
3846 goto illegal_op;
3847 gen_op_mov_reg_T0[ot][reg]();
3848 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3849 if (ot == OT_WORD)
3850 gen_op_boundw(pc_start - s->cs_base);
3851 else
3852 gen_op_boundl(pc_start - s->cs_base);
3853 break;
3854 case 0x1c8 ... 0x1cf: /* bswap reg */
3855 reg = b & 7;
3856 gen_op_mov_TN_reg[OT_LONG][0][reg]();
3857 gen_op_bswapl_T0();
3858 gen_op_mov_reg_T0[OT_LONG][reg]();
3859 break;
3860 case 0xd6: /* salc */
3861 if (s->cc_op != CC_OP_DYNAMIC)
3862 gen_op_set_cc_op(s->cc_op);
3863 gen_op_salc();
3864 break;
3865 case 0xe0: /* loopnz */
3866 case 0xe1: /* loopz */
3867 if (s->cc_op != CC_OP_DYNAMIC)
3868 gen_op_set_cc_op(s->cc_op);
3869 /* FALL THRU */
3870 case 0xe2: /* loop */
3871 case 0xe3: /* jecxz */
3872 val = (int8_t)insn_get(s, OT_BYTE);
3873 next_eip = s->pc - s->cs_base;
3874 val += next_eip;
3875 if (s->dflag == 0)
3876 val &= 0xffff;
3877 gen_op_loop[s->aflag][b & 3](val, next_eip);
3878 gen_eob(s);
3879 break;
3880 case 0x130: /* wrmsr */
3881 case 0x132: /* rdmsr */
3882 if (s->cpl != 0) {
3883 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3884 } else {
3885 if (b & 2)
3886 gen_op_rdmsr();
3887 else
3888 gen_op_wrmsr();
3889 }
3890 break;
3891 case 0x131: /* rdtsc */
3892 gen_op_rdtsc();
3893 break;
023fe10d
FB		 3894 case 0x134: /* sysenter */
3895 if (!s->pe) {
3896 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3897 } else {
3898 if (s->cc_op != CC_OP_DYNAMIC) {
3899 gen_op_set_cc_op(s->cc_op);
3900 s->cc_op = CC_OP_DYNAMIC;
3901 }
3902 gen_op_jmp_im(pc_start - s->cs_base);
3903 gen_op_sysenter();
3904 gen_eob(s);
3905 }
3906 break;
3907 case 0x135: /* sysexit */
3908 if (!s->pe) {
3909 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3910 } else {
3911 if (s->cc_op != CC_OP_DYNAMIC) {
3912 gen_op_set_cc_op(s->cc_op);
3913 s->cc_op = CC_OP_DYNAMIC;
3914 }
3915 gen_op_jmp_im(pc_start - s->cs_base);
3916 gen_op_sysexit();
3917 gen_eob(s);
3918 }
3919 break;
2c0262af
FB		 3920 case 0x1a2: /* cpuid */
3921 gen_op_cpuid();
3922 break;
3923 case 0xf4: /* hlt */
3924 if (s->cpl != 0) {
3925 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3926 } else {
3927 if (s->cc_op != CC_OP_DYNAMIC)
3928 gen_op_set_cc_op(s->cc_op);
3929 gen_op_jmp_im(s->pc - s->cs_base);
3930 gen_op_hlt();
3931 s->is_jmp = 3;
3932 }
3933 break;
3934 case 0x100:
61382a50 3935 modrm = ldub_code(s->pc++);
2c0262af
FB		 3936 mod = (modrm >> 6) & 3;
3937 op = (modrm >> 3) & 7;
3938 switch(op) {
3939 case 0: /* sldt */
f115e911
FB		 3940 if (!s->pe || s->vm86)
3941 goto illegal_op;
2c0262af
FB		 3942 gen_op_movl_T0_env(offsetof(CPUX86State,ldt.selector));
3943 ot = OT_WORD;
3944 if (mod == 3)
3945 ot += s->dflag;
3946 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3947 break;
3948 case 2: /* lldt */
f115e911
FB		 3949 if (!s->pe || s->vm86)
3950 goto illegal_op;
2c0262af
FB		 3951 if (s->cpl != 0) {
3952 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3953 } else {
3954 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3955 gen_op_jmp_im(pc_start - s->cs_base);
3956 gen_op_lldt_T0();
3957 }
3958 break;
3959 case 1: /* str */
f115e911
FB		 3960 if (!s->pe || s->vm86)
3961 goto illegal_op;
2c0262af
FB		 3962 gen_op_movl_T0_env(offsetof(CPUX86State,tr.selector));
3963 ot = OT_WORD;
3964 if (mod == 3)
3965 ot += s->dflag;
3966 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3967 break;
3968 case 3: /* ltr */
f115e911
FB		 3969 if (!s->pe || s->vm86)
3970 goto illegal_op;
2c0262af
FB		 3971 if (s->cpl != 0) {
3972 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3973 } else {
3974 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3975 gen_op_jmp_im(pc_start - s->cs_base);
3976 gen_op_ltr_T0();
3977 }
3978 break;
3979 case 4: /* verr */
3980 case 5: /* verw */
f115e911
FB		 3981 if (!s->pe || s->vm86)
3982 goto illegal_op;
3983 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3984 if (s->cc_op != CC_OP_DYNAMIC)
3985 gen_op_set_cc_op(s->cc_op);
3986 if (op == 4)
3987 gen_op_verr();
3988 else
3989 gen_op_verw();
3990 s->cc_op = CC_OP_EFLAGS;
3991 break;
2c0262af
FB		 3992 default:
3993 goto illegal_op;
3994 }
3995 break;
3996 case 0x101:
61382a50 3997 modrm = ldub_code(s->pc++);
2c0262af
FB		 3998 mod = (modrm >> 6) & 3;
3999 op = (modrm >> 3) & 7;
4000 switch(op) {
4001 case 0: /* sgdt */
4002 case 1: /* sidt */
4003 if (mod == 3)
4004 goto illegal_op;
4005 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4006 if (op == 0)
4007 gen_op_movl_T0_env(offsetof(CPUX86State,gdt.limit));
4008 else
4009 gen_op_movl_T0_env(offsetof(CPUX86State,idt.limit));
4010 gen_op_st_T0_A0[OT_WORD + s->mem_index]();
4011 gen_op_addl_A0_im(2);
4012 if (op == 0)
4013 gen_op_movl_T0_env(offsetof(CPUX86State,gdt.base));
4014 else
4015 gen_op_movl_T0_env(offsetof(CPUX86State,idt.base));
4016 if (!s->dflag)
4017 gen_op_andl_T0_im(0xffffff);
4018 gen_op_st_T0_A0[OT_LONG + s->mem_index]();
4019 break;
4020 case 2: /* lgdt */
4021 case 3: /* lidt */
4022 if (mod == 3)
4023 goto illegal_op;
4024 if (s->cpl != 0) {
4025 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4026 } else {
4027 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4028 gen_op_ld_T1_A0[OT_WORD + s->mem_index]();
4029 gen_op_addl_A0_im(2);
4030 gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
4031 if (!s->dflag)
4032 gen_op_andl_T0_im(0xffffff);
4033 if (op == 2) {
4034 gen_op_movl_env_T0(offsetof(CPUX86State,gdt.base));
4035 gen_op_movl_env_T1(offsetof(CPUX86State,gdt.limit));
4036 } else {
4037 gen_op_movl_env_T0(offsetof(CPUX86State,idt.base));
4038 gen_op_movl_env_T1(offsetof(CPUX86State,idt.limit));
4039 }
4040 }
4041 break;
4042 case 4: /* smsw */
4043 gen_op_movl_T0_env(offsetof(CPUX86State,cr[0]));
4044 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
4045 break;
4046 case 6: /* lmsw */
4047 if (s->cpl != 0) {
4048 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4049 } else {
4050 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
4051 gen_op_lmsw_T0();
d71b9a8b
FB		 4052 gen_op_jmp_im(s->pc - s->cs_base);
4053 gen_eob(s);
2c0262af
FB		 4054 }
4055 break;
4056 case 7: /* invlpg */
4057 if (s->cpl != 0) {
4058 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4059 } else {
4060 if (mod == 3)
4061 goto illegal_op;
4062 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4063 gen_op_invlpg_A0();
3415a4dd
FB		 4064 gen_op_jmp_im(s->pc - s->cs_base);
4065 gen_eob(s);
2c0262af
FB		 4066 }
4067 break;
4068 default:
4069 goto illegal_op;
4070 }
4071 break;
3415a4dd
FB		 4072 case 0x108: /* invd */
4073 case 0x109: /* wbinvd */
4074 if (s->cpl != 0) {
4075 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4076 } else {
4077 /* nothing to do */
4078 }
4079 break;
f115e911
FB		 4080 case 0x63: /* arpl */
4081 if (!s->pe || s->vm86)
4082 goto illegal_op;
4083 ot = dflag ? OT_LONG : OT_WORD;
4084 modrm = ldub_code(s->pc++);
4085 reg = (modrm >> 3) & 7;
4086 mod = (modrm >> 6) & 3;
4087 rm = modrm & 7;
4088 if (mod != 3) {
4089 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4090 gen_op_ld_T0_A0[ot + s->mem_index]();
4091 } else {
4092 gen_op_mov_TN_reg[ot][0][rm]();
4093 }
4094 if (s->cc_op != CC_OP_DYNAMIC)
4095 gen_op_set_cc_op(s->cc_op);
4096 gen_op_arpl();
4097 s->cc_op = CC_OP_EFLAGS;
4098 if (mod != 3) {
4099 gen_op_st_T0_A0[ot + s->mem_index]();
4100 } else {
4101 gen_op_mov_reg_T0[ot][rm]();
4102 }
4103 gen_op_arpl_update();
4104 break;
2c0262af
FB		 4105 case 0x102: /* lar */
4106 case 0x103: /* lsl */
4107 if (!s->pe || s->vm86)
4108 goto illegal_op;
4109 ot = dflag ? OT_LONG : OT_WORD;
61382a50 4110 modrm = ldub_code(s->pc++);
2c0262af
FB		 4111 reg = (modrm >> 3) & 7;
4112 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4113 gen_op_mov_TN_reg[ot][1][reg]();
4114 if (s->cc_op != CC_OP_DYNAMIC)
4115 gen_op_set_cc_op(s->cc_op);
4116 if (b == 0x102)
4117 gen_op_lar();
4118 else
4119 gen_op_lsl();
4120 s->cc_op = CC_OP_EFLAGS;
4121 gen_op_mov_reg_T1[ot][reg]();
4122 break;
4123 case 0x118:
61382a50 4124 modrm = ldub_code(s->pc++);
2c0262af
FB		 4125 mod = (modrm >> 6) & 3;
4126 op = (modrm >> 3) & 7;
4127 switch(op) {
4128 case 0: /* prefetchnta */
4129 case 1: /* prefetchnt0 */
4130 case 2: /* prefetchnt0 */
4131 case 3: /* prefetchnt0 */
4132 if (mod == 3)
4133 goto illegal_op;
4134 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4135 /* nothing more to do */
4136 break;
4137 default:
4138 goto illegal_op;
4139 }
4140 break;
4141 case 0x120: /* mov reg, crN */
4142 case 0x122: /* mov crN, reg */
4143 if (s->cpl != 0) {
4144 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4145 } else {
61382a50 4146 modrm = ldub_code(s->pc++);
2c0262af
FB		 4147 if ((modrm & 0xc0) != 0xc0)
4148 goto illegal_op;
4149 rm = modrm & 7;
4150 reg = (modrm >> 3) & 7;
4151 switch(reg) {
4152 case 0:
4153 case 2:
4154 case 3:
4155 case 4:
4156 if (b & 2) {
4157 gen_op_mov_TN_reg[OT_LONG][0][rm]();
4158 gen_op_movl_crN_T0(reg);
4159 gen_op_jmp_im(s->pc - s->cs_base);
4160 gen_eob(s);
4161 } else {
4162 gen_op_movl_T0_env(offsetof(CPUX86State,cr[reg]));
4163 gen_op_mov_reg_T0[OT_LONG][rm]();
4164 }
4165 break;
4166 default:
4167 goto illegal_op;
4168 }
4169 }
4170 break;
4171 case 0x121: /* mov reg, drN */
4172 case 0x123: /* mov drN, reg */
4173 if (s->cpl != 0) {
4174 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4175 } else {
61382a50 4176 modrm = ldub_code(s->pc++);
2c0262af
FB		 4177 if ((modrm & 0xc0) != 0xc0)
4178 goto illegal_op;
4179 rm = modrm & 7;
4180 reg = (modrm >> 3) & 7;
4181 /* XXX: do it dynamically with CR4.DE bit */
4182 if (reg == 4 || reg == 5)
4183 goto illegal_op;
4184 if (b & 2) {
4185 gen_op_mov_TN_reg[OT_LONG][0][rm]();
4186 gen_op_movl_drN_T0(reg);
4187 gen_op_jmp_im(s->pc - s->cs_base);
4188 gen_eob(s);
4189 } else {
4190 gen_op_movl_T0_env(offsetof(CPUX86State,dr[reg]));
4191 gen_op_mov_reg_T0[OT_LONG][rm]();
4192 }
4193 }
4194 break;
4195 case 0x106: /* clts */
4196 if (s->cpl != 0) {
4197 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4198 } else {
4199 gen_op_clts();
7eee2a50
FB		 4200 /* abort block because static cpu state changed */
4201 gen_op_jmp_im(s->pc - s->cs_base);
4202 gen_eob(s);
2c0262af
FB		 4203 }
4204 break;
4205 default:
4206 goto illegal_op;
4207 }
4208 /* lock generation */
4209 if (s->prefix & PREFIX_LOCK)
4210 gen_op_unlock();
4211 return s->pc;
4212 illegal_op:
ab1f142b
FB		 4213 if (s->prefix & PREFIX_LOCK)
4214 gen_op_unlock();
2c0262af
FB		 4215 /* XXX: ensure that no lock was generated */
4216 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
4217 return s->pc;
4218}
4219
4220#define CC_OSZAPC (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C)
4221#define CC_OSZAP (CC_O | CC_S | CC_Z | CC_A | CC_P)
4222
4223/* flags read by an operation */
4224static uint16_t opc_read_flags[NB_OPS] = {
4225 [INDEX_op_aas] = CC_A,
4226 [INDEX_op_aaa] = CC_A,
4227 [INDEX_op_das] = CC_A | CC_C,
4228 [INDEX_op_daa] = CC_A | CC_C,
4229
2c0262af
FB		 4230 /* subtle: due to the incl/decl implementation, C is used */
4231 [INDEX_op_update_inc_cc] = CC_C,
4232
4233 [INDEX_op_into] = CC_O,
4234
4235 [INDEX_op_jb_subb] = CC_C,
4236 [INDEX_op_jb_subw] = CC_C,
4237 [INDEX_op_jb_subl] = CC_C,
4238
4239 [INDEX_op_jz_subb] = CC_Z,
4240 [INDEX_op_jz_subw] = CC_Z,
4241 [INDEX_op_jz_subl] = CC_Z,
4242
4243 [INDEX_op_jbe_subb] = CC_Z | CC_C,
4244 [INDEX_op_jbe_subw] = CC_Z | CC_C,
4245 [INDEX_op_jbe_subl] = CC_Z | CC_C,
4246
4247 [INDEX_op_js_subb] = CC_S,
4248 [INDEX_op_js_subw] = CC_S,
4249 [INDEX_op_js_subl] = CC_S,
4250
4251 [INDEX_op_jl_subb] = CC_O | CC_S,
4252 [INDEX_op_jl_subw] = CC_O | CC_S,
4253 [INDEX_op_jl_subl] = CC_O | CC_S,
4254
4255 [INDEX_op_jle_subb] = CC_O | CC_S | CC_Z,
4256 [INDEX_op_jle_subw] = CC_O | CC_S | CC_Z,
4257 [INDEX_op_jle_subl] = CC_O | CC_S | CC_Z,
4258
4259 [INDEX_op_loopnzw] = CC_Z,
4260 [INDEX_op_loopnzl] = CC_Z,
4261 [INDEX_op_loopzw] = CC_Z,
4262 [INDEX_op_loopzl] = CC_Z,
4263
4264 [INDEX_op_seto_T0_cc] = CC_O,
4265 [INDEX_op_setb_T0_cc] = CC_C,
4266 [INDEX_op_setz_T0_cc] = CC_Z,
4267 [INDEX_op_setbe_T0_cc] = CC_Z | CC_C,
4268 [INDEX_op_sets_T0_cc] = CC_S,
4269 [INDEX_op_setp_T0_cc] = CC_P,
4270 [INDEX_op_setl_T0_cc] = CC_O | CC_S,
4271 [INDEX_op_setle_T0_cc] = CC_O | CC_S | CC_Z,
4272
4273 [INDEX_op_setb_T0_subb] = CC_C,
4274 [INDEX_op_setb_T0_subw] = CC_C,
4275 [INDEX_op_setb_T0_subl] = CC_C,
4276
4277 [INDEX_op_setz_T0_subb] = CC_Z,
4278 [INDEX_op_setz_T0_subw] = CC_Z,
4279 [INDEX_op_setz_T0_subl] = CC_Z,
4280
4281 [INDEX_op_setbe_T0_subb] = CC_Z | CC_C,
4282 [INDEX_op_setbe_T0_subw] = CC_Z | CC_C,
4283 [INDEX_op_setbe_T0_subl] = CC_Z | CC_C,
4284
4285 [INDEX_op_sets_T0_subb] = CC_S,
4286 [INDEX_op_sets_T0_subw] = CC_S,
4287 [INDEX_op_sets_T0_subl] = CC_S,
4288
4289 [INDEX_op_setl_T0_subb] = CC_O | CC_S,
4290 [INDEX_op_setl_T0_subw] = CC_O | CC_S,
4291 [INDEX_op_setl_T0_subl] = CC_O | CC_S,
4292
4293 [INDEX_op_setle_T0_subb] = CC_O | CC_S | CC_Z,
4294 [INDEX_op_setle_T0_subw] = CC_O | CC_S | CC_Z,
4295 [INDEX_op_setle_T0_subl] = CC_O | CC_S | CC_Z,
4296
4297 [INDEX_op_movl_T0_eflags] = CC_OSZAPC,
4298 [INDEX_op_cmc] = CC_C,
4299 [INDEX_op_salc] = CC_C,
4300
7399c5a9
FB		 4301 /* needed for correct flag optimisation before string ops */
4302 [INDEX_op_jz_ecxw] = CC_OSZAPC,
4303 [INDEX_op_jz_ecxl] = CC_OSZAPC,
4304 [INDEX_op_jz_ecxw_im] = CC_OSZAPC,
4305 [INDEX_op_jz_ecxl_im] = CC_OSZAPC,
4306
4f31916f
FB		 4307#define DEF_READF(SUFFIX)\
4308 [INDEX_op_adcb ## SUFFIX ## _T0_T1_cc] = CC_C,\
4309 [INDEX_op_adcw ## SUFFIX ## _T0_T1_cc] = CC_C,\
4310 [INDEX_op_adcl ## SUFFIX ## _T0_T1_cc] = CC_C,\
4311 [INDEX_op_sbbb ## SUFFIX ## _T0_T1_cc] = CC_C,\
4312 [INDEX_op_sbbw ## SUFFIX ## _T0_T1_cc] = CC_C,\
4313 [INDEX_op_sbbl ## SUFFIX ## _T0_T1_cc] = CC_C,\
4314\
4315 [INDEX_op_rclb ## SUFFIX ## _T0_T1_cc] = CC_C,\
4316 [INDEX_op_rclw ## SUFFIX ## _T0_T1_cc] = CC_C,\
4317 [INDEX_op_rcll ## SUFFIX ## _T0_T1_cc] = CC_C,\
4318 [INDEX_op_rcrb ## SUFFIX ## _T0_T1_cc] = CC_C,\
4319 [INDEX_op_rcrw ## SUFFIX ## _T0_T1_cc] = CC_C,\
4320 [INDEX_op_rcrl ## SUFFIX ## _T0_T1_cc] = CC_C,
4321
4322
4bb2fcc7 4323 DEF_READF( )
4f31916f
FB		 4324 DEF_READF(_raw)
4325#ifndef CONFIG_USER_ONLY
4326 DEF_READF(_kernel)
4327 DEF_READF(_user)
4328#endif
2c0262af
FB		 4329};
4330
4331/* flags written by an operation */
4332static uint16_t opc_write_flags[NB_OPS] = {
4333 [INDEX_op_update2_cc] = CC_OSZAPC,
4334 [INDEX_op_update1_cc] = CC_OSZAPC,
4335 [INDEX_op_cmpl_T0_T1_cc] = CC_OSZAPC,
4336 [INDEX_op_update_neg_cc] = CC_OSZAPC,
4337 /* subtle: due to the incl/decl implementation, C is used */
4338 [INDEX_op_update_inc_cc] = CC_OSZAPC,
4339 [INDEX_op_testl_T0_T1_cc] = CC_OSZAPC,
4340
2c0262af
FB		 4341 [INDEX_op_mulb_AL_T0] = CC_OSZAPC,
4342 [INDEX_op_imulb_AL_T0] = CC_OSZAPC,
4343 [INDEX_op_mulw_AX_T0] = CC_OSZAPC,
4344 [INDEX_op_imulw_AX_T0] = CC_OSZAPC,
4345 [INDEX_op_mull_EAX_T0] = CC_OSZAPC,
4346 [INDEX_op_imull_EAX_T0] = CC_OSZAPC,
4347 [INDEX_op_imulw_T0_T1] = CC_OSZAPC,
4348 [INDEX_op_imull_T0_T1] = CC_OSZAPC,
4349
4350 /* bcd */
4351 [INDEX_op_aam] = CC_OSZAPC,
4352 [INDEX_op_aad] = CC_OSZAPC,
4353 [INDEX_op_aas] = CC_OSZAPC,
4354 [INDEX_op_aaa] = CC_OSZAPC,
4355 [INDEX_op_das] = CC_OSZAPC,
4356 [INDEX_op_daa] = CC_OSZAPC,
4357
4358 [INDEX_op_movb_eflags_T0] = CC_S | CC_Z | CC_A | CC_P | CC_C,
4359 [INDEX_op_movw_eflags_T0] = CC_OSZAPC,
4360 [INDEX_op_movl_eflags_T0] = CC_OSZAPC,
4136f33c
FB		 4361 [INDEX_op_movw_eflags_T0_io] = CC_OSZAPC,
4362 [INDEX_op_movl_eflags_T0_io] = CC_OSZAPC,
4363 [INDEX_op_movw_eflags_T0_cpl0] = CC_OSZAPC,
4364 [INDEX_op_movl_eflags_T0_cpl0] = CC_OSZAPC,
2c0262af
FB		 4365 [INDEX_op_clc] = CC_C,
4366 [INDEX_op_stc] = CC_C,
4367 [INDEX_op_cmc] = CC_C,
4368
2c0262af
FB		 4369 [INDEX_op_btw_T0_T1_cc] = CC_OSZAPC,
4370 [INDEX_op_btl_T0_T1_cc] = CC_OSZAPC,
4371 [INDEX_op_btsw_T0_T1_cc] = CC_OSZAPC,
4372 [INDEX_op_btsl_T0_T1_cc] = CC_OSZAPC,
4373 [INDEX_op_btrw_T0_T1_cc] = CC_OSZAPC,
4374 [INDEX_op_btrl_T0_T1_cc] = CC_OSZAPC,
4375 [INDEX_op_btcw_T0_T1_cc] = CC_OSZAPC,
4376 [INDEX_op_btcl_T0_T1_cc] = CC_OSZAPC,
4377
4378 [INDEX_op_bsfw_T0_cc] = CC_OSZAPC,
4379 [INDEX_op_bsfl_T0_cc] = CC_OSZAPC,
4380 [INDEX_op_bsrw_T0_cc] = CC_OSZAPC,
4381 [INDEX_op_bsrl_T0_cc] = CC_OSZAPC,
4382
4383 [INDEX_op_cmpxchgb_T0_T1_EAX_cc] = CC_OSZAPC,
4384 [INDEX_op_cmpxchgw_T0_T1_EAX_cc] = CC_OSZAPC,
4385 [INDEX_op_cmpxchgl_T0_T1_EAX_cc] = CC_OSZAPC,
4386
2c0262af
FB		 4387 [INDEX_op_cmpxchg8b] = CC_Z,
4388 [INDEX_op_lar] = CC_Z,
4389 [INDEX_op_lsl] = CC_Z,
4390 [INDEX_op_fcomi_ST0_FT0] = CC_Z | CC_P | CC_C,
4391 [INDEX_op_fucomi_ST0_FT0] = CC_Z | CC_P | CC_C,
4f31916f
FB		 4392
4393#define DEF_WRITEF(SUFFIX)\
4394 [INDEX_op_adcb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4395 [INDEX_op_adcw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4396 [INDEX_op_adcl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4397 [INDEX_op_sbbb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4398 [INDEX_op_sbbw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4399 [INDEX_op_sbbl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4400\
4401 [INDEX_op_rolb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4402 [INDEX_op_rolw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4403 [INDEX_op_roll ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4404 [INDEX_op_rorb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4405 [INDEX_op_rorw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4406 [INDEX_op_rorl ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4407\
4408 [INDEX_op_rclb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4409 [INDEX_op_rclw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4410 [INDEX_op_rcll ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4411 [INDEX_op_rcrb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4412 [INDEX_op_rcrw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4413 [INDEX_op_rcrl ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4414\
4415 [INDEX_op_shlb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4416 [INDEX_op_shlw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4417 [INDEX_op_shll ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4418\
4419 [INDEX_op_shrb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4420 [INDEX_op_shrw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4421 [INDEX_op_shrl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4422\
4423 [INDEX_op_sarb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4424 [INDEX_op_sarw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4425 [INDEX_op_sarl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4426\
4427 [INDEX_op_shldw ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
4428 [INDEX_op_shldl ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
4429 [INDEX_op_shldw ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
4430 [INDEX_op_shldl ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
4431\
4432 [INDEX_op_shrdw ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
4433 [INDEX_op_shrdl ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
4434 [INDEX_op_shrdw ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
4435 [INDEX_op_shrdl ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
4436\
4437 [INDEX_op_cmpxchgb ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
4438 [INDEX_op_cmpxchgw ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
4439 [INDEX_op_cmpxchgl ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,
4440
4441
4bb2fcc7 4442 DEF_WRITEF( )
4f31916f
FB		 4443 DEF_WRITEF(_raw)
4444#ifndef CONFIG_USER_ONLY
4445 DEF_WRITEF(_kernel)
4446 DEF_WRITEF(_user)
4447#endif
2c0262af
FB		 4448};
4449
4450/* simpler form of an operation if no flags need to be generated */
4451static uint16_t opc_simpler[NB_OPS] = {
4452 [INDEX_op_update2_cc] = INDEX_op_nop,
4453 [INDEX_op_update1_cc] = INDEX_op_nop,
4454 [INDEX_op_update_neg_cc] = INDEX_op_nop,
4455#if 0
4456 /* broken: CC_OP logic must be rewritten */
4457 [INDEX_op_update_inc_cc] = INDEX_op_nop,
4458#endif
2c0262af
FB		 4459
4460 [INDEX_op_shlb_T0_T1_cc] = INDEX_op_shlb_T0_T1,
4461 [INDEX_op_shlw_T0_T1_cc] = INDEX_op_shlw_T0_T1,
4462 [INDEX_op_shll_T0_T1_cc] = INDEX_op_shll_T0_T1,
4463
4464 [INDEX_op_shrb_T0_T1_cc] = INDEX_op_shrb_T0_T1,
4465 [INDEX_op_shrw_T0_T1_cc] = INDEX_op_shrw_T0_T1,
4466 [INDEX_op_shrl_T0_T1_cc] = INDEX_op_shrl_T0_T1,
4467
4468 [INDEX_op_sarb_T0_T1_cc] = INDEX_op_sarb_T0_T1,
4469 [INDEX_op_sarw_T0_T1_cc] = INDEX_op_sarw_T0_T1,
4470 [INDEX_op_sarl_T0_T1_cc] = INDEX_op_sarl_T0_T1,
4f31916f
FB		 4471
4472#define DEF_SIMPLER(SUFFIX)\
4473 [INDEX_op_rolb ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolb ## SUFFIX ## _T0_T1,\
4474 [INDEX_op_rolw ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolw ## SUFFIX ## _T0_T1,\
4475 [INDEX_op_roll ## SUFFIX ## _T0_T1_cc] = INDEX_op_roll ## SUFFIX ## _T0_T1,\
4476\
4477 [INDEX_op_rorb ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorb ## SUFFIX ## _T0_T1,\
4478 [INDEX_op_rorw ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorw ## SUFFIX ## _T0_T1,\
4479 [INDEX_op_rorl ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorl ## SUFFIX ## _T0_T1,
4480
4bb2fcc7 4481 DEF_SIMPLER( )
4f31916f
FB		 4482 DEF_SIMPLER(_raw)
4483#ifndef CONFIG_USER_ONLY
4484 DEF_SIMPLER(_kernel)
4485 DEF_SIMPLER(_user)
4486#endif
2c0262af
FB		 4487};
4488
4489void optimize_flags_init(void)
4490{
4491 int i;
4492 /* put default values in arrays */
4493 for(i = 0; i < NB_OPS; i++) {
4494 if (opc_simpler[i] == 0)
4495 opc_simpler[i] = i;
4496 }
4497}
4498
4499/* CPU flags computation optimization: we move backward thru the
4500 generated code to see which flags are needed. The operation is
4501 modified if suitable */
4502static void optimize_flags(uint16_t *opc_buf, int opc_buf_len)
4503{
4504 uint16_t *opc_ptr;
4505 int live_flags, write_flags, op;
4506
4507 opc_ptr = opc_buf + opc_buf_len;
4508 /* live_flags contains the flags needed by the next instructions
4509 in the code. At the end of the bloc, we consider that all the
4510 flags are live. */
4511 live_flags = CC_OSZAPC;
4512 while (opc_ptr > opc_buf) {
4513 op = *--opc_ptr;
4514 /* if none of the flags written by the instruction is used,
4515 then we can try to find a simpler instruction */
4516 write_flags = opc_write_flags[op];
4517 if ((live_flags & write_flags) == 0) {
4518 *opc_ptr = opc_simpler[op];
4519 }
4520 /* compute the live flags before the instruction */
4521 live_flags &= ~write_flags;
4522 live_flags |= opc_read_flags[op];
4523 }
4524}
4525
4526/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
4527 basic block 'tb'. If search_pc is TRUE, also generate PC
4528 information for each intermediate instruction. */
4529static inline int gen_intermediate_code_internal(CPUState *env,
4530 TranslationBlock *tb,
4531 int search_pc)
4532{
4533 DisasContext dc1, *dc = &dc1;
4534 uint8_t *pc_ptr;
4535 uint16_t *gen_opc_end;
d720b93d 4536 int flags, j, lj, cflags;
2c0262af
FB		 4537 uint8_t *pc_start;
4538 uint8_t *cs_base;
4539
4540 /* generate intermediate code */
4541 pc_start = (uint8_t *)tb->pc;
4542 cs_base = (uint8_t *)tb->cs_base;
4543 flags = tb->flags;
d720b93d 4544 cflags = tb->cflags;
3a1d9b8b 4545
4f31916f 4546 dc->pe = (flags >> HF_PE_SHIFT) & 1;
2c0262af
FB		 4547 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
4548 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
4549 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
4550 dc->f_st = 0;
4551 dc->vm86 = (flags >> VM_SHIFT) & 1;
4552 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
4553 dc->iopl = (flags >> IOPL_SHIFT) & 3;
4554 dc->tf = (flags >> TF_SHIFT) & 1;
34865134 4555 dc->singlestep_enabled = env->singlestep_enabled;
2c0262af
FB		 4556 dc->cc_op = CC_OP_DYNAMIC;
4557 dc->cs_base = cs_base;
4558 dc->tb = tb;
4559 dc->popl_esp_hack = 0;
4560 /* select memory access functions */
4561 dc->mem_index = 0;
4562 if (flags & HF_SOFTMMU_MASK) {
4563 if (dc->cpl == 3)
4564 dc->mem_index = 6;
4565 else
4566 dc->mem_index = 3;
4567 }
7eee2a50 4568 dc->flags = flags;
a2cc3b24
FB		 4569 dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
4570 (flags & HF_INHIBIT_IRQ_MASK)
415fa2ea 4571#ifndef CONFIG_SOFTMMU
2c0262af
FB		 4572 || (flags & HF_SOFTMMU_MASK)
4573#endif
4574 );
4f31916f
FB		 4575#if 0
4576 /* check addseg logic */
dc196a57 4577 if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
4f31916f
FB		 4578 printf("ERROR addseg\n");
4579#endif
4580
2c0262af
FB		 4581 gen_opc_ptr = gen_opc_buf;
4582 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4583 gen_opparam_ptr = gen_opparam_buf;
4584
4585 dc->is_jmp = DISAS_NEXT;
4586 pc_ptr = pc_start;
4587 lj = -1;
4588
2c0262af
FB		 4589 for(;;) {
4590 if (env->nb_breakpoints > 0) {
4591 for(j = 0; j < env->nb_breakpoints; j++) {
4592 if (env->breakpoints[j] == (unsigned long)pc_ptr) {
4593 gen_debug(dc, pc_ptr - dc->cs_base);
4594 break;
4595 }
4596 }
4597 }
4598 if (search_pc) {
4599 j = gen_opc_ptr - gen_opc_buf;
4600 if (lj < j) {
4601 lj++;
4602 while (lj < j)
4603 gen_opc_instr_start[lj++] = 0;
4604 }
4605 gen_opc_pc[lj] = (uint32_t)pc_ptr;
4606 gen_opc_cc_op[lj] = dc->cc_op;
4607 gen_opc_instr_start[lj] = 1;
4608 }
4609 pc_ptr = disas_insn(dc, pc_ptr);
4610 /* stop translation if indicated */
4611 if (dc->is_jmp)
4612 break;
4613 /* if single step mode, we generate only one instruction and
4614 generate an exception */
a2cc3b24
FB		 4615 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
4616 the flag and abort the translation to give the irqs a
4617 change to be happen */
4618 if (dc->tf || dc->singlestep_enabled ||
d720b93d
FB		 4619 (flags & HF_INHIBIT_IRQ_MASK) ||
4620 (cflags & CF_SINGLE_INSN)) {
2c0262af
FB		 4621 gen_op_jmp_im(pc_ptr - dc->cs_base);
4622 gen_eob(dc);
4623 break;
4624 }
4625 /* if too long translation, stop generation too */
4626 if (gen_opc_ptr >= gen_opc_end ||
4627 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32)) {
4628 gen_op_jmp_im(pc_ptr - dc->cs_base);
4629 gen_eob(dc);
4630 break;
4631 }
4632 }
4633 *gen_opc_ptr = INDEX_op_end;
4634 /* we don't forget to fill the last values */
4635 if (search_pc) {
4636 j = gen_opc_ptr - gen_opc_buf;
4637 lj++;
4638 while (lj <= j)
4639 gen_opc_instr_start[lj++] = 0;
4640 }
4641
4642#ifdef DEBUG_DISAS
658c8bda
FB		 4643 if (loglevel & CPU_LOG_TB_CPU) {
4644 cpu_dump_state(env, logfile, X86_DUMP_CCOP);
4645 }
e19e89a5 4646 if (loglevel & CPU_LOG_TB_IN_ASM) {
2c0262af
FB		 4647 fprintf(logfile, "----------------\n");
4648 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4649 disas(logfile, pc_start, pc_ptr - pc_start, 0, !dc->code32);
4650 fprintf(logfile, "\n");
e19e89a5
FB		 4651 if (loglevel & CPU_LOG_TB_OP) {
4652 fprintf(logfile, "OP:\n");
4653 dump_ops(gen_opc_buf, gen_opparam_buf);
4654 fprintf(logfile, "\n");
4655 }
2c0262af
FB		 4656 }
4657#endif
4658
4659 /* optimize flag computations */
4660 optimize_flags(gen_opc_buf, gen_opc_ptr - gen_opc_buf);
4661
4662#ifdef DEBUG_DISAS
e19e89a5 4663 if (loglevel & CPU_LOG_TB_OP_OPT) {
2c0262af
FB		 4664 fprintf(logfile, "AFTER FLAGS OPT:\n");
4665 dump_ops(gen_opc_buf, gen_opparam_buf);
4666 fprintf(logfile, "\n");
4667 }
4668#endif
4669 if (!search_pc)
4670 tb->size = pc_ptr - pc_start;
4671 return 0;
4672}
4673
4674int gen_intermediate_code(CPUState *env, TranslationBlock *tb)
4675{
4676 return gen_intermediate_code_internal(env, tb, 0);
4677}
4678
4679int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
4680{
4681 return gen_intermediate_code_internal(env, tb, 1);
4682}
4683
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