[qemu.git] / hw / cris / axis_dev88.c

/*
 * QEMU model for the AXIS devboard 88.
 *
 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "hw/sysbus.h"
#include "net/net.h"
#include "hw/block/flash.h"
#include "hw/boards.h"
#include "hw/cris/etraxfs.h"
#include "hw/loader.h"
#include "elf.h"
#include "boot.h"
#include "sysemu/blockdev.h"
#include "exec/address-spaces.h"

#define D(x)
#define DNAND(x)

struct nand_state_t
{
    DeviceState *nand;
    MemoryRegion iomem;
    unsigned int rdy:1;
    unsigned int ale:1;
    unsigned int cle:1;
    unsigned int ce:1;
};

static struct nand_state_t nand_state;
static uint64_t nand_read(void *opaque, hwaddr addr, unsigned size)
{
    struct nand_state_t *s = opaque;
    uint32_t r;
    int rdy;

    r = nand_getio(s->nand);
    nand_getpins(s->nand, &rdy);
    s->rdy = rdy;

    DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
    return r;
}

static void
nand_write(void *opaque, hwaddr addr, uint64_t value,
           unsigned size)
{
    struct nand_state_t *s = opaque;
    int rdy;

    DNAND(printf("%s addr=%x v=%x\n", __func__, addr, (unsigned)value));
    nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
    nand_setio(s->nand, value);
    nand_getpins(s->nand, &rdy);
    s->rdy = rdy;
}

static const MemoryRegionOps nand_ops = {
    .read = nand_read,
    .write = nand_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

struct tempsensor_t
{
    unsigned int shiftreg;
    unsigned int count;
    enum {
        ST_OUT, ST_IN, ST_Z
    } state;

    uint16_t regs[3];
};

static void tempsensor_clkedge(struct tempsensor_t *s,
                               unsigned int clk, unsigned int data_in)
{
    D(printf("%s clk=%d state=%d sr=%x\n", __func__,
             clk, s->state, s->shiftreg));
    if (s->count == 0) {
        s->count = 16;
        s->state = ST_OUT;
    }
    switch (s->state) {
        case ST_OUT:
            /* Output reg is clocked at negedge.  */
            if (!clk) {
                s->count--;
                s->shiftreg <<= 1;
                if (s->count == 0) {
                    s->shiftreg = 0;
                    s->state = ST_IN;
                    s->count = 16;
                }
            }
            break;
        case ST_Z:
            if (clk) {
                s->count--;
                if (s->count == 0) {
                    s->shiftreg = 0;
                    s->state = ST_OUT;
                    s->count = 16;
                }
            }
            break;
        case ST_IN:
            /* Indata is sampled at posedge.  */
            if (clk) {
                s->count--;
                s->shiftreg <<= 1;
                s->shiftreg |= data_in & 1;
                if (s->count == 0) {
                    D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
                    s->regs[0] = s->shiftreg;
                    s->state = ST_OUT;
                    s->count = 16;

                    if ((s->regs[0] & 0xff) == 0) {
                        /* 25 degrees celcius.  */
                        s->shiftreg = 0x0b9f;
                    } else if ((s->regs[0] & 0xff) == 0xff) {
                        /* Sensor ID, 0x8100 LM70.  */
                        s->shiftreg = 0x8100;
                    } else
                        printf("Invalid tempsens state %x\n", s->regs[0]);
                }
            }
            break;
    }
}


#define RW_PA_DOUT    0x00
#define R_PA_DIN      0x01
#define RW_PA_OE      0x02
#define RW_PD_DOUT    0x10
#define R_PD_DIN      0x11
#define RW_PD_OE      0x12

static struct gpio_state_t
{
    MemoryRegion iomem;
    struct nand_state_t *nand;
    struct tempsensor_t tempsensor;
    uint32_t regs[0x5c / 4];
} gpio_state;

static uint64_t gpio_read(void *opaque, hwaddr addr, unsigned size)
{
    struct gpio_state_t *s = opaque;
    uint32_t r = 0;

    addr >>= 2;
    switch (addr)
    {
        case R_PA_DIN:
            r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];

            /* Encode pins from the nand.  */
            r |= s->nand->rdy << 7;
            break;
        case R_PD_DIN:
            r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];

            /* Encode temp sensor pins.  */
            r |= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
            break;

        default:
            r = s->regs[addr];
            break;
    }
    return r;
    D(printf("%s %x=%x\n", __func__, addr, r));
}

static void gpio_write(void *opaque, hwaddr addr, uint64_t value,
                       unsigned size)
{
    struct gpio_state_t *s = opaque;
    D(printf("%s %x=%x\n", __func__, addr, (unsigned)value));

    addr >>= 2;
    switch (addr)
    {
        case RW_PA_DOUT:
            /* Decode nand pins.  */
            s->nand->ale = !!(value & (1 << 6));
            s->nand->cle = !!(value & (1 << 5));
            s->nand->ce  = !!(value & (1 << 4));

            s->regs[addr] = value;
            break;

        case RW_PD_DOUT:
            /* Temp sensor clk.  */
            if ((s->regs[addr] ^ value) & 2)
                tempsensor_clkedge(&s->tempsensor, !!(value & 2),
                                   !!(value & 16));
            s->regs[addr] = value;
            break;

        default:
            s->regs[addr] = value;
            break;
    }
}

static const MemoryRegionOps gpio_ops = {
    .read = gpio_read,
    .write = gpio_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

#define INTMEM_SIZE (128 * 1024)

static struct cris_load_info li;

static
void axisdev88_init(QEMUMachineInitArgs *args)
{
    ram_addr_t ram_size = args->ram_size;
    const char *cpu_model = args->cpu_model;
    const char *kernel_filename = args->kernel_filename;
    const char *kernel_cmdline = args->kernel_cmdline;
    CRISCPU *cpu;
    CPUCRISState *env;
    DeviceState *dev;
    SysBusDevice *s;
    DriveInfo *nand;
    qemu_irq irq[30], nmi[2], *cpu_irq;
    void *etraxfs_dmac;
    struct etraxfs_dma_client *dma_eth;
    int i;
    MemoryRegion *address_space_mem = get_system_memory();
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);

    /* init CPUs */
    if (cpu_model == NULL) {
        cpu_model = "crisv32";
    }
    cpu = cpu_cris_init(cpu_model);
    env = &cpu->env;

    /* allocate RAM */
    memory_region_init_ram(phys_ram, NULL, "axisdev88.ram", ram_size);
    vmstate_register_ram_global(phys_ram);
    memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram);

    /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the 
       internal memory.  */
    memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram", INTMEM_SIZE);
    vmstate_register_ram_global(phys_intmem);
    memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);

      /* Attach a NAND flash to CS1.  */
    nand = drive_get(IF_MTD, 0, 0);
    nand_state.nand = nand_init(nand ? nand->bdrv : NULL,
                                NAND_MFR_STMICRO, 0x39);
    memory_region_init_io(&nand_state.iomem, NULL, &nand_ops, &nand_state,
                          "nand", 0x05000000);
    memory_region_add_subregion(address_space_mem, 0x10000000,
                                &nand_state.iomem);

    gpio_state.nand = &nand_state;
    memory_region_init_io(&gpio_state.iomem, NULL, &gpio_ops, &gpio_state,
                          "gpio", 0x5c);
    memory_region_add_subregion(address_space_mem, 0x3001a000,
                                &gpio_state.iomem);


    cpu_irq = cris_pic_init_cpu(env);
    dev = qdev_create(NULL, "etraxfs,pic");
    /* FIXME: Is there a proper way to signal vectors to the CPU core?  */
    qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(s, 0, 0x3001c000);
    sysbus_connect_irq(s, 0, cpu_irq[0]);
    sysbus_connect_irq(s, 1, cpu_irq[1]);
    for (i = 0; i < 30; i++) {
        irq[i] = qdev_get_gpio_in(dev, i);
    }
    nmi[0] = qdev_get_gpio_in(dev, 30);
    nmi[1] = qdev_get_gpio_in(dev, 31);

    etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
    for (i = 0; i < 10; i++) {
        /* On ETRAX, odd numbered channels are inputs.  */
        etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
    }

    /* Add the two ethernet blocks.  */
    dma_eth = g_malloc0(sizeof dma_eth[0] * 4); /* Allocate 4 channels.  */
    etraxfs_eth_init(&nd_table[0], 0x30034000, 1, &dma_eth[0], &dma_eth[1]);
    if (nb_nics > 1) {
        etraxfs_eth_init(&nd_table[1], 0x30036000, 2, &dma_eth[2], &dma_eth[3]);
    }

    /* The DMA Connector block is missing, hardwire things for now.  */
    etraxfs_dmac_connect_client(etraxfs_dmac, 0, &dma_eth[0]);
    etraxfs_dmac_connect_client(etraxfs_dmac, 1, &dma_eth[1]);
    if (nb_nics > 1) {
        etraxfs_dmac_connect_client(etraxfs_dmac, 6, &dma_eth[2]);
        etraxfs_dmac_connect_client(etraxfs_dmac, 7, &dma_eth[3]);
    }

    /* 2 timers.  */
    sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
    sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);

    for (i = 0; i < 4; i++) {
        sysbus_create_simple("etraxfs,serial", 0x30026000 + i * 0x2000,
                             irq[0x14 + i]);
    }

    if (!kernel_filename) {
        fprintf(stderr, "Kernel image must be specified\n");
        exit(1);
    }

    li.image_filename = kernel_filename;
    li.cmdline = kernel_cmdline;
    cris_load_image(cpu, &li);
}

static QEMUMachine axisdev88_machine = {
    .name = "axis-dev88",
    .desc = "AXIS devboard 88",
    .init = axisdev88_init,
    .is_default = 1,
    DEFAULT_MACHINE_OPTIONS,
};

static void axisdev88_machine_init(void)
{
    qemu_register_machine(&axisdev88_machine);
}

machine_init(axisdev88_machine_init);
Commit	Line	Data
10c144e2 EI	1	/*
	2	* QEMU model for the AXIS devboard 88.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
4b816985	24
83c9f4ca	25	#include "hw/sysbus.h"
1422e32d	26	#include "net/net.h"
0d09e41a	27	#include "hw/block/flash.h"
83c9f4ca	28	#include "hw/boards.h"
0d09e41a	29	#include "hw/cris/etraxfs.h"
83c9f4ca	30	#include "hw/loader.h"
ca20cf32	31	#include "elf.h"
47b43a1f	32	#include "boot.h"
9c17d615	33	#include "sysemu/blockdev.h"
022c62cb	34	#include "exec/address-spaces.h"
10c144e2 EI	35
	36	#define D(x)
	37	#define DNAND(x)
	38
	39	struct nand_state_t
	40	{
d4220389	41	DeviceState *nand;
838335ec	42	MemoryRegion iomem;
10c144e2 EI	43	unsigned int rdy:1;
	44	unsigned int ale:1;
	45	unsigned int cle:1;
	46	unsigned int ce:1;
	47	};
	48
	49	static struct nand_state_t nand_state;
a8170e5e	50	static uint64_t nand_read(void *opaque, hwaddr addr, unsigned size)
10c144e2 EI	51	{
	52	struct nand_state_t *s = opaque;
	53	uint32_t r;
	54	int rdy;
	55
	56	r = nand_getio(s->nand);
	57	nand_getpins(s->nand, &rdy);
	58	s->rdy = rdy;
	59
	60	DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
	61	return r;
	62	}
	63
	64	static void
a8170e5e	65	nand_write(void *opaque, hwaddr addr, uint64_t value,
838335ec	66	unsigned size)
10c144e2 EI	67	{
	68	struct nand_state_t *s = opaque;
	69	int rdy;
	70
838335ec	71	DNAND(printf("%s addr=%x v=%x\n", __func__, addr, (unsigned)value));
10c144e2 EI	72	nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
	73	nand_setio(s->nand, value);
	74	nand_getpins(s->nand, &rdy);
	75	s->rdy = rdy;
	76	}
	77
838335ec AK	78	static const MemoryRegionOps nand_ops = {
	79	.read = nand_read,
	80	.write = nand_write,
	81	.endianness = DEVICE_NATIVE_ENDIAN,
10c144e2 EI	82	};
10c144e2 EI	83
4a1e6bea EI	84	struct tempsensor_t
	85	{
	86	unsigned int shiftreg;
	87	unsigned int count;
	88	enum {
	89	ST_OUT, ST_IN, ST_Z
	90	} state;
	91
	92	uint16_t regs[3];
	93	};
	94
	95	static void tempsensor_clkedge(struct tempsensor_t *s,
	96	unsigned int clk, unsigned int data_in)
	97	{
	98	D(printf("%s clk=%d state=%d sr=%x\n", __func__,
	99	clk, s->state, s->shiftreg));
	100	if (s->count == 0) {
	101	s->count = 16;
	102	s->state = ST_OUT;
	103	}
	104	switch (s->state) {
	105	case ST_OUT:
	106	/* Output reg is clocked at negedge. */
	107	if (!clk) {
	108	s->count--;
	109	s->shiftreg <<= 1;
	110	if (s->count == 0) {
	111	s->shiftreg = 0;
	112	s->state = ST_IN;
	113	s->count = 16;
	114	}
	115	}
	116	break;
	117	case ST_Z:
	118	if (clk) {
	119	s->count--;
	120	if (s->count == 0) {
	121	s->shiftreg = 0;
	122	s->state = ST_OUT;
	123	s->count = 16;
	124	}
	125	}
	126	break;
	127	case ST_IN:
	128	/* Indata is sampled at posedge. */
	129	if (clk) {
	130	s->count--;
	131	s->shiftreg <<= 1;
	132	s->shiftreg \|= data_in & 1;
	133	if (s->count == 0) {
	134	D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
	135	s->regs[0] = s->shiftreg;
	136	s->state = ST_OUT;
	137	s->count = 16;
	138
	139	if ((s->regs[0] & 0xff) == 0) {
	140	/* 25 degrees celcius. */
	141	s->shiftreg = 0x0b9f;
	142	} else if ((s->regs[0] & 0xff) == 0xff) {
	143	/* Sensor ID, 0x8100 LM70. */
	144	s->shiftreg = 0x8100;
	145	} else
	146	printf("Invalid tempsens state %x\n", s->regs[0]);
	147	}
148	}
149	break;
150	}
151	}
152
153
154	#define RW_PA_DOUT 0x00
155	#define R_PA_DIN 0x01
156	#define RW_PA_OE 0x02
157	#define RW_PD_DOUT 0x10
158	#define R_PD_DIN 0x11
159	#define RW_PD_OE 0x12
160
161	static struct gpio_state_t
10c144e2	162	{
838335ec	163	MemoryRegion iomem;
10c144e2	164	struct nand_state_t *nand;
4a1e6bea	165	struct tempsensor_t tempsensor;
10c144e2 EI	166	uint32_t regs[0x5c / 4];
	167	} gpio_state;
	168
a8170e5e	169	static uint64_t gpio_read(void *opaque, hwaddr addr, unsigned size)
10c144e2 EI	170	{
	171	struct gpio_state_t *s = opaque;
	172	uint32_t r = 0;
	173
	174	addr >>= 2;
	175	switch (addr)
	176	{
	177	case R_PA_DIN:
	178	r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];
	179
	180	/* Encode pins from the nand. */
	181	r \|= s->nand->rdy << 7;
	182	break;
4a1e6bea EI	183	case R_PD_DIN:
	184	r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];
	185
	186	/* Encode temp sensor pins. */
	187	r \|= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
	188	break;
	189
10c144e2 EI	190	default:
	191	r = s->regs[addr];
	192	break;
	193	}
	194	return r;
	195	D(printf("%s %x=%x\n", __func__, addr, r));
	196	}
	197
a8170e5e	198	static void gpio_write(void *opaque, hwaddr addr, uint64_t value,
838335ec	199	unsigned size)
10c144e2 EI	200	{
10c144e2 EI	201	struct gpio_state_t *s = opaque;
838335ec	202	D(printf("%s %x=%x\n", __func__, addr, (unsigned)value));
10c144e2 EI	203
	204	addr >>= 2;
	205	switch (addr)
	206	{
	207	case RW_PA_DOUT:
	208	/* Decode nand pins. */
	209	s->nand->ale = !!(value & (1 << 6));
	210	s->nand->cle = !!(value & (1 << 5));
	211	s->nand->ce = !!(value & (1 << 4));
	212
	213	s->regs[addr] = value;
	214	break;
4a1e6bea EI	215
	216	case RW_PD_DOUT:
	217	/* Temp sensor clk. */
	218	if ((s->regs[addr] ^ value) & 2)
	219	tempsensor_clkedge(&s->tempsensor, !!(value & 2),
	220	!!(value & 16));
	221	s->regs[addr] = value;
	222	break;
	223
10c144e2 EI	224	default:
	225	s->regs[addr] = value;
	226	break;
	227	}
	228	}
	229
838335ec AK	230	static const MemoryRegionOps gpio_ops = {
	231	.read = gpio_read,
	232	.write = gpio_write,
	233	.endianness = DEVICE_NATIVE_ENDIAN,
	234	.valid = {
	235	.min_access_size = 4,
	236	.max_access_size = 4,
	237	},
10c144e2 EI	238	};
	239
	240	#define INTMEM_SIZE (128 * 1024)
	241
77d4f95e	242	static struct cris_load_info li;
409dbce5	243
10c144e2	244	static
5f072e1f	245	void axisdev88_init(QEMUMachineInitArgs *args)
10c144e2	246	{
5f072e1f EH	247	ram_addr_t ram_size = args->ram_size;
	248	const char *cpu_model = args->cpu_model;
	249	const char *kernel_filename = args->kernel_filename;
	250	const char *kernel_cmdline = args->kernel_cmdline;
ddeb9ae5	251	CRISCPU *cpu;
fc9bb176	252	CPUCRISState *env;
fd6dc90b EI	253	DeviceState *dev;
fd6dc90b EI	254	SysBusDevice *s;
522f253c	255	DriveInfo *nand;
fd6dc90b	256	qemu_irq irq[30], nmi[2], *cpu_irq;
10c144e2	257	void *etraxfs_dmac;
1da005b3	258	struct etraxfs_dma_client *dma_eth;
10c144e2	259	int i;
b0e3d5ac AK	260	MemoryRegion *address_space_mem = get_system_memory();
	261	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
	262	MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);
10c144e2 EI	263
	264	/* init CPUs */
	265	if (cpu_model == NULL) {
	266	cpu_model = "crisv32";
	267	}
ddeb9ae5 AF	268	cpu = cpu_cris_init(cpu_model);
ddeb9ae5 AF	269	env = &cpu->env;
10c144e2 EI	270
10c144e2 EI	271	/* allocate RAM */
2c9b15ca	272	memory_region_init_ram(phys_ram, NULL, "axisdev88.ram", ram_size);
c5705a77	273	vmstate_register_ram_global(phys_ram);
b0e3d5ac	274	memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram);
10c144e2 EI	275
	276	/* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
	277	internal memory. */
2c9b15ca	278	memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram", INTMEM_SIZE);
c5705a77	279	vmstate_register_ram_global(phys_intmem);
b0e3d5ac	280	memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);
10c144e2 EI	281
10c144e2 EI	282	/* Attach a NAND flash to CS1. */
522f253c PM	283	nand = drive_get(IF_MTD, 0, 0);
	284	nand_state.nand = nand_init(nand ? nand->bdrv : NULL,
	285	NAND_MFR_STMICRO, 0x39);
2c9b15ca	286	memory_region_init_io(&nand_state.iomem, NULL, &nand_ops, &nand_state,
838335ec AK	287	"nand", 0x05000000);
	288	memory_region_add_subregion(address_space_mem, 0x10000000,
	289	&nand_state.iomem);
10c144e2 EI	290
10c144e2 EI	291	gpio_state.nand = &nand_state;
2c9b15ca	292	memory_region_init_io(&gpio_state.iomem, NULL, &gpio_ops, &gpio_state,
838335ec AK	293	"gpio", 0x5c);
	294	memory_region_add_subregion(address_space_mem, 0x3001a000,
	295	&gpio_state.iomem);
10c144e2 EI	296
10c144e2 EI	297
fd6dc90b EI	298	cpu_irq = cris_pic_init_cpu(env);
	299	dev = qdev_create(NULL, "etraxfs,pic");
	300	/* FIXME: Is there a proper way to signal vectors to the CPU core? */
ee6847d1	301	qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
e23a1b33	302	qdev_init_nofail(dev);
1356b98d	303	s = SYS_BUS_DEVICE(dev);
fd6dc90b EI	304	sysbus_mmio_map(s, 0, 0x3001c000);
	305	sysbus_connect_irq(s, 0, cpu_irq[0]);
	306	sysbus_connect_irq(s, 1, cpu_irq[1]);
	307	for (i = 0; i < 30; i++) {
067a3ddc	308	irq[i] = qdev_get_gpio_in(dev, i);
fd6dc90b	309	}
067a3ddc PB	310	nmi[0] = qdev_get_gpio_in(dev, 30);
067a3ddc PB	311	nmi[1] = qdev_get_gpio_in(dev, 31);
73cfd29f	312
ba494313	313	etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
10c144e2 EI	314	for (i = 0; i < 10; i++) {
10c144e2 EI	315	/* On ETRAX, odd numbered channels are inputs. */
73cfd29f	316	etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
10c144e2 EI	317	}
	318
	319	/* Add the two ethernet blocks. */
7267c094	320	dma_eth = g_malloc0(sizeof dma_eth[0] * 4); /* Allocate 4 channels. */
1da005b3 EI	321	etraxfs_eth_init(&nd_table[0], 0x30034000, 1, &dma_eth[0], &dma_eth[1]);
	322	if (nb_nics > 1) {
	323	etraxfs_eth_init(&nd_table[1], 0x30036000, 2, &dma_eth[2], &dma_eth[3]);
	324	}
10c144e2 EI	325
10c144e2 EI	326	/* The DMA Connector block is missing, hardwire things for now. */
1da005b3 EI	327	etraxfs_dmac_connect_client(etraxfs_dmac, 0, &dma_eth[0]);
	328	etraxfs_dmac_connect_client(etraxfs_dmac, 1, &dma_eth[1]);
	329	if (nb_nics > 1) {
	330	etraxfs_dmac_connect_client(etraxfs_dmac, 6, &dma_eth[2]);
	331	etraxfs_dmac_connect_client(etraxfs_dmac, 7, &dma_eth[3]);
10c144e2 EI	332	}
	333
	334	/* 2 timers. */
3b1fd90e EI	335	sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
3b1fd90e EI	336	sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);
10c144e2 EI	337
10c144e2 EI	338	for (i = 0; i < 4; i++) {
4b816985	339	sysbus_create_simple("etraxfs,serial", 0x30026000 + i * 0x2000,
3b1fd90e	340	irq[0x14 + i]);
10c144e2 EI	341	}
10c144e2 EI	342
77d4f95e EI	343	if (!kernel_filename) {
	344	fprintf(stderr, "Kernel image must be specified\n");
	345	exit(1);
10c144e2	346	}
77d4f95e EI	347
	348	li.image_filename = kernel_filename;
	349	li.cmdline = kernel_cmdline;
5935664f	350	cris_load_image(cpu, &li);
10c144e2 EI	351	}
10c144e2 EI	352
f80f9ec9	353	static QEMUMachine axisdev88_machine = {
10c144e2 EI	354	.name = "axis-dev88",
	355	.desc = "AXIS devboard 88",
	356	.init = axisdev88_init,
bbea04df	357	.is_default = 1,
e4ada29e	358	DEFAULT_MACHINE_OPTIONS,
10c144e2	359	};
f80f9ec9 AL	360
	361	static void axisdev88_machine_init(void)
	362	{
	363	qemu_register_machine(&axisdev88_machine);
	364	}
	365
	366	machine_init(axisdev88_machine_init);