[qemu.git] / hw / ppc4xx_devs.c

/*
 * QEMU PowerPC 4xx embedded processors shared devices emulation
 *
 * Copyright (c) 2007 Jocelyn Mayer
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "ppc.h"
#include "ppc4xx.h"
#include "qemu-log.h"

//#define DEBUG_MMIO
//#define DEBUG_UNASSIGNED
#define DEBUG_UIC


#ifdef DEBUG_UIC
#  define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
#else
#  define LOG_UIC(...) do { } while (0)
#endif

/*****************************************************************************/
/* Generic PowerPC 4xx processor instanciation */
CPUState *ppc4xx_init (const char *cpu_model,
                       clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
                       uint32_t sysclk)
{
    CPUState *env;

    /* init CPUs */
    env = cpu_init(cpu_model);
    if (!env) {
        fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
                cpu_model);
        exit(1);
    }
    cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
    cpu_clk->opaque = env;
    /* Set time-base frequency to sysclk */
    tb_clk->cb = ppc_emb_timers_init(env, sysclk, PPC_INTERRUPT_PIT);
    tb_clk->opaque = env;
    ppc_dcr_init(env, NULL, NULL);
    /* Register qemu callbacks */
    qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);

    return env;
}

/*****************************************************************************/
/* "Universal" Interrupt controller */
enum {
    DCR_UICSR  = 0x000,
    DCR_UICSRS = 0x001,
    DCR_UICER  = 0x002,
    DCR_UICCR  = 0x003,
    DCR_UICPR  = 0x004,
    DCR_UICTR  = 0x005,
    DCR_UICMSR = 0x006,
    DCR_UICVR  = 0x007,
    DCR_UICVCR = 0x008,
    DCR_UICMAX = 0x009,
};

#define UIC_MAX_IRQ 32
typedef struct ppcuic_t ppcuic_t;
struct ppcuic_t {
    uint32_t dcr_base;
    int use_vectors;
    uint32_t level;  /* Remembers the state of level-triggered interrupts. */
    uint32_t uicsr;  /* Status register */
    uint32_t uicer;  /* Enable register */
    uint32_t uiccr;  /* Critical register */
    uint32_t uicpr;  /* Polarity register */
    uint32_t uictr;  /* Triggering register */
    uint32_t uicvcr; /* Vector configuration register */
    uint32_t uicvr;
    qemu_irq *irqs;
};

static void ppcuic_trigger_irq (ppcuic_t *uic)
{
    uint32_t ir, cr;
    int start, end, inc, i;

    /* Trigger interrupt if any is pending */
    ir = uic->uicsr & uic->uicer & (~uic->uiccr);
    cr = uic->uicsr & uic->uicer & uic->uiccr;
    LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32
                " uiccr %08" PRIx32 "\n"
                "   %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
                __func__, uic->uicsr, uic->uicer, uic->uiccr,
                uic->uicsr & uic->uicer, ir, cr);
    if (ir != 0x0000000) {
        LOG_UIC("Raise UIC interrupt\n");
        qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
    } else {
        LOG_UIC("Lower UIC interrupt\n");
        qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
    }
    /* Trigger critical interrupt if any is pending and update vector */
    if (cr != 0x0000000) {
        qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
        if (uic->use_vectors) {
            /* Compute critical IRQ vector */
            if (uic->uicvcr & 1) {
                start = 31;
                end = 0;
                inc = -1;
            } else {
                start = 0;
                end = 31;
                inc = 1;
            }
            uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
            for (i = start; i <= end; i += inc) {
                if (cr & (1 << i)) {
                    uic->uicvr += (i - start) * 512 * inc;
                    break;
                }
            }
        }
        LOG_UIC("Raise UIC critical interrupt - "
                    "vector %08" PRIx32 "\n", uic->uicvr);
    } else {
        LOG_UIC("Lower UIC critical interrupt\n");
        qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
        uic->uicvr = 0x00000000;
    }
}

static void ppcuic_set_irq (void *opaque, int irq_num, int level)
{
    ppcuic_t *uic;
    uint32_t mask, sr;

    uic = opaque;
    mask = 1 << (31-irq_num);
    LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
                " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
                __func__, irq_num, level,
                uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
    if (irq_num < 0 || irq_num > 31)
        return;
    sr = uic->uicsr;

    /* Update status register */
    if (uic->uictr & mask) {
        /* Edge sensitive interrupt */
        if (level == 1)
            uic->uicsr |= mask;
    } else {
        /* Level sensitive interrupt */
        if (level == 1) {
            uic->uicsr |= mask;
            uic->level |= mask;
        } else {
            uic->uicsr &= ~mask;
            uic->level &= ~mask;
        }
    }
    LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => "
                "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
    if (sr != uic->uicsr)
        ppcuic_trigger_irq(uic);
}

static uint32_t dcr_read_uic (void *opaque, int dcrn)
{
    ppcuic_t *uic;
    uint32_t ret;

    uic = opaque;
    dcrn -= uic->dcr_base;
    switch (dcrn) {
    case DCR_UICSR:
    case DCR_UICSRS:
        ret = uic->uicsr;
        break;
    case DCR_UICER:
        ret = uic->uicer;
        break;
    case DCR_UICCR:
        ret = uic->uiccr;
        break;
    case DCR_UICPR:
        ret = uic->uicpr;
        break;
    case DCR_UICTR:
        ret = uic->uictr;
        break;
    case DCR_UICMSR:
        ret = uic->uicsr & uic->uicer;
        break;
    case DCR_UICVR:
        if (!uic->use_vectors)
            goto no_read;
        ret = uic->uicvr;
        break;
    case DCR_UICVCR:
        if (!uic->use_vectors)
            goto no_read;
        ret = uic->uicvcr;
        break;
    default:
    no_read:
        ret = 0x00000000;
        break;
    }

    return ret;
}

static void dcr_write_uic (void *opaque, int dcrn, uint32_t val)
{
    ppcuic_t *uic;

    uic = opaque;
    dcrn -= uic->dcr_base;
    LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val);
    switch (dcrn) {
    case DCR_UICSR:
        uic->uicsr &= ~val;
        uic->uicsr |= uic->level;
        ppcuic_trigger_irq(uic);
        break;
    case DCR_UICSRS:
        uic->uicsr |= val;
        ppcuic_trigger_irq(uic);
        break;
    case DCR_UICER:
        uic->uicer = val;
        ppcuic_trigger_irq(uic);
        break;
    case DCR_UICCR:
        uic->uiccr = val;
        ppcuic_trigger_irq(uic);
        break;
    case DCR_UICPR:
        uic->uicpr = val;
        break;
    case DCR_UICTR:
        uic->uictr = val;
        ppcuic_trigger_irq(uic);
        break;
    case DCR_UICMSR:
        break;
    case DCR_UICVR:
        break;
    case DCR_UICVCR:
        uic->uicvcr = val & 0xFFFFFFFD;
        ppcuic_trigger_irq(uic);
        break;
    }
}

static void ppcuic_reset (void *opaque)
{
    ppcuic_t *uic;

    uic = opaque;
    uic->uiccr = 0x00000000;
    uic->uicer = 0x00000000;
    uic->uicpr = 0x00000000;
    uic->uicsr = 0x00000000;
    uic->uictr = 0x00000000;
    if (uic->use_vectors) {
        uic->uicvcr = 0x00000000;
        uic->uicvr = 0x0000000;
    }
}

qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
                       uint32_t dcr_base, int has_ssr, int has_vr)
{
    ppcuic_t *uic;
    int i;

    uic = qemu_mallocz(sizeof(ppcuic_t));
    uic->dcr_base = dcr_base;
    uic->irqs = irqs;
    if (has_vr)
        uic->use_vectors = 1;
    for (i = 0; i < DCR_UICMAX; i++) {
        ppc_dcr_register(env, dcr_base + i, uic,
                         &dcr_read_uic, &dcr_write_uic);
    }
    qemu_register_reset(ppcuic_reset, uic);

    return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
}

/*****************************************************************************/
/* SDRAM controller */
typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
struct ppc4xx_sdram_t {
    uint32_t addr;
    int nbanks;
    target_phys_addr_t ram_bases[4];
    target_phys_addr_t ram_sizes[4];
    uint32_t besr0;
    uint32_t besr1;
    uint32_t bear;
    uint32_t cfg;
    uint32_t status;
    uint32_t rtr;
    uint32_t pmit;
    uint32_t bcr[4];
    uint32_t tr;
    uint32_t ecccfg;
    uint32_t eccesr;
    qemu_irq irq;
};

enum {
    SDRAM0_CFGADDR = 0x010,
    SDRAM0_CFGDATA = 0x011,
};

/* XXX: TOFIX: some patches have made this code become inconsistent:
 *      there are type inconsistencies, mixing target_phys_addr_t, target_ulong
 *      and uint32_t
 */
static uint32_t sdram_bcr (target_phys_addr_t ram_base,
                           target_phys_addr_t ram_size)
{
    uint32_t bcr;

    switch (ram_size) {
    case (4 * 1024 * 1024):
        bcr = 0x00000000;
        break;
    case (8 * 1024 * 1024):
        bcr = 0x00020000;
        break;
    case (16 * 1024 * 1024):
        bcr = 0x00040000;
        break;
    case (32 * 1024 * 1024):
        bcr = 0x00060000;
        break;
    case (64 * 1024 * 1024):
        bcr = 0x00080000;
        break;
    case (128 * 1024 * 1024):
        bcr = 0x000A0000;
        break;
    case (256 * 1024 * 1024):
        bcr = 0x000C0000;
        break;
    default:
        printf("%s: invalid RAM size " TARGET_FMT_plx "\n", __func__,
               ram_size);
        return 0x00000000;
    }
    bcr |= ram_base & 0xFF800000;
    bcr |= 1;

    return bcr;
}

static inline target_phys_addr_t sdram_base(uint32_t bcr)
{
    return bcr & 0xFF800000;
}

static target_ulong sdram_size (uint32_t bcr)
{
    target_ulong size;
    int sh;

    sh = (bcr >> 17) & 0x7;
    if (sh == 7)
        size = -1;
    else
        size = (4 * 1024 * 1024) << sh;

    return size;
}

static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
{
    if (*bcrp & 0x00000001) {
        /* Unmap RAM */
#ifdef DEBUG_SDRAM
        printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
               __func__, sdram_base(*bcrp), sdram_size(*bcrp));
#endif
        cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
                                     IO_MEM_UNASSIGNED);
    }
    *bcrp = bcr & 0xFFDEE001;
    if (enabled && (bcr & 0x00000001)) {
#ifdef DEBUG_SDRAM
        printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
               __func__, sdram_base(bcr), sdram_size(bcr));
#endif
        cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
                                     sdram_base(bcr) | IO_MEM_RAM);
    }
}

static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
{
    int i;

    for (i = 0; i < sdram->nbanks; i++) {
        if (sdram->ram_sizes[i] != 0) {
            sdram_set_bcr(&sdram->bcr[i],
                          sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]),
                          1);
        } else {
            sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0);
        }
    }
}

static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
{
    int i;

    for (i = 0; i < sdram->nbanks; i++) {
#ifdef DEBUG_SDRAM
        printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
               __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
#endif
        cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
                                     sdram_size(sdram->bcr[i]),
                                     IO_MEM_UNASSIGNED);
    }
}

static uint32_t dcr_read_sdram (void *opaque, int dcrn)
{
    ppc4xx_sdram_t *sdram;
    uint32_t ret;

    sdram = opaque;
    switch (dcrn) {
    case SDRAM0_CFGADDR:
        ret = sdram->addr;
        break;
    case SDRAM0_CFGDATA:
        switch (sdram->addr) {
        case 0x00: /* SDRAM_BESR0 */
            ret = sdram->besr0;
            break;
        case 0x08: /* SDRAM_BESR1 */
            ret = sdram->besr1;
            break;
        case 0x10: /* SDRAM_BEAR */
            ret = sdram->bear;
            break;
        case 0x20: /* SDRAM_CFG */
            ret = sdram->cfg;
            break;
        case 0x24: /* SDRAM_STATUS */
            ret = sdram->status;
            break;
        case 0x30: /* SDRAM_RTR */
            ret = sdram->rtr;
            break;
        case 0x34: /* SDRAM_PMIT */
            ret = sdram->pmit;
            break;
        case 0x40: /* SDRAM_B0CR */
            ret = sdram->bcr[0];
            break;
        case 0x44: /* SDRAM_B1CR */
            ret = sdram->bcr[1];
            break;
        case 0x48: /* SDRAM_B2CR */
            ret = sdram->bcr[2];
            break;
        case 0x4C: /* SDRAM_B3CR */
            ret = sdram->bcr[3];
            break;
        case 0x80: /* SDRAM_TR */
            ret = -1; /* ? */
            break;
        case 0x94: /* SDRAM_ECCCFG */
            ret = sdram->ecccfg;
            break;
        case 0x98: /* SDRAM_ECCESR */
            ret = sdram->eccesr;
            break;
        default: /* Error */
            ret = -1;
            break;
        }
        break;
    default:
        /* Avoid gcc warning */
        ret = 0x00000000;
        break;
    }

    return ret;
}

static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val)
{
    ppc4xx_sdram_t *sdram;

    sdram = opaque;
    switch (dcrn) {
    case SDRAM0_CFGADDR:
        sdram->addr = val;
        break;
    case SDRAM0_CFGDATA:
        switch (sdram->addr) {
        case 0x00: /* SDRAM_BESR0 */
            sdram->besr0 &= ~val;
            break;
        case 0x08: /* SDRAM_BESR1 */
            sdram->besr1 &= ~val;
            break;
        case 0x10: /* SDRAM_BEAR */
            sdram->bear = val;
            break;
        case 0x20: /* SDRAM_CFG */
            val &= 0xFFE00000;
            if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
#ifdef DEBUG_SDRAM
                printf("%s: enable SDRAM controller\n", __func__);
#endif
                /* validate all RAM mappings */
                sdram_map_bcr(sdram);
                sdram->status &= ~0x80000000;
            } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
#ifdef DEBUG_SDRAM
                printf("%s: disable SDRAM controller\n", __func__);
#endif
                /* invalidate all RAM mappings */
                sdram_unmap_bcr(sdram);
                sdram->status |= 0x80000000;
            }
            if (!(sdram->cfg & 0x40000000) && (val & 0x40000000))
                sdram->status |= 0x40000000;
            else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000))
                sdram->status &= ~0x40000000;
            sdram->cfg = val;
            break;
        case 0x24: /* SDRAM_STATUS */
            /* Read-only register */
            break;
        case 0x30: /* SDRAM_RTR */
            sdram->rtr = val & 0x3FF80000;
            break;
        case 0x34: /* SDRAM_PMIT */
            sdram->pmit = (val & 0xF8000000) | 0x07C00000;
            break;
        case 0x40: /* SDRAM_B0CR */
            sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000);
            break;
        case 0x44: /* SDRAM_B1CR */
            sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000);
            break;
        case 0x48: /* SDRAM_B2CR */
            sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000);
            break;
        case 0x4C: /* SDRAM_B3CR */
            sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000);
            break;
        case 0x80: /* SDRAM_TR */
            sdram->tr = val & 0x018FC01F;
            break;
        case 0x94: /* SDRAM_ECCCFG */
            sdram->ecccfg = val & 0x00F00000;
            break;
        case 0x98: /* SDRAM_ECCESR */
            val &= 0xFFF0F000;
            if (sdram->eccesr == 0 && val != 0)
                qemu_irq_raise(sdram->irq);
            else if (sdram->eccesr != 0 && val == 0)
                qemu_irq_lower(sdram->irq);
            sdram->eccesr = val;
            break;
        default: /* Error */
            break;
        }
        break;
    }
}

static void sdram_reset (void *opaque)
{
    ppc4xx_sdram_t *sdram;

    sdram = opaque;
    sdram->addr = 0x00000000;
    sdram->bear = 0x00000000;
    sdram->besr0 = 0x00000000; /* No error */
    sdram->besr1 = 0x00000000; /* No error */
    sdram->cfg = 0x00000000;
    sdram->ecccfg = 0x00000000; /* No ECC */
    sdram->eccesr = 0x00000000; /* No error */
    sdram->pmit = 0x07C00000;
    sdram->rtr = 0x05F00000;
    sdram->tr = 0x00854009;
    /* We pre-initialize RAM banks */
    sdram->status = 0x00000000;
    sdram->cfg = 0x00800000;
}

void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
                        target_phys_addr_t *ram_bases,
                        target_phys_addr_t *ram_sizes,
                        int do_init)
{
    ppc4xx_sdram_t *sdram;

    sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
    sdram->irq = irq;
    sdram->nbanks = nbanks;
    memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
    memcpy(sdram->ram_bases, ram_bases,
           nbanks * sizeof(target_phys_addr_t));
    memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
    memcpy(sdram->ram_sizes, ram_sizes,
           nbanks * sizeof(target_phys_addr_t));
    qemu_register_reset(&sdram_reset, sdram);
    ppc_dcr_register(env, SDRAM0_CFGADDR,
                     sdram, &dcr_read_sdram, &dcr_write_sdram);
    ppc_dcr_register(env, SDRAM0_CFGDATA,
                     sdram, &dcr_read_sdram, &dcr_write_sdram);
    if (do_init)
        sdram_map_bcr(sdram);
}

/* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory.
 *
 * sdram_bank_sizes[] must be 0-terminated.
 *
 * The 4xx SDRAM controller supports a small number of banks, and each bank
 * must be one of a small set of sizes. The number of banks and the supported
 * sizes varies by SoC. */
ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
                               target_phys_addr_t ram_bases[],
                               target_phys_addr_t ram_sizes[],
                               const unsigned int sdram_bank_sizes[])
{
    ram_addr_t size_left = ram_size;
    int i;
    int j;

    for (i = 0; i < nr_banks; i++) {
        for (j = 0; sdram_bank_sizes[j] != 0; j++) {
            unsigned int bank_size = sdram_bank_sizes[j];

            if (bank_size <= size_left) {
                char name[32];
                snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
                ram_bases[i] = qemu_ram_alloc(NULL, name, bank_size);
                ram_sizes[i] = bank_size;
                size_left -= bank_size;
                break;
            }
        }

        if (!size_left) {
            /* No need to use the remaining banks. */
            break;
        }
    }

    ram_size -= size_left;
    if (size_left)
        printf("Truncating memory to %d MiB to fit SDRAM controller limits.\n",
               (int)(ram_size >> 20));

    return ram_size;
}
Commit	Line	Data
008ff9d7 JM	1	/*
	2	* QEMU PowerPC 4xx embedded processors shared devices emulation
	3	*
	4	* Copyright (c) 2007 Jocelyn Mayer
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
87ecb68b PB	25	#include "ppc.h"
008ff9d7	26	#include "ppc4xx.h"
3b3fb322	27	#include "qemu-log.h"
008ff9d7 JM	28
008ff9d7 JM	29	//#define DEBUG_MMIO
aae9366a	30	//#define DEBUG_UNASSIGNED
008ff9d7 JM	31	#define DEBUG_UIC
008ff9d7 JM	32
d12d51d5 AL	33
d12d51d5 AL	34	#ifdef DEBUG_UIC
93fcfe39	35	# define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
d12d51d5 AL	36	#else
	37	# define LOG_UIC(...) do { } while (0)
	38	#endif
	39
008ff9d7 JM	40	/*****************************************************************************/
008ff9d7 JM	41	/* Generic PowerPC 4xx processor instanciation */
b55266b5	42	CPUState ppc4xx_init (const char cpu_model,
c227f099	43	clk_setup_t cpu_clk, clk_setup_t tb_clk,
008ff9d7 JM	44	uint32_t sysclk)
	45	{
	46	CPUState *env;
008ff9d7 JM	47
008ff9d7 JM	48	/* init CPUs */
aaed909a FB	49	env = cpu_init(cpu_model);
	50	if (!env) {
	51	fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
	52	cpu_model);
	53	exit(1);
008ff9d7	54	}
008ff9d7 JM	55	cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
	56	cpu_clk->opaque = env;
	57	/* Set time-base frequency to sysclk */
d63cb48d	58	tb_clk->cb = ppc_emb_timers_init(env, sysclk, PPC_INTERRUPT_PIT);
008ff9d7 JM	59	tb_clk->opaque = env;
	60	ppc_dcr_init(env, NULL, NULL);
	61	/* Register qemu callbacks */
d84bda46	62	qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
008ff9d7 JM	63
	64	return env;
	65	}
	66
008ff9d7 JM	67	/*****************************************************************************/
	68	/* "Universal" Interrupt controller */
	69	enum {
	70	DCR_UICSR = 0x000,
	71	DCR_UICSRS = 0x001,
	72	DCR_UICER = 0x002,
	73	DCR_UICCR = 0x003,
	74	DCR_UICPR = 0x004,
	75	DCR_UICTR = 0x005,
	76	DCR_UICMSR = 0x006,
	77	DCR_UICVR = 0x007,
	78	DCR_UICVCR = 0x008,
	79	DCR_UICMAX = 0x009,
	80	};
	81
	82	#define UIC_MAX_IRQ 32
c227f099 AL	83	typedef struct ppcuic_t ppcuic_t;
c227f099 AL	84	struct ppcuic_t {
008ff9d7 JM	85	uint32_t dcr_base;
008ff9d7 JM	86	int use_vectors;
4c54e875	87	uint32_t level; /* Remembers the state of level-triggered interrupts. */
008ff9d7 JM	88	uint32_t uicsr; /* Status register */
	89	uint32_t uicer; /* Enable register */
	90	uint32_t uiccr; /* Critical register */
	91	uint32_t uicpr; /* Polarity register */
	92	uint32_t uictr; /* Triggering register */
	93	uint32_t uicvcr; /* Vector configuration register */
	94	uint32_t uicvr;
	95	qemu_irq *irqs;
	96	};
	97
c227f099	98	static void ppcuic_trigger_irq (ppcuic_t *uic)
008ff9d7 JM	99	{
	100	uint32_t ir, cr;
	101	int start, end, inc, i;
	102
	103	/* Trigger interrupt if any is pending */
	104	ir = uic->uicsr & uic->uicer & (~uic->uiccr);
	105	cr = uic->uicsr & uic->uicer & uic->uiccr;
d12d51d5	106	LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32
aae9366a JM	107	" uiccr %08" PRIx32 "\n"
	108	" %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
	109	__func__, uic->uicsr, uic->uicer, uic->uiccr,
008ff9d7	110	uic->uicsr & uic->uicer, ir, cr);
008ff9d7	111	if (ir != 0x0000000) {
d12d51d5	112	LOG_UIC("Raise UIC interrupt\n");
008ff9d7 JM	113	qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
008ff9d7 JM	114	} else {
d12d51d5	115	LOG_UIC("Lower UIC interrupt\n");
008ff9d7 JM	116	qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
	117	}
	118	/* Trigger critical interrupt if any is pending and update vector */
	119	if (cr != 0x0000000) {
	120	qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
	121	if (uic->use_vectors) {
	122	/* Compute critical IRQ vector */
	123	if (uic->uicvcr & 1) {
	124	start = 31;
	125	end = 0;
	126	inc = -1;
	127	} else {
	128	start = 0;
	129	end = 31;
	130	inc = 1;
	131	}
	132	uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
	133	for (i = start; i <= end; i += inc) {
	134	if (cr & (1 << i)) {
	135	uic->uicvr += (i - start) * 512 * inc;
	136	break;
	137	}
	138	}
	139	}
d12d51d5	140	LOG_UIC("Raise UIC critical interrupt - "
aae9366a	141	"vector %08" PRIx32 "\n", uic->uicvr);
008ff9d7	142	} else {
d12d51d5	143	LOG_UIC("Lower UIC critical interrupt\n");
008ff9d7 JM	144	qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
	145	uic->uicvr = 0x00000000;
	146	}
	147	}
	148
	149	static void ppcuic_set_irq (void *opaque, int irq_num, int level)
	150	{
c227f099	151	ppcuic_t *uic;
008ff9d7 JM	152	uint32_t mask, sr;
	153
	154	uic = opaque;
923e5e33	155	mask = 1 << (31-irq_num);
d12d51d5	156	LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
aae9366a JM	157	" mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
aae9366a JM	158	__func__, irq_num, level,
008ff9d7	159	uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
008ff9d7 JM	160	if (irq_num < 0 \|\| irq_num > 31)
	161	return;
	162	sr = uic->uicsr;
50bf72b3	163
008ff9d7 JM	164	/* Update status register */
	165	if (uic->uictr & mask) {
	166	/* Edge sensitive interrupt */
	167	if (level == 1)
	168	uic->uicsr \|= mask;
	169	} else {
	170	/* Level sensitive interrupt */
4c54e875	171	if (level == 1) {
008ff9d7	172	uic->uicsr \|= mask;
4c54e875 AJ	173	uic->level \|= mask;
4c54e875 AJ	174	} else {
008ff9d7	175	uic->uicsr &= ~mask;
4c54e875 AJ	176	uic->level &= ~mask;
4c54e875 AJ	177	}
008ff9d7	178	}
d12d51d5	179	LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => "
aae9366a	180	"%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
008ff9d7 JM	181	if (sr != uic->uicsr)
	182	ppcuic_trigger_irq(uic);
	183	}
	184
73b01960	185	static uint32_t dcr_read_uic (void *opaque, int dcrn)
008ff9d7	186	{
c227f099	187	ppcuic_t *uic;
73b01960	188	uint32_t ret;
008ff9d7 JM	189
	190	uic = opaque;
	191	dcrn -= uic->dcr_base;
	192	switch (dcrn) {
	193	case DCR_UICSR:
	194	case DCR_UICSRS:
	195	ret = uic->uicsr;
	196	break;
	197	case DCR_UICER:
	198	ret = uic->uicer;
	199	break;
	200	case DCR_UICCR:
	201	ret = uic->uiccr;
	202	break;
	203	case DCR_UICPR:
	204	ret = uic->uicpr;
	205	break;
	206	case DCR_UICTR:
	207	ret = uic->uictr;
	208	break;
	209	case DCR_UICMSR:
	210	ret = uic->uicsr & uic->uicer;
	211	break;
	212	case DCR_UICVR:
	213	if (!uic->use_vectors)
	214	goto no_read;
	215	ret = uic->uicvr;
	216	break;
	217	case DCR_UICVCR:
	218	if (!uic->use_vectors)
	219	goto no_read;
	220	ret = uic->uicvcr;
	221	break;
	222	default:
	223	no_read:
	224	ret = 0x00000000;
	225	break;
	226	}
	227
	228	return ret;
	229	}
	230
73b01960	231	static void dcr_write_uic (void *opaque, int dcrn, uint32_t val)
008ff9d7	232	{
c227f099	233	ppcuic_t *uic;
008ff9d7 JM	234
	235	uic = opaque;
	236	dcrn -= uic->dcr_base;
73b01960	237	LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val);
008ff9d7 JM	238	switch (dcrn) {
	239	case DCR_UICSR:
	240	uic->uicsr &= ~val;
4c54e875	241	uic->uicsr \|= uic->level;
008ff9d7 JM	242	ppcuic_trigger_irq(uic);
	243	break;
	244	case DCR_UICSRS:
	245	uic->uicsr \|= val;
	246	ppcuic_trigger_irq(uic);
	247	break;
	248	case DCR_UICER:
	249	uic->uicer = val;
	250	ppcuic_trigger_irq(uic);
	251	break;
	252	case DCR_UICCR:
	253	uic->uiccr = val;
	254	ppcuic_trigger_irq(uic);
	255	break;
	256	case DCR_UICPR:
	257	uic->uicpr = val;
008ff9d7 JM	258	break;
	259	case DCR_UICTR:
	260	uic->uictr = val;
	261	ppcuic_trigger_irq(uic);
	262	break;
	263	case DCR_UICMSR:
	264	break;
	265	case DCR_UICVR:
	266	break;
	267	case DCR_UICVCR:
	268	uic->uicvcr = val & 0xFFFFFFFD;
	269	ppcuic_trigger_irq(uic);
	270	break;
	271	}
	272	}
	273
	274	static void ppcuic_reset (void *opaque)
	275	{
c227f099	276	ppcuic_t *uic;
008ff9d7 JM	277
	278	uic = opaque;
	279	uic->uiccr = 0x00000000;
	280	uic->uicer = 0x00000000;
	281	uic->uicpr = 0x00000000;
	282	uic->uicsr = 0x00000000;
	283	uic->uictr = 0x00000000;
	284	if (uic->use_vectors) {
	285	uic->uicvcr = 0x00000000;
	286	uic->uicvr = 0x0000000;
	287	}
	288	}
	289
	290	qemu_irq ppcuic_init (CPUState env, qemu_irq *irqs,
	291	uint32_t dcr_base, int has_ssr, int has_vr)
	292	{
c227f099	293	ppcuic_t *uic;
008ff9d7 JM	294	int i;
008ff9d7 JM	295
c227f099	296	uic = qemu_mallocz(sizeof(ppcuic_t));
487414f1 AL	297	uic->dcr_base = dcr_base;
	298	uic->irqs = irqs;
	299	if (has_vr)
	300	uic->use_vectors = 1;
	301	for (i = 0; i < DCR_UICMAX; i++) {
	302	ppc_dcr_register(env, dcr_base + i, uic,
	303	&dcr_read_uic, &dcr_write_uic);
008ff9d7	304	}
a08d4367	305	qemu_register_reset(ppcuic_reset, uic);
008ff9d7 JM	306
	307	return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
	308	}
61b24405 AJ	309
	310	/*****************************************************************************/
	311	/* SDRAM controller */
c227f099 AL	312	typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
c227f099 AL	313	struct ppc4xx_sdram_t {
61b24405 AJ	314	uint32_t addr;
61b24405 AJ	315	int nbanks;
c227f099 AL	316	target_phys_addr_t ram_bases[4];
c227f099 AL	317	target_phys_addr_t ram_sizes[4];
61b24405 AJ	318	uint32_t besr0;
	319	uint32_t besr1;
	320	uint32_t bear;
	321	uint32_t cfg;
	322	uint32_t status;
	323	uint32_t rtr;
	324	uint32_t pmit;
	325	uint32_t bcr[4];
	326	uint32_t tr;
	327	uint32_t ecccfg;
	328	uint32_t eccesr;
	329	qemu_irq irq;
	330	};
	331
	332	enum {
	333	SDRAM0_CFGADDR = 0x010,
	334	SDRAM0_CFGDATA = 0x011,
	335	};
	336
	337	/* XXX: TOFIX: some patches have made this code become inconsistent:
c227f099	338	* there are type inconsistencies, mixing target_phys_addr_t, target_ulong
61b24405 AJ	339	* and uint32_t
61b24405 AJ	340	*/
c227f099 AL	341	static uint32_t sdram_bcr (target_phys_addr_t ram_base,
c227f099 AL	342	target_phys_addr_t ram_size)
61b24405 AJ	343	{
	344	uint32_t bcr;
	345
	346	switch (ram_size) {
	347	case (4 * 1024 * 1024):
	348	bcr = 0x00000000;
	349	break;
	350	case (8 * 1024 * 1024):
	351	bcr = 0x00020000;
	352	break;
	353	case (16 * 1024 * 1024):
	354	bcr = 0x00040000;
	355	break;
	356	case (32 * 1024 * 1024):
	357	bcr = 0x00060000;
	358	break;
	359	case (64 * 1024 * 1024):
	360	bcr = 0x00080000;
	361	break;
	362	case (128 * 1024 * 1024):
	363	bcr = 0x000A0000;
	364	break;
	365	case (256 * 1024 * 1024):
	366	bcr = 0x000C0000;
	367	break;
	368	default:
90e189ec BS	369	printf("%s: invalid RAM size " TARGET_FMT_plx "\n", __func__,
90e189ec BS	370	ram_size);
61b24405 AJ	371	return 0x00000000;
	372	}
	373	bcr \|= ram_base & 0xFF800000;
	374	bcr \|= 1;
	375
	376	return bcr;
	377	}
	378
c227f099	379	static inline target_phys_addr_t sdram_base(uint32_t bcr)
61b24405 AJ	380	{
	381	return bcr & 0xFF800000;
	382	}
	383
	384	static target_ulong sdram_size (uint32_t bcr)
	385	{
	386	target_ulong size;
	387	int sh;
	388
	389	sh = (bcr >> 17) & 0x7;
	390	if (sh == 7)
	391	size = -1;
	392	else
	393	size = (4 * 1024 * 1024) << sh;
	394
	395	return size;
	396	}
	397
	398	static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
	399	{
	400	if (*bcrp & 0x00000001) {
	401	/* Unmap RAM */
	402	#ifdef DEBUG_SDRAM
90e189ec	403	printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
61b24405 AJ	404	__func__, sdram_base(bcrp), sdram_size(bcrp));
	405	#endif
	406	cpu_register_physical_memory(sdram_base(bcrp), sdram_size(bcrp),
	407	IO_MEM_UNASSIGNED);
	408	}
	409	*bcrp = bcr & 0xFFDEE001;
	410	if (enabled && (bcr & 0x00000001)) {
	411	#ifdef DEBUG_SDRAM
90e189ec	412	printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
61b24405 AJ	413	__func__, sdram_base(bcr), sdram_size(bcr));
	414	#endif
	415	cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
	416	sdram_base(bcr) \| IO_MEM_RAM);
	417	}
	418	}
	419
c227f099	420	static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
61b24405 AJ	421	{
	422	int i;
	423
	424	for (i = 0; i < sdram->nbanks; i++) {
	425	if (sdram->ram_sizes[i] != 0) {
	426	sdram_set_bcr(&sdram->bcr[i],
	427	sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]),
	428	1);
	429	} else {
	430	sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0);
	431	}
	432	}
	433	}
	434
c227f099	435	static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
61b24405 AJ	436	{
	437	int i;
	438
	439	for (i = 0; i < sdram->nbanks; i++) {
	440	#ifdef DEBUG_SDRAM
90e189ec	441	printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
61b24405 AJ	442	__func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
	443	#endif
	444	cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
	445	sdram_size(sdram->bcr[i]),
	446	IO_MEM_UNASSIGNED);
	447	}
	448	}
	449
73b01960	450	static uint32_t dcr_read_sdram (void *opaque, int dcrn)
61b24405	451	{
c227f099	452	ppc4xx_sdram_t *sdram;
73b01960	453	uint32_t ret;
61b24405 AJ	454
	455	sdram = opaque;
	456	switch (dcrn) {
	457	case SDRAM0_CFGADDR:
	458	ret = sdram->addr;
	459	break;
	460	case SDRAM0_CFGDATA:
	461	switch (sdram->addr) {
	462	case 0x00: /* SDRAM_BESR0 */
	463	ret = sdram->besr0;
	464	break;
	465	case 0x08: /* SDRAM_BESR1 */
	466	ret = sdram->besr1;
	467	break;
	468	case 0x10: /* SDRAM_BEAR */
	469	ret = sdram->bear;
	470	break;
	471	case 0x20: /* SDRAM_CFG */
	472	ret = sdram->cfg;
	473	break;
	474	case 0x24: /* SDRAM_STATUS */
	475	ret = sdram->status;
	476	break;
	477	case 0x30: /* SDRAM_RTR */
	478	ret = sdram->rtr;
	479	break;
	480	case 0x34: /* SDRAM_PMIT */
	481	ret = sdram->pmit;
	482	break;
	483	case 0x40: /* SDRAM_B0CR */
	484	ret = sdram->bcr[0];
	485	break;
	486	case 0x44: /* SDRAM_B1CR */
	487	ret = sdram->bcr[1];
	488	break;
	489	case 0x48: /* SDRAM_B2CR */
	490	ret = sdram->bcr[2];
	491	break;
	492	case 0x4C: /* SDRAM_B3CR */
	493	ret = sdram->bcr[3];
	494	break;
	495	case 0x80: /* SDRAM_TR */
	496	ret = -1; /* ? */
	497	break;
	498	case 0x94: /* SDRAM_ECCCFG */
	499	ret = sdram->ecccfg;
	500	break;
	501	case 0x98: /* SDRAM_ECCESR */
	502	ret = sdram->eccesr;
	503	break;
	504	default: /* Error */
	505	ret = -1;
	506	break;
	507	}
	508	break;
	509	default:
	510	/* Avoid gcc warning */
	511	ret = 0x00000000;
	512	break;
	513	}
	514
	515	return ret;
	516	}
	517
73b01960	518	static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val)
61b24405	519	{
c227f099	520	ppc4xx_sdram_t *sdram;
61b24405 AJ	521
	522	sdram = opaque;
	523	switch (dcrn) {
	524	case SDRAM0_CFGADDR:
	525	sdram->addr = val;
	526	break;
	527	case SDRAM0_CFGDATA:
	528	switch (sdram->addr) {
	529	case 0x00: /* SDRAM_BESR0 */
	530	sdram->besr0 &= ~val;
	531	break;
	532	case 0x08: /* SDRAM_BESR1 */
	533	sdram->besr1 &= ~val;
	534	break;
	535	case 0x10: /* SDRAM_BEAR */
	536	sdram->bear = val;
	537	break;
	538	case 0x20: /* SDRAM_CFG */
	539	val &= 0xFFE00000;
	540	if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
	541	#ifdef DEBUG_SDRAM
	542	printf("%s: enable SDRAM controller\n", __func__);
	543	#endif
	544	/* validate all RAM mappings */
	545	sdram_map_bcr(sdram);
	546	sdram->status &= ~0x80000000;
	547	} else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
	548	#ifdef DEBUG_SDRAM
	549	printf("%s: disable SDRAM controller\n", __func__);
	550	#endif
	551	/* invalidate all RAM mappings */
	552	sdram_unmap_bcr(sdram);
	553	sdram->status \|= 0x80000000;
	554	}
	555	if (!(sdram->cfg & 0x40000000) && (val & 0x40000000))
	556	sdram->status \|= 0x40000000;
	557	else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000))
	558	sdram->status &= ~0x40000000;
	559	sdram->cfg = val;
	560	break;
	561	case 0x24: /* SDRAM_STATUS */
	562	/* Read-only register */
	563	break;
	564	case 0x30: /* SDRAM_RTR */
	565	sdram->rtr = val & 0x3FF80000;
	566	break;
	567	case 0x34: /* SDRAM_PMIT */
	568	sdram->pmit = (val & 0xF8000000) \| 0x07C00000;
	569	break;
	570	case 0x40: /* SDRAM_B0CR */
	571	sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000);
	572	break;
	573	case 0x44: /* SDRAM_B1CR */
	574	sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000);
	575	break;
	576	case 0x48: /* SDRAM_B2CR */
	577	sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000);
	578	break;
	579	case 0x4C: /* SDRAM_B3CR */
	580	sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000);
	581	break;
	582	case 0x80: /* SDRAM_TR */
	583	sdram->tr = val & 0x018FC01F;
	584	break;
585	case 0x94: /* SDRAM_ECCCFG */
586	sdram->ecccfg = val & 0x00F00000;
587	break;
588	case 0x98: /* SDRAM_ECCESR */
589	val &= 0xFFF0F000;
590	if (sdram->eccesr == 0 && val != 0)
591	qemu_irq_raise(sdram->irq);
592	else if (sdram->eccesr != 0 && val == 0)
593	qemu_irq_lower(sdram->irq);
594	sdram->eccesr = val;
595	break;
596	default: /* Error */
597	break;
598	}
599	break;
600	}
601	}
602
603	static void sdram_reset (void *opaque)
604	{
c227f099	605	ppc4xx_sdram_t *sdram;
61b24405 AJ	606
	607	sdram = opaque;
	608	sdram->addr = 0x00000000;
	609	sdram->bear = 0x00000000;
	610	sdram->besr0 = 0x00000000; /* No error */
	611	sdram->besr1 = 0x00000000; /* No error */
	612	sdram->cfg = 0x00000000;
	613	sdram->ecccfg = 0x00000000; /* No ECC */
	614	sdram->eccesr = 0x00000000; /* No error */
	615	sdram->pmit = 0x07C00000;
	616	sdram->rtr = 0x05F00000;
	617	sdram->tr = 0x00854009;
	618	/* We pre-initialize RAM banks */
	619	sdram->status = 0x00000000;
	620	sdram->cfg = 0x00800000;
61b24405 AJ	621	}
61b24405 AJ	622
80e8bd2b	623	void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
c227f099 AL	624	target_phys_addr_t *ram_bases,
c227f099 AL	625	target_phys_addr_t *ram_sizes,
61b24405 AJ	626	int do_init)
61b24405 AJ	627	{
c227f099	628	ppc4xx_sdram_t *sdram;
61b24405	629
c227f099	630	sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
487414f1 AL	631	sdram->irq = irq;
487414f1 AL	632	sdram->nbanks = nbanks;
c227f099	633	memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
487414f1	634	memcpy(sdram->ram_bases, ram_bases,
c227f099 AL	635	nbanks * sizeof(target_phys_addr_t));
c227f099 AL	636	memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
487414f1	637	memcpy(sdram->ram_sizes, ram_sizes,
c227f099	638	nbanks * sizeof(target_phys_addr_t));
a08d4367	639	qemu_register_reset(&sdram_reset, sdram);
487414f1 AL	640	ppc_dcr_register(env, SDRAM0_CFGADDR,
	641	sdram, &dcr_read_sdram, &dcr_write_sdram);
	642	ppc_dcr_register(env, SDRAM0_CFGDATA,
	643	sdram, &dcr_read_sdram, &dcr_write_sdram);
	644	if (do_init)
	645	sdram_map_bcr(sdram);
61b24405	646	}
b7da58fd AJ	647
	648	/* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory.
	649	*
	650	* sdram_bank_sizes[] must be 0-terminated.
	651	*
	652	* The 4xx SDRAM controller supports a small number of banks, and each bank
	653	* must be one of a small set of sizes. The number of banks and the supported
	654	* sizes varies by SoC. */
c227f099 AL	655	ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
	656	target_phys_addr_t ram_bases[],
	657	target_phys_addr_t ram_sizes[],
b7da58fd AJ	658	const unsigned int sdram_bank_sizes[])
b7da58fd AJ	659	{
c227f099	660	ram_addr_t size_left = ram_size;
b7da58fd AJ	661	int i;
	662	int j;
	663
	664	for (i = 0; i < nr_banks; i++) {
	665	for (j = 0; sdram_bank_sizes[j] != 0; j++) {
	666	unsigned int bank_size = sdram_bank_sizes[j];
	667
5c130f65	668	if (bank_size <= size_left) {
1724f049 AW	669	char name[32];
	670	snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
	671	ram_bases[i] = qemu_ram_alloc(NULL, name, bank_size);
b7da58fd	672	ram_sizes[i] = bank_size;
5c130f65	673	size_left -= bank_size;
b7da58fd AJ	674	break;
	675	}
	676	}
	677
5c130f65	678	if (!size_left) {
b7da58fd AJ	679	/* No need to use the remaining banks. */
	680	break;
	681	}
	682	}
	683
5c130f65	684	ram_size -= size_left;
d23ab920	685	if (size_left)
b7da58fd	686	printf("Truncating memory to %d MiB to fit SDRAM controller limits.\n",
5c130f65	687	(int)(ram_size >> 20));
b7da58fd	688
5c130f65	689	return ram_size;
b7da58fd	690	}