[qemu.git] / hw / axis_dev88.c

/*
 * QEMU model for the AXIS devboard 88.
 *
 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sysbus.h"
#include "net.h"
#include "flash.h"
#include "boards.h"
#include "etraxfs.h"
#include "loader.h"
#include "elf.h"
#include "cris-boot.h"

#define D(x)
#define DNAND(x)

struct nand_state_t
{
    NANDFlashState *nand;
    unsigned int rdy:1;
    unsigned int ale:1;
    unsigned int cle:1;
    unsigned int ce:1;
};

static struct nand_state_t nand_state;
static uint32_t nand_readl (void *opaque, target_phys_addr_t addr)
{
    struct nand_state_t *s = opaque;
    uint32_t r;
    int rdy;

    r = nand_getio(s->nand);
    nand_getpins(s->nand, &rdy);
    s->rdy = rdy;

    DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
    return r;
}

static void
nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
    struct nand_state_t *s = opaque;
    int rdy;

    DNAND(printf("%s addr=%x v=%x\n", __func__, addr, value));
    nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
    nand_setio(s->nand, value);
    nand_getpins(s->nand, &rdy);
    s->rdy = rdy;
}

static CPUReadMemoryFunc * const nand_read[] = {
    &nand_readl,
    &nand_readl,
    &nand_readl,
};

static CPUWriteMemoryFunc * const nand_write[] = {
    &nand_writel,
    &nand_writel,
    &nand_writel,
};


struct tempsensor_t
{
    unsigned int shiftreg;
    unsigned int count;
    enum {
        ST_OUT, ST_IN, ST_Z
    } state;

    uint16_t regs[3];
};

static void tempsensor_clkedge(struct tempsensor_t *s,
                               unsigned int clk, unsigned int data_in)
{
    D(printf("%s clk=%d state=%d sr=%x\n", __func__,
             clk, s->state, s->shiftreg));
    if (s->count == 0) {
        s->count = 16;
        s->state = ST_OUT;
    }
    switch (s->state) {
        case ST_OUT:
            /* Output reg is clocked at negedge.  */
            if (!clk) {
                s->count--;
                s->shiftreg <<= 1;
                if (s->count == 0) {
                    s->shiftreg = 0;
                    s->state = ST_IN;
                    s->count = 16;
                }
            }
            break;
        case ST_Z:
            if (clk) {
                s->count--;
                if (s->count == 0) {
                    s->shiftreg = 0;
                    s->state = ST_OUT;
                    s->count = 16;
                }
            }
            break;
        case ST_IN:
            /* Indata is sampled at posedge.  */
            if (clk) {
                s->count--;
                s->shiftreg <<= 1;
                s->shiftreg |= data_in & 1;
                if (s->count == 0) {
                    D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
                    s->regs[0] = s->shiftreg;
                    s->state = ST_OUT;
                    s->count = 16;

                    if ((s->regs[0] & 0xff) == 0) {
                        /* 25 degrees celcius.  */
                        s->shiftreg = 0x0b9f;
                    } else if ((s->regs[0] & 0xff) == 0xff) {
                        /* Sensor ID, 0x8100 LM70.  */
                        s->shiftreg = 0x8100;
                    } else
                        printf("Invalid tempsens state %x\n", s->regs[0]);
                }
            }
            break;
    }
}


#define RW_PA_DOUT    0x00
#define R_PA_DIN      0x01
#define RW_PA_OE      0x02
#define RW_PD_DOUT    0x10
#define R_PD_DIN      0x11
#define RW_PD_OE      0x12

static struct gpio_state_t
{
    struct nand_state_t *nand;
    struct tempsensor_t tempsensor;
    uint32_t regs[0x5c / 4];
} gpio_state;

static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr)
{
    struct gpio_state_t *s = opaque;
    uint32_t r = 0;

    addr >>= 2;
    switch (addr)
    {
        case R_PA_DIN:
            r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];

            /* Encode pins from the nand.  */
            r |= s->nand->rdy << 7;
            break;
        case R_PD_DIN:
            r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];

            /* Encode temp sensor pins.  */
            r |= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
            break;

        default:
            r = s->regs[addr];
            break;
    }
    return r;
    D(printf("%s %x=%x\n", __func__, addr, r));
}

static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
    struct gpio_state_t *s = opaque;
    D(printf("%s %x=%x\n", __func__, addr, value));

    addr >>= 2;
    switch (addr)
    {
        case RW_PA_DOUT:
            /* Decode nand pins.  */
            s->nand->ale = !!(value & (1 << 6));
            s->nand->cle = !!(value & (1 << 5));
            s->nand->ce  = !!(value & (1 << 4));

            s->regs[addr] = value;
            break;

        case RW_PD_DOUT:
            /* Temp sensor clk.  */
            if ((s->regs[addr] ^ value) & 2)
                tempsensor_clkedge(&s->tempsensor, !!(value & 2),
                                   !!(value & 16));
            s->regs[addr] = value;
            break;

        default:
            s->regs[addr] = value;
            break;
    }
}

static CPUReadMemoryFunc * const gpio_read[] = {
    NULL, NULL,
    &gpio_readl,
};

static CPUWriteMemoryFunc * const gpio_write[] = {
    NULL, NULL,
    &gpio_writel,
};

#define INTMEM_SIZE (128 * 1024)

static struct cris_load_info li;

static
void axisdev88_init (ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    CPUState *env;
    DeviceState *dev;
    SysBusDevice *s;
    qemu_irq irq[30], nmi[2], *cpu_irq;
    void *etraxfs_dmac;
    struct etraxfs_dma_client *eth[2] = {NULL, NULL};
    int i;
    int nand_regs;
    int gpio_regs;
    ram_addr_t phys_ram;
    ram_addr_t phys_intmem;

    /* init CPUs */
    if (cpu_model == NULL) {
        cpu_model = "crisv32";
    }
    env = cpu_init(cpu_model);

    /* allocate RAM */
    phys_ram = qemu_ram_alloc(NULL, "axisdev88.ram", ram_size);
    cpu_register_physical_memory(0x40000000, ram_size, phys_ram | IO_MEM_RAM);

    /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the 
       internal memory.  */
    phys_intmem = qemu_ram_alloc(NULL, "axisdev88.chipram", INTMEM_SIZE);
    cpu_register_physical_memory(0x38000000, INTMEM_SIZE,
                                 phys_intmem | IO_MEM_RAM);


      /* Attach a NAND flash to CS1.  */
    nand_state.nand = nand_init(NAND_MFR_STMICRO, 0x39);
    nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state,
                                       DEVICE_NATIVE_ENDIAN);
    cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs);

    gpio_state.nand = &nand_state;
    gpio_regs = cpu_register_io_memory(gpio_read, gpio_write, &gpio_state,
                                       DEVICE_NATIVE_ENDIAN);
    cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs);


    cpu_irq = cris_pic_init_cpu(env);
    dev = qdev_create(NULL, "etraxfs,pic");
    /* FIXME: Is there a proper way to signal vectors to the CPU core?  */
    qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    sysbus_mmio_map(s, 0, 0x3001c000);
    sysbus_connect_irq(s, 0, cpu_irq[0]);
    sysbus_connect_irq(s, 1, cpu_irq[1]);
    for (i = 0; i < 30; i++) {
        irq[i] = qdev_get_gpio_in(dev, i);
    }
    nmi[0] = qdev_get_gpio_in(dev, 30);
    nmi[1] = qdev_get_gpio_in(dev, 31);

    etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
    for (i = 0; i < 10; i++) {
        /* On ETRAX, odd numbered channels are inputs.  */
        etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
    }

    /* Add the two ethernet blocks.  */
    eth[0] = etraxfs_eth_init(&nd_table[0], 0x30034000, 1);
    if (nb_nics > 1)
        eth[1] = etraxfs_eth_init(&nd_table[1], 0x30036000, 2);

    /* The DMA Connector block is missing, hardwire things for now.  */
    etraxfs_dmac_connect_client(etraxfs_dmac, 0, eth[0]);
    etraxfs_dmac_connect_client(etraxfs_dmac, 1, eth[0] + 1);
    if (eth[1]) {
        etraxfs_dmac_connect_client(etraxfs_dmac, 6, eth[1]);
        etraxfs_dmac_connect_client(etraxfs_dmac, 7, eth[1] + 1);
    }

    /* 2 timers.  */
    sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
    sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);

    for (i = 0; i < 4; i++) {
        sysbus_create_simple("etraxfs,serial", 0x30026000 + i * 0x2000,
                             irq[0x14 + i]);
    }

    if (!kernel_filename) {
        fprintf(stderr, "Kernel image must be specified\n");
        exit(1);
    }

    li.image_filename = kernel_filename;
    li.cmdline = kernel_cmdline;
    cris_load_image(env, &li);
}

static QEMUMachine axisdev88_machine = {
    .name = "axis-dev88",
    .desc = "AXIS devboard 88",
    .init = axisdev88_init,
};

static void axisdev88_machine_init(void)
{
    qemu_register_machine(&axisdev88_machine);
}

machine_init(axisdev88_machine_init);
Commit	Line	Data
10c144e2 EI	1	/*
	2	* QEMU model for the AXIS devboard 88.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
4b816985 EI	24
4b816985 EI	25	#include "sysbus.h"
10c144e2 EI	26	#include "net.h"
10c144e2 EI	27	#include "flash.h"
10c144e2	28	#include "boards.h"
10c144e2	29	#include "etraxfs.h"
ca20cf32 BS	30	#include "loader.h"
ca20cf32 BS	31	#include "elf.h"
77d4f95e	32	#include "cris-boot.h"
10c144e2 EI	33
	34	#define D(x)
	35	#define DNAND(x)
	36
	37	struct nand_state_t
	38	{
bc24a225	39	NANDFlashState *nand;
10c144e2 EI	40	unsigned int rdy:1;
	41	unsigned int ale:1;
	42	unsigned int cle:1;
	43	unsigned int ce:1;
	44	};
	45
	46	static struct nand_state_t nand_state;
c227f099	47	static uint32_t nand_readl (void *opaque, target_phys_addr_t addr)
10c144e2 EI	48	{
	49	struct nand_state_t *s = opaque;
	50	uint32_t r;
	51	int rdy;
	52
	53	r = nand_getio(s->nand);
	54	nand_getpins(s->nand, &rdy);
	55	s->rdy = rdy;
	56
	57	DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
	58	return r;
	59	}
	60
	61	static void
c227f099	62	nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
10c144e2 EI	63	{
	64	struct nand_state_t *s = opaque;
	65	int rdy;
	66
	67	DNAND(printf("%s addr=%x v=%x\n", __func__, addr, value));
	68	nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
	69	nand_setio(s->nand, value);
	70	nand_getpins(s->nand, &rdy);
	71	s->rdy = rdy;
	72	}
	73
d60efc6b	74	static CPUReadMemoryFunc * const nand_read[] = {
10c144e2 EI	75	&nand_readl,
	76	&nand_readl,
	77	&nand_readl,
	78	};
	79
d60efc6b	80	static CPUWriteMemoryFunc * const nand_write[] = {
10c144e2 EI	81	&nand_writel,
	82	&nand_writel,
	83	&nand_writel,
	84	};
	85
4a1e6bea EI	86
	87	struct tempsensor_t
	88	{
	89	unsigned int shiftreg;
	90	unsigned int count;
	91	enum {
	92	ST_OUT, ST_IN, ST_Z
	93	} state;
	94
	95	uint16_t regs[3];
	96	};
	97
	98	static void tempsensor_clkedge(struct tempsensor_t *s,
	99	unsigned int clk, unsigned int data_in)
	100	{
	101	D(printf("%s clk=%d state=%d sr=%x\n", __func__,
	102	clk, s->state, s->shiftreg));
	103	if (s->count == 0) {
	104	s->count = 16;
	105	s->state = ST_OUT;
	106	}
	107	switch (s->state) {
	108	case ST_OUT:
	109	/* Output reg is clocked at negedge. */
	110	if (!clk) {
	111	s->count--;
	112	s->shiftreg <<= 1;
	113	if (s->count == 0) {
	114	s->shiftreg = 0;
	115	s->state = ST_IN;
	116	s->count = 16;
	117	}
	118	}
	119	break;
	120	case ST_Z:
	121	if (clk) {
	122	s->count--;
	123	if (s->count == 0) {
	124	s->shiftreg = 0;
	125	s->state = ST_OUT;
	126	s->count = 16;
	127	}
	128	}
	129	break;
	130	case ST_IN:
	131	/* Indata is sampled at posedge. */
	132	if (clk) {
	133	s->count--;
	134	s->shiftreg <<= 1;
	135	s->shiftreg \|= data_in & 1;
	136	if (s->count == 0) {
	137	D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
	138	s->regs[0] = s->shiftreg;
	139	s->state = ST_OUT;
	140	s->count = 16;
	141
	142	if ((s->regs[0] & 0xff) == 0) {
	143	/* 25 degrees celcius. */
	144	s->shiftreg = 0x0b9f;
	145	} else if ((s->regs[0] & 0xff) == 0xff) {
	146	/* Sensor ID, 0x8100 LM70. */
	147	s->shiftreg = 0x8100;
	148	} else
	149	printf("Invalid tempsens state %x\n", s->regs[0]);
150	}
151	}
152	break;
153	}
154	}
155
156
157	#define RW_PA_DOUT 0x00
158	#define R_PA_DIN 0x01
159	#define RW_PA_OE 0x02
160	#define RW_PD_DOUT 0x10
161	#define R_PD_DIN 0x11
162	#define RW_PD_OE 0x12
163
164	static struct gpio_state_t
10c144e2 EI	165	{
10c144e2 EI	166	struct nand_state_t *nand;
4a1e6bea	167	struct tempsensor_t tempsensor;
10c144e2 EI	168	uint32_t regs[0x5c / 4];
	169	} gpio_state;
	170
c227f099	171	static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr)
10c144e2 EI	172	{
	173	struct gpio_state_t *s = opaque;
	174	uint32_t r = 0;
	175
	176	addr >>= 2;
	177	switch (addr)
	178	{
	179	case R_PA_DIN:
	180	r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];
	181
	182	/* Encode pins from the nand. */
	183	r \|= s->nand->rdy << 7;
	184	break;
4a1e6bea EI	185	case R_PD_DIN:
	186	r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];
	187
	188	/* Encode temp sensor pins. */
	189	r \|= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
	190	break;
	191
10c144e2 EI	192	default:
	193	r = s->regs[addr];
	194	break;
	195	}
	196	return r;
	197	D(printf("%s %x=%x\n", __func__, addr, r));
	198	}
	199
c227f099	200	static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
10c144e2 EI	201	{
	202	struct gpio_state_t *s = opaque;
	203	D(printf("%s %x=%x\n", __func__, addr, value));
	204
	205	addr >>= 2;
	206	switch (addr)
	207	{
	208	case RW_PA_DOUT:
	209	/* Decode nand pins. */
	210	s->nand->ale = !!(value & (1 << 6));
	211	s->nand->cle = !!(value & (1 << 5));
	212	s->nand->ce = !!(value & (1 << 4));
	213
	214	s->regs[addr] = value;
	215	break;
4a1e6bea EI	216
	217	case RW_PD_DOUT:
	218	/* Temp sensor clk. */
	219	if ((s->regs[addr] ^ value) & 2)
	220	tempsensor_clkedge(&s->tempsensor, !!(value & 2),
	221	!!(value & 16));
	222	s->regs[addr] = value;
	223	break;
	224
10c144e2 EI	225	default:
	226	s->regs[addr] = value;
	227	break;
	228	}
	229	}
	230
d60efc6b	231	static CPUReadMemoryFunc * const gpio_read[] = {
10c144e2 EI	232	NULL, NULL,
	233	&gpio_readl,
	234	};
	235
d60efc6b	236	static CPUWriteMemoryFunc * const gpio_write[] = {
10c144e2 EI	237	NULL, NULL,
	238	&gpio_writel,
	239	};
	240
	241	#define INTMEM_SIZE (128 * 1024)
	242
77d4f95e	243	static struct cris_load_info li;
409dbce5	244
10c144e2	245	static
c227f099	246	void axisdev88_init (ram_addr_t ram_size,
ef998233	247	const char *boot_device,
10c144e2 EI	248	const char kernel_filename, const char kernel_cmdline,
	249	const char initrd_filename, const char cpu_model)
	250	{
	251	CPUState *env;
fd6dc90b EI	252	DeviceState *dev;
	253	SysBusDevice *s;
	254	qemu_irq irq[30], nmi[2], *cpu_irq;
10c144e2 EI	255	void *etraxfs_dmac;
10c144e2 EI	256	struct etraxfs_dma_client *eth[2] = {NULL, NULL};
10c144e2 EI	257	int i;
	258	int nand_regs;
	259	int gpio_regs;
c227f099 AL	260	ram_addr_t phys_ram;
c227f099 AL	261	ram_addr_t phys_intmem;
10c144e2 EI	262
	263	/* init CPUs */
	264	if (cpu_model == NULL) {
	265	cpu_model = "crisv32";
	266	}
	267	env = cpu_init(cpu_model);
10c144e2 EI	268
10c144e2 EI	269	/* allocate RAM */
1724f049	270	phys_ram = qemu_ram_alloc(NULL, "axisdev88.ram", ram_size);
10c144e2 EI	271	cpu_register_physical_memory(0x40000000, ram_size, phys_ram \| IO_MEM_RAM);
	272
	273	/* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
	274	internal memory. */
1724f049	275	phys_intmem = qemu_ram_alloc(NULL, "axisdev88.chipram", INTMEM_SIZE);
10c144e2 EI	276	cpu_register_physical_memory(0x38000000, INTMEM_SIZE,
	277	phys_intmem \| IO_MEM_RAM);
	278
	279
	280	/* Attach a NAND flash to CS1. */
4a1e6bea	281	nand_state.nand = nand_init(NAND_MFR_STMICRO, 0x39);
2507c12a AG	282	nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state,
2507c12a AG	283	DEVICE_NATIVE_ENDIAN);
10c144e2 EI	284	cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs);
	285
	286	gpio_state.nand = &nand_state;
2507c12a AG	287	gpio_regs = cpu_register_io_memory(gpio_read, gpio_write, &gpio_state,
2507c12a AG	288	DEVICE_NATIVE_ENDIAN);
4a1e6bea	289	cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs);
10c144e2 EI	290
10c144e2 EI	291
fd6dc90b EI	292	cpu_irq = cris_pic_init_cpu(env);
	293	dev = qdev_create(NULL, "etraxfs,pic");
	294	/* FIXME: Is there a proper way to signal vectors to the CPU core? */
ee6847d1	295	qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
e23a1b33	296	qdev_init_nofail(dev);
fd6dc90b EI	297	s = sysbus_from_qdev(dev);
	298	sysbus_mmio_map(s, 0, 0x3001c000);
	299	sysbus_connect_irq(s, 0, cpu_irq[0]);
	300	sysbus_connect_irq(s, 1, cpu_irq[1]);
	301	for (i = 0; i < 30; i++) {
067a3ddc	302	irq[i] = qdev_get_gpio_in(dev, i);
fd6dc90b	303	}
067a3ddc PB	304	nmi[0] = qdev_get_gpio_in(dev, 30);
067a3ddc PB	305	nmi[1] = qdev_get_gpio_in(dev, 31);
73cfd29f	306
ba494313	307	etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
10c144e2 EI	308	for (i = 0; i < 10; i++) {
10c144e2 EI	309	/* On ETRAX, odd numbered channels are inputs. */
73cfd29f	310	etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
10c144e2 EI	311	}
	312
	313	/* Add the two ethernet blocks. */
ba494313	314	eth[0] = etraxfs_eth_init(&nd_table[0], 0x30034000, 1);
0ae18cee	315	if (nb_nics > 1)
ba494313	316	eth[1] = etraxfs_eth_init(&nd_table[1], 0x30036000, 2);
10c144e2 EI	317
	318	/* The DMA Connector block is missing, hardwire things for now. */
	319	etraxfs_dmac_connect_client(etraxfs_dmac, 0, eth[0]);
	320	etraxfs_dmac_connect_client(etraxfs_dmac, 1, eth[0] + 1);
	321	if (eth[1]) {
	322	etraxfs_dmac_connect_client(etraxfs_dmac, 6, eth[1]);
	323	etraxfs_dmac_connect_client(etraxfs_dmac, 7, eth[1] + 1);
	324	}
	325
	326	/* 2 timers. */
3b1fd90e EI	327	sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
3b1fd90e EI	328	sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);
10c144e2 EI	329
10c144e2 EI	330	for (i = 0; i < 4; i++) {
4b816985	331	sysbus_create_simple("etraxfs,serial", 0x30026000 + i * 0x2000,
3b1fd90e	332	irq[0x14 + i]);
10c144e2 EI	333	}
10c144e2 EI	334
77d4f95e EI	335	if (!kernel_filename) {
	336	fprintf(stderr, "Kernel image must be specified\n");
	337	exit(1);
10c144e2	338	}
77d4f95e EI	339
	340	li.image_filename = kernel_filename;
	341	li.cmdline = kernel_cmdline;
	342	cris_load_image(env, &li);
10c144e2 EI	343	}
10c144e2 EI	344
f80f9ec9	345	static QEMUMachine axisdev88_machine = {
10c144e2 EI	346	.name = "axis-dev88",
	347	.desc = "AXIS devboard 88",
	348	.init = axisdev88_init,
10c144e2	349	};
f80f9ec9 AL	350
	351	static void axisdev88_machine_init(void)
	352	{
	353	qemu_register_machine(&axisdev88_machine);
	354	}
	355
	356	machine_init(axisdev88_machine_init);