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[qemu.git] / hw / scsi / mptsas.c
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e351b826
PB		 1/*
2 * QEMU LSI SAS1068 Host Bus Adapter emulation
3 * Based on the QEMU Megaraid emulator
4 *
5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs
6 * Copyright (c) 2012 Verizon, Inc.
7 * Copyright (c) 2016 Red Hat, Inc.
8 *
9 * Authors: Don Slutz, Paolo Bonzini
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25#include "qemu/osdep.h"
e351b826
PB		 26#include "hw/pci/pci.h"
27#include "sysemu/dma.h"
e351b826
PB		 28#include "hw/pci/msi.h"
29#include "qemu/iov.h"
db725815 30#include "qemu/main-loop.h"
0b8fa32f 31#include "qemu/module.h"
e351b826 32#include "hw/scsi/scsi.h"
08e2c9f1 33#include "scsi/constants.h"
e351b826 34#include "trace.h"
1108b2f8 35#include "qapi/error.h"
e351b826 36#include "mptsas.h"
ca77ee28 37#include "migration/qemu-file-types.h"
d6454270 38#include "migration/vmstate.h"
e351b826
PB		 39#include "mpi.h"
40
41#define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
42#define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
43
44#define TYPE_MPTSAS1068 "mptsas1068"
45
46#define MPT_SAS(obj) \
47 OBJECT_CHECK(MPTSASState, (obj), TYPE_MPTSAS1068)
48
49#define MPTSAS1068_PRODUCT_ID \
50 (MPI_FW_HEADER_PID_FAMILY_1068_SAS | \
51 MPI_FW_HEADER_PID_PROD_INITIATOR_SCSI | \
52 MPI_FW_HEADER_PID_TYPE_SAS)
53
54struct MPTSASRequest {
55 MPIMsgSCSIIORequest scsi_io;
56 SCSIRequest *sreq;
57 QEMUSGList qsg;
58 MPTSASState *dev;
59
60 QTAILQ_ENTRY(MPTSASRequest) next;
61};
62
63static void mptsas_update_interrupt(MPTSASState *s)
64{
65 PCIDevice *pci = (PCIDevice *) s;
66 uint32_t state = s->intr_status & ~(s->intr_mask | MPI_HIS_IOP_DOORBELL_STATUS);
67
2e2aa316 68 if (msi_enabled(pci)) {
e351b826
PB		 69 if (state) {
70 trace_mptsas_irq_msi(s);
71 msi_notify(pci, 0);
72 }
73 }
74
75 trace_mptsas_irq_intx(s, !!state);
76 pci_set_irq(pci, !!state);
77}
78
79static void mptsas_set_fault(MPTSASState *s, uint32_t code)
80{
81 if ((s->state & MPI_IOC_STATE_FAULT) == 0) {
82 s->state = MPI_IOC_STATE_FAULT | code;
83 }
84}
85
86#define MPTSAS_FIFO_INVALID(s, name) \
87 ((s)->name##_head > ARRAY_SIZE((s)->name) || \
88 (s)->name##_tail > ARRAY_SIZE((s)->name))
89
90#define MPTSAS_FIFO_EMPTY(s, name) \
91 ((s)->name##_head == (s)->name##_tail)
92
93#define MPTSAS_FIFO_FULL(s, name) \
94 ((s)->name##_head == ((s)->name##_tail + 1) % ARRAY_SIZE((s)->name))
95
96#define MPTSAS_FIFO_GET(s, name) ({ \
97 uint32_t _val = (s)->name[(s)->name##_head++]; \
98 (s)->name##_head %= ARRAY_SIZE((s)->name); \
99 _val; \
100})
101
102#define MPTSAS_FIFO_PUT(s, name, val) do { \
103 (s)->name[(s)->name##_tail++] = (val); \
104 (s)->name##_tail %= ARRAY_SIZE((s)->name); \
105} while(0)
106
107static void mptsas_post_reply(MPTSASState *s, MPIDefaultReply *reply)
108{
109 PCIDevice *pci = (PCIDevice *) s;
110 uint32_t addr_lo;
111
112 if (MPTSAS_FIFO_EMPTY(s, reply_free) || MPTSAS_FIFO_FULL(s, reply_post)) {
113 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES);
114 return;
115 }
116
117 addr_lo = MPTSAS_FIFO_GET(s, reply_free);
118
119 pci_dma_write(pci, addr_lo | s->host_mfa_high_addr, reply,
120 MIN(s->reply_frame_size, 4 * reply->MsgLength));
121
122 MPTSAS_FIFO_PUT(s, reply_post, MPI_ADDRESS_REPLY_A_BIT | (addr_lo >> 1));
123
124 s->intr_status |= MPI_HIS_REPLY_MESSAGE_INTERRUPT;
125 if (s->doorbell_state == DOORBELL_WRITE) {
126 s->doorbell_state = DOORBELL_NONE;
127 s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT;
128 }
129 mptsas_update_interrupt(s);
130}
131
132void mptsas_reply(MPTSASState *s, MPIDefaultReply *reply)
133{
134 if (s->doorbell_state == DOORBELL_WRITE) {
135 /* The reply is sent out in 16 bit chunks, while the size
136 * in the reply is in 32 bit units.
137 */
138 s->doorbell_state = DOORBELL_READ;
139 s->doorbell_reply_idx = 0;
140 s->doorbell_reply_size = reply->MsgLength * 2;
141 memcpy(s->doorbell_reply, reply, s->doorbell_reply_size * 2);
142 s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT;
143 mptsas_update_interrupt(s);
144 } else {
145 mptsas_post_reply(s, reply);
146 }
147}
148
149static void mptsas_turbo_reply(MPTSASState *s, uint32_t msgctx)
150{
151 if (MPTSAS_FIFO_FULL(s, reply_post)) {
152 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES);
153 return;
154 }
155
156 /* The reply is just the message context ID (bit 31 = clear). */
157 MPTSAS_FIFO_PUT(s, reply_post, msgctx);
158
159 s->intr_status |= MPI_HIS_REPLY_MESSAGE_INTERRUPT;
160 mptsas_update_interrupt(s);
161}
162
163#define MPTSAS_MAX_REQUEST_SIZE 52
164
165static const int mpi_request_sizes[] = {
166 [MPI_FUNCTION_SCSI_IO_REQUEST] = sizeof(MPIMsgSCSIIORequest),
167 [MPI_FUNCTION_SCSI_TASK_MGMT] = sizeof(MPIMsgSCSITaskMgmt),
168 [MPI_FUNCTION_IOC_INIT] = sizeof(MPIMsgIOCInit),
169 [MPI_FUNCTION_IOC_FACTS] = sizeof(MPIMsgIOCFacts),
170 [MPI_FUNCTION_CONFIG] = sizeof(MPIMsgConfig),
171 [MPI_FUNCTION_PORT_FACTS] = sizeof(MPIMsgPortFacts),
172 [MPI_FUNCTION_PORT_ENABLE] = sizeof(MPIMsgPortEnable),
173 [MPI_FUNCTION_EVENT_NOTIFICATION] = sizeof(MPIMsgEventNotify),
174};
175
176static dma_addr_t mptsas_ld_sg_base(MPTSASState *s, uint32_t flags_and_length,
177 dma_addr_t *sgaddr)
178{
179 PCIDevice *pci = (PCIDevice *) s;
180 dma_addr_t addr;
181
182 if (flags_and_length & MPI_SGE_FLAGS_64_BIT_ADDRESSING) {
183 addr = ldq_le_pci_dma(pci, *sgaddr + 4);
184 *sgaddr += 12;
185 } else {
186 addr = ldl_le_pci_dma(pci, *sgaddr + 4);
187 *sgaddr += 8;
188 }
189 return addr;
190}
191
192static int mptsas_build_sgl(MPTSASState *s, MPTSASRequest *req, hwaddr addr)
193{
194 PCIDevice *pci = (PCIDevice *) s;
195 hwaddr next_chain_addr;
196 uint32_t left;
197 hwaddr sgaddr;
198 uint32_t chain_offset;
199
200 chain_offset = req->scsi_io.ChainOffset;
201 next_chain_addr = addr + chain_offset * sizeof(uint32_t);
202 sgaddr = addr + sizeof(MPIMsgSCSIIORequest);
203 pci_dma_sglist_init(&req->qsg, pci, 4);
204 left = req->scsi_io.DataLength;
205
206 for(;;) {
207 dma_addr_t addr, len;
208 uint32_t flags_and_length;
209
210 flags_and_length = ldl_le_pci_dma(pci, sgaddr);
211 len = flags_and_length & MPI_SGE_LENGTH_MASK;
212 if ((flags_and_length & MPI_SGE_FLAGS_ELEMENT_TYPE_MASK)
213 != MPI_SGE_FLAGS_SIMPLE_ELEMENT ||
214 (!len &&
215 !(flags_and_length & MPI_SGE_FLAGS_END_OF_LIST) &&
216 !(flags_and_length & MPI_SGE_FLAGS_END_OF_BUFFER))) {
217 return MPI_IOCSTATUS_INVALID_SGL;
218 }
219
220 len = MIN(len, left);
221 if (!len) {
222 /* We reached the desired transfer length, ignore extra
223 * elements of the s/g list.
224 */
225 break;
226 }
227
228 addr = mptsas_ld_sg_base(s, flags_and_length, &sgaddr);
229 qemu_sglist_add(&req->qsg, addr, len);
230 left -= len;
231
232 if (flags_and_length & MPI_SGE_FLAGS_END_OF_LIST) {
233 break;
234 }
235
236 if (flags_and_length & MPI_SGE_FLAGS_LAST_ELEMENT) {
237 if (!chain_offset) {
238 break;
239 }
240
241 flags_and_length = ldl_le_pci_dma(pci, next_chain_addr);
242 if ((flags_and_length & MPI_SGE_FLAGS_ELEMENT_TYPE_MASK)
243 != MPI_SGE_FLAGS_CHAIN_ELEMENT) {
244 return MPI_IOCSTATUS_INVALID_SGL;
245 }
246
247 sgaddr = mptsas_ld_sg_base(s, flags_and_length, &next_chain_addr);
248 chain_offset =
249 (flags_and_length & MPI_SGE_CHAIN_OFFSET_MASK) >> MPI_SGE_CHAIN_OFFSET_SHIFT;
250 next_chain_addr = sgaddr + chain_offset * sizeof(uint32_t);
251 }
252 }
253 return 0;
254}
255
256static void mptsas_free_request(MPTSASRequest *req)
257{
258 MPTSASState *s = req->dev;
259
260 if (req->sreq != NULL) {
261 req->sreq->hba_private = NULL;
262 scsi_req_unref(req->sreq);
263 req->sreq = NULL;
264 QTAILQ_REMOVE(&s->pending, req, next);
265 }
266 qemu_sglist_destroy(&req->qsg);
267 g_free(req);
268}
269
270static int mptsas_scsi_device_find(MPTSASState *s, int bus, int target,
271 uint8_t *lun, SCSIDevice **sdev)
272{
273 if (bus != 0) {
274 return MPI_IOCSTATUS_SCSI_INVALID_BUS;
275 }
276
277 if (target >= s->max_devices) {
278 return MPI_IOCSTATUS_SCSI_INVALID_TARGETID;
279 }
280
281 *sdev = scsi_device_find(&s->bus, bus, target, lun[1]);
282 if (!*sdev) {
283 return MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE;
284 }
285
286 return 0;
287}
288
289static int mptsas_process_scsi_io_request(MPTSASState *s,
290 MPIMsgSCSIIORequest *scsi_io,
291 hwaddr addr)
292{
293 MPTSASRequest *req;
294 MPIMsgSCSIIOReply reply;
295 SCSIDevice *sdev;
296 int status;
297
298 mptsas_fix_scsi_io_endianness(scsi_io);
299
300 trace_mptsas_process_scsi_io_request(s, scsi_io->Bus, scsi_io->TargetID,
301 scsi_io->LUN[1], scsi_io->DataLength);
302
303 status = mptsas_scsi_device_find(s, scsi_io->Bus, scsi_io->TargetID,
304 scsi_io->LUN, &sdev);
305 if (status) {
306 goto bad;
307 }
308
670e56d3 309 req = g_new0(MPTSASRequest, 1);
e351b826
PB		 310 QTAILQ_INSERT_TAIL(&s->pending, req, next);
311 req->scsi_io = *scsi_io;
312 req->dev = s;
313
314 status = mptsas_build_sgl(s, req, addr);
315 if (status) {
316 goto free_bad;
317 }
318
319 if (req->qsg.size < scsi_io->DataLength) {
320 trace_mptsas_sgl_overflow(s, scsi_io->MsgContext, scsi_io->DataLength,
321 req->qsg.size);
322 status = MPI_IOCSTATUS_INVALID_SGL;
323 goto free_bad;
324 }
325
326 req->sreq = scsi_req_new(sdev, scsi_io->MsgContext,
327 scsi_io->LUN[1], scsi_io->CDB, req);
328
329 if (req->sreq->cmd.xfer > scsi_io->DataLength) {
330 goto overrun;
331 }
332 switch (scsi_io->Control & MPI_SCSIIO_CONTROL_DATADIRECTION_MASK) {
333 case MPI_SCSIIO_CONTROL_NODATATRANSFER:
334 if (req->sreq->cmd.mode != SCSI_XFER_NONE) {
335 goto overrun;
336 }
337 break;
338
339 case MPI_SCSIIO_CONTROL_WRITE:
340 if (req->sreq->cmd.mode != SCSI_XFER_TO_DEV) {
341 goto overrun;
342 }
343 break;
344
345 case MPI_SCSIIO_CONTROL_READ:
346 if (req->sreq->cmd.mode != SCSI_XFER_FROM_DEV) {
347 goto overrun;
348 }
349 break;
350 }
351
352 if (scsi_req_enqueue(req->sreq)) {
353 scsi_req_continue(req->sreq);
354 }
355 return 0;
356
357overrun:
358 trace_mptsas_scsi_overflow(s, scsi_io->MsgContext, req->sreq->cmd.xfer,
359 scsi_io->DataLength);
360 status = MPI_IOCSTATUS_SCSI_DATA_OVERRUN;
361free_bad:
362 mptsas_free_request(req);
363bad:
364 memset(&reply, 0, sizeof(reply));
365 reply.TargetID = scsi_io->TargetID;
366 reply.Bus = scsi_io->Bus;
367 reply.MsgLength = sizeof(reply) / 4;
368 reply.Function = scsi_io->Function;
369 reply.CDBLength = scsi_io->CDBLength;
370 reply.SenseBufferLength = scsi_io->SenseBufferLength;
371 reply.MsgContext = scsi_io->MsgContext;
372 reply.SCSIState = MPI_SCSI_STATE_NO_SCSI_STATUS;
373 reply.IOCStatus = status;
374
375 mptsas_fix_scsi_io_reply_endianness(&reply);
376 mptsas_reply(s, (MPIDefaultReply *)&reply);
377
378 return 0;
379}
380
381typedef struct {
382 Notifier notifier;
383 MPTSASState *s;
384 MPIMsgSCSITaskMgmtReply *reply;
385} MPTSASCancelNotifier;
386
387static void mptsas_cancel_notify(Notifier *notifier, void *data)
388{
389 MPTSASCancelNotifier *n = container_of(notifier,
390 MPTSASCancelNotifier,
391 notifier);
392
393 /* Abusing IOCLogInfo to store the expected number of requests... */
394 if (++n->reply->TerminationCount == n->reply->IOCLogInfo) {
395 n->reply->IOCLogInfo = 0;
396 mptsas_fix_scsi_task_mgmt_reply_endianness(n->reply);
397 mptsas_post_reply(n->s, (MPIDefaultReply *)n->reply);
398 g_free(n->reply);
399 }
400 g_free(n);
401}
402
403static void mptsas_process_scsi_task_mgmt(MPTSASState *s, MPIMsgSCSITaskMgmt *req)
404{
405 MPIMsgSCSITaskMgmtReply reply;
406 MPIMsgSCSITaskMgmtReply *reply_async;
407 int status, count;
408 SCSIDevice *sdev;
409 SCSIRequest *r, *next;
410 BusChild *kid;
411
412 mptsas_fix_scsi_task_mgmt_endianness(req);
413
414 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req));
415 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req));
416 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply));
417
418 memset(&reply, 0, sizeof(reply));
419 reply.TargetID = req->TargetID;
420 reply.Bus = req->Bus;
421 reply.MsgLength = sizeof(reply) / 4;
422 reply.Function = req->Function;
423 reply.TaskType = req->TaskType;
424 reply.MsgContext = req->MsgContext;
425
426 switch (req->TaskType) {
427 case MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK:
428 case MPI_SCSITASKMGMT_TASKTYPE_QUERY_TASK:
429 status = mptsas_scsi_device_find(s, req->Bus, req->TargetID,
430 req->LUN, &sdev);
431 if (status) {
432 reply.IOCStatus = status;
433 goto out;
434 }
435 if (sdev->lun != req->LUN[1]) {
436 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN;
437 goto out;
438 }
439
440 QTAILQ_FOREACH_SAFE(r, &sdev->requests, next, next) {
441 MPTSASRequest *cmd_req = r->hba_private;
442 if (cmd_req && cmd_req->scsi_io.MsgContext == req->TaskMsgContext) {
443 break;
444 }
445 }
446 if (r) {
447 /*
448 * Assert that the request has not been completed yet, we
449 * check for it in the loop above.
450 */
451 assert(r->hba_private);
452 if (req->TaskType == MPI_SCSITASKMGMT_TASKTYPE_QUERY_TASK) {
453 /* "If the specified command is present in the task set, then
454 * return a service response set to FUNCTION SUCCEEDED".
455 */
456 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_SUCCEEDED;
457 } else {
458 MPTSASCancelNotifier *notifier;
459
460 reply_async = g_memdup(&reply, sizeof(MPIMsgSCSITaskMgmtReply));
461 reply_async->IOCLogInfo = INT_MAX;
462
463 count = 1;
464 notifier = g_new(MPTSASCancelNotifier, 1);
465 notifier->s = s;
466 notifier->reply = reply_async;
467 notifier->notifier.notify = mptsas_cancel_notify;
468 scsi_req_cancel_async(r, &notifier->notifier);
469 goto reply_maybe_async;
470 }
471 }
472 break;
473
474 case MPI_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
475 case MPI_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET:
476 status = mptsas_scsi_device_find(s, req->Bus, req->TargetID,
477 req->LUN, &sdev);
478 if (status) {
479 reply.IOCStatus = status;
480 goto out;
481 }
482 if (sdev->lun != req->LUN[1]) {
483 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN;
484 goto out;
485 }
486
487 reply_async = g_memdup(&reply, sizeof(MPIMsgSCSITaskMgmtReply));
488 reply_async->IOCLogInfo = INT_MAX;
489
490 count = 0;
491 QTAILQ_FOREACH_SAFE(r, &sdev->requests, next, next) {
492 if (r->hba_private) {
493 MPTSASCancelNotifier *notifier;
494
495 count++;
496 notifier = g_new(MPTSASCancelNotifier, 1);
497 notifier->s = s;
498 notifier->reply = reply_async;
499 notifier->notifier.notify = mptsas_cancel_notify;
500 scsi_req_cancel_async(r, &notifier->notifier);
501 }
502 }
503
504reply_maybe_async:
505 if (reply_async->TerminationCount < count) {
506 reply_async->IOCLogInfo = count;
507 return;
508 }
18557e64 509 g_free(reply_async);
e351b826
PB		 510 reply.TerminationCount = count;
511 break;
512
513 case MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
514 status = mptsas_scsi_device_find(s, req->Bus, req->TargetID,
515 req->LUN, &sdev);
516 if (status) {
517 reply.IOCStatus = status;
518 goto out;
519 }
520 if (sdev->lun != req->LUN[1]) {
521 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN;
522 goto out;
523 }
524 qdev_reset_all(&sdev->qdev);
525 break;
526
527 case MPI_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
528 if (req->Bus != 0) {
529 reply.IOCStatus = MPI_IOCSTATUS_SCSI_INVALID_BUS;
530 goto out;
531 }
532 if (req->TargetID > s->max_devices) {
533 reply.IOCStatus = MPI_IOCSTATUS_SCSI_INVALID_TARGETID;
534 goto out;
535 }
536
537 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
538 sdev = SCSI_DEVICE(kid->child);
539 if (sdev->channel == 0 && sdev->id == req->TargetID) {
540 qdev_reset_all(kid->child);
541 }
542 }
543 break;
544
545 case MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS:
824755ba 546 qbus_reset_all(BUS(&s->bus));
e351b826
PB		 547 break;
548
549 default:
550 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED;
551 break;
552 }
553
554out:
555 mptsas_fix_scsi_task_mgmt_reply_endianness(&reply);
556 mptsas_post_reply(s, (MPIDefaultReply *)&reply);
557}
558
559static void mptsas_process_ioc_init(MPTSASState *s, MPIMsgIOCInit *req)
560{
561 MPIMsgIOCInitReply reply;
562
563 mptsas_fix_ioc_init_endianness(req);
564
565 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req));
566 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req));
567 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply));
568
569 s->who_init = req->WhoInit;
570 s->reply_frame_size = req->ReplyFrameSize;
571 s->max_buses = req->MaxBuses;
572 s->max_devices = req->MaxDevices ? req->MaxDevices : 256;
573 s->host_mfa_high_addr = (hwaddr)req->HostMfaHighAddr << 32;
574 s->sense_buffer_high_addr = (hwaddr)req->SenseBufferHighAddr << 32;
575
576 if (s->state == MPI_IOC_STATE_READY) {
577 s->state = MPI_IOC_STATE_OPERATIONAL;
578 }
579
580 memset(&reply, 0, sizeof(reply));
581 reply.WhoInit = s->who_init;
582 reply.MsgLength = sizeof(reply) / 4;
583 reply.Function = req->Function;
584 reply.MaxDevices = s->max_devices;
585 reply.MaxBuses = s->max_buses;
586 reply.MsgContext = req->MsgContext;
587
588 mptsas_fix_ioc_init_reply_endianness(&reply);
589 mptsas_reply(s, (MPIDefaultReply *)&reply);
590}
591
592static void mptsas_process_ioc_facts(MPTSASState *s,
593 MPIMsgIOCFacts *req)
594{
595 MPIMsgIOCFactsReply reply;
596
597 mptsas_fix_ioc_facts_endianness(req);
598
599 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req));
600 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req));
601 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply));
602
603 memset(&reply, 0, sizeof(reply));
604 reply.MsgVersion = 0x0105;
605 reply.MsgLength = sizeof(reply) / 4;
606 reply.Function = req->Function;
607 reply.MsgContext = req->MsgContext;
608 reply.MaxChainDepth = MPTSAS_MAXIMUM_CHAIN_DEPTH;
609 reply.WhoInit = s->who_init;
610 reply.BlockSize = MPTSAS_MAX_REQUEST_SIZE / sizeof(uint32_t);
611 reply.ReplyQueueDepth = ARRAY_SIZE(s->reply_post) - 1;
612 QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->reply_post) != ARRAY_SIZE(s->reply_free));
613
614 reply.RequestFrameSize = 128;
615 reply.ProductID = MPTSAS1068_PRODUCT_ID;
616 reply.CurrentHostMfaHighAddr = s->host_mfa_high_addr >> 32;
617 reply.GlobalCredits = ARRAY_SIZE(s->request_post) - 1;
618 reply.NumberOfPorts = MPTSAS_NUM_PORTS;
619 reply.CurrentSenseBufferHighAddr = s->sense_buffer_high_addr >> 32;
620 reply.CurReplyFrameSize = s->reply_frame_size;
621 reply.MaxDevices = s->max_devices;
622 reply.MaxBuses = s->max_buses;
623 reply.FWVersionDev = 0;
624 reply.FWVersionUnit = 0x92;
625 reply.FWVersionMinor = 0x32;
626 reply.FWVersionMajor = 0x1;
627
628 mptsas_fix_ioc_facts_reply_endianness(&reply);
629 mptsas_reply(s, (MPIDefaultReply *)&reply);
630}
631
632static void mptsas_process_port_facts(MPTSASState *s,
633 MPIMsgPortFacts *req)
634{
635 MPIMsgPortFactsReply reply;
636
637 mptsas_fix_port_facts_endianness(req);
638
639 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req));
640 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req));
641 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply));
642
643 memset(&reply, 0, sizeof(reply));
644 reply.MsgLength = sizeof(reply) / 4;
645 reply.Function = req->Function;
646 reply.PortNumber = req->PortNumber;
647 reply.MsgContext = req->MsgContext;
648
649 if (req->PortNumber < MPTSAS_NUM_PORTS) {
650 reply.PortType = MPI_PORTFACTS_PORTTYPE_SAS;
651 reply.MaxDevices = MPTSAS_NUM_PORTS;
652 reply.PortSCSIID = MPTSAS_NUM_PORTS;
653 reply.ProtocolFlags = MPI_PORTFACTS_PROTOCOL_LOGBUSADDR | MPI_PORTFACTS_PROTOCOL_INITIATOR;
654 }
655
656 mptsas_fix_port_facts_reply_endianness(&reply);
657 mptsas_reply(s, (MPIDefaultReply *)&reply);
658}
659
660static void mptsas_process_port_enable(MPTSASState *s,
661 MPIMsgPortEnable *req)
662{
663 MPIMsgPortEnableReply reply;
664
665 mptsas_fix_port_enable_endianness(req);
666
667 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req));
668 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req));
669 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply));
670
671 memset(&reply, 0, sizeof(reply));
672 reply.MsgLength = sizeof(reply) / 4;
673 reply.PortNumber = req->PortNumber;
674 reply.Function = req->Function;
675 reply.MsgContext = req->MsgContext;
676
677 mptsas_fix_port_enable_reply_endianness(&reply);
678 mptsas_reply(s, (MPIDefaultReply *)&reply);
679}
680
681static void mptsas_process_event_notification(MPTSASState *s,
682 MPIMsgEventNotify *req)
683{
684 MPIMsgEventNotifyReply reply;
685
686 mptsas_fix_event_notification_endianness(req);
687
688 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req));
689 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req));
690 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply));
691
692 /* Don't even bother storing whether event notification is enabled,
693 * since it is not accessible.
694 */
695
696 memset(&reply, 0, sizeof(reply));
697 reply.EventDataLength = sizeof(reply.Data) / 4;
698 reply.MsgLength = sizeof(reply) / 4;
699 reply.Function = req->Function;
700
701 /* This is set because events are sent through the reply FIFOs. */
702 reply.MsgFlags = MPI_MSGFLAGS_CONTINUATION_REPLY;
703
704 reply.MsgContext = req->MsgContext;
705 reply.Event = MPI_EVENT_EVENT_CHANGE;
706 reply.Data[0] = !!req->Switch;
707
708 mptsas_fix_event_notification_reply_endianness(&reply);
709 mptsas_reply(s, (MPIDefaultReply *)&reply);
710}
711
712static void mptsas_process_message(MPTSASState *s, MPIRequestHeader *req)
713{
714 trace_mptsas_process_message(s, req->Function, req->MsgContext);
715 switch (req->Function) {
716 case MPI_FUNCTION_SCSI_TASK_MGMT:
717 mptsas_process_scsi_task_mgmt(s, (MPIMsgSCSITaskMgmt *)req);
718 break;
719
720 case MPI_FUNCTION_IOC_INIT:
721 mptsas_process_ioc_init(s, (MPIMsgIOCInit *)req);
722 break;
723
724 case MPI_FUNCTION_IOC_FACTS:
725 mptsas_process_ioc_facts(s, (MPIMsgIOCFacts *)req);
726 break;
727
728 case MPI_FUNCTION_PORT_FACTS:
729 mptsas_process_port_facts(s, (MPIMsgPortFacts *)req);
730 break;
731
732 case MPI_FUNCTION_PORT_ENABLE:
733 mptsas_process_port_enable(s, (MPIMsgPortEnable *)req);
734 break;
735
736 case MPI_FUNCTION_EVENT_NOTIFICATION:
737 mptsas_process_event_notification(s, (MPIMsgEventNotify *)req);
738 break;
739
740 case MPI_FUNCTION_CONFIG:
741 mptsas_process_config(s, (MPIMsgConfig *)req);
742 break;
743
744 default:
745 trace_mptsas_unhandled_cmd(s, req->Function, 0);
746 mptsas_set_fault(s, MPI_IOCSTATUS_INVALID_FUNCTION);
747 break;
748 }
749}
750
751static void mptsas_fetch_request(MPTSASState *s)
752{
753 PCIDevice *pci = (PCIDevice *) s;
754 char req[MPTSAS_MAX_REQUEST_SIZE];
755 MPIRequestHeader *hdr = (MPIRequestHeader *)req;
756 hwaddr addr;
757 int size;
758
e351b826
PB		 759 /* Read the message header from the guest first. */
760 addr = s->host_mfa_high_addr | MPTSAS_FIFO_GET(s, request_post);
b01a2d07 761 pci_dma_read(pci, addr, req, sizeof(*hdr));
e351b826
PB		 762
763 if (hdr->Function < ARRAY_SIZE(mpi_request_sizes) &&
764 mpi_request_sizes[hdr->Function]) {
765 /* Read the rest of the request based on the type. Do not
766 * reread everything, as that could cause a TOC/TOU mismatch
767 * and leak data from the QEMU stack.
768 */
769 size = mpi_request_sizes[hdr->Function];
770 assert(size <= MPTSAS_MAX_REQUEST_SIZE);
b01a2d07
LQ		 771 pci_dma_read(pci, addr + sizeof(*hdr), &req[sizeof(*hdr)],
772 size - sizeof(*hdr));
e351b826
PB		 773 }
774
775 if (hdr->Function == MPI_FUNCTION_SCSI_IO_REQUEST) {
776 /* SCSI I/O requests are separate from mptsas_process_message
777 * because they cannot be sent through the doorbell yet.
778 */
779 mptsas_process_scsi_io_request(s, (MPIMsgSCSIIORequest *)req, addr);
780 } else {
781 mptsas_process_message(s, (MPIRequestHeader *)req);
782 }
783}
784
785static void mptsas_fetch_requests(void *opaque)
786{
787 MPTSASState *s = opaque;
788
06630554
PP		 789 if (s->state != MPI_IOC_STATE_OPERATIONAL) {
790 mptsas_set_fault(s, MPI_IOCSTATUS_INVALID_STATE);
791 return;
792 }
e351b826
PB		 793 while (!MPTSAS_FIFO_EMPTY(s, request_post)) {
794 mptsas_fetch_request(s);
795 }
796}
797
798static void mptsas_soft_reset(MPTSASState *s)
799{
800 uint32_t save_mask;
801
802 trace_mptsas_reset(s);
803
804 /* Temporarily disable interrupts */
805 save_mask = s->intr_mask;
806 s->intr_mask = MPI_HIM_DIM | MPI_HIM_RIM;
807 mptsas_update_interrupt(s);
808
824755ba 809 qbus_reset_all(BUS(&s->bus));
e351b826
PB		 810 s->intr_status = 0;
811 s->intr_mask = save_mask;
812
813 s->reply_free_tail = 0;
814 s->reply_free_head = 0;
815 s->reply_post_tail = 0;
816 s->reply_post_head = 0;
817 s->request_post_tail = 0;
818 s->request_post_head = 0;
819 qemu_bh_cancel(s->request_bh);
820
821 s->state = MPI_IOC_STATE_READY;
822}
823
824static uint32_t mptsas_doorbell_read(MPTSASState *s)
825{
826 uint32_t ret;
827
9155b760 828 ret = (s->who_init << MPI_DOORBELL_WHO_INIT_SHIFT) & MPI_DOORBELL_WHO_INIT_MASK;
e351b826
PB		 829 ret |= s->state;
830 switch (s->doorbell_state) {
831 case DOORBELL_NONE:
832 break;
833
834 case DOORBELL_WRITE:
835 ret |= MPI_DOORBELL_ACTIVE;
836 break;
837
838 case DOORBELL_READ:
839 /* Get rid of the IOC fault code. */
840 ret &= ~MPI_DOORBELL_DATA_MASK;
841
842 assert(s->intr_status & MPI_HIS_DOORBELL_INTERRUPT);
843 assert(s->doorbell_reply_idx <= s->doorbell_reply_size);
844
845 ret |= MPI_DOORBELL_ACTIVE;
846 if (s->doorbell_reply_idx < s->doorbell_reply_size) {
847 /* For more information about this endian switch, see the
848 * commit message for commit 36b62ae ("fw_cfg: fix endianness in
849 * fw_cfg_data_mem_read() / _write()", 2015-01-16).
850 */
851 ret |= le16_to_cpu(s->doorbell_reply[s->doorbell_reply_idx++]);
852 }
853 break;
854
855 default:
856 abort();
857 }
858
859 return ret;
860}
861
862static void mptsas_doorbell_write(MPTSASState *s, uint32_t val)
863{
864 if (s->doorbell_state == DOORBELL_WRITE) {
865 if (s->doorbell_idx < s->doorbell_cnt) {
866 /* For more information about this endian switch, see the
867 * commit message for commit 36b62ae ("fw_cfg: fix endianness in
868 * fw_cfg_data_mem_read() / _write()", 2015-01-16).
869 */
870 s->doorbell_msg[s->doorbell_idx++] = cpu_to_le32(val);
871 if (s->doorbell_idx == s->doorbell_cnt) {
872 mptsas_process_message(s, (MPIRequestHeader *)s->doorbell_msg);
873 }
874 }
875 return;
876 }
877
878 switch ((val & MPI_DOORBELL_FUNCTION_MASK) >> MPI_DOORBELL_FUNCTION_SHIFT) {
879 case MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET:
880 mptsas_soft_reset(s);
881 break;
882 case MPI_FUNCTION_IO_UNIT_RESET:
883 break;
884 case MPI_FUNCTION_HANDSHAKE:
885 s->doorbell_state = DOORBELL_WRITE;
886 s->doorbell_idx = 0;
887 s->doorbell_cnt = (val & MPI_DOORBELL_ADD_DWORDS_MASK)
888 >> MPI_DOORBELL_ADD_DWORDS_SHIFT;
889 s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT;
890 mptsas_update_interrupt(s);
891 break;
892 default:
893 trace_mptsas_unhandled_doorbell_cmd(s, val);
894 break;
895 }
896}
897
898static void mptsas_write_sequence_write(MPTSASState *s, uint32_t val)
899{
900 /* If the diagnostic register is enabled, any write to this register
901 * will disable it. Otherwise, the guest has to do a magic five-write
902 * sequence.
903 */
904 if (s->diagnostic & MPI_DIAG_DRWE) {
905 goto disable;
906 }
907
908 switch (s->diagnostic_idx) {
909 case 0:
910 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_1ST_KEY_VALUE) {
911 goto disable;
912 }
913 break;
914 case 1:
915 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_2ND_KEY_VALUE) {
916 goto disable;
917 }
918 break;
919 case 2:
920 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_3RD_KEY_VALUE) {
921 goto disable;
922 }
923 break;
924 case 3:
925 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_4TH_KEY_VALUE) {
926 goto disable;
927 }
928 break;
929 case 4:
930 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_5TH_KEY_VALUE) {
931 goto disable;
932 }
933 /* Prepare Spaceball One for departure, and change the
934 * combination on my luggage!
935 */
936 s->diagnostic |= MPI_DIAG_DRWE;
937 break;
938 }
939 s->diagnostic_idx++;
940 return;
941
942disable:
943 s->diagnostic &= ~MPI_DIAG_DRWE;
944 s->diagnostic_idx = 0;
945}
946
947static int mptsas_hard_reset(MPTSASState *s)
948{
949 mptsas_soft_reset(s);
950
951 s->intr_mask = MPI_HIM_DIM | MPI_HIM_RIM;
952
953 s->host_mfa_high_addr = 0;
954 s->sense_buffer_high_addr = 0;
955 s->reply_frame_size = 0;
956 s->max_devices = MPTSAS_NUM_PORTS;
957 s->max_buses = 1;
958
959 return 0;
960}
961
962static void mptsas_interrupt_status_write(MPTSASState *s)
963{
964 switch (s->doorbell_state) {
965 case DOORBELL_NONE:
966 case DOORBELL_WRITE:
967 s->intr_status &= ~MPI_HIS_DOORBELL_INTERRUPT;
968 break;
969
970 case DOORBELL_READ:
971 /* The reply can be read continuously, so leave the interrupt up. */
972 assert(s->intr_status & MPI_HIS_DOORBELL_INTERRUPT);
973 if (s->doorbell_reply_idx == s->doorbell_reply_size) {
974 s->doorbell_state = DOORBELL_NONE;
975 }
976 break;
977
978 default:
979 abort();
980 }
981 mptsas_update_interrupt(s);
982}
983
984static uint32_t mptsas_reply_post_read(MPTSASState *s)
985{
986 uint32_t ret;
987
988 if (!MPTSAS_FIFO_EMPTY(s, reply_post)) {
989 ret = MPTSAS_FIFO_GET(s, reply_post);
990 } else {
991 ret = -1;
992 s->intr_status &= ~MPI_HIS_REPLY_MESSAGE_INTERRUPT;
993 mptsas_update_interrupt(s);
994 }
995
996 return ret;
997}
998
999static uint64_t mptsas_mmio_read(void *opaque, hwaddr addr,
1000 unsigned size)
1001{
1002 MPTSASState *s = opaque;
1003 uint32_t ret = 0;
1004
1005 switch (addr & ~3) {
1006 case MPI_DOORBELL_OFFSET:
1007 ret = mptsas_doorbell_read(s);
1008 break;
1009
1010 case MPI_DIAGNOSTIC_OFFSET:
1011 ret = s->diagnostic;
1012 break;
1013
1014 case MPI_HOST_INTERRUPT_STATUS_OFFSET:
1015 ret = s->intr_status;
1016 break;
1017
1018 case MPI_HOST_INTERRUPT_MASK_OFFSET:
1019 ret = s->intr_mask;
1020 break;
1021
1022 case MPI_REPLY_POST_FIFO_OFFSET:
1023 ret = mptsas_reply_post_read(s);
1024 break;
1025
1026 default:
1027 trace_mptsas_mmio_unhandled_read(s, addr);
1028 break;
1029 }
1030 trace_mptsas_mmio_read(s, addr, ret);
1031 return ret;
1032}
1033
1034static void mptsas_mmio_write(void *opaque, hwaddr addr,
1035 uint64_t val, unsigned size)
1036{
1037 MPTSASState *s = opaque;
1038
1039 trace_mptsas_mmio_write(s, addr, val);
1040 switch (addr) {
1041 case MPI_DOORBELL_OFFSET:
1042 mptsas_doorbell_write(s, val);
1043 break;
1044
1045 case MPI_WRITE_SEQUENCE_OFFSET:
1046 mptsas_write_sequence_write(s, val);
1047 break;
1048
1049 case MPI_DIAGNOSTIC_OFFSET:
1050 if (val & MPI_DIAG_RESET_ADAPTER) {
1051 mptsas_hard_reset(s);
1052 }
1053 break;
1054
1055 case MPI_HOST_INTERRUPT_STATUS_OFFSET:
1056 mptsas_interrupt_status_write(s);
1057 break;
1058
1059 case MPI_HOST_INTERRUPT_MASK_OFFSET:
1060 s->intr_mask = val & (MPI_HIM_RIM | MPI_HIM_DIM);
1061 mptsas_update_interrupt(s);
1062 break;
1063
1064 case MPI_REQUEST_POST_FIFO_OFFSET:
1065 if (MPTSAS_FIFO_FULL(s, request_post)) {
1066 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES);
1067 } else {
1068 MPTSAS_FIFO_PUT(s, request_post, val & ~0x03);
1069 qemu_bh_schedule(s->request_bh);
1070 }
1071 break;
1072
1073 case MPI_REPLY_FREE_FIFO_OFFSET:
1074 if (MPTSAS_FIFO_FULL(s, reply_free)) {
1075 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES);
1076 } else {
1077 MPTSAS_FIFO_PUT(s, reply_free, val);
1078 }
1079 break;
1080
1081 default:
1082 trace_mptsas_mmio_unhandled_write(s, addr, val);
1083 break;
1084 }
1085}
1086
1087static const MemoryRegionOps mptsas_mmio_ops = {
1088 .read = mptsas_mmio_read,
1089 .write = mptsas_mmio_write,
1090 .endianness = DEVICE_LITTLE_ENDIAN,
1091 .impl = {
1092 .min_access_size = 4,
1093 .max_access_size = 4,
1094 }
1095};
1096
1097static const MemoryRegionOps mptsas_port_ops = {
1098 .read = mptsas_mmio_read,
1099 .write = mptsas_mmio_write,
1100 .endianness = DEVICE_LITTLE_ENDIAN,
1101 .impl = {
1102 .min_access_size = 4,
1103 .max_access_size = 4,
1104 }
1105};
1106
1107static uint64_t mptsas_diag_read(void *opaque, hwaddr addr,
1108 unsigned size)
1109{
1110 MPTSASState *s = opaque;
1111 trace_mptsas_diag_read(s, addr, 0);
1112 return 0;
1113}
1114
1115static void mptsas_diag_write(void *opaque, hwaddr addr,
1116 uint64_t val, unsigned size)
1117{
1118 MPTSASState *s = opaque;
1119 trace_mptsas_diag_write(s, addr, val);
1120}
1121
1122static const MemoryRegionOps mptsas_diag_ops = {
1123 .read = mptsas_diag_read,
1124 .write = mptsas_diag_write,
1125 .endianness = DEVICE_LITTLE_ENDIAN,
1126 .impl = {
1127 .min_access_size = 4,
1128 .max_access_size = 4,
1129 }
1130};
1131
1132static QEMUSGList *mptsas_get_sg_list(SCSIRequest *sreq)
1133{
1134 MPTSASRequest *req = sreq->hba_private;
1135
1136 return &req->qsg;
1137}
1138
1139static void mptsas_command_complete(SCSIRequest *sreq,
1140 uint32_t status, size_t resid)
1141{
1142 MPTSASRequest *req = sreq->hba_private;
1143 MPTSASState *s = req->dev;
1144 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
1145 uint8_t sense_len;
1146
1147 hwaddr sense_buffer_addr = req->dev->sense_buffer_high_addr |
1148 req->scsi_io.SenseBufferLowAddr;
1149
1150 trace_mptsas_command_complete(s, req->scsi_io.MsgContext, status, resid);
1151
1152 sense_len = scsi_req_get_sense(sreq, sense_buf, SCSI_SENSE_BUF_SIZE);
1153 if (sense_len > 0) {
1154 pci_dma_write(PCI_DEVICE(s), sense_buffer_addr, sense_buf,
1155 MIN(req->scsi_io.SenseBufferLength, sense_len));
1156 }
1157
1158 if (sreq->status != GOOD || resid ||
1159 req->dev->doorbell_state == DOORBELL_WRITE) {
1160 MPIMsgSCSIIOReply reply;
1161
1162 memset(&reply, 0, sizeof(reply));
1163 reply.TargetID = req->scsi_io.TargetID;
1164 reply.Bus = req->scsi_io.Bus;
1165 reply.MsgLength = sizeof(reply) / 4;
1166 reply.Function = req->scsi_io.Function;
1167 reply.CDBLength = req->scsi_io.CDBLength;
1168 reply.SenseBufferLength = req->scsi_io.SenseBufferLength;
1169 reply.MsgFlags = req->scsi_io.MsgFlags;
1170 reply.MsgContext = req->scsi_io.MsgContext;
1171 reply.SCSIStatus = sreq->status;
1172 if (sreq->status == GOOD) {
1173 reply.TransferCount = req->scsi_io.DataLength - resid;
1174 if (resid) {
1175 reply.IOCStatus = MPI_IOCSTATUS_SCSI_DATA_UNDERRUN;
1176 }
1177 } else {
1178 reply.SCSIState = MPI_SCSI_STATE_AUTOSENSE_VALID;
1179 reply.SenseCount = sense_len;
1180 reply.IOCStatus = MPI_IOCSTATUS_SCSI_DATA_UNDERRUN;
1181 }
1182
1183 mptsas_fix_scsi_io_reply_endianness(&reply);
1184 mptsas_post_reply(req->dev, (MPIDefaultReply *)&reply);
1185 } else {
1186 mptsas_turbo_reply(req->dev, req->scsi_io.MsgContext);
1187 }
1188
1189 mptsas_free_request(req);
1190}
1191
1192static void mptsas_request_cancelled(SCSIRequest *sreq)
1193{
1194 MPTSASRequest *req = sreq->hba_private;
1195 MPIMsgSCSIIOReply reply;
1196
1197 memset(&reply, 0, sizeof(reply));
1198 reply.TargetID = req->scsi_io.TargetID;
1199 reply.Bus = req->scsi_io.Bus;
1200 reply.MsgLength = sizeof(reply) / 4;
1201 reply.Function = req->scsi_io.Function;
1202 reply.CDBLength = req->scsi_io.CDBLength;
1203 reply.SenseBufferLength = req->scsi_io.SenseBufferLength;
1204 reply.MsgFlags = req->scsi_io.MsgFlags;
1205 reply.MsgContext = req->scsi_io.MsgContext;
1206 reply.SCSIState = MPI_SCSI_STATE_NO_SCSI_STATUS;
1207 reply.IOCStatus = MPI_IOCSTATUS_SCSI_TASK_TERMINATED;
1208
1209 mptsas_fix_scsi_io_reply_endianness(&reply);
1210 mptsas_post_reply(req->dev, (MPIDefaultReply *)&reply);
1211 mptsas_free_request(req);
1212}
1213
1214static void mptsas_save_request(QEMUFile *f, SCSIRequest *sreq)
1215{
1216 MPTSASRequest *req = sreq->hba_private;
1217 int i;
1218
1219 qemu_put_buffer(f, (unsigned char *)&req->scsi_io, sizeof(req->scsi_io));
1220 qemu_put_be32(f, req->qsg.nsg);
1221 for (i = 0; i < req->qsg.nsg; i++) {
1222 qemu_put_be64(f, req->qsg.sg[i].base);
1223 qemu_put_be64(f, req->qsg.sg[i].len);
1224 }
1225}
1226
1227static void *mptsas_load_request(QEMUFile *f, SCSIRequest *sreq)
1228{
1229 SCSIBus *bus = sreq->bus;
1230 MPTSASState *s = container_of(bus, MPTSASState, bus);
1231 PCIDevice *pci = PCI_DEVICE(s);
1232 MPTSASRequest *req;
1233 int i, n;
1234
1235 req = g_new(MPTSASRequest, 1);
1236 qemu_get_buffer(f, (unsigned char *)&req->scsi_io, sizeof(req->scsi_io));
1237
1238 n = qemu_get_be32(f);
1239 /* TODO: add a way for SCSIBusInfo's load_request to fail,
1240 * and fail migration instead of asserting here.
262a69f4
EB		 1241 * This is just one thing (there are probably more) that must be
1242 * fixed before we can allow NDEBUG compilation.
e351b826 1243 */
e351b826
PB		 1244 assert(n >= 0);
1245
1246 pci_dma_sglist_init(&req->qsg, pci, n);
1247 for (i = 0; i < n; i++) {
1248 uint64_t base = qemu_get_be64(f);
1249 uint64_t len = qemu_get_be64(f);
1250 qemu_sglist_add(&req->qsg, base, len);
1251 }
1252
1253 scsi_req_ref(sreq);
1254 req->sreq = sreq;
1255 req->dev = s;
1256
1257 return req;
1258}
1259
1260static const struct SCSIBusInfo mptsas_scsi_info = {
1261 .tcq = true,
1262 .max_target = MPTSAS_NUM_PORTS,
1263 .max_lun = 1,
1264
1265 .get_sg_list = mptsas_get_sg_list,
1266 .complete = mptsas_command_complete,
1267 .cancel = mptsas_request_cancelled,
1268 .save_request = mptsas_save_request,
1269 .load_request = mptsas_load_request,
1270};
1271
afe4c953 1272static void mptsas_scsi_realize(PCIDevice *dev, Error **errp)
e351b826 1273{
e351b826 1274 MPTSASState *s = MPT_SAS(dev);
1108b2f8
C		 1275 Error *err = NULL;
1276 int ret;
e351b826
PB		 1277
1278 dev->config[PCI_LATENCY_TIMER] = 0;
1279 dev->config[PCI_INTERRUPT_PIN] = 0x01;
1280
1108b2f8
C		 1281 if (s->msi != ON_OFF_AUTO_OFF) {
1282 ret = msi_init(dev, 0, 1, true, false, &err);
1283 /* Any error other than -ENOTSUP(board's MSI support is broken)
1284 * is a programming error */
1285 assert(!ret || ret == -ENOTSUP);
1286 if (ret && s->msi == ON_OFF_AUTO_ON) {
1287 /* Can't satisfy user's explicit msi=on request, fail */
1288 error_append_hint(&err, "You have to use msi=auto (default) or "
1289 "msi=off with this machine type.\n");
1290 error_propagate(errp, err);
1108b2f8 1291 return;
1108b2f8 1292 }
2e2aa316
C		 1293 assert(!err || s->msi == ON_OFF_AUTO_AUTO);
1294 /* With msi=auto, we fall back to MSI off silently */
1295 error_free(err);
1296
0b646f44
PB		 1297 /* Only used for migration. */
1298 s->msi_in_use = (ret == 0);
1108b2f8
C		 1299 }
1300
e351b826
PB		 1301 memory_region_init_io(&s->mmio_io, OBJECT(s), &mptsas_mmio_ops, s,
1302 "mptsas-mmio", 0x4000);
1303 memory_region_init_io(&s->port_io, OBJECT(s), &mptsas_port_ops, s,
1304 "mptsas-io", 256);
1305 memory_region_init_io(&s->diag_io, OBJECT(s), &mptsas_diag_ops, s,
1306 "mptsas-diag", 0x10000);
1307
e351b826
PB		 1308 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
1309 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY |
1310 PCI_BASE_ADDRESS_MEM_TYPE_32, &s->mmio_io);
1311 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY |
1312 PCI_BASE_ADDRESS_MEM_TYPE_32, &s->diag_io);
1313
1314 if (!s->sas_addr) {
1315 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
1316 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
cdc57472 1317 s->sas_addr |= (pci_dev_bus_num(dev) << 16);
e351b826
PB		 1318 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8);
1319 s->sas_addr |= PCI_FUNC(dev->devfn);
1320 }
1321 s->max_devices = MPTSAS_NUM_PORTS;
1322
1323 s->request_bh = qemu_bh_new(mptsas_fetch_requests, s);
1324
1325 QTAILQ_INIT(&s->pending);
1326
1327 scsi_bus_new(&s->bus, sizeof(s->bus), &dev->qdev, &mptsas_scsi_info, NULL);
e351b826
PB		 1328}
1329
1330static void mptsas_scsi_uninit(PCIDevice *dev)
1331{
1332 MPTSASState *s = MPT_SAS(dev);
1333
1334 qemu_bh_delete(s->request_bh);
2e2aa316 1335 msi_uninit(dev);
e351b826
PB		 1336}
1337
1338static void mptsas_reset(DeviceState *dev)
1339{
1340 MPTSASState *s = MPT_SAS(dev);
1341
1342 mptsas_hard_reset(s);
1343}
1344
1345static int mptsas_post_load(void *opaque, int version_id)
1346{
1347 MPTSASState *s = opaque;
1348
1349 if (s->doorbell_idx > s->doorbell_cnt ||
1350 s->doorbell_cnt > ARRAY_SIZE(s->doorbell_msg) ||
1351 s->doorbell_reply_idx > s->doorbell_reply_size ||
1352 s->doorbell_reply_size > ARRAY_SIZE(s->doorbell_reply) ||
1353 MPTSAS_FIFO_INVALID(s, request_post) ||
1354 MPTSAS_FIFO_INVALID(s, reply_post) ||
1355 MPTSAS_FIFO_INVALID(s, reply_free) ||
1356 s->diagnostic_idx > 4) {
1357 return -EINVAL;
1358 }
1359
1360 return 0;
1361}
1362
1363static const VMStateDescription vmstate_mptsas = {
1364 .name = "mptsas",
1365 .version_id = 0,
1366 .minimum_version_id = 0,
1367 .minimum_version_id_old = 0,
1368 .post_load = mptsas_post_load,
1369 .fields = (VMStateField[]) {
1370 VMSTATE_PCI_DEVICE(dev, MPTSASState),
0b646f44 1371 VMSTATE_BOOL(msi_in_use, MPTSASState),
e351b826
PB		 1372 VMSTATE_UINT32(state, MPTSASState),
1373 VMSTATE_UINT8(who_init, MPTSASState),
1374 VMSTATE_UINT8(doorbell_state, MPTSASState),
1375 VMSTATE_UINT32_ARRAY(doorbell_msg, MPTSASState, 256),
1376 VMSTATE_INT32(doorbell_idx, MPTSASState),
1377 VMSTATE_INT32(doorbell_cnt, MPTSASState),
1378
1379 VMSTATE_UINT16_ARRAY(doorbell_reply, MPTSASState, 256),
1380 VMSTATE_INT32(doorbell_reply_idx, MPTSASState),
1381 VMSTATE_INT32(doorbell_reply_size, MPTSASState),
1382
1383 VMSTATE_UINT32(diagnostic, MPTSASState),
1384 VMSTATE_UINT8(diagnostic_idx, MPTSASState),
1385
1386 VMSTATE_UINT32(intr_status, MPTSASState),
1387 VMSTATE_UINT32(intr_mask, MPTSASState),
1388
1389 VMSTATE_UINT32_ARRAY(request_post, MPTSASState,
1390 MPTSAS_REQUEST_QUEUE_DEPTH + 1),
1391 VMSTATE_UINT16(request_post_head, MPTSASState),
1392 VMSTATE_UINT16(request_post_tail, MPTSASState),
1393
1394 VMSTATE_UINT32_ARRAY(reply_post, MPTSASState,
1395 MPTSAS_REPLY_QUEUE_DEPTH + 1),
1396 VMSTATE_UINT16(reply_post_head, MPTSASState),
1397 VMSTATE_UINT16(reply_post_tail, MPTSASState),
1398
1399 VMSTATE_UINT32_ARRAY(reply_free, MPTSASState,
1400 MPTSAS_REPLY_QUEUE_DEPTH + 1),
1401 VMSTATE_UINT16(reply_free_head, MPTSASState),
1402 VMSTATE_UINT16(reply_free_tail, MPTSASState),
1403
1404 VMSTATE_UINT16(max_buses, MPTSASState),
1405 VMSTATE_UINT16(max_devices, MPTSASState),
1406 VMSTATE_UINT16(reply_frame_size, MPTSASState),
1407 VMSTATE_UINT64(host_mfa_high_addr, MPTSASState),
1408 VMSTATE_UINT64(sense_buffer_high_addr, MPTSASState),
1409 VMSTATE_END_OF_LIST()
1410 }
1411};
1412
1413static Property mptsas_properties[] = {
1414 DEFINE_PROP_UINT64("sas_address", MPTSASState, sas_addr, 0),
1415 /* TODO: test MSI support under Windows */
444dd1af 1416 DEFINE_PROP_ON_OFF_AUTO("msi", MPTSASState, msi, ON_OFF_AUTO_AUTO),
e351b826
PB		 1417 DEFINE_PROP_END_OF_LIST(),
1418};
1419
1420static void mptsas1068_class_init(ObjectClass *oc, void *data)
1421{
1422 DeviceClass *dc = DEVICE_CLASS(oc);
1423 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
1424
afe4c953 1425 pc->realize = mptsas_scsi_realize;
e351b826
PB		 1426 pc->exit = mptsas_scsi_uninit;
1427 pc->romfile = 0;
1428 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
1429 pc->device_id = PCI_DEVICE_ID_LSI_SAS1068;
1430 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
1431 pc->subsystem_id = 0x8000;
1432 pc->class_id = PCI_CLASS_STORAGE_SCSI;
1433 dc->props = mptsas_properties;
1434 dc->reset = mptsas_reset;
1435 dc->vmsd = &vmstate_mptsas;
1436 dc->desc = "LSI SAS 1068";
a736d719 1437 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
e351b826
PB		 1438}
1439
1440static const TypeInfo mptsas_info = {
1441 .name = TYPE_MPTSAS1068,
1442 .parent = TYPE_PCI_DEVICE,
1443 .instance_size = sizeof(MPTSASState),
1444 .class_init = mptsas1068_class_init,
fd3b02c8
EH		 1445 .interfaces = (InterfaceInfo[]) {
1446 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1447 { },
1448 },
e351b826
PB		 1449};
1450
1451static void mptsas_register_types(void)
1452{
1453 type_register(&mptsas_info);
1454}
1455
1456type_init(mptsas_register_types)
Empty description
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