[qemu.git] / hw / rx / rx-gdbsim.c

/*
 * RX QEMU GDB simulator
 *
 * Copyright (c) 2019 Yoshinori Sato
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu/cutils.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/hw.h"
#include "hw/sysbus.h"
#include "hw/loader.h"
#include "hw/rx/rx62n.h"
#include "sysemu/sysemu.h"
#include "sysemu/qtest.h"
#include "sysemu/device_tree.h"
#include "hw/boards.h"
#include "qom/object.h"

/* Same address of GDB integrated simulator */
#define SDRAM_BASE  EXT_CS_BASE

struct RxGdbSimMachineClass {
    /*< private >*/
    MachineClass parent_class;
    /*< public >*/
    const char *mcu_name;
    uint32_t xtal_freq_hz;
};
typedef struct RxGdbSimMachineClass RxGdbSimMachineClass;

struct RxGdbSimMachineState {
    /*< private >*/
    MachineState parent_obj;
    /*< public >*/
    RX62NState mcu;
};
typedef struct RxGdbSimMachineState RxGdbSimMachineState;

#define TYPE_RX_GDBSIM_MACHINE MACHINE_TYPE_NAME("rx62n-common")

#define RX_GDBSIM_MACHINE(obj) \
    OBJECT_CHECK(RxGdbSimMachineState, (obj), TYPE_RX_GDBSIM_MACHINE)

#define RX_GDBSIM_MACHINE_CLASS(klass) \
    OBJECT_CLASS_CHECK(RxGdbSimMachineClass, (klass), TYPE_RX_GDBSIM_MACHINE)
#define RX_GDBSIM_MACHINE_GET_CLASS(obj) \
    OBJECT_GET_CLASS(RxGdbSimMachineClass, (obj), TYPE_RX_GDBSIM_MACHINE)

static void rx_load_image(RXCPU *cpu, const char *filename,
                          uint32_t start, uint32_t size)
{
    static uint32_t extable[32];
    long kernel_size;
    int i;

    kernel_size = load_image_targphys(filename, start, size);
    if (kernel_size < 0) {
        fprintf(stderr, "qemu: could not load kernel '%s'\n", filename);
        exit(1);
    }
    cpu->env.pc = start;

    /* setup exception trap trampoline */
    /* linux kernel only works little-endian mode */
    for (i = 0; i < ARRAY_SIZE(extable); i++) {
        extable[i] = cpu_to_le32(0x10 + i * 4);
    }
    rom_add_blob_fixed("extable", extable, sizeof(extable), VECTOR_TABLE_BASE);
}

static void rx_gdbsim_init(MachineState *machine)
{
    MachineClass *mc = MACHINE_GET_CLASS(machine);
    RxGdbSimMachineState *s = RX_GDBSIM_MACHINE(machine);
    RxGdbSimMachineClass *rxc = RX_GDBSIM_MACHINE_GET_CLASS(machine);
    MemoryRegion *sysmem = get_system_memory();
    const char *kernel_filename = machine->kernel_filename;
    const char *dtb_filename = machine->dtb;

    if (machine->ram_size < mc->default_ram_size) {
        char *sz = size_to_str(mc->default_ram_size);
        error_report("Invalid RAM size, should be more than %s", sz);
        g_free(sz);
    }

    /* Allocate memory space */
    memory_region_add_subregion(sysmem, SDRAM_BASE, machine->ram);

    /* Initialize MCU */
    object_initialize_child(OBJECT(machine), "mcu", &s->mcu, rxc->mcu_name);
    object_property_set_link(OBJECT(&s->mcu), "main-bus", OBJECT(sysmem),
                             &error_abort);
    object_property_set_uint(OBJECT(&s->mcu), "xtal-frequency-hz",
                             rxc->xtal_freq_hz, &error_abort);
    object_property_set_bool(OBJECT(&s->mcu), "load-kernel",
                             kernel_filename != NULL, &error_abort);
    qdev_realize(DEVICE(&s->mcu), NULL, &error_abort);

    /* Load kernel and dtb */
    if (kernel_filename) {
        ram_addr_t kernel_offset;

        /*
         * The kernel image is loaded into
         * the latter half of the SDRAM space.
         */
        kernel_offset = machine->ram_size / 2;
        rx_load_image(RX_CPU(first_cpu), kernel_filename,
                      SDRAM_BASE + kernel_offset, kernel_offset);
        if (dtb_filename) {
            ram_addr_t dtb_offset;
            int dtb_size;
            void *dtb;

            dtb = load_device_tree(dtb_filename, &dtb_size);
            if (dtb == NULL) {
                error_report("Couldn't open dtb file %s", dtb_filename);
                exit(1);
            }
            if (machine->kernel_cmdline &&
                qemu_fdt_setprop_string(dtb, "/chosen", "bootargs",
                                        machine->kernel_cmdline) < 0) {
                error_report("Couldn't set /chosen/bootargs");
                exit(1);
            }
            /* DTB is located at the end of SDRAM space. */
            dtb_offset = machine->ram_size - dtb_size;
            rom_add_blob_fixed("dtb", dtb, dtb_size,
                               SDRAM_BASE + dtb_offset);
            /* Set dtb address to R1 */
            RX_CPU(first_cpu)->env.regs[1] = SDRAM_BASE + dtb_offset;
        }
    }
}

static void rx_gdbsim_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->init = rx_gdbsim_init;
    mc->default_cpu_type = TYPE_RX62N_CPU;
    mc->default_ram_size = 16 * MiB;
    mc->default_ram_id = "ext-sdram";
}

static void rx62n7_class_init(ObjectClass *oc, void *data)
{
    RxGdbSimMachineClass *rxc = RX_GDBSIM_MACHINE_CLASS(oc);
    MachineClass *mc = MACHINE_CLASS(oc);

    rxc->mcu_name = TYPE_R5F562N7_MCU;
    rxc->xtal_freq_hz = 12 * 1000 * 1000;
    mc->desc = "gdb simulator (R5F562N7 MCU and external RAM)";
};

static void rx62n8_class_init(ObjectClass *oc, void *data)
{
    RxGdbSimMachineClass *rxc = RX_GDBSIM_MACHINE_CLASS(oc);
    MachineClass *mc = MACHINE_CLASS(oc);

    rxc->mcu_name = TYPE_R5F562N8_MCU;
    rxc->xtal_freq_hz = 12 * 1000 * 1000;
    mc->desc = "gdb simulator (R5F562N8 MCU and external RAM)";
};

static const TypeInfo rx_gdbsim_types[] = {
    {
        .name           = MACHINE_TYPE_NAME("gdbsim-r5f562n7"),
        .parent         = TYPE_RX_GDBSIM_MACHINE,
        .class_init     = rx62n7_class_init,
    }, {
        .name           = MACHINE_TYPE_NAME("gdbsim-r5f562n8"),
        .parent         = TYPE_RX_GDBSIM_MACHINE,
        .class_init     = rx62n8_class_init,
    }, {
        .name           = TYPE_RX_GDBSIM_MACHINE,
        .parent         = TYPE_MACHINE,
        .instance_size  = sizeof(RxGdbSimMachineState),
        .class_size     = sizeof(RxGdbSimMachineClass),
        .class_init     = rx_gdbsim_class_init,
        .abstract       = true,
     }
};

DEFINE_TYPES(rx_gdbsim_types)
Commit	Line	Data
bda19d7b YS	1	/*
	2	* RX QEMU GDB simulator
	3	*
	4	* Copyright (c) 2019 Yoshinori Sato
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2 or later, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along with
	16	* this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
	19	#include "qemu/osdep.h"
	20	#include "qemu/cutils.h"
	21	#include "qemu/error-report.h"
	22	#include "qapi/error.h"
	23	#include "qemu-common.h"
	24	#include "cpu.h"
	25	#include "hw/hw.h"
	26	#include "hw/sysbus.h"
	27	#include "hw/loader.h"
	28	#include "hw/rx/rx62n.h"
	29	#include "sysemu/sysemu.h"
	30	#include "sysemu/qtest.h"
	31	#include "sysemu/device_tree.h"
	32	#include "hw/boards.h"
db1015e9	33	#include "qom/object.h"
bda19d7b YS	34
	35	/* Same address of GDB integrated simulator */
	36	#define SDRAM_BASE EXT_CS_BASE
	37
db1015e9	38	struct RxGdbSimMachineClass {
bda19d7b YS	39	/< private >/
	40	MachineClass parent_class;
	41	/< public >/
	42	const char *mcu_name;
	43	uint32_t xtal_freq_hz;
db1015e9 EH	44	};
db1015e9 EH	45	typedef struct RxGdbSimMachineClass RxGdbSimMachineClass;
bda19d7b	46
db1015e9	47	struct RxGdbSimMachineState {
bda19d7b YS	48	/< private >/
	49	MachineState parent_obj;
	50	/< public >/
	51	RX62NState mcu;
db1015e9 EH	52	};
db1015e9 EH	53	typedef struct RxGdbSimMachineState RxGdbSimMachineState;
bda19d7b YS	54
	55	#define TYPE_RX_GDBSIM_MACHINE MACHINE_TYPE_NAME("rx62n-common")
	56
	57	#define RX_GDBSIM_MACHINE(obj) \
	58	OBJECT_CHECK(RxGdbSimMachineState, (obj), TYPE_RX_GDBSIM_MACHINE)
	59
	60	#define RX_GDBSIM_MACHINE_CLASS(klass) \
	61	OBJECT_CLASS_CHECK(RxGdbSimMachineClass, (klass), TYPE_RX_GDBSIM_MACHINE)
	62	#define RX_GDBSIM_MACHINE_GET_CLASS(obj) \
	63	OBJECT_GET_CLASS(RxGdbSimMachineClass, (obj), TYPE_RX_GDBSIM_MACHINE)
	64
	65	static void rx_load_image(RXCPU cpu, const char filename,
	66	uint32_t start, uint32_t size)
	67	{
	68	static uint32_t extable[32];
	69	long kernel_size;
	70	int i;
	71
	72	kernel_size = load_image_targphys(filename, start, size);
	73	if (kernel_size < 0) {
	74	fprintf(stderr, "qemu: could not load kernel '%s'\n", filename);
	75	exit(1);
	76	}
	77	cpu->env.pc = start;
	78
	79	/* setup exception trap trampoline */
	80	/* linux kernel only works little-endian mode */
	81	for (i = 0; i < ARRAY_SIZE(extable); i++) {
	82	extable[i] = cpu_to_le32(0x10 + i * 4);
	83	}
	84	rom_add_blob_fixed("extable", extable, sizeof(extable), VECTOR_TABLE_BASE);
	85	}
	86
	87	static void rx_gdbsim_init(MachineState *machine)
	88	{
	89	MachineClass *mc = MACHINE_GET_CLASS(machine);
	90	RxGdbSimMachineState *s = RX_GDBSIM_MACHINE(machine);
	91	RxGdbSimMachineClass *rxc = RX_GDBSIM_MACHINE_GET_CLASS(machine);
	92	MemoryRegion *sysmem = get_system_memory();
	93	const char *kernel_filename = machine->kernel_filename;
	94	const char *dtb_filename = machine->dtb;
	95
	96	if (machine->ram_size < mc->default_ram_size) {
	97	char *sz = size_to_str(mc->default_ram_size);
	98	error_report("Invalid RAM size, should be more than %s", sz);
	99	g_free(sz);
	100	}
	101
	102	/* Allocate memory space */
	103	memory_region_add_subregion(sysmem, SDRAM_BASE, machine->ram);
	104
	105	/* Initialize MCU */
	106	object_initialize_child(OBJECT(machine), "mcu", &s->mcu, rxc->mcu_name);
5325cc34 MA	107	object_property_set_link(OBJECT(&s->mcu), "main-bus", OBJECT(sysmem),
	108	&error_abort);
	109	object_property_set_uint(OBJECT(&s->mcu), "xtal-frequency-hz",
	110	rxc->xtal_freq_hz, &error_abort);
	111	object_property_set_bool(OBJECT(&s->mcu), "load-kernel",
	112	kernel_filename != NULL, &error_abort);
bda19d7b YS	113	qdev_realize(DEVICE(&s->mcu), NULL, &error_abort);
	114
	115	/* Load kernel and dtb */
	116	if (kernel_filename) {
	117	ram_addr_t kernel_offset;
	118
	119	/*
	120	* The kernel image is loaded into
	121	* the latter half of the SDRAM space.
	122	*/
	123	kernel_offset = machine->ram_size / 2;
38688fdb	124	rx_load_image(RX_CPU(first_cpu), kernel_filename,
bda19d7b YS	125	SDRAM_BASE + kernel_offset, kernel_offset);
	126	if (dtb_filename) {
	127	ram_addr_t dtb_offset;
	128	int dtb_size;
	129	void *dtb;
	130
	131	dtb = load_device_tree(dtb_filename, &dtb_size);
	132	if (dtb == NULL) {
	133	error_report("Couldn't open dtb file %s", dtb_filename);
	134	exit(1);
	135	}
	136	if (machine->kernel_cmdline &&
	137	qemu_fdt_setprop_string(dtb, "/chosen", "bootargs",
	138	machine->kernel_cmdline) < 0) {
	139	error_report("Couldn't set /chosen/bootargs");
	140	exit(1);
	141	}
	142	/* DTB is located at the end of SDRAM space. */
	143	dtb_offset = machine->ram_size - dtb_size;
	144	rom_add_blob_fixed("dtb", dtb, dtb_size,
	145	SDRAM_BASE + dtb_offset);
	146	/* Set dtb address to R1 */
38688fdb	147	RX_CPU(first_cpu)->env.regs[1] = SDRAM_BASE + dtb_offset;
bda19d7b YS	148	}
	149	}
	150	}
	151
	152	static void rx_gdbsim_class_init(ObjectClass oc, void data)
	153	{
	154	MachineClass *mc = MACHINE_CLASS(oc);
	155
	156	mc->init = rx_gdbsim_init;
	157	mc->default_cpu_type = TYPE_RX62N_CPU;
	158	mc->default_ram_size = 16 * MiB;
	159	mc->default_ram_id = "ext-sdram";
	160	}
	161
	162	static void rx62n7_class_init(ObjectClass oc, void data)
	163	{
	164	RxGdbSimMachineClass *rxc = RX_GDBSIM_MACHINE_CLASS(oc);
	165	MachineClass *mc = MACHINE_CLASS(oc);
	166
	167	rxc->mcu_name = TYPE_R5F562N7_MCU;
	168	rxc->xtal_freq_hz = 12 * 1000 * 1000;
	169	mc->desc = "gdb simulator (R5F562N7 MCU and external RAM)";
	170	};
	171
	172	static void rx62n8_class_init(ObjectClass oc, void data)
	173	{
	174	RxGdbSimMachineClass *rxc = RX_GDBSIM_MACHINE_CLASS(oc);
	175	MachineClass *mc = MACHINE_CLASS(oc);
	176
	177	rxc->mcu_name = TYPE_R5F562N8_MCU;
	178	rxc->xtal_freq_hz = 12 * 1000 * 1000;
	179	mc->desc = "gdb simulator (R5F562N8 MCU and external RAM)";
	180	};
	181
	182	static const TypeInfo rx_gdbsim_types[] = {
	183	{
	184	.name = MACHINE_TYPE_NAME("gdbsim-r5f562n7"),
	185	.parent = TYPE_RX_GDBSIM_MACHINE,
	186	.class_init = rx62n7_class_init,
	187	}, {
	188	.name = MACHINE_TYPE_NAME("gdbsim-r5f562n8"),
	189	.parent = TYPE_RX_GDBSIM_MACHINE,
	190	.class_init = rx62n8_class_init,
	191	}, {
	192	.name = TYPE_RX_GDBSIM_MACHINE,
	193	.parent = TYPE_MACHINE,
	194	.instance_size = sizeof(RxGdbSimMachineState),
	195	.class_size = sizeof(RxGdbSimMachineClass),
	196	.class_init = rx_gdbsim_class_init,
	197	.abstract = true,
	198	}
	199	};
	200
	201	DEFINE_TYPES(rx_gdbsim_types)