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050c2ea0 PM |
1 | /* |
2 | * ARM CMSDK APB watchdog emulation | |
3 | * | |
4 | * Copyright (c) 2018 Linaro Limited | |
5 | * Written by Peter Maydell | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * This is a model of the "APB watchdog" which is part of the Cortex-M | |
14 | * System Design Kit (CMSDK) and documented in the Cortex-M System | |
15 | * Design Kit Technical Reference Manual (ARM DDI0479C): | |
16 | * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit | |
17 | * | |
18 | * QEMU interface: | |
19 | * + QOM property "wdogclk-frq": frequency at which the watchdog is clocked | |
20 | * + sysbus MMIO region 0: the register bank | |
21 | * + sysbus IRQ 0: watchdog interrupt | |
22 | * | |
23 | * In real hardware the watchdog's reset output is just a GPIO line | |
24 | * which can then be masked by the board or treated as a simple interrupt. | |
25 | * (For instance the IoTKit does this with the non-secure watchdog, so that | |
26 | * secure code can control whether non-secure code can perform a system | |
27 | * reset via its watchdog.) In QEMU, we just wire up the watchdog reset | |
28 | * to watchdog_perform_action(), at least for the moment. | |
29 | */ | |
30 | ||
31 | #ifndef CMSDK_APB_WATCHDOG_H | |
32 | #define CMSDK_APB_WATCHDOG_H | |
33 | ||
34 | #include "hw/sysbus.h" | |
35 | #include "hw/ptimer.h" | |
36 | ||
37 | #define TYPE_CMSDK_APB_WATCHDOG "cmsdk-apb-watchdog" | |
38 | #define CMSDK_APB_WATCHDOG(obj) OBJECT_CHECK(CMSDKAPBWatchdog, (obj), \ | |
39 | TYPE_CMSDK_APB_WATCHDOG) | |
40 | ||
566528f8 MH |
41 | /* |
42 | * This shares the same struct (and cast macro) as the base | |
43 | * cmsdk-apb-watchdog device. | |
44 | */ | |
45 | #define TYPE_LUMINARY_WATCHDOG "luminary-watchdog" | |
46 | ||
050c2ea0 PM |
47 | typedef struct CMSDKAPBWatchdog { |
48 | /*< private >*/ | |
49 | SysBusDevice parent_obj; | |
50 | ||
51 | /*< public >*/ | |
52 | MemoryRegion iomem; | |
53 | qemu_irq wdogint; | |
54 | uint32_t wdogclk_frq; | |
566528f8 | 55 | bool is_luminary; |
050c2ea0 PM |
56 | struct ptimer_state *timer; |
57 | ||
58 | uint32_t control; | |
59 | uint32_t intstatus; | |
60 | uint32_t lock; | |
61 | uint32_t itcr; | |
62 | uint32_t itop; | |
63 | uint32_t resetstatus; | |
566528f8 | 64 | const uint32_t *id; |
050c2ea0 PM |
65 | } CMSDKAPBWatchdog; |
66 | ||
67 | #endif |