[qemu.git] / hw / timer / i8254.c

/*
 * QEMU 8253/8254 interval timer emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw/hw.h"
#include "hw/i386/pc.h"
#include "hw/isa/isa.h"
#include "qemu/timer.h"
#include "hw/timer/i8254.h"
#include "hw/timer/i8254_internal.h"

//#define DEBUG_PIT

#define RW_STATE_LSB 1
#define RW_STATE_MSB 2
#define RW_STATE_WORD0 3
#define RW_STATE_WORD1 4

#define PIT_CLASS(class) OBJECT_CLASS_CHECK(PITClass, (class), TYPE_I8254)
#define PIT_GET_CLASS(obj) OBJECT_GET_CLASS(PITClass, (obj), TYPE_I8254)

typedef struct PITClass {
    PITCommonClass parent_class;

    DeviceRealize parent_realize;
} PITClass;

static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);

static int pit_get_count(PITChannelState *s)
{
    uint64_t d;
    int counter;

    d = muldiv64(qemu_get_clock_ns(vm_clock) - s->count_load_time, PIT_FREQ,
                 get_ticks_per_sec());
    switch(s->mode) {
    case 0:
    case 1:
    case 4:
    case 5:
        counter = (s->count - d) & 0xffff;
        break;
    case 3:
        /* XXX: may be incorrect for odd counts */
        counter = s->count - ((2 * d) % s->count);
        break;
    default:
        counter = s->count - (d % s->count);
        break;
    }
    return counter;
}

/* val must be 0 or 1 */
static void pit_set_channel_gate(PITCommonState *s, PITChannelState *sc,
                                 int val)
{
    switch (sc->mode) {
    default:
    case 0:
    case 4:
        /* XXX: just disable/enable counting */
        break;
    case 1:
    case 5:
        if (sc->gate < val) {
            /* restart counting on rising edge */
            sc->count_load_time = qemu_get_clock_ns(vm_clock);
            pit_irq_timer_update(sc, sc->count_load_time);
        }
        break;
    case 2:
    case 3:
        if (sc->gate < val) {
            /* restart counting on rising edge */
            sc->count_load_time = qemu_get_clock_ns(vm_clock);
            pit_irq_timer_update(sc, sc->count_load_time);
        }
        /* XXX: disable/enable counting */
        break;
    }
    sc->gate = val;
}

static inline void pit_load_count(PITChannelState *s, int val)
{
    if (val == 0)
        val = 0x10000;
    s->count_load_time = qemu_get_clock_ns(vm_clock);
    s->count = val;
    pit_irq_timer_update(s, s->count_load_time);
}

/* if already latched, do not latch again */
static void pit_latch_count(PITChannelState *s)
{
    if (!s->count_latched) {
        s->latched_count = pit_get_count(s);
        s->count_latched = s->rw_mode;
    }
}

static void pit_ioport_write(void *opaque, hwaddr addr,
                             uint64_t val, unsigned size)
{
    PITCommonState *pit = opaque;
    int channel, access;
    PITChannelState *s;

    addr &= 3;
    if (addr == 3) {
        channel = val >> 6;
        if (channel == 3) {
            /* read back command */
            for(channel = 0; channel < 3; channel++) {
                s = &pit->channels[channel];
                if (val & (2 << channel)) {
                    if (!(val & 0x20)) {
                        pit_latch_count(s);
                    }
                    if (!(val & 0x10) && !s->status_latched) {
                        /* status latch */
                        /* XXX: add BCD and null count */
                        s->status =
                            (pit_get_out(s,
                                         qemu_get_clock_ns(vm_clock)) << 7) |
                            (s->rw_mode << 4) |
                            (s->mode << 1) |
                            s->bcd;
                        s->status_latched = 1;
                    }
                }
            }
        } else {
            s = &pit->channels[channel];
            access = (val >> 4) & 3;
            if (access == 0) {
                pit_latch_count(s);
            } else {
                s->rw_mode = access;
                s->read_state = access;
                s->write_state = access;

                s->mode = (val >> 1) & 7;
                s->bcd = val & 1;
                /* XXX: update irq timer ? */
            }
        }
    } else {
        s = &pit->channels[addr];
        switch(s->write_state) {
        default:
        case RW_STATE_LSB:
            pit_load_count(s, val);
            break;
        case RW_STATE_MSB:
            pit_load_count(s, val << 8);
            break;
        case RW_STATE_WORD0:
            s->write_latch = val;
            s->write_state = RW_STATE_WORD1;
            break;
        case RW_STATE_WORD1:
            pit_load_count(s, s->write_latch | (val << 8));
            s->write_state = RW_STATE_WORD0;
            break;
        }
    }
}

static uint64_t pit_ioport_read(void *opaque, hwaddr addr,
                                unsigned size)
{
    PITCommonState *pit = opaque;
    int ret, count;
    PITChannelState *s;

    addr &= 3;
    s = &pit->channels[addr];
    if (s->status_latched) {
        s->status_latched = 0;
        ret = s->status;
    } else if (s->count_latched) {
        switch(s->count_latched) {
        default:
        case RW_STATE_LSB:
            ret = s->latched_count & 0xff;
            s->count_latched = 0;
            break;
        case RW_STATE_MSB:
            ret = s->latched_count >> 8;
            s->count_latched = 0;
            break;
        case RW_STATE_WORD0:
            ret = s->latched_count & 0xff;
            s->count_latched = RW_STATE_MSB;
            break;
        }
    } else {
        switch(s->read_state) {
        default:
        case RW_STATE_LSB:
            count = pit_get_count(s);
            ret = count & 0xff;
            break;
        case RW_STATE_MSB:
            count = pit_get_count(s);
            ret = (count >> 8) & 0xff;
            break;
        case RW_STATE_WORD0:
            count = pit_get_count(s);
            ret = count & 0xff;
            s->read_state = RW_STATE_WORD1;
            break;
        case RW_STATE_WORD1:
            count = pit_get_count(s);
            ret = (count >> 8) & 0xff;
            s->read_state = RW_STATE_WORD0;
            break;
        }
    }
    return ret;
}

static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
{
    int64_t expire_time;
    int irq_level;

    if (!s->irq_timer || s->irq_disabled) {
        return;
    }
    expire_time = pit_get_next_transition_time(s, current_time);
    irq_level = pit_get_out(s, current_time);
    qemu_set_irq(s->irq, irq_level);
#ifdef DEBUG_PIT
    printf("irq_level=%d next_delay=%f\n",
           irq_level,
           (double)(expire_time - current_time) / get_ticks_per_sec());
#endif
    s->next_transition_time = expire_time;
    if (expire_time != -1)
        qemu_mod_timer(s->irq_timer, expire_time);
    else
        qemu_del_timer(s->irq_timer);
}

static void pit_irq_timer(void *opaque)
{
    PITChannelState *s = opaque;

    pit_irq_timer_update(s, s->next_transition_time);
}

static void pit_reset(DeviceState *dev)
{
    PITCommonState *pit = PIT_COMMON(dev);
    PITChannelState *s;

    pit_reset_common(pit);

    s = &pit->channels[0];
    if (!s->irq_disabled) {
        qemu_mod_timer(s->irq_timer, s->next_transition_time);
    }
}

/* When HPET is operating in legacy mode, suppress the ignored timer IRQ,
 * reenable it when legacy mode is left again. */
static void pit_irq_control(void *opaque, int n, int enable)
{
    PITCommonState *pit = opaque;
    PITChannelState *s = &pit->channels[0];

    if (enable) {
        s->irq_disabled = 0;
        pit_irq_timer_update(s, qemu_get_clock_ns(vm_clock));
    } else {
        s->irq_disabled = 1;
        qemu_del_timer(s->irq_timer);
    }
}

static const MemoryRegionOps pit_ioport_ops = {
    .read = pit_ioport_read,
    .write = pit_ioport_write,
    .impl = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void pit_post_load(PITCommonState *s)
{
    PITChannelState *sc = &s->channels[0];

    if (sc->next_transition_time != -1) {
        qemu_mod_timer(sc->irq_timer, sc->next_transition_time);
    } else {
        qemu_del_timer(sc->irq_timer);
    }
}

static void pit_realizefn(DeviceState *dev, Error **err)
{
    PITCommonState *pit = PIT_COMMON(dev);
    PITClass *pc = PIT_GET_CLASS(dev);
    PITChannelState *s;

    s = &pit->channels[0];
    /* the timer 0 is connected to an IRQ */
    s->irq_timer = qemu_new_timer_ns(vm_clock, pit_irq_timer, s);
    qdev_init_gpio_out(dev, &s->irq, 1);

    memory_region_init_io(&pit->ioports, OBJECT(pit), &pit_ioport_ops,
                          pit, "pit", 4);

    qdev_init_gpio_in(dev, pit_irq_control, 1);

    pc->parent_realize(dev, err);
}

static Property pit_properties[] = {
    DEFINE_PROP_HEX32("iobase", PITCommonState, iobase,  -1),
    DEFINE_PROP_END_OF_LIST(),
};

static void pit_class_initfn(ObjectClass *klass, void *data)
{
    PITClass *pc = PIT_CLASS(klass);
    PITCommonClass *k = PIT_COMMON_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    pc->parent_realize = dc->realize;
    dc->realize = pit_realizefn;
    k->set_channel_gate = pit_set_channel_gate;
    k->get_channel_info = pit_get_channel_info_common;
    k->post_load = pit_post_load;
    dc->reset = pit_reset;
    dc->props = pit_properties;
}

static const TypeInfo pit_info = {
    .name          = TYPE_I8254,
    .parent        = TYPE_PIT_COMMON,
    .instance_size = sizeof(PITCommonState),
    .class_init    = pit_class_initfn,
    .class_size    = sizeof(PITClass),
};

static void pit_register_types(void)
{
    type_register_static(&pit_info);
}

type_init(pit_register_types)
Commit	Line	Data
80cabfad FB	1	/*
80cabfad FB	2	* QEMU 8253/8254 interval timer emulation
5fafdf24	3	*
80cabfad	4	* Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24	5	*
80cabfad FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
83c9f4ca	24	#include "hw/hw.h"
0d09e41a PB	25	#include "hw/i386/pc.h"
0d09e41a PB	26	#include "hw/isa/isa.h"
1de7afc9	27	#include "qemu/timer.h"
0d09e41a PB	28	#include "hw/timer/i8254.h"
0d09e41a PB	29	#include "hw/timer/i8254_internal.h"
80cabfad	30
b0a21b53 FB	31	//#define DEBUG_PIT
b0a21b53 FB	32
ec844b96 FB	33	#define RW_STATE_LSB 1
	34	#define RW_STATE_MSB 2
	35	#define RW_STATE_WORD0 3
	36	#define RW_STATE_WORD1 4
80cabfad	37
a15d0912 AF	38	#define PIT_CLASS(class) OBJECT_CLASS_CHECK(PITClass, (class), TYPE_I8254)
	39	#define PIT_GET_CLASS(obj) OBJECT_GET_CLASS(PITClass, (obj), TYPE_I8254)
	40
	41	typedef struct PITClass {
	42	PITCommonClass parent_class;
	43
	44	DeviceRealize parent_realize;
	45	} PITClass;
	46
b0a21b53 FB	47	static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
b0a21b53 FB	48
80cabfad FB	49	static int pit_get_count(PITChannelState *s)
	50	{
	51	uint64_t d;
	52	int counter;
	53
74475455	54	d = muldiv64(qemu_get_clock_ns(vm_clock) - s->count_load_time, PIT_FREQ,
6ee093c9	55	get_ticks_per_sec());
80cabfad FB	56	switch(s->mode) {
	57	case 0:
	58	case 1:
	59	case 4:
	60	case 5:
	61	counter = (s->count - d) & 0xffff;
	62	break;
	63	case 3:
	64	/* XXX: may be incorrect for odd counts */
	65	counter = s->count - ((2 * d) % s->count);
	66	break;
	67	default:
	68	counter = s->count - (d % s->count);
	69	break;
	70	}
	71	return counter;
	72	}
	73
80cabfad	74	/* val must be 0 or 1 */
d11e859e JK	75	static void pit_set_channel_gate(PITCommonState s, PITChannelState sc,
d11e859e JK	76	int val)
80cabfad	77	{
d11e859e	78	switch (sc->mode) {
80cabfad FB	79	default:
	80	case 0:
	81	case 4:
	82	/* XXX: just disable/enable counting */
	83	break;
	84	case 1:
	85	case 5:
d11e859e	86	if (sc->gate < val) {
80cabfad	87	/* restart counting on rising edge */
d11e859e JK	88	sc->count_load_time = qemu_get_clock_ns(vm_clock);
d11e859e JK	89	pit_irq_timer_update(sc, sc->count_load_time);
80cabfad FB	90	}
	91	break;
	92	case 2:
	93	case 3:
d11e859e	94	if (sc->gate < val) {
80cabfad	95	/* restart counting on rising edge */
d11e859e JK	96	sc->count_load_time = qemu_get_clock_ns(vm_clock);
d11e859e JK	97	pit_irq_timer_update(sc, sc->count_load_time);
80cabfad FB	98	}
	99	/* XXX: disable/enable counting */
	100	break;
	101	}
d11e859e	102	sc->gate = val;
fd06c375 FB	103	}
fd06c375 FB	104
80cabfad FB	105	static inline void pit_load_count(PITChannelState *s, int val)
	106	{
	107	if (val == 0)
	108	val = 0x10000;
74475455	109	s->count_load_time = qemu_get_clock_ns(vm_clock);
80cabfad	110	s->count = val;
b0a21b53	111	pit_irq_timer_update(s, s->count_load_time);
80cabfad FB	112	}
80cabfad FB	113
ec844b96 FB	114	/* if already latched, do not latch again */
	115	static void pit_latch_count(PITChannelState *s)
	116	{
	117	if (!s->count_latched) {
	118	s->latched_count = pit_get_count(s);
	119	s->count_latched = s->rw_mode;
	120	}
	121	}
	122
0505bcde AG	123	static void pit_ioport_write(void *opaque, hwaddr addr,
0505bcde AG	124	uint64_t val, unsigned size)
80cabfad	125	{
d11e859e	126	PITCommonState *pit = opaque;
80cabfad FB	127	int channel, access;
	128	PITChannelState *s;
	129
	130	addr &= 3;
	131	if (addr == 3) {
	132	channel = val >> 6;
ec844b96 FB	133	if (channel == 3) {
	134	/* read back command */
	135	for(channel = 0; channel < 3; channel++) {
	136	s = &pit->channels[channel];
	137	if (val & (2 << channel)) {
	138	if (!(val & 0x20)) {
	139	pit_latch_count(s);
	140	}
	141	if (!(val & 0x10) && !s->status_latched) {
	142	/* status latch */
	143	/* XXX: add BCD and null count */
4aa5d285 JK	144	s->status =
	145	(pit_get_out(s,
	146	qemu_get_clock_ns(vm_clock)) << 7) \|
ec844b96 FB	147	(s->rw_mode << 4) \|
	148	(s->mode << 1) \|
	149	s->bcd;
	150	s->status_latched = 1;
	151	}
	152	}
	153	}
	154	} else {
	155	s = &pit->channels[channel];
	156	access = (val >> 4) & 3;
	157	if (access == 0) {
	158	pit_latch_count(s);
	159	} else {
	160	s->rw_mode = access;
	161	s->read_state = access;
	162	s->write_state = access;
	163
	164	s->mode = (val >> 1) & 7;
	165	s->bcd = val & 1;
	166	/* XXX: update irq timer ? */
	167	}
80cabfad FB	168	}
80cabfad FB	169	} else {
ec844b96 FB	170	s = &pit->channels[addr];
	171	switch(s->write_state) {
	172	default:
80cabfad FB	173	case RW_STATE_LSB:
	174	pit_load_count(s, val);
	175	break;
	176	case RW_STATE_MSB:
	177	pit_load_count(s, val << 8);
	178	break;
	179	case RW_STATE_WORD0:
ec844b96 FB	180	s->write_latch = val;
	181	s->write_state = RW_STATE_WORD1;
	182	break;
80cabfad	183	case RW_STATE_WORD1:
ec844b96 FB	184	pit_load_count(s, s->write_latch \| (val << 8));
ec844b96 FB	185	s->write_state = RW_STATE_WORD0;
80cabfad FB	186	break;
	187	}
	188	}
	189	}
	190
0505bcde AG	191	static uint64_t pit_ioport_read(void *opaque, hwaddr addr,
0505bcde AG	192	unsigned size)
80cabfad	193	{
d11e859e	194	PITCommonState *pit = opaque;
80cabfad FB	195	int ret, count;
80cabfad FB	196	PITChannelState *s;
3b46e624	197
80cabfad	198	addr &= 3;
ec844b96 FB	199	s = &pit->channels[addr];
	200	if (s->status_latched) {
	201	s->status_latched = 0;
	202	ret = s->status;
	203	} else if (s->count_latched) {
	204	switch(s->count_latched) {
	205	default:
	206	case RW_STATE_LSB:
	207	ret = s->latched_count & 0xff;
	208	s->count_latched = 0;
	209	break;
	210	case RW_STATE_MSB:
80cabfad	211	ret = s->latched_count >> 8;
ec844b96 FB	212	s->count_latched = 0;
	213	break;
	214	case RW_STATE_WORD0:
80cabfad	215	ret = s->latched_count & 0xff;
ec844b96 FB	216	s->count_latched = RW_STATE_MSB;
	217	break;
	218	}
	219	} else {
	220	switch(s->read_state) {
	221	default:
	222	case RW_STATE_LSB:
	223	count = pit_get_count(s);
	224	ret = count & 0xff;
	225	break;
	226	case RW_STATE_MSB:
	227	count = pit_get_count(s);
	228	ret = (count >> 8) & 0xff;
	229	break;
	230	case RW_STATE_WORD0:
	231	count = pit_get_count(s);
	232	ret = count & 0xff;
	233	s->read_state = RW_STATE_WORD1;
	234	break;
	235	case RW_STATE_WORD1:
	236	count = pit_get_count(s);
	237	ret = (count >> 8) & 0xff;
	238	s->read_state = RW_STATE_WORD0;
	239	break;
	240	}
80cabfad FB	241	}
	242	return ret;
	243	}
	244
b0a21b53 FB	245	static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
	246	{
	247	int64_t expire_time;
	248	int irq_level;
	249
ce967e2f	250	if (!s->irq_timer \|\| s->irq_disabled) {
b0a21b53	251	return;
ce967e2f	252	}
b0a21b53	253	expire_time = pit_get_next_transition_time(s, current_time);
4aa5d285	254	irq_level = pit_get_out(s, current_time);
d537cf6c	255	qemu_set_irq(s->irq, irq_level);
b0a21b53 FB	256	#ifdef DEBUG_PIT
b0a21b53 FB	257	printf("irq_level=%d next_delay=%f\n",
5fafdf24	258	irq_level,
6ee093c9	259	(double)(expire_time - current_time) / get_ticks_per_sec());
b0a21b53 FB	260	#endif
	261	s->next_transition_time = expire_time;
	262	if (expire_time != -1)
	263	qemu_mod_timer(s->irq_timer, expire_time);
	264	else
	265	qemu_del_timer(s->irq_timer);
	266	}
	267
	268	static void pit_irq_timer(void *opaque)
	269	{
	270	PITChannelState *s = opaque;
	271
	272	pit_irq_timer_update(s, s->next_transition_time);
	273	}
	274
d11e859e	275	static void pit_reset(DeviceState *dev)
b0a21b53	276	{
3afe7e14	277	PITCommonState *pit = PIT_COMMON(dev);
b0a21b53	278	PITChannelState *s;
b0a21b53	279
d11e859e	280	pit_reset_common(pit);
5122b431	281
d11e859e JK	282	s = &pit->channels[0];
	283	if (!s->irq_disabled) {
	284	qemu_mod_timer(s->irq_timer, s->next_transition_time);
80cabfad	285	}
d7d02e3c FB	286	}
d7d02e3c FB	287
ce967e2f JK	288	/* When HPET is operating in legacy mode, suppress the ignored timer IRQ,
	289	* reenable it when legacy mode is left again. */
	290	static void pit_irq_control(void *opaque, int n, int enable)
16b29ae1	291	{
d11e859e	292	PITCommonState *pit = opaque;
ce967e2f JK	293	PITChannelState *s = &pit->channels[0];
	294
	295	if (enable) {
	296	s->irq_disabled = 0;
	297	pit_irq_timer_update(s, qemu_get_clock_ns(vm_clock));
	298	} else {
	299	s->irq_disabled = 1;
	300	qemu_del_timer(s->irq_timer);
	301	}
16b29ae1 AL	302	}
16b29ae1 AL	303
60ea6aa8	304	static const MemoryRegionOps pit_ioport_ops = {
0505bcde AG	305	.read = pit_ioport_read,
	306	.write = pit_ioport_write,
	307	.impl = {
	308	.min_access_size = 1,
	309	.max_access_size = 1,
	310	},
	311	.endianness = DEVICE_LITTLE_ENDIAN,
60ea6aa8 RH	312	};
60ea6aa8 RH	313
3fbc1c0c JK	314	static void pit_post_load(PITCommonState *s)
	315	{
	316	PITChannelState *sc = &s->channels[0];
	317
	318	if (sc->next_transition_time != -1) {
	319	qemu_mod_timer(sc->irq_timer, sc->next_transition_time);
	320	} else {
	321	qemu_del_timer(sc->irq_timer);
	322	}
	323	}
	324
a15d0912	325	static void pit_realizefn(DeviceState dev, Error *err)
d7d02e3c	326	{
a15d0912 AF	327	PITCommonState *pit = PIT_COMMON(dev);
a15d0912 AF	328	PITClass *pc = PIT_GET_CLASS(dev);
d7d02e3c FB	329	PITChannelState *s;
	330
	331	s = &pit->channels[0];
	332	/* the timer 0 is connected to an IRQ */
74475455	333	s->irq_timer = qemu_new_timer_ns(vm_clock, pit_irq_timer, s);
a15d0912	334	qdev_init_gpio_out(dev, &s->irq, 1);
80cabfad	335
853dca12 PB	336	memory_region_init_io(&pit->ioports, OBJECT(pit), &pit_ioport_ops,
853dca12 PB	337	pit, "pit", 4);
ce967e2f	338
a15d0912	339	qdev_init_gpio_in(dev, pit_irq_control, 1);
ca22a3a3	340
a15d0912	341	pc->parent_realize(dev, err);
64d7e9a4 BS	342	}
64d7e9a4 BS	343
39bffca2	344	static Property pit_properties[] = {
d11e859e	345	DEFINE_PROP_HEX32("iobase", PITCommonState, iobase, -1),
39bffca2 AL	346	DEFINE_PROP_END_OF_LIST(),
	347	};
	348
8f04ee08 AL	349	static void pit_class_initfn(ObjectClass klass, void data)
8f04ee08 AL	350	{
a15d0912	351	PITClass *pc = PIT_CLASS(klass);
d11e859e	352	PITCommonClass *k = PIT_COMMON_CLASS(klass);
39bffca2	353	DeviceClass *dc = DEVICE_CLASS(klass);
d11e859e	354
a15d0912 AF	355	pc->parent_realize = dc->realize;
a15d0912 AF	356	dc->realize = pit_realizefn;
d11e859e JK	357	k->set_channel_gate = pit_set_channel_gate;
d11e859e JK	358	k->get_channel_info = pit_get_channel_info_common;
3fbc1c0c	359	k->post_load = pit_post_load;
39bffca2	360	dc->reset = pit_reset;
39bffca2	361	dc->props = pit_properties;
8f04ee08 AL	362	}
8f04ee08 AL	363
8c43a6f0	364	static const TypeInfo pit_info = {
3afe7e14	365	.name = TYPE_I8254,
d11e859e JK	366	.parent = TYPE_PIT_COMMON,
d11e859e JK	367	.instance_size = sizeof(PITCommonState),
39bffca2	368	.class_init = pit_class_initfn,
a15d0912	369	.class_size = sizeof(PITClass),
64d7e9a4 BS	370	};
64d7e9a4 BS	371
83f7d43a	372	static void pit_register_types(void)
64d7e9a4	373	{
39bffca2	374	type_register_static(&pit_info);
80cabfad	375	}
83f7d43a AF	376
83f7d43a AF	377	type_init(pit_register_types)