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78d6da97
FB		 1/*
2 * x86 CPU test
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
3a27ad0b 20#define _GNU_SOURCE
4d1135e4
FB		 21#include <stdlib.h>
22#include <stdio.h>
e3e86d56 23#include <string.h>
6dbad63e 24#include <inttypes.h>
4d1135e4 25#include <math.h>
3a27ad0b
FB		 26#include <signal.h>
27#include <setjmp.h>
070893f4 28#include <errno.h>
3a27ad0b
FB		 29#include <sys/ucontext.h>
30#include <sys/mman.h>
4d1135e4 31
776f2227 32#if !defined(__x86_64__)
acae4681 33#define TEST_VM86
776f2227
FB		 34#define TEST_SEGS
35#endif
3ff0631e 36//#define LINUX_VM86_IOPL_FIX
791c2261 37//#define TEST_P4_FLAGS
776f2227
FB		 38#if defined(__x86_64__)
39#define TEST_SSE
40#define TEST_CMOV 1
41#define TEST_FCOMI 1
42#else
43#define TEST_CMOV 0
44#define TEST_FCOMI 0
45#endif
46
47#if defined(__x86_64__)
48#define FMT64X "%016lx"
49#define FMTLX "%016lx"
50#define X86_64_ONLY(x) x
51#else
52#define FMT64X "%016llx"
53#define FMTLX "%08lx"
54#define X86_64_ONLY(x)
55#endif
56
57#ifdef TEST_VM86
58#include <asm/vm86.h>
59#endif
5dd9488c 60
4d1135e4
FB		 61#define xglue(x, y) x ## y
62#define glue(x, y) xglue(x, y)
63#define stringify(s) tostring(s)
64#define tostring(s) #s
65
66#define CC_C 0x0001
67#define CC_P 0x0004
68#define CC_A 0x0010
69#define CC_Z 0x0040
70#define CC_S 0x0080
71#define CC_O 0x0800
72
776f2227 73#define __init_call __attribute__ ((unused,__section__ ("initcall")))
4d1135e4 74
4b74fe1f
FB		 75#define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)
76
776f2227
FB		 77#if defined(__x86_64__)
78static inline long i2l(long v)
79{
80 return v | ((v ^ 0xabcd) << 32);
81}
82#else
83static inline long i2l(long v)
84{
85 return v;
86}
87#endif
88
4d1135e4
FB		 89#define OP add
90#include "test-i386.h"
91
92#define OP sub
93#include "test-i386.h"
94
95#define OP xor
96#include "test-i386.h"
97
98#define OP and
99#include "test-i386.h"
100
101#define OP or
102#include "test-i386.h"
103
104#define OP cmp
105#include "test-i386.h"
106
107#define OP adc
108#define OP_CC
109#include "test-i386.h"
110
111#define OP sbb
112#define OP_CC
113#include "test-i386.h"
114
115#define OP inc
116#define OP_CC
117#define OP1
118#include "test-i386.h"
119
120#define OP dec
121#define OP_CC
122#define OP1
123#include "test-i386.h"
124
125#define OP neg
126#define OP_CC
127#define OP1
128#include "test-i386.h"
129
130#define OP not
131#define OP_CC
132#define OP1
133#include "test-i386.h"
134
4b74fe1f
FB		 135#undef CC_MASK
136#define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O)
137
379ca80d
FB		 138#define OP shl
139#include "test-i386-shift.h"
140
141#define OP shr
142#include "test-i386-shift.h"
143
144#define OP sar
145#include "test-i386-shift.h"
146
147#define OP rol
148#include "test-i386-shift.h"
149
150#define OP ror
151#include "test-i386-shift.h"
152
153#define OP rcr
154#define OP_CC
155#include "test-i386-shift.h"
156
157#define OP rcl
158#define OP_CC
159#include "test-i386-shift.h"
160
d57c4e01
FB		 161#define OP shld
162#define OP_SHIFTD
163#define OP_NOBYTE
164#include "test-i386-shift.h"
165
166#define OP shrd
167#define OP_SHIFTD
168#define OP_NOBYTE
169#include "test-i386-shift.h"
170
171/* XXX: should be more precise ? */
172#undef CC_MASK
173#define CC_MASK (CC_C)
174
175#define OP bt
176#define OP_NOBYTE
177#include "test-i386-shift.h"
178
179#define OP bts
180#define OP_NOBYTE
181#include "test-i386-shift.h"
182
183#define OP btr
184#define OP_NOBYTE
185#include "test-i386-shift.h"
186
187#define OP btc
188#define OP_NOBYTE
189#include "test-i386-shift.h"
379ca80d 190
4d1135e4 191/* lea test (modrm support) */
776f2227
FB		 192#define TEST_LEAQ(STR)\
193{\
194 asm("lea " STR ", %0"\
195 : "=r" (res)\
196 : "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
197 printf("lea %s = " FMTLX "\n", STR, res);\
198}
199
4d1135e4
FB		 200#define TEST_LEA(STR)\
201{\
776f2227 202 asm("lea " STR ", %0"\
4d1135e4
FB		 203 : "=r" (res)\
204 : "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
776f2227 205 printf("lea %s = " FMTLX "\n", STR, res);\
4d1135e4
FB		 206}
207
208#define TEST_LEA16(STR)\
209{\
210 asm(".code16 ; .byte 0x67 ; leal " STR ", %0 ; .code32"\
211 : "=wq" (res)\
212 : "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
776f2227 213 printf("lea %s = %08lx\n", STR, res);\
4d1135e4
FB		 214}
215
216
217void test_lea(void)
218{
776f2227
FB		 219 long eax, ebx, ecx, edx, esi, edi, res;
220 eax = i2l(0x0001);
221 ebx = i2l(0x0002);
222 ecx = i2l(0x0004);
223 edx = i2l(0x0008);
224 esi = i2l(0x0010);
225 edi = i2l(0x0020);
4d1135e4
FB		 226
227 TEST_LEA("0x4000");
228
229 TEST_LEA("(%%eax)");
230 TEST_LEA("(%%ebx)");
231 TEST_LEA("(%%ecx)");
232 TEST_LEA("(%%edx)");
233 TEST_LEA("(%%esi)");
234 TEST_LEA("(%%edi)");
235
236 TEST_LEA("0x40(%%eax)");
237 TEST_LEA("0x40(%%ebx)");
238 TEST_LEA("0x40(%%ecx)");
239 TEST_LEA("0x40(%%edx)");
240 TEST_LEA("0x40(%%esi)");
241 TEST_LEA("0x40(%%edi)");
242
243 TEST_LEA("0x4000(%%eax)");
244 TEST_LEA("0x4000(%%ebx)");
245 TEST_LEA("0x4000(%%ecx)");
246 TEST_LEA("0x4000(%%edx)");
247 TEST_LEA("0x4000(%%esi)");
248 TEST_LEA("0x4000(%%edi)");
249
250 TEST_LEA("(%%eax, %%ecx)");
251 TEST_LEA("(%%ebx, %%edx)");
252 TEST_LEA("(%%ecx, %%ecx)");
253 TEST_LEA("(%%edx, %%ecx)");
254 TEST_LEA("(%%esi, %%ecx)");
255 TEST_LEA("(%%edi, %%ecx)");
256
257 TEST_LEA("0x40(%%eax, %%ecx)");
258 TEST_LEA("0x4000(%%ebx, %%edx)");
259
260 TEST_LEA("(%%ecx, %%ecx, 2)");
261 TEST_LEA("(%%edx, %%ecx, 4)");
262 TEST_LEA("(%%esi, %%ecx, 8)");
263
264 TEST_LEA("(,%%eax, 2)");
265 TEST_LEA("(,%%ebx, 4)");
266 TEST_LEA("(,%%ecx, 8)");
267
268 TEST_LEA("0x40(,%%eax, 2)");
269 TEST_LEA("0x40(,%%ebx, 4)");
270 TEST_LEA("0x40(,%%ecx, 8)");
271
272
273 TEST_LEA("-10(%%ecx, %%ecx, 2)");
274 TEST_LEA("-10(%%edx, %%ecx, 4)");
275 TEST_LEA("-10(%%esi, %%ecx, 8)");
276
277 TEST_LEA("0x4000(%%ecx, %%ecx, 2)");
278 TEST_LEA("0x4000(%%edx, %%ecx, 4)");
279 TEST_LEA("0x4000(%%esi, %%ecx, 8)");
280
776f2227
FB		 281#if defined(__x86_64__)
282 TEST_LEAQ("0x4000");
283 TEST_LEAQ("0x4000(%%rip)");
284
285 TEST_LEAQ("(%%rax)");
286 TEST_LEAQ("(%%rbx)");
287 TEST_LEAQ("(%%rcx)");
288 TEST_LEAQ("(%%rdx)");
289 TEST_LEAQ("(%%rsi)");
290 TEST_LEAQ("(%%rdi)");
291
292 TEST_LEAQ("0x40(%%rax)");
293 TEST_LEAQ("0x40(%%rbx)");
294 TEST_LEAQ("0x40(%%rcx)");
295 TEST_LEAQ("0x40(%%rdx)");
296 TEST_LEAQ("0x40(%%rsi)");
297 TEST_LEAQ("0x40(%%rdi)");
298
299 TEST_LEAQ("0x4000(%%rax)");
300 TEST_LEAQ("0x4000(%%rbx)");
301 TEST_LEAQ("0x4000(%%rcx)");
302 TEST_LEAQ("0x4000(%%rdx)");
303 TEST_LEAQ("0x4000(%%rsi)");
304 TEST_LEAQ("0x4000(%%rdi)");
305
306 TEST_LEAQ("(%%rax, %%rcx)");
307 TEST_LEAQ("(%%rbx, %%rdx)");
308 TEST_LEAQ("(%%rcx, %%rcx)");
309 TEST_LEAQ("(%%rdx, %%rcx)");
310 TEST_LEAQ("(%%rsi, %%rcx)");
311 TEST_LEAQ("(%%rdi, %%rcx)");
312
313 TEST_LEAQ("0x40(%%rax, %%rcx)");
314 TEST_LEAQ("0x4000(%%rbx, %%rdx)");
315
316 TEST_LEAQ("(%%rcx, %%rcx, 2)");
317 TEST_LEAQ("(%%rdx, %%rcx, 4)");
318 TEST_LEAQ("(%%rsi, %%rcx, 8)");
319
320 TEST_LEAQ("(,%%rax, 2)");
321 TEST_LEAQ("(,%%rbx, 4)");
322 TEST_LEAQ("(,%%rcx, 8)");
323
324 TEST_LEAQ("0x40(,%%rax, 2)");
325 TEST_LEAQ("0x40(,%%rbx, 4)");
326 TEST_LEAQ("0x40(,%%rcx, 8)");
327
328
329 TEST_LEAQ("-10(%%rcx, %%rcx, 2)");
330 TEST_LEAQ("-10(%%rdx, %%rcx, 4)");
331 TEST_LEAQ("-10(%%rsi, %%rcx, 8)");
332
333 TEST_LEAQ("0x4000(%%rcx, %%rcx, 2)");
334 TEST_LEAQ("0x4000(%%rdx, %%rcx, 4)");
335 TEST_LEAQ("0x4000(%%rsi, %%rcx, 8)");
336#else
4d1135e4
FB		 337 /* limited 16 bit addressing test */
338 TEST_LEA16("0x4000");
339 TEST_LEA16("(%%bx)");
340 TEST_LEA16("(%%si)");
341 TEST_LEA16("(%%di)");
342 TEST_LEA16("0x40(%%bx)");
343 TEST_LEA16("0x40(%%si)");
344 TEST_LEA16("0x40(%%di)");
345 TEST_LEA16("0x4000(%%bx)");
346 TEST_LEA16("0x4000(%%si)");
347 TEST_LEA16("(%%bx,%%si)");
348 TEST_LEA16("(%%bx,%%di)");
349 TEST_LEA16("0x40(%%bx,%%si)");
350 TEST_LEA16("0x40(%%bx,%%di)");
351 TEST_LEA16("0x4000(%%bx,%%si)");
352 TEST_LEA16("0x4000(%%bx,%%di)");
776f2227 353#endif
4d1135e4
FB		 354}
355
356#define TEST_JCC(JCC, v1, v2)\
357{\
5dd9488c 358 int res;\
4d1135e4
FB		 359 asm("movl $1, %0\n\t"\
360 "cmpl %2, %1\n\t"\
5dd9488c 361 "j" JCC " 1f\n\t"\
4d1135e4
FB		 362 "movl $0, %0\n\t"\
363 "1:\n\t"\
364 : "=r" (res)\
365 : "r" (v1), "r" (v2));\
5dd9488c
FB		 366 printf("%-10s %d\n", "j" JCC, res);\
367\
368 asm("movl $0, %0\n\t"\
369 "cmpl %2, %1\n\t"\
370 "set" JCC " %b0\n\t"\
371 : "=r" (res)\
372 : "r" (v1), "r" (v2));\
373 printf("%-10s %d\n", "set" JCC, res);\
374 if (TEST_CMOV) {\
776f2227
FB		 375 long val = i2l(1);\
376 long res = i2l(0x12345678);\
377X86_64_ONLY(\
378 asm("cmpl %2, %1\n\t"\
379 "cmov" JCC "q %3, %0\n\t"\
5dd9488c 380 : "=r" (res)\
776f2227
FB		 381 : "r" (v1), "r" (v2), "m" (val), "0" (res));\
382 printf("%-10s R=" FMTLX "\n", "cmov" JCC "l", res);)\
383 asm("cmpl %2, %1\n\t"\
384 "cmov" JCC "l %k3, %k0\n\t"\
385 : "=r" (res)\
386 : "r" (v1), "r" (v2), "m" (val), "0" (res));\
387 printf("%-10s R=" FMTLX "\n", "cmov" JCC "l", res);\
388 asm("cmpl %2, %1\n\t"\
5dd9488c
FB		 389 "cmov" JCC "w %w3, %w0\n\t"\
390 : "=r" (res)\
776f2227
FB		 391 : "r" (v1), "r" (v2), "r" (1), "0" (res));\
392 printf("%-10s R=" FMTLX "\n", "cmov" JCC "w", res);\
5dd9488c 393 } \
4d1135e4
FB		 394}
395
396/* various jump tests */
397void test_jcc(void)
398{
5dd9488c
FB		 399 TEST_JCC("ne", 1, 1);
400 TEST_JCC("ne", 1, 0);
4d1135e4 401
5dd9488c
FB		 402 TEST_JCC("e", 1, 1);
403 TEST_JCC("e", 1, 0);
4d1135e4 404
5dd9488c
FB		 405 TEST_JCC("l", 1, 1);
406 TEST_JCC("l", 1, 0);
407 TEST_JCC("l", 1, -1);
4d1135e4 408
5dd9488c
FB		 409 TEST_JCC("le", 1, 1);
410 TEST_JCC("le", 1, 0);
411 TEST_JCC("le", 1, -1);
4d1135e4 412
5dd9488c
FB		 413 TEST_JCC("ge", 1, 1);
414 TEST_JCC("ge", 1, 0);
415 TEST_JCC("ge", -1, 1);
4d1135e4 416
5dd9488c
FB		 417 TEST_JCC("g", 1, 1);
418 TEST_JCC("g", 1, 0);
419 TEST_JCC("g", 1, -1);
4d1135e4 420
5dd9488c
FB		 421 TEST_JCC("b", 1, 1);
422 TEST_JCC("b", 1, 0);
423 TEST_JCC("b", 1, -1);
4d1135e4 424
5dd9488c
FB		 425 TEST_JCC("be", 1, 1);
426 TEST_JCC("be", 1, 0);
427 TEST_JCC("be", 1, -1);
4d1135e4 428
5dd9488c
FB		 429 TEST_JCC("ae", 1, 1);
430 TEST_JCC("ae", 1, 0);
431 TEST_JCC("ae", 1, -1);
4d1135e4 432
5dd9488c
FB		 433 TEST_JCC("a", 1, 1);
434 TEST_JCC("a", 1, 0);
435 TEST_JCC("a", 1, -1);
4d1135e4
FB		 436
437
5dd9488c
FB		 438 TEST_JCC("p", 1, 1);
439 TEST_JCC("p", 1, 0);
4d1135e4 440
5dd9488c
FB		 441 TEST_JCC("np", 1, 1);
442 TEST_JCC("np", 1, 0);
4d1135e4 443
5dd9488c
FB		 444 TEST_JCC("o", 0x7fffffff, 0);
445 TEST_JCC("o", 0x7fffffff, -1);
4d1135e4 446
5dd9488c
FB		 447 TEST_JCC("no", 0x7fffffff, 0);
448 TEST_JCC("no", 0x7fffffff, -1);
4d1135e4 449
5dd9488c
FB		 450 TEST_JCC("s", 0, 1);
451 TEST_JCC("s", 0, -1);
452 TEST_JCC("s", 0, 0);
4d1135e4 453
5dd9488c
FB		 454 TEST_JCC("ns", 0, 1);
455 TEST_JCC("ns", 0, -1);
456 TEST_JCC("ns", 0, 0);
4d1135e4
FB		 457}
458
4b74fe1f 459#undef CC_MASK
791c2261
FB		 460#ifdef TEST_P4_FLAGS
461#define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)
462#else
4b74fe1f 463#define CC_MASK (CC_O | CC_C)
791c2261 464#endif
4b74fe1f
FB		 465
466#define OP mul
467#include "test-i386-muldiv.h"
468
469#define OP imul
470#include "test-i386-muldiv.h"
471
776f2227 472void test_imulw2(long op0, long op1)
4b74fe1f 473{
776f2227 474 long res, s1, s0, flags;
4b74fe1f
FB		 475 s0 = op0;
476 s1 = op1;
477 res = s0;
478 flags = 0;
acae4681 479 asm volatile ("push %4\n\t"
4b74fe1f
FB		 480 "popf\n\t"
481 "imulw %w2, %w0\n\t"
482 "pushf\n\t"
776f2227 483 "pop %1\n\t"
4b74fe1f
FB		 484 : "=q" (res), "=g" (flags)
485 : "q" (s1), "0" (res), "1" (flags));
776f2227 486 printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
4b74fe1f
FB		 487 "imulw", s0, s1, res, flags & CC_MASK);
488}
489
776f2227 490void test_imull2(long op0, long op1)
4b74fe1f 491{
776f2227 492 long res, s1, s0, flags;
4b74fe1f
FB		 493 s0 = op0;
494 s1 = op1;
495 res = s0;
496 flags = 0;
acae4681 497 asm volatile ("push %4\n\t"
4b74fe1f 498 "popf\n\t"
776f2227 499 "imull %k2, %k0\n\t"
4b74fe1f 500 "pushf\n\t"
776f2227 501 "pop %1\n\t"
4b74fe1f
FB		 502 : "=q" (res), "=g" (flags)
503 : "q" (s1), "0" (res), "1" (flags));
776f2227 504 printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
4b74fe1f
FB		 505 "imull", s0, s1, res, flags & CC_MASK);
506}
507
776f2227
FB		 508#if defined(__x86_64__)
509void test_imulq2(long op0, long op1)
510{
511 long res, s1, s0, flags;
512 s0 = op0;
513 s1 = op1;
514 res = s0;
515 flags = 0;
516 asm volatile ("push %4\n\t"
517 "popf\n\t"
518 "imulq %2, %0\n\t"
519 "pushf\n\t"
520 "pop %1\n\t"
521 : "=q" (res), "=g" (flags)
522 : "q" (s1), "0" (res), "1" (flags));
523 printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
524 "imulq", s0, s1, res, flags & CC_MASK);
525}
526#endif
527
528#define TEST_IMUL_IM(size, rsize, op0, op1)\
b5075d29 529{\
776f2227 530 long res, flags, s1;\
b5075d29
FB		 531 flags = 0;\
532 res = 0;\
776f2227 533 s1 = op1;\
acae4681 534 asm volatile ("push %3\n\t"\
b5075d29 535 "popf\n\t"\
776f2227 536 "imul" size " $" #op0 ", %" rsize "2, %" rsize "0\n\t" \
b5075d29 537 "pushf\n\t"\
776f2227 538 "pop %1\n\t"\
b5075d29 539 : "=r" (res), "=g" (flags)\
776f2227
FB		 540 : "r" (s1), "1" (flags), "0" (res));\
541 printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",\
542 "imul" size " im", (long)op0, (long)op1, res, flags & CC_MASK);\
b5075d29
FB		 543}
544
545
791c2261
FB		 546#undef CC_MASK
547#define CC_MASK (0)
548
549#define OP div
550#include "test-i386-muldiv.h"
551
552#define OP idiv
553#include "test-i386-muldiv.h"
554
4b74fe1f
FB		 555void test_mul(void)
556{
557 test_imulb(0x1234561d, 4);
558 test_imulb(3, -4);
559 test_imulb(0x80, 0x80);
560 test_imulb(0x10, 0x10);
561
562 test_imulw(0, 0x1234001d, 45);
563 test_imulw(0, 23, -45);
564 test_imulw(0, 0x8000, 0x8000);
565 test_imulw(0, 0x100, 0x100);
566
567 test_imull(0, 0x1234001d, 45);
568 test_imull(0, 23, -45);
569 test_imull(0, 0x80000000, 0x80000000);
570 test_imull(0, 0x10000, 0x10000);
571
572 test_mulb(0x1234561d, 4);
573 test_mulb(3, -4);
574 test_mulb(0x80, 0x80);
575 test_mulb(0x10, 0x10);
576
577 test_mulw(0, 0x1234001d, 45);
578 test_mulw(0, 23, -45);
579 test_mulw(0, 0x8000, 0x8000);
580 test_mulw(0, 0x100, 0x100);
581
582 test_mull(0, 0x1234001d, 45);
583 test_mull(0, 23, -45);
584 test_mull(0, 0x80000000, 0x80000000);
585 test_mull(0, 0x10000, 0x10000);
586
587 test_imulw2(0x1234001d, 45);
588 test_imulw2(23, -45);
589 test_imulw2(0x8000, 0x8000);
590 test_imulw2(0x100, 0x100);
591
592 test_imull2(0x1234001d, 45);
593 test_imull2(23, -45);
594 test_imull2(0x80000000, 0x80000000);
595 test_imull2(0x10000, 0x10000);
596
b5075d29
FB		 597 TEST_IMUL_IM("w", "w", 45, 0x1234);
598 TEST_IMUL_IM("w", "w", -45, 23);
599 TEST_IMUL_IM("w", "w", 0x8000, 0x80000000);
600 TEST_IMUL_IM("w", "w", 0x7fff, 0x1000);
601
776f2227
FB		 602 TEST_IMUL_IM("l", "k", 45, 0x1234);
603 TEST_IMUL_IM("l", "k", -45, 23);
604 TEST_IMUL_IM("l", "k", 0x8000, 0x80000000);
605 TEST_IMUL_IM("l", "k", 0x7fff, 0x1000);
b5075d29 606
4b74fe1f
FB		 607 test_idivb(0x12341678, 0x127e);
608 test_idivb(0x43210123, -5);
609 test_idivb(0x12340004, -1);
610
611 test_idivw(0, 0x12345678, 12347);
612 test_idivw(0, -23223, -45);
613 test_idivw(0, 0x12348000, -1);
614 test_idivw(0x12343, 0x12345678, 0x81238567);
615
616 test_idivl(0, 0x12345678, 12347);
617 test_idivl(0, -233223, -45);
618 test_idivl(0, 0x80000000, -1);
619 test_idivl(0x12343, 0x12345678, 0x81234567);
620
621 test_divb(0x12341678, 0x127e);
622 test_divb(0x43210123, -5);
623 test_divb(0x12340004, -1);
624
625 test_divw(0, 0x12345678, 12347);
626 test_divw(0, -23223, -45);
627 test_divw(0, 0x12348000, -1);
628 test_divw(0x12343, 0x12345678, 0x81238567);
629
630 test_divl(0, 0x12345678, 12347);
631 test_divl(0, -233223, -45);
632 test_divl(0, 0x80000000, -1);
633 test_divl(0x12343, 0x12345678, 0x81234567);
776f2227
FB		 634
635#if defined(__x86_64__)
636 test_imulq(0, 0x1234001d1234001d, 45);
637 test_imulq(0, 23, -45);
638 test_imulq(0, 0x8000000000000000, 0x8000000000000000);
639 test_imulq(0, 0x100000000, 0x100000000);
640
641 test_mulq(0, 0x1234001d1234001d, 45);
642 test_mulq(0, 23, -45);
643 test_mulq(0, 0x8000000000000000, 0x8000000000000000);
644 test_mulq(0, 0x100000000, 0x100000000);
645
646 test_imulq2(0x1234001d1234001d, 45);
647 test_imulq2(23, -45);
648 test_imulq2(0x8000000000000000, 0x8000000000000000);
649 test_imulq2(0x100000000, 0x100000000);
650
651 TEST_IMUL_IM("q", "", 45, 0x12341234);
652 TEST_IMUL_IM("q", "", -45, 23);
653 TEST_IMUL_IM("q", "", 0x8000, 0x8000000000000000);
654 TEST_IMUL_IM("q", "", 0x7fff, 0x10000000);
655
656 test_idivq(0, 0x12345678abcdef, 12347);
657 test_idivq(0, -233223, -45);
658 test_idivq(0, 0x8000000000000000, -1);
659 test_idivq(0x12343, 0x12345678, 0x81234567);
660
661 test_divq(0, 0x12345678abcdef, 12347);
662 test_divq(0, -233223, -45);
663 test_divq(0, 0x8000000000000000, -1);
664 test_divq(0x12343, 0x12345678, 0x81234567);
665#endif
4b74fe1f
FB		 666}
667
9d8e9c09
FB		 668#define TEST_BSX(op, size, op0)\
669{\
776f2227 670 long res, val, resz;\
9d8e9c09 671 val = op0;\
776f2227
FB		 672 asm("xor %1, %1\n"\
673 "mov $0x12345678, %0\n"\
7f5e1452 674 #op " %" size "2, %" size "0 ; setz %b1" \
9d8e9c09
FB		 675 : "=r" (res), "=q" (resz)\
676 : "g" (val));\
776f2227 677 printf("%-10s A=" FMTLX " R=" FMTLX " %ld\n", #op, val, res, resz);\
9d8e9c09
FB		 678}
679
680void test_bsx(void)
681{
682 TEST_BSX(bsrw, "w", 0);
683 TEST_BSX(bsrw, "w", 0x12340128);
9d8e9c09
FB		 684 TEST_BSX(bsfw, "w", 0);
685 TEST_BSX(bsfw, "w", 0x12340128);
776f2227
FB		 686 TEST_BSX(bsrl, "k", 0);
687 TEST_BSX(bsrl, "k", 0x00340128);
688 TEST_BSX(bsfl, "k", 0);
689 TEST_BSX(bsfl, "k", 0x00340128);
690#if defined(__x86_64__)
691 TEST_BSX(bsrq, "", 0);
692 TEST_BSX(bsrq, "", 0x003401281234);
693 TEST_BSX(bsfq, "", 0);
694 TEST_BSX(bsfq, "", 0x003401281234);
695#endif
9d8e9c09
FB		 696}
697
55480af8
FB		 698/**********************************************/
699
9d8e9c09
FB		 700void test_fops(double a, double b)
701{
702 printf("a=%f b=%f a+b=%f\n", a, b, a + b);
703 printf("a=%f b=%f a-b=%f\n", a, b, a - b);
704 printf("a=%f b=%f a*b=%f\n", a, b, a * b);
705 printf("a=%f b=%f a/b=%f\n", a, b, a / b);
706 printf("a=%f b=%f fmod(a, b)=%f\n", a, b, fmod(a, b));
707 printf("a=%f sqrt(a)=%f\n", a, sqrt(a));
708 printf("a=%f sin(a)=%f\n", a, sin(a));
709 printf("a=%f cos(a)=%f\n", a, cos(a));
710 printf("a=%f tan(a)=%f\n", a, tan(a));
711 printf("a=%f log(a)=%f\n", a, log(a));
712 printf("a=%f exp(a)=%f\n", a, exp(a));
713 printf("a=%f b=%f atan2(a, b)=%f\n", a, b, atan2(a, b));
714 /* just to test some op combining */
715 printf("a=%f asin(sin(a))=%f\n", a, asin(sin(a)));
716 printf("a=%f acos(cos(a))=%f\n", a, acos(cos(a)));
717 printf("a=%f atan(tan(a))=%f\n", a, atan(tan(a)));
718
719}
720
721void test_fcmp(double a, double b)
722{
723 printf("(%f<%f)=%d\n",
724 a, b, a < b);
725 printf("(%f<=%f)=%d\n",
726 a, b, a <= b);
727 printf("(%f==%f)=%d\n",
728 a, b, a == b);
729 printf("(%f>%f)=%d\n",
730 a, b, a > b);
731 printf("(%f<=%f)=%d\n",
732 a, b, a >= b);
03bfca94 733 if (TEST_FCOMI) {
776f2227 734 long eflags;
03bfca94
FB		 735 /* test f(u)comi instruction */
736 asm("fcomi %2, %1\n"
737 "pushf\n"
738 "pop %0\n"
739 : "=r" (eflags)
740 : "t" (a), "u" (b));
776f2227 741 printf("fcomi(%f %f)=%08lx\n", a, b, eflags & (CC_Z | CC_P | CC_C));
03bfca94 742 }
9d8e9c09
FB		 743}
744
745void test_fcvt(double a)
746{
747 float fa;
748 long double la;
ea768640
FB		 749 int16_t fpuc;
750 int i;
751 int64_t lla;
752 int ia;
753 int16_t wa;
754 double ra;
9d8e9c09
FB		 755
756 fa = a;
757 la = a;
758 printf("(float)%f = %f\n", a, fa);
759 printf("(long double)%f = %Lf\n", a, la);
776f2227
FB		 760 printf("a=" FMT64X "\n", *(uint64_t *)&a);
761 printf("la=" FMT64X " %04x\n", *(uint64_t *)&la,
c5e9815d 762 *(unsigned short *)((char *)(&la) + 8));
ea768640
FB		 763
764 /* test all roundings */
765 asm volatile ("fstcw %0" : "=m" (fpuc));
766 for(i=0;i<4;i++) {
767 asm volatile ("fldcw %0" : : "m" ((fpuc & ~0x0c00) | (i << 10)));
768 asm volatile ("fist %0" : "=m" (wa) : "t" (a));
769 asm volatile ("fistl %0" : "=m" (ia) : "t" (a));
770 asm volatile ("fistpll %0" : "=m" (lla) : "t" (a) : "st");
771 asm volatile ("frndint ; fstl %0" : "=m" (ra) : "t" (a));
772 asm volatile ("fldcw %0" : : "m" (fpuc));
773 printf("(short)a = %d\n", wa);
774 printf("(int)a = %d\n", ia);
776f2227 775 printf("(int64_t)a = " FMT64X "\n", lla);
ea768640
FB		 776 printf("rint(a) = %f\n", ra);
777 }
9d8e9c09
FB		 778}
779
780#define TEST(N) \
781 asm("fld" #N : "=t" (a)); \
782 printf("fld" #N "= %f\n", a);
783
784void test_fconst(void)
785{
786 double a;
787 TEST(1);
788 TEST(l2t);
789 TEST(l2e);
790 TEST(pi);
791 TEST(lg2);
792 TEST(ln2);
793 TEST(z);
794}
795
c5e9815d
FB		 796void test_fbcd(double a)
797{
798 unsigned short bcd[5];
799 double b;
800
801 asm("fbstp %0" : "=m" (bcd[0]) : "t" (a) : "st");
802 asm("fbld %1" : "=t" (b) : "m" (bcd[0]));
803 printf("a=%f bcd=%04x%04x%04x%04x%04x b=%f\n",
804 a, bcd[4], bcd[3], bcd[2], bcd[1], bcd[0], b);
805}
806
6b2b6112 807#define TEST_ENV(env, save, restore)\
03bfca94
FB		 808{\
809 memset((env), 0xaa, sizeof(*(env)));\
6b2b6112
FB		 810 for(i=0;i<5;i++)\
811 asm volatile ("fldl %0" : : "m" (dtab[i]));\
085339a1
FB		 812 asm volatile (save " %0\n" : : "m" (*(env)));\
813 asm volatile (restore " %0\n": : "m" (*(env)));\
6b2b6112
FB		 814 for(i=0;i<5;i++)\
815 asm volatile ("fstpl %0" : "=m" (rtab[i]));\
816 for(i=0;i<5;i++)\
817 printf("res[%d]=%f\n", i, rtab[i]);\
03bfca94
FB		 818 printf("fpuc=%04x fpus=%04x fptag=%04x\n",\
819 (env)->fpuc,\
820 (env)->fpus & 0xff00,\
821 (env)->fptag);\
03bfca94
FB		 822}
823
824void test_fenv(void)
825{
826 struct __attribute__((packed)) {
827 uint16_t fpuc;
828 uint16_t dummy1;
829 uint16_t fpus;
830 uint16_t dummy2;
831 uint16_t fptag;
832 uint16_t dummy3;
833 uint32_t ignored[4];
834 long double fpregs[8];
835 } float_env32;
836 struct __attribute__((packed)) {
837 uint16_t fpuc;
838 uint16_t fpus;
839 uint16_t fptag;
840 uint16_t ignored[4];
841 long double fpregs[8];
842 } float_env16;
6b2b6112
FB		 843 double dtab[8];
844 double rtab[8];
845 int i;
846
847 for(i=0;i<8;i++)
848 dtab[i] = i + 1;
03bfca94 849
6b2b6112
FB		 850 TEST_ENV(&float_env16, "data16 fnstenv", "data16 fldenv");
851 TEST_ENV(&float_env16, "data16 fnsave", "data16 frstor");
852 TEST_ENV(&float_env32, "fnstenv", "fldenv");
853 TEST_ENV(&float_env32, "fnsave", "frstor");
665656a9
FB		 854
855 /* test for ffree */
856 for(i=0;i<5;i++)
857 asm volatile ("fldl %0" : : "m" (dtab[i]));
858 asm volatile("ffree %st(2)");
859 asm volatile ("fnstenv %0\n" : : "m" (float_env32));
860 asm volatile ("fninit");
861 printf("fptag=%04x\n", float_env32.fptag);
03bfca94
FB		 862}
863
75175024
FB		 864
865#define TEST_FCMOV(a, b, eflags, CC)\
866{\
867 double res;\
868 asm("push %3\n"\
869 "popf\n"\
870 "fcmov" CC " %2, %0\n"\
871 : "=t" (res)\
872 : "0" (a), "u" (b), "g" (eflags));\
776f2227
FB		 873 printf("fcmov%s eflags=0x%04lx-> %f\n", \
874 CC, (long)eflags, res);\
75175024
FB		 875}
876
877void test_fcmov(void)
878{
879 double a, b;
776f2227 880 long eflags, i;
75175024
FB		 881
882 a = 1.0;
883 b = 2.0;
884 for(i = 0; i < 4; i++) {
885 eflags = 0;
886 if (i & 1)
887 eflags |= CC_C;
888 if (i & 2)
889 eflags |= CC_Z;
890 TEST_FCMOV(a, b, eflags, "b");
891 TEST_FCMOV(a, b, eflags, "e");
892 TEST_FCMOV(a, b, eflags, "be");
893 TEST_FCMOV(a, b, eflags, "nb");
894 TEST_FCMOV(a, b, eflags, "ne");
895 TEST_FCMOV(a, b, eflags, "nbe");
896 }
897 TEST_FCMOV(a, b, 0, "u");
9cdf757f
FB		 898 TEST_FCMOV(a, b, CC_P, "u");
899 TEST_FCMOV(a, b, 0, "nu");
75175024
FB		 900 TEST_FCMOV(a, b, CC_P, "nu");
901}
902
9d8e9c09
FB		 903void test_floats(void)
904{
905 test_fops(2, 3);
906 test_fops(1.4, -5);
907 test_fcmp(2, -1);
908 test_fcmp(2, 2);
909 test_fcmp(2, 3);
ea768640
FB		 910 test_fcvt(0.5);
911 test_fcvt(-0.5);
9d8e9c09
FB		 912 test_fcvt(1.0/7.0);
913 test_fcvt(-1.0/9.0);
ea768640
FB		 914 test_fcvt(32768);
915 test_fcvt(-1e20);
9d8e9c09 916 test_fconst();
c5e9815d
FB		 917 test_fbcd(1234567890123456);
918 test_fbcd(-123451234567890);
03bfca94 919 test_fenv();
75175024
FB		 920 if (TEST_CMOV) {
921 test_fcmov();
922 }
9d8e9c09 923}
4b74fe1f 924
55480af8 925/**********************************************/
776f2227 926#if !defined(__x86_64__)
55480af8
FB		 927
928#define TEST_BCD(op, op0, cc_in, cc_mask)\
929{\
930 int res, flags;\
931 res = op0;\
932 flags = cc_in;\
933 asm ("push %3\n\t"\
934 "popf\n\t"\
935 #op "\n\t"\
936 "pushf\n\t"\
776f2227 937 "pop %1\n\t"\
55480af8
FB		 938 : "=a" (res), "=g" (flags)\
939 : "0" (res), "1" (flags));\
940 printf("%-10s A=%08x R=%08x CCIN=%04x CC=%04x\n",\
941 #op, op0, res, cc_in, flags & cc_mask);\
942}
943
944void test_bcd(void)
945{
946 TEST_BCD(daa, 0x12340503, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
947 TEST_BCD(daa, 0x12340506, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
948 TEST_BCD(daa, 0x12340507, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
949 TEST_BCD(daa, 0x12340559, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
950 TEST_BCD(daa, 0x12340560, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
951 TEST_BCD(daa, 0x1234059f, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
952 TEST_BCD(daa, 0x123405a0, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
953 TEST_BCD(daa, 0x12340503, 0, (CC_C | CC_P | CC_Z | CC_S | CC_A));
954 TEST_BCD(daa, 0x12340506, 0, (CC_C | CC_P | CC_Z | CC_S | CC_A));
955 TEST_BCD(daa, 0x12340503, CC_C, (CC_C | CC_P | CC_Z | CC_S | CC_A));
956 TEST_BCD(daa, 0x12340506, CC_C, (CC_C | CC_P | CC_Z | CC_S | CC_A));
957 TEST_BCD(daa, 0x12340503, CC_C | CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
958 TEST_BCD(daa, 0x12340506, CC_C | CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
959
960 TEST_BCD(das, 0x12340503, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
961 TEST_BCD(das, 0x12340506, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
962 TEST_BCD(das, 0x12340507, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
963 TEST_BCD(das, 0x12340559, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
964 TEST_BCD(das, 0x12340560, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
965 TEST_BCD(das, 0x1234059f, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
966 TEST_BCD(das, 0x123405a0, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
967 TEST_BCD(das, 0x12340503, 0, (CC_C | CC_P | CC_Z | CC_S | CC_A));
968 TEST_BCD(das, 0x12340506, 0, (CC_C | CC_P | CC_Z | CC_S | CC_A));
969 TEST_BCD(das, 0x12340503, CC_C, (CC_C | CC_P | CC_Z | CC_S | CC_A));
970 TEST_BCD(das, 0x12340506, CC_C, (CC_C | CC_P | CC_Z | CC_S | CC_A));
971 TEST_BCD(das, 0x12340503, CC_C | CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
972 TEST_BCD(das, 0x12340506, CC_C | CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_A));
973
974 TEST_BCD(aaa, 0x12340205, CC_A, (CC_C | CC_A));
975 TEST_BCD(aaa, 0x12340306, CC_A, (CC_C | CC_A));
976 TEST_BCD(aaa, 0x1234040a, CC_A, (CC_C | CC_A));
977 TEST_BCD(aaa, 0x123405fa, CC_A, (CC_C | CC_A));
978 TEST_BCD(aaa, 0x12340205, 0, (CC_C | CC_A));
979 TEST_BCD(aaa, 0x12340306, 0, (CC_C | CC_A));
980 TEST_BCD(aaa, 0x1234040a, 0, (CC_C | CC_A));
981 TEST_BCD(aaa, 0x123405fa, 0, (CC_C | CC_A));
982
983 TEST_BCD(aas, 0x12340205, CC_A, (CC_C | CC_A));
984 TEST_BCD(aas, 0x12340306, CC_A, (CC_C | CC_A));
985 TEST_BCD(aas, 0x1234040a, CC_A, (CC_C | CC_A));
986 TEST_BCD(aas, 0x123405fa, CC_A, (CC_C | CC_A));
987 TEST_BCD(aas, 0x12340205, 0, (CC_C | CC_A));
988 TEST_BCD(aas, 0x12340306, 0, (CC_C | CC_A));
989 TEST_BCD(aas, 0x1234040a, 0, (CC_C | CC_A));
990 TEST_BCD(aas, 0x123405fa, 0, (CC_C | CC_A));
991
992 TEST_BCD(aam, 0x12340547, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A));
993 TEST_BCD(aad, 0x12340407, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A));
994}
776f2227 995#endif
55480af8 996
e5918247
FB		 997#define TEST_XCHG(op, size, opconst)\
998{\
776f2227
FB		 999 long op0, op1;\
1000 op0 = i2l(0x12345678);\
1001 op1 = i2l(0xfbca7654);\
e5918247
FB		 1002 asm(#op " %" size "0, %" size "1" \
1003 : "=q" (op0), opconst (op1) \
1004 : "0" (op0), "1" (op1));\
776f2227 1005 printf("%-10s A=" FMTLX " B=" FMTLX "\n",\
e5918247
FB		 1006 #op, op0, op1);\
1007}
1008
1009#define TEST_CMPXCHG(op, size, opconst, eax)\
1010{\
776f2227
FB		 1011 long op0, op1, op2;\
1012 op0 = i2l(0x12345678);\
1013 op1 = i2l(0xfbca7654);\
1014 op2 = i2l(eax);\
e5918247
FB		 1015 asm(#op " %" size "0, %" size "1" \
1016 : "=q" (op0), opconst (op1) \
776f2227
FB		 1017 : "0" (op0), "1" (op1), "a" (op2));\
1018 printf("%-10s EAX=" FMTLX " A=" FMTLX " C=" FMTLX "\n",\
1019 #op, op2, op0, op1);\
e5918247
FB		 1020}
1021
1022void test_xchg(void)
1023{
776f2227
FB		 1024#if defined(__x86_64__)
1025 TEST_XCHG(xchgq, "", "=q");
1026#endif
1027 TEST_XCHG(xchgl, "k", "=q");
e5918247
FB		 1028 TEST_XCHG(xchgw, "w", "=q");
1029 TEST_XCHG(xchgb, "b", "=q");
1030
776f2227
FB		 1031#if defined(__x86_64__)
1032 TEST_XCHG(xchgq, "", "=m");
1033#endif
1034 TEST_XCHG(xchgl, "k", "=m");
e5918247
FB		 1035 TEST_XCHG(xchgw, "w", "=m");
1036 TEST_XCHG(xchgb, "b", "=m");
1037
776f2227
FB		 1038#if defined(__x86_64__)
1039 TEST_XCHG(xaddq, "", "=q");
1040#endif
1041 TEST_XCHG(xaddl, "k", "=q");
e5918247
FB		 1042 TEST_XCHG(xaddw, "w", "=q");
1043 TEST_XCHG(xaddb, "b", "=q");
1044
d575b78a
FB		 1045 {
1046 int res;
1047 res = 0x12345678;
1048 asm("xaddl %1, %0" : "=r" (res) : "0" (res));
1049 printf("xaddl same res=%08x\n", res);
1050 }
1051
776f2227
FB		 1052#if defined(__x86_64__)
1053 TEST_XCHG(xaddq, "", "=m");
1054#endif
1055 TEST_XCHG(xaddl, "k", "=m");
e5918247
FB		 1056 TEST_XCHG(xaddw, "w", "=m");
1057 TEST_XCHG(xaddb, "b", "=m");
1058
776f2227
FB		 1059#if defined(__x86_64__)
1060 TEST_CMPXCHG(cmpxchgq, "", "=q", 0xfbca7654);
1061#endif
1062 TEST_CMPXCHG(cmpxchgl, "k", "=q", 0xfbca7654);
e5918247
FB		 1063 TEST_CMPXCHG(cmpxchgw, "w", "=q", 0xfbca7654);
1064 TEST_CMPXCHG(cmpxchgb, "b", "=q", 0xfbca7654);
1065
776f2227
FB		 1066#if defined(__x86_64__)
1067 TEST_CMPXCHG(cmpxchgq, "", "=q", 0xfffefdfc);
1068#endif
1069 TEST_CMPXCHG(cmpxchgl, "k", "=q", 0xfffefdfc);
e5918247
FB		 1070 TEST_CMPXCHG(cmpxchgw, "w", "=q", 0xfffefdfc);
1071 TEST_CMPXCHG(cmpxchgb, "b", "=q", 0xfffefdfc);
1072
776f2227
FB		 1073#if defined(__x86_64__)
1074 TEST_CMPXCHG(cmpxchgq, "", "=m", 0xfbca7654);
1075#endif
1076 TEST_CMPXCHG(cmpxchgl, "k", "=m", 0xfbca7654);
e5918247
FB		 1077 TEST_CMPXCHG(cmpxchgw, "w", "=m", 0xfbca7654);
1078 TEST_CMPXCHG(cmpxchgb, "b", "=m", 0xfbca7654);
1079
776f2227
FB		 1080#if defined(__x86_64__)
1081 TEST_CMPXCHG(cmpxchgq, "", "=m", 0xfffefdfc);
1082#endif
1083 TEST_CMPXCHG(cmpxchgl, "k", "=m", 0xfffefdfc);
e5918247
FB		 1084 TEST_CMPXCHG(cmpxchgw, "w", "=m", 0xfffefdfc);
1085 TEST_CMPXCHG(cmpxchgb, "b", "=m", 0xfffefdfc);
d575b78a
FB		 1086
1087 {
1088 uint64_t op0, op1, op2;
776f2227 1089 long i, eflags;
d575b78a
FB		 1090
1091 for(i = 0; i < 2; i++) {
1092 op0 = 0x123456789abcd;
1093 if (i == 0)
1094 op1 = 0xfbca765423456;
1095 else
1096 op1 = op0;
1097 op2 = 0x6532432432434;
1098 asm("cmpxchg8b %1\n"
1099 "pushf\n"
776f2227 1100 "pop %2\n"
d575b78a
FB		 1101 : "=A" (op0), "=m" (op1), "=g" (eflags)
1102 : "0" (op0), "m" (op1), "b" ((int)op2), "c" ((int)(op2 >> 32)));
776f2227 1103 printf("cmpxchg8b: op0=" FMT64X " op1=" FMT64X " CC=%02lx\n",
d575b78a
FB		 1104 op0, op1, eflags & CC_Z);
1105 }
1106 }
e5918247
FB		 1107}
1108
776f2227 1109#ifdef TEST_SEGS
6dbad63e
FB		 1110/**********************************************/
1111/* segmentation tests */
1112
1113#include <asm/ldt.h>
1114#include <linux/unistd.h>
73bdea19 1115#include <linux/version.h>
6dbad63e
FB		 1116
1117_syscall3(int, modify_ldt, int, func, void *, ptr, unsigned long, bytecount)
1118
73bdea19
FB		 1119#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 66)
1120#define modify_ldt_ldt_s user_desc
1121#endif
1122
776f2227
FB		 1123#define MK_SEL(n) (((n) << 3) | 7)
1124
6dbad63e
FB		 1125uint8_t seg_data1[4096];
1126uint8_t seg_data2[4096];
1127
288426fe
FB		 1128#define TEST_LR(op, size, seg, mask)\
1129{\
1130 int res, res2;\
1131 res = 0x12345678;\
1132 asm (op " %" size "2, %" size "0\n" \
1133 "movl $0, %1\n"\
1134 "jnz 1f\n"\
1135 "movl $1, %1\n"\
1136 "1:\n"\
1137 : "=r" (res), "=r" (res2) : "m" (seg), "0" (res));\
1138 printf(op ": Z=%d %08x\n", res2, res & ~(mask));\
1139}
1140
6dbad63e
FB		 1141/* NOTE: we use Linux modify_ldt syscall */
1142void test_segs(void)
1143{
1144 struct modify_ldt_ldt_s ldt;
1145 long long ldt_table[3];
04369ff2 1146 int res, res2;
6dbad63e 1147 char tmp;
e1d4294a
FB		 1148 struct {
1149 uint32_t offset;
1150 uint16_t seg;
1151 } __attribute__((packed)) segoff;
6dbad63e
FB		 1152
1153 ldt.entry_number = 1;
1154 ldt.base_addr = (unsigned long)&seg_data1;
1155 ldt.limit = (sizeof(seg_data1) + 0xfff) >> 12;
1156 ldt.seg_32bit = 1;
1157 ldt.contents = MODIFY_LDT_CONTENTS_DATA;
1158 ldt.read_exec_only = 0;
1159 ldt.limit_in_pages = 1;
1160 ldt.seg_not_present = 0;
1161 ldt.useable = 1;
1162 modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
1163
1164 ldt.entry_number = 2;
1165 ldt.base_addr = (unsigned long)&seg_data2;
1166 ldt.limit = (sizeof(seg_data2) + 0xfff) >> 12;
1167 ldt.seg_32bit = 1;
1168 ldt.contents = MODIFY_LDT_CONTENTS_DATA;
1169 ldt.read_exec_only = 0;
1170 ldt.limit_in_pages = 1;
1171 ldt.seg_not_present = 0;
1172 ldt.useable = 1;
1173 modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
1174
1175 modify_ldt(0, &ldt_table, sizeof(ldt_table)); /* read ldt entries */
04369ff2
FB		 1176#if 0
1177 {
1178 int i;
1179 for(i=0;i<3;i++)
1180 printf("%d: %016Lx\n", i, ldt_table[i]);
1181 }
1182#endif
6dbad63e
FB		 1183 /* do some tests with fs or gs */
1184 asm volatile ("movl %0, %%fs" : : "r" (MK_SEL(1)));
6dbad63e
FB		 1185
1186 seg_data1[1] = 0xaa;
1187 seg_data2[1] = 0x55;
1188
1189 asm volatile ("fs movzbl 0x1, %0" : "=r" (res));
1190 printf("FS[1] = %02x\n", res);
1191
070893f4
FB		 1192 asm volatile ("pushl %%gs\n"
1193 "movl %1, %%gs\n"
1194 "gs movzbl 0x1, %0\n"
1195 "popl %%gs\n"
1196 : "=r" (res)
1197 : "r" (MK_SEL(2)));
6dbad63e
FB		 1198 printf("GS[1] = %02x\n", res);
1199
1200 /* tests with ds/ss (implicit segment case) */
1201 tmp = 0xa5;
1202 asm volatile ("pushl %%ebp\n\t"
1203 "pushl %%ds\n\t"
1204 "movl %2, %%ds\n\t"
1205 "movl %3, %%ebp\n\t"
1206 "movzbl 0x1, %0\n\t"
1207 "movzbl (%%ebp), %1\n\t"
1208 "popl %%ds\n\t"
1209 "popl %%ebp\n\t"
1210 : "=r" (res), "=r" (res2)
1211 : "r" (MK_SEL(1)), "r" (&tmp));
1212 printf("DS[1] = %02x\n", res);
1213 printf("SS[tmp] = %02x\n", res2);
e1d4294a
FB		 1214
1215 segoff.seg = MK_SEL(2);
1216 segoff.offset = 0xabcdef12;
1217 asm volatile("lfs %2, %0\n\t"
1218 "movl %%fs, %1\n\t"
1219 : "=r" (res), "=g" (res2)
1220 : "m" (segoff));
1221 printf("FS:reg = %04x:%08x\n", res2, res);
288426fe
FB		 1222
1223 TEST_LR("larw", "w", MK_SEL(2), 0x0100);
1224 TEST_LR("larl", "", MK_SEL(2), 0x0100);
1225 TEST_LR("lslw", "w", MK_SEL(2), 0);
1226 TEST_LR("lsll", "", MK_SEL(2), 0);
1227
1228 TEST_LR("larw", "w", 0xfff8, 0);
1229 TEST_LR("larl", "", 0xfff8, 0);
1230 TEST_LR("lslw", "w", 0xfff8, 0);
1231 TEST_LR("lsll", "", 0xfff8, 0);
6dbad63e 1232}
55480af8 1233
e5918247
FB		 1234/* 16 bit code test */
1235extern char code16_start, code16_end;
1236extern char code16_func1;
1237extern char code16_func2;
1238extern char code16_func3;
a300e691 1239
e5918247 1240void test_code16(void)
1a9353d2 1241{
e5918247
FB		 1242 struct modify_ldt_ldt_s ldt;
1243 int res, res2;
a300e691 1244
e5918247
FB		 1245 /* build a code segment */
1246 ldt.entry_number = 1;
1247 ldt.base_addr = (unsigned long)&code16_start;
1248 ldt.limit = &code16_end - &code16_start;
1249 ldt.seg_32bit = 0;
1250 ldt.contents = MODIFY_LDT_CONTENTS_CODE;
1251 ldt.read_exec_only = 0;
1252 ldt.limit_in_pages = 0;
1253 ldt.seg_not_present = 0;
1254 ldt.useable = 1;
1255 modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
a300e691 1256
e5918247
FB		 1257 /* call the first function */
1258 asm volatile ("lcall %1, %2"
1259 : "=a" (res)
1260 : "i" (MK_SEL(1)), "i" (&code16_func1): "memory", "cc");
1261 printf("func1() = 0x%08x\n", res);
1262 asm volatile ("lcall %2, %3"
1263 : "=a" (res), "=c" (res2)
1264 : "i" (MK_SEL(1)), "i" (&code16_func2): "memory", "cc");
1265 printf("func2() = 0x%08x spdec=%d\n", res, res2);
1266 asm volatile ("lcall %1, %2"
1267 : "=a" (res)
1268 : "i" (MK_SEL(1)), "i" (&code16_func3): "memory", "cc");
1269 printf("func3() = 0x%08x\n", res);
1a9353d2 1270}
776f2227 1271#endif
1a9353d2 1272
dd3587f3
FB		 1273extern char func_lret32;
1274extern char func_iret32;
1275
e1d4294a
FB		 1276void test_misc(void)
1277{
1278 char table[256];
776f2227 1279 long res, i;
e1d4294a
FB		 1280
1281 for(i=0;i<256;i++) table[i] = 256 - i;
1282 res = 0x12345678;
1283 asm ("xlat" : "=a" (res) : "b" (table), "0" (res));
776f2227 1284 printf("xlat: EAX=" FMTLX "\n", res);
dd3587f3 1285
776f2227
FB		 1286#if !defined(__x86_64__)
1287 asm volatile ("push %%cs ; call %1"
dd3587f3
FB		 1288 : "=a" (res)
1289 : "m" (func_lret32): "memory", "cc");
776f2227 1290 printf("func_lret32=" FMTLX "\n", res);
dd3587f3 1291
776f2227 1292 asm volatile ("pushf ; push %%cs ; call %1"
dd3587f3
FB		 1293 : "=a" (res)
1294 : "m" (func_iret32): "memory", "cc");
776f2227
FB		 1295 printf("func_iret32=" FMTLX "\n", res);
1296#endif
dd3587f3 1297
776f2227
FB		 1298#if defined(__x86_64__)
1299 /* specific popl test */
1300 asm volatile ("push $12345432 ; push $0x9abcdef ; pop (%%rsp) ; pop %0"
1301 : "=g" (res));
1302 printf("popl esp=" FMTLX "\n", res);
1303#else
dd3587f3
FB		 1304 /* specific popl test */
1305 asm volatile ("pushl $12345432 ; pushl $0x9abcdef ; popl (%%esp) ; popl %0"
1306 : "=g" (res));
776f2227 1307 printf("popl esp=" FMTLX "\n", res);
b2b5fb22
FB		 1308
1309 /* specific popw test */
1310 asm volatile ("pushl $12345432 ; pushl $0x9abcdef ; popw (%%esp) ; addl $2, %%esp ; popl %0"
1311 : "=g" (res));
776f2227
FB		 1312 printf("popw esp=" FMTLX "\n", res);
1313#endif
e1d4294a
FB		 1314}
1315
1316uint8_t str_buffer[4096];
1317
1318#define TEST_STRING1(OP, size, DF, REP)\
1319{\
776f2227 1320 long esi, edi, eax, ecx, eflags;\
e1d4294a
FB		 1321\
1322 esi = (long)(str_buffer + sizeof(str_buffer) / 2);\
1323 edi = (long)(str_buffer + sizeof(str_buffer) / 2) + 16;\
776f2227 1324 eax = i2l(0x12345678);\
e1d4294a
FB		 1325 ecx = 17;\
1326\
776f2227 1327 asm volatile ("push $0\n\t"\
e1d4294a
FB		 1328 "popf\n\t"\
1329 DF "\n\t"\
1330 REP #OP size "\n\t"\
1331 "cld\n\t"\
1332 "pushf\n\t"\
776f2227 1333 "pop %4\n\t"\
e1d4294a
FB		 1334 : "=S" (esi), "=D" (edi), "=a" (eax), "=c" (ecx), "=g" (eflags)\
1335 : "0" (esi), "1" (edi), "2" (eax), "3" (ecx));\
776f2227 1336 printf("%-10s ESI=" FMTLX " EDI=" FMTLX " EAX=" FMTLX " ECX=" FMTLX " EFL=%04x\n",\
e1d4294a 1337 REP #OP size, esi, edi, eax, ecx,\
776f2227 1338 (int)(eflags & (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)));\
e1d4294a
FB		 1339}
1340
1341#define TEST_STRING(OP, REP)\
1342 TEST_STRING1(OP, "b", "", REP);\
1343 TEST_STRING1(OP, "w", "", REP);\
1344 TEST_STRING1(OP, "l", "", REP);\
776f2227 1345 X86_64_ONLY(TEST_STRING1(OP, "q", "", REP));\
e1d4294a
FB		 1346 TEST_STRING1(OP, "b", "std", REP);\
1347 TEST_STRING1(OP, "w", "std", REP);\
776f2227
FB		 1348 TEST_STRING1(OP, "l", "std", REP);\
1349 X86_64_ONLY(TEST_STRING1(OP, "q", "std", REP))
e1d4294a
FB		 1350
1351void test_string(void)
1352{
1353 int i;
1354 for(i = 0;i < sizeof(str_buffer); i++)
1355 str_buffer[i] = i + 0x56;
1356 TEST_STRING(stos, "");
1357 TEST_STRING(stos, "rep ");
1358 TEST_STRING(lods, ""); /* to verify stos */
1359 TEST_STRING(lods, "rep ");
1360 TEST_STRING(movs, "");
1361 TEST_STRING(movs, "rep ");
1362 TEST_STRING(lods, ""); /* to verify stos */
1363
1364 /* XXX: better tests */
1365 TEST_STRING(scas, "");
1366 TEST_STRING(scas, "repz ");
1367 TEST_STRING(scas, "repnz ");
1368 TEST_STRING(cmps, "");
1369 TEST_STRING(cmps, "repz ");
1370 TEST_STRING(cmps, "repnz ");
1371}
e5918247 1372
776f2227 1373#ifdef TEST_VM86
3a27ad0b
FB		 1374/* VM86 test */
1375
1376static inline void set_bit(uint8_t *a, unsigned int bit)
1377{
1378 a[bit / 8] |= (1 << (bit % 8));
1379}
1380
1381static inline uint8_t *seg_to_linear(unsigned int seg, unsigned int reg)
1382{
1383 return (uint8_t *)((seg << 4) + (reg & 0xffff));
1384}
1385
1386static inline void pushw(struct vm86_regs *r, int val)
1387{
1388 r->esp = (r->esp & ~0xffff) | ((r->esp - 2) & 0xffff);
1389 *(uint16_t *)seg_to_linear(r->ss, r->esp) = val;
1390}
1391
1392#undef __syscall_return
1393#define __syscall_return(type, res) \
1394do { \
1395 return (type) (res); \
1396} while (0)
1397
1398_syscall2(int, vm86, int, func, struct vm86plus_struct *, v86)
1399
1400extern char vm86_code_start;
1401extern char vm86_code_end;
1402
1403#define VM86_CODE_CS 0x100
1404#define VM86_CODE_IP 0x100
1405
1406void test_vm86(void)
1407{
1408 struct vm86plus_struct ctx;
1409 struct vm86_regs *r;
1410 uint8_t *vm86_mem;
1411 int seg, ret;
1412
1413 vm86_mem = mmap((void *)0x00000000, 0x110000,
1414 PROT_WRITE | PROT_READ | PROT_EXEC,
1415 MAP_FIXED | MAP_ANON | MAP_PRIVATE, -1, 0);
1416 if (vm86_mem == MAP_FAILED) {
1417 printf("ERROR: could not map vm86 memory");
1418 return;
1419 }
1420 memset(&ctx, 0, sizeof(ctx));
1421
1422 /* init basic registers */
1423 r = &ctx.regs;
1424 r->eip = VM86_CODE_IP;
1425 r->esp = 0xfffe;
1426 seg = VM86_CODE_CS;
1427 r->cs = seg;
1428 r->ss = seg;
1429 r->ds = seg;
1430 r->es = seg;
1431 r->fs = seg;
1432 r->gs = seg;
1433 r->eflags = VIF_MASK;
1434
1435 /* move code to proper address. We use the same layout as a .com
1436 dos program. */
1437 memcpy(vm86_mem + (VM86_CODE_CS << 4) + VM86_CODE_IP,
1438 &vm86_code_start, &vm86_code_end - &vm86_code_start);
1439
1440 /* mark int 0x21 as being emulated */
1441 set_bit((uint8_t *)&ctx.int_revectored, 0x21);
1442
1443 for(;;) {
1444 ret = vm86(VM86_ENTER, &ctx);
1445 switch(VM86_TYPE(ret)) {
1446 case VM86_INTx:
1447 {
3ff0631e 1448 int int_num, ah, v;
3a27ad0b
FB		 1449
1450 int_num = VM86_ARG(ret);
1451 if (int_num != 0x21)
1452 goto unknown_int;
1453 ah = (r->eax >> 8) & 0xff;
1454 switch(ah) {
1455 case 0x00: /* exit */
1456 goto the_end;
1457 case 0x02: /* write char */
1458 {
1459 uint8_t c = r->edx;
1460 putchar(c);
1461 }
1462 break;
1463 case 0x09: /* write string */
1464 {
1465 uint8_t c, *ptr;
1466 ptr = seg_to_linear(r->ds, r->edx);
1467 for(;;) {
1468 c = *ptr++;
1469 if (c == '$')
1470 break;
1471 putchar(c);
1472 }
1473 r->eax = (r->eax & ~0xff) | '$';
1474 }
1475 break;
3ff0631e
FB		 1476 case 0xff: /* extension: write eflags number in edx */
1477 v = (int)r->edx;
1478#ifndef LINUX_VM86_IOPL_FIX
1479 v &= ~0x3000;
1480#endif
1481 printf("%08x\n", v);
3a27ad0b
FB		 1482 break;
1483 default:
1484 unknown_int:
1485 printf("unsupported int 0x%02x\n", int_num);
1486 goto the_end;
1487 }
1488 }
1489 break;
1490 case VM86_SIGNAL:
1491 /* a signal came, we just ignore that */
1492 break;
1493 case VM86_STI:
1494 break;
1495 default:
1496 printf("ERROR: unhandled vm86 return code (0x%x)\n", ret);
1497 goto the_end;
1498 }
1499 }
1500 the_end:
1501 printf("VM86 end\n");
1502 munmap(vm86_mem, 0x110000);
1503}
776f2227 1504#endif
3a27ad0b
FB		 1505
1506/* exception tests */
776f2227 1507#if defined(__i386__) && !defined(REG_EAX)
3a27ad0b
FB		 1508#define REG_EAX EAX
1509#define REG_EBX EBX
1510#define REG_ECX ECX
1511#define REG_EDX EDX
1512#define REG_ESI ESI
1513#define REG_EDI EDI
1514#define REG_EBP EBP
1515#define REG_ESP ESP
1516#define REG_EIP EIP
1517#define REG_EFL EFL
1518#define REG_TRAPNO TRAPNO
1519#define REG_ERR ERR
1520#endif
1521
776f2227
FB		 1522#if defined(__x86_64__)
1523#define REG_EIP REG_RIP
1524#endif
1525
3a27ad0b 1526jmp_buf jmp_env;
3a27ad0b
FB		 1527int v1;
1528int tab[2];
1529
1530void sig_handler(int sig, siginfo_t *info, void *puc)
1531{
1532 struct ucontext *uc = puc;
1533
1534 printf("si_signo=%d si_errno=%d si_code=%d",
1535 info->si_signo, info->si_errno, info->si_code);
e3b32540
FB		 1536 printf(" si_addr=0x%08lx",
1537 (unsigned long)info->si_addr);
3a27ad0b
FB		 1538 printf("\n");
1539
776f2227
FB		 1540 printf("trapno=" FMTLX " err=" FMTLX,
1541 (long)uc->uc_mcontext.gregs[REG_TRAPNO],
1542 (long)uc->uc_mcontext.gregs[REG_ERR]);
1543 printf(" EIP=" FMTLX, (long)uc->uc_mcontext.gregs[REG_EIP]);
3a27ad0b
FB		 1544 printf("\n");
1545 longjmp(jmp_env, 1);
1546}
1547
1548void test_exceptions(void)
1549{
1550 struct sigaction act;
1551 volatile int val;
1552
1553 act.sa_sigaction = sig_handler;
1554 sigemptyset(&act.sa_mask);
776f2227 1555 act.sa_flags = SA_SIGINFO | SA_NODEFER;
3a27ad0b
FB		 1556 sigaction(SIGFPE, &act, NULL);
1557 sigaction(SIGILL, &act, NULL);
1558 sigaction(SIGSEGV, &act, NULL);
e3b32540 1559 sigaction(SIGBUS, &act, NULL);
3a27ad0b
FB		 1560 sigaction(SIGTRAP, &act, NULL);
1561
1562 /* test division by zero reporting */
e3b32540 1563 printf("DIVZ exception:\n");
3a27ad0b
FB		 1564 if (setjmp(jmp_env) == 0) {
1565 /* now divide by zero */
1566 v1 = 0;
1567 v1 = 2 / v1;
1568 }
1569
776f2227 1570#if !defined(__x86_64__)
e3b32540 1571 printf("BOUND exception:\n");
3a27ad0b
FB		 1572 if (setjmp(jmp_env) == 0) {
1573 /* bound exception */
1574 tab[0] = 1;
1575 tab[1] = 10;
e82d8ade 1576 asm volatile ("bound %0, %1" : : "r" (11), "m" (tab[0]));
3a27ad0b 1577 }
776f2227 1578#endif
3a27ad0b 1579
776f2227 1580#ifdef TEST_SEGS
e3b32540
FB		 1581 printf("segment exceptions:\n");
1582 if (setjmp(jmp_env) == 0) {
1583 /* load an invalid segment */
1584 asm volatile ("movl %0, %%fs" : : "r" ((0x1234 << 3) | 1));
1585 }
1586 if (setjmp(jmp_env) == 0) {
1587 /* null data segment is valid */
1588 asm volatile ("movl %0, %%fs" : : "r" (3));
1589 /* null stack segment */
1590 asm volatile ("movl %0, %%ss" : : "r" (3));
1591 }
1592
776f2227
FB		 1593 {
1594 struct modify_ldt_ldt_s ldt;
1595 ldt.entry_number = 1;
1596 ldt.base_addr = (unsigned long)&seg_data1;
1597 ldt.limit = (sizeof(seg_data1) + 0xfff) >> 12;
1598 ldt.seg_32bit = 1;
1599 ldt.contents = MODIFY_LDT_CONTENTS_DATA;
1600 ldt.read_exec_only = 0;
1601 ldt.limit_in_pages = 1;
1602 ldt.seg_not_present = 1;
1603 ldt.useable = 1;
1604 modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
1605
1606 if (setjmp(jmp_env) == 0) {
1607 /* segment not present */
1608 asm volatile ("movl %0, %%fs" : : "r" (MK_SEL(1)));
1609 }
e3b32540 1610 }
776f2227 1611#endif
e3b32540 1612
3a27ad0b 1613 /* test SEGV reporting */
e3b32540 1614 printf("PF exception:\n");
3a27ad0b 1615 if (setjmp(jmp_env) == 0) {
e3b32540 1616 val = 1;
ede28208
FB		 1617 /* we add a nop to test a weird PC retrieval case */
1618 asm volatile ("nop");
3a27ad0b
FB		 1619 /* now store in an invalid address */
1620 *(char *)0x1234 = 1;
1621 }
1622
1623 /* test SEGV reporting */
e3b32540 1624 printf("PF exception:\n");
3a27ad0b 1625 if (setjmp(jmp_env) == 0) {
e3b32540 1626 val = 1;
3a27ad0b
FB		 1627 /* read from an invalid address */
1628 v1 = *(char *)0x1234;
1629 }
1630
3a27ad0b
FB		 1631 /* test illegal instruction reporting */
1632 printf("UD2 exception:\n");
1633 if (setjmp(jmp_env) == 0) {
1634 /* now execute an invalid instruction */
1635 asm volatile("ud2");
1636 }
4120b61d
FB		 1637 printf("lock nop exception:\n");
1638 if (setjmp(jmp_env) == 0) {
1639 /* now execute an invalid instruction */
1640 asm volatile("lock nop");
1641 }
3a27ad0b
FB		 1642
1643 printf("INT exception:\n");
1644 if (setjmp(jmp_env) == 0) {
1645 asm volatile ("int $0xfd");
1646 }
e3b32540
FB		 1647 if (setjmp(jmp_env) == 0) {
1648 asm volatile ("int $0x01");
1649 }
1650 if (setjmp(jmp_env) == 0) {
1651 asm volatile (".byte 0xcd, 0x03");
1652 }
1653 if (setjmp(jmp_env) == 0) {
1654 asm volatile ("int $0x04");
1655 }
1656 if (setjmp(jmp_env) == 0) {
1657 asm volatile ("int $0x05");
1658 }
3a27ad0b
FB		 1659
1660 printf("INT3 exception:\n");
1661 if (setjmp(jmp_env) == 0) {
1662 asm volatile ("int3");
1663 }
1664
1665 printf("CLI exception:\n");
1666 if (setjmp(jmp_env) == 0) {
1667 asm volatile ("cli");
1668 }
1669
1670 printf("STI exception:\n");
1671 if (setjmp(jmp_env) == 0) {
1672 asm volatile ("cli");
1673 }
1674
776f2227 1675#if !defined(__x86_64__)
3a27ad0b
FB		 1676 printf("INTO exception:\n");
1677 if (setjmp(jmp_env) == 0) {
1678 /* overflow exception */
1679 asm volatile ("addl $1, %0 ; into" : : "r" (0x7fffffff));
1680 }
776f2227 1681#endif
3a27ad0b
FB		 1682
1683 printf("OUTB exception:\n");
1684 if (setjmp(jmp_env) == 0) {
1685 asm volatile ("outb %%al, %%dx" : : "d" (0x4321), "a" (0));
1686 }
1687
1688 printf("INB exception:\n");
1689 if (setjmp(jmp_env) == 0) {
1690 asm volatile ("inb %%dx, %%al" : "=a" (val) : "d" (0x4321));
1691 }
1692
1693 printf("REP OUTSB exception:\n");
1694 if (setjmp(jmp_env) == 0) {
1695 asm volatile ("rep outsb" : : "d" (0x4321), "S" (tab), "c" (1));
1696 }
1697
1698 printf("REP INSB exception:\n");
1699 if (setjmp(jmp_env) == 0) {
1700 asm volatile ("rep insb" : : "d" (0x4321), "D" (tab), "c" (1));
1701 }
1702
1703 printf("HLT exception:\n");
1704 if (setjmp(jmp_env) == 0) {
1705 asm volatile ("hlt");
1706 }
1707
1708 printf("single step exception:\n");
1709 val = 0;
1710 if (setjmp(jmp_env) == 0) {
1711 asm volatile ("pushf\n"
1712 "orl $0x00100, (%%esp)\n"
1713 "popf\n"
1714 "movl $0xabcd, %0\n"
1715 "movl $0x0, %0\n" : "=m" (val) : : "cc", "memory");
1716 }
1717 printf("val=0x%x\n", val);
1718}
1719
776f2227 1720#if !defined(__x86_64__)
3ff0631e
FB		 1721/* specific precise single step test */
1722void sig_trap_handler(int sig, siginfo_t *info, void *puc)
1723{
1724 struct ucontext *uc = puc;
776f2227 1725 printf("EIP=" FMTLX "\n", (long)uc->uc_mcontext.gregs[REG_EIP]);
3ff0631e
FB		 1726}
1727
1728const uint8_t sstep_buf1[4] = { 1, 2, 3, 4};
1729uint8_t sstep_buf2[4];
1730
1731void test_single_step(void)
1732{
1733 struct sigaction act;
1734 volatile int val;
1735 int i;
1736
1737 val = 0;
1738 act.sa_sigaction = sig_trap_handler;
1739 sigemptyset(&act.sa_mask);
1740 act.sa_flags = SA_SIGINFO;
1741 sigaction(SIGTRAP, &act, NULL);
1742 asm volatile ("pushf\n"
1743 "orl $0x00100, (%%esp)\n"
1744 "popf\n"
1745 "movl $0xabcd, %0\n"
1746
1747 /* jmp test */
1748 "movl $3, %%ecx\n"
1749 "1:\n"
1750 "addl $1, %0\n"
1751 "decl %%ecx\n"
1752 "jnz 1b\n"
1753
1754 /* movsb: the single step should stop at each movsb iteration */
1755 "movl $sstep_buf1, %%esi\n"
1756 "movl $sstep_buf2, %%edi\n"
1757 "movl $0, %%ecx\n"
1758 "rep movsb\n"
1759 "movl $3, %%ecx\n"
1760 "rep movsb\n"
1761 "movl $1, %%ecx\n"
1762 "rep movsb\n"
1763
1764 /* cmpsb: the single step should stop at each cmpsb iteration */
1765 "movl $sstep_buf1, %%esi\n"
1766 "movl $sstep_buf2, %%edi\n"
1767 "movl $0, %%ecx\n"
1768 "rep cmpsb\n"
1769 "movl $4, %%ecx\n"
1770 "rep cmpsb\n"
1771
1772 /* getpid() syscall: single step should skip one
1773 instruction */
1774 "movl $20, %%eax\n"
1775 "int $0x80\n"
1776 "movl $0, %%eax\n"
1777
1778 /* when modifying SS, trace is not done on the next
1779 instruction */
1780 "movl %%ss, %%ecx\n"
1781 "movl %%ecx, %%ss\n"
1782 "addl $1, %0\n"
1783 "movl $1, %%eax\n"
1784 "movl %%ecx, %%ss\n"
1785 "jmp 1f\n"
1786 "addl $1, %0\n"
1787 "1:\n"
1788 "movl $1, %%eax\n"
1789 "pushl %%ecx\n"
1790 "popl %%ss\n"
1791 "addl $1, %0\n"
1792 "movl $1, %%eax\n"
1793
1794 "pushf\n"
1795 "andl $~0x00100, (%%esp)\n"
1796 "popf\n"
1797 : "=m" (val)
1798 :
1799 : "cc", "memory", "eax", "ecx", "esi", "edi");
1800 printf("val=%d\n", val);
1801 for(i = 0; i < 4; i++)
1802 printf("sstep_buf2[%d] = %d\n", i, sstep_buf2[i]);
1803}
1804
3a27ad0b
FB		 1805/* self modifying code test */
1806uint8_t code[] = {
1807 0xb8, 0x1, 0x00, 0x00, 0x00, /* movl $1, %eax */
1808 0xc3, /* ret */
1809};
1810
1190935d
FB		 1811asm("smc_code2:\n"
1812 "movl 4(%esp), %eax\n"
1813 "movl %eax, smc_patch_addr2 + 1\n"
1814 "nop\n"
1815 "nop\n"
1816 "nop\n"
1817 "nop\n"
1818 "nop\n"
1819 "nop\n"
1820 "nop\n"
1821 "nop\n"
1822 "smc_patch_addr2:\n"
1823 "movl $1, %eax\n"
1824 "ret\n");
d1fe2b24 1825
1190935d
FB		 1826typedef int FuncType(void);
1827extern int smc_code2(int);
3a27ad0b
FB		 1828void test_self_modifying_code(void)
1829{
d1fe2b24 1830 int i;
3a27ad0b 1831
3a27ad0b 1832 printf("self modifying code:\n");
d1fe2b24
FB		 1833 printf("func1 = 0x%x\n", ((FuncType *)code)());
1834 for(i = 2; i <= 4; i++) {
1835 code[1] = i;
1836 printf("func%d = 0x%x\n", i, ((FuncType *)code)());
1837 }
1190935d
FB		 1838
1839 /* more difficult test : the modified code is just after the
1840 modifying instruction. It is forbidden in Intel specs, but it
1841 is used by old DOS programs */
1842 for(i = 2; i <= 4; i++) {
1843 printf("smc_code2(%d) = %d\n", i, smc_code2(i));
1844 }
3a27ad0b 1845}
776f2227 1846#endif
61a8c4ec 1847
776f2227
FB		 1848long enter_stack[4096];
1849
1850#if defined(__x86_64__)
1851#define RSP "%%rsp"
1852#define RBP "%%rbp"
1853#else
1854#define RSP "%%esp"
1855#define RBP "%%ebp"
1856#endif
61a8c4ec
FB		 1857
1858#define TEST_ENTER(size, stack_type, level)\
1859{\
776f2227 1860 long esp_save, esp_val, ebp_val, ebp_save, i;\
61a8c4ec
FB		 1861 stack_type *ptr, *stack_end, *stack_ptr;\
1862 memset(enter_stack, 0, sizeof(enter_stack));\
1863 stack_end = stack_ptr = (stack_type *)(enter_stack + 4096);\
1864 ebp_val = (long)stack_ptr;\
1865 for(i=1;i<=32;i++)\
1866 *--stack_ptr = i;\
1867 esp_val = (long)stack_ptr;\
776f2227
FB		 1868 asm("mov " RSP ", %[esp_save]\n"\
1869 "mov " RBP ", %[ebp_save]\n"\
1870 "mov %[esp_val], " RSP "\n"\
1871 "mov %[ebp_val], " RBP "\n"\
1872 "enter" size " $8, $" #level "\n"\
1873 "mov " RSP ", %[esp_val]\n"\
1874 "mov " RBP ", %[ebp_val]\n"\
1875 "mov %[esp_save], " RSP "\n"\
1876 "mov %[ebp_save], " RBP "\n"\
61a8c4ec
FB		 1877 : [esp_save] "=r" (esp_save),\
1878 [ebp_save] "=r" (ebp_save),\
1879 [esp_val] "=r" (esp_val),\
1880 [ebp_val] "=r" (ebp_val)\
1881 : "[esp_val]" (esp_val),\
1882 "[ebp_val]" (ebp_val));\
1883 printf("level=%d:\n", level);\
776f2227
FB		 1884 printf("esp_val=" FMTLX "\n", esp_val - (long)stack_end);\
1885 printf("ebp_val=" FMTLX "\n", ebp_val - (long)stack_end);\
61a8c4ec 1886 for(ptr = (stack_type *)esp_val; ptr < stack_end; ptr++)\
776f2227 1887 printf(FMTLX "\n", (long)ptr[0]);\
61a8c4ec
FB		 1888}
1889
1890static void test_enter(void)
1891{
776f2227
FB		 1892#if defined(__x86_64__)
1893 TEST_ENTER("q", uint64_t, 0);
1894 TEST_ENTER("q", uint64_t, 1);
1895 TEST_ENTER("q", uint64_t, 2);
1896 TEST_ENTER("q", uint64_t, 31);
1897#else
61a8c4ec
FB		 1898 TEST_ENTER("l", uint32_t, 0);
1899 TEST_ENTER("l", uint32_t, 1);
1900 TEST_ENTER("l", uint32_t, 2);
1901 TEST_ENTER("l", uint32_t, 31);
776f2227 1902#endif
61a8c4ec
FB		 1903
1904 TEST_ENTER("w", uint16_t, 0);
1905 TEST_ENTER("w", uint16_t, 1);
1906 TEST_ENTER("w", uint16_t, 2);
1907 TEST_ENTER("w", uint16_t, 31);
1908}
1909
085339a1
FB		 1910#ifdef TEST_SSE
1911
1912typedef int __m64 __attribute__ ((__mode__ (__V2SI__)));
1913typedef int __m128 __attribute__ ((__mode__(__V4SF__)));
1914
1915typedef union {
1916 double d[2];
1917 float s[4];
1918 uint32_t l[4];
1919 uint64_t q[2];
1920 __m128 dq;
1921} XMMReg;
1922
1923static uint64_t __attribute__((aligned(16))) test_values[4][2] = {
1924 { 0x456723c698694873, 0xdc515cff944a58ec },
1925 { 0x1f297ccd58bad7ab, 0x41f21efba9e3e146 },
1926 { 0x007c62c2085427f8, 0x231be9e8cde7438d },
1927 { 0x0f76255a085427f8, 0xc233e9e8c4c9439a },
1928};
1929
1930#define SSE_OP(op)\
1931{\
1932 asm volatile (#op " %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
776f2227 1933 printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
085339a1
FB		 1934 #op,\
1935 a.q[1], a.q[0],\
1936 b.q[1], b.q[0],\
1937 r.q[1], r.q[0]);\
1938}
1939
1940#define SSE_OP2(op)\
1941{\
1942 int i;\
1943 for(i=0;i<2;i++) {\
1944 a.q[0] = test_values[2*i][0];\
1945 a.q[1] = test_values[2*i][1];\
1946 b.q[0] = test_values[2*i+1][0];\
1947 b.q[1] = test_values[2*i+1][1];\
1948 SSE_OP(op);\
1949 }\
1950}
1951
1952#define MMX_OP2(op)\
1953{\
1954 int i;\
1955 for(i=0;i<2;i++) {\
1956 a.q[0] = test_values[2*i][0];\
1957 b.q[0] = test_values[2*i+1][0];\
1958 asm volatile (#op " %2, %0" : "=y" (r.q[0]) : "0" (a.q[0]), "y" (b.q[0]));\
776f2227 1959 printf("%-9s: a=" FMT64X " b=" FMT64X " r=" FMT64X "\n",\
085339a1
FB		 1960 #op,\
1961 a.q[0],\
1962 b.q[0],\
1963 r.q[0]);\
1964 }\
1965 SSE_OP2(op);\
1966}
1967
97ed14ae
FB		 1968#define SHUF_OP(op, ib)\
1969{\
97ed14ae
FB		 1970 a.q[0] = test_values[0][0];\
1971 a.q[1] = test_values[0][1];\
1972 b.q[0] = test_values[1][0];\
1973 b.q[1] = test_values[1][1];\
1974 asm volatile (#op " $" #ib ", %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
776f2227 1975 printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
97ed14ae
FB		 1976 #op,\
1977 a.q[1], a.q[0],\
1978 b.q[1], b.q[0],\
1979 ib,\
1980 r.q[1], r.q[0]);\
1981}
1982
085339a1
FB		 1983#define PSHUF_OP(op, ib)\
1984{\
1985 int i;\
1986 for(i=0;i<2;i++) {\
1987 a.q[0] = test_values[2*i][0];\
1988 a.q[1] = test_values[2*i][1];\
1989 asm volatile (#op " $" #ib ", %1, %0" : "=x" (r.dq) : "x" (a.dq));\
776f2227 1990 printf("%-9s: a=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
085339a1
FB		 1991 #op,\
1992 a.q[1], a.q[0],\
1993 ib,\
1994 r.q[1], r.q[0]);\
1995 }\
1996}
1997
1998#define SHIFT_IM(op, ib)\
1999{\
2000 int i;\
2001 for(i=0;i<2;i++) {\
2002 a.q[0] = test_values[2*i][0];\
2003 a.q[1] = test_values[2*i][1];\
2004 asm volatile (#op " $" #ib ", %0" : "=x" (r.dq) : "0" (a.dq));\
776f2227 2005 printf("%-9s: a=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
085339a1
FB		 2006 #op,\
2007 a.q[1], a.q[0],\
2008 ib,\
2009 r.q[1], r.q[0]);\
2010 }\
2011}
2012
2013#define SHIFT_OP(op, ib)\
2014{\
2015 int i;\
2016 SHIFT_IM(op, ib);\
2017 for(i=0;i<2;i++) {\
2018 a.q[0] = test_values[2*i][0];\
2019 a.q[1] = test_values[2*i][1];\
2020 b.q[0] = ib;\
2021 b.q[1] = 0;\
2022 asm volatile (#op " %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
776f2227 2023 printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
085339a1
FB		 2024 #op,\
2025 a.q[1], a.q[0],\
2026 b.q[1], b.q[0],\
2027 r.q[1], r.q[0]);\
2028 }\
2029}
2030
2031#define MOVMSK(op)\
2032{\
2033 int i, reg;\
2034 for(i=0;i<2;i++) {\
2035 a.q[0] = test_values[2*i][0];\
2036 a.q[1] = test_values[2*i][1];\
2037 asm volatile (#op " %1, %0" : "=r" (reg) : "x" (a.dq));\
776f2227 2038 printf("%-9s: a=" FMT64X "" FMT64X " r=%08x\n",\
085339a1
FB		 2039 #op,\
2040 a.q[1], a.q[0],\
2041 reg);\
2042 }\
2043}
2044
2045#define SSE_OPS(a) \
2046SSE_OP(a ## ps);\
2047SSE_OP(a ## ss);
2048
2049#define SSE_OPD(a) \
2050SSE_OP(a ## pd);\
2051SSE_OP(a ## sd);
2052
2053#define SSE_COMI(op, field)\
2054{\
2055 unsigned int eflags;\
2056 XMMReg a, b;\
2057 a.field[0] = a1;\
2058 b.field[0] = b1;\
2059 asm volatile (#op " %2, %1\n"\
2060 "pushf\n"\
2061 "pop %0\n"\
2062 : "=m" (eflags)\
2063 : "x" (a.dq), "x" (b.dq));\
2064 printf("%-9s: a=%f b=%f cc=%04x\n",\
2065 #op, a1, b1,\
2066 eflags & (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A));\
2067}
2068
2069void test_sse_comi(double a1, double b1)
2070{
2071 SSE_COMI(ucomiss, s);
2072 SSE_COMI(ucomisd, d);
2073 SSE_COMI(comiss, s);
2074 SSE_COMI(comisd, d);
2075}
2076
2077#define CVT_OP_XMM(op)\
2078{\
2079 asm volatile (#op " %1, %0" : "=x" (r.dq) : "x" (a.dq));\
776f2227 2080 printf("%-9s: a=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
085339a1
FB		 2081 #op,\
2082 a.q[1], a.q[0],\
2083 r.q[1], r.q[0]);\
2084}
2085
2086#define CVT_OP_XMM2MMX(op)\
2087{\
2088 asm volatile (#op " %1, %0" : "=y" (r.q[0]) : "x" (a.dq));\
776f2227 2089 printf("%-9s: a=" FMT64X "" FMT64X " r=" FMT64X "\n",\
085339a1
FB		 2090 #op,\
2091 a.q[1], a.q[0],\
2092 r.q[0]);\
2093}
2094
2095#define CVT_OP_MMX2XMM(op)\
2096{\
2097 asm volatile (#op " %1, %0" : "=x" (r.dq) : "y" (a.q[0]));\
776f2227 2098 printf("%-9s: a=" FMT64X " r=" FMT64X "" FMT64X "\n",\
085339a1
FB		 2099 #op,\
2100 a.q[0],\
2101 r.q[1], r.q[0]);\
2102}
2103
2104#define CVT_OP_REG2XMM(op)\
2105{\
2106 asm volatile (#op " %1, %0" : "=x" (r.dq) : "r" (a.l[0]));\
776f2227 2107 printf("%-9s: a=%08x r=" FMT64X "" FMT64X "\n",\
085339a1
FB		 2108 #op,\
2109 a.l[0],\
2110 r.q[1], r.q[0]);\
2111}
2112
2113#define CVT_OP_XMM2REG(op)\
2114{\
2115 asm volatile (#op " %1, %0" : "=r" (r.l[0]) : "x" (a.dq));\
776f2227 2116 printf("%-9s: a=" FMT64X "" FMT64X " r=%08x\n",\
085339a1
FB		 2117 #op,\
2118 a.q[1], a.q[0],\
2119 r.l[0]);\
2120}
2121
a4682cc2
FB		 2122struct fpxstate {
2123 uint16_t fpuc;
2124 uint16_t fpus;
2125 uint16_t fptag;
2126 uint16_t fop;
2127 uint32_t fpuip;
2128 uint16_t cs_sel;
2129 uint16_t dummy0;
2130 uint32_t fpudp;
2131 uint16_t ds_sel;
2132 uint16_t dummy1;
2133 uint32_t mxcsr;
2134 uint32_t mxcsr_mask;
2135 uint8_t fpregs1[8 * 16];
2136 uint8_t xmm_regs[8 * 16];
2137 uint8_t dummy2[224];
2138};
2139
2140static struct fpxstate fpx_state __attribute__((aligned(16)));
2141static struct fpxstate fpx_state2 __attribute__((aligned(16)));
2142
2143void test_fxsave(void)
2144{
2145 struct fpxstate *fp = &fpx_state;
2146 struct fpxstate *fp2 = &fpx_state2;
776f2227 2147 int i, nb_xmm;
a4682cc2
FB		 2148 XMMReg a, b;
2149 a.q[0] = test_values[0][0];
2150 a.q[1] = test_values[0][1];
2151 b.q[0] = test_values[1][0];
2152 b.q[1] = test_values[1][1];
2153
2154 asm("movdqa %2, %%xmm0\n"
2155 "movdqa %3, %%xmm7\n"
776f2227
FB		 2156#if defined(__x86_64__)
2157 "movdqa %2, %%xmm15\n"
2158#endif
a4682cc2
FB		 2159 " fld1\n"
2160 " fldpi\n"
2161 " fldln2\n"
2162 " fxsave %0\n"
2163 " fxrstor %0\n"
2164 " fxsave %1\n"
2165 " fninit\n"
2166 : "=m" (*(uint32_t *)fp2), "=m" (*(uint32_t *)fp)
2167 : "m" (a), "m" (b));
2168 printf("fpuc=%04x\n", fp->fpuc);
2169 printf("fpus=%04x\n", fp->fpus);
2170 printf("fptag=%04x\n", fp->fptag);
2171 for(i = 0; i < 3; i++) {
776f2227 2172 printf("ST%d: " FMT64X " %04x\n",
a4682cc2
FB		 2173 i,
2174 *(uint64_t *)&fp->fpregs1[i * 16],
2175 *(uint16_t *)&fp->fpregs1[i * 16 + 8]);
2176 }
2177 printf("mxcsr=%08x\n", fp->mxcsr & 0x1f80);
776f2227
FB		 2178#if defined(__x86_64__)
2179 nb_xmm = 16;
2180#else
2181 nb_xmm = 8;
2182#endif
2183 for(i = 0; i < nb_xmm; i++) {
2184 printf("xmm%d: " FMT64X "" FMT64X "\n",
a4682cc2
FB		 2185 i,
2186 *(uint64_t *)&fp->xmm_regs[i * 16],
2187 *(uint64_t *)&fp->xmm_regs[i * 16 + 8]);
2188 }
2189}
2190
085339a1
FB		 2191void test_sse(void)
2192{
2193 XMMReg r, a, b;
2194
2195 MMX_OP2(punpcklbw);
2196 MMX_OP2(punpcklwd);
2197 MMX_OP2(punpckldq);
2198 MMX_OP2(packsswb);
2199 MMX_OP2(pcmpgtb);
2200 MMX_OP2(pcmpgtw);
2201 MMX_OP2(pcmpgtd);
2202 MMX_OP2(packuswb);
2203 MMX_OP2(punpckhbw);
2204 MMX_OP2(punpckhwd);
2205 MMX_OP2(punpckhdq);
2206 MMX_OP2(packssdw);
2207 MMX_OP2(pcmpeqb);
2208 MMX_OP2(pcmpeqw);
2209 MMX_OP2(pcmpeqd);
2210
2211 MMX_OP2(paddq);
2212 MMX_OP2(pmullw);
2213 MMX_OP2(psubusb);
2214 MMX_OP2(psubusw);
2215 MMX_OP2(pminub);
2216 MMX_OP2(pand);
2217 MMX_OP2(paddusb);
2218 MMX_OP2(paddusw);
2219 MMX_OP2(pmaxub);
2220 MMX_OP2(pandn);
2221
2222 MMX_OP2(pmulhuw);
2223 MMX_OP2(pmulhw);
2224
2225 MMX_OP2(psubsb);
2226 MMX_OP2(psubsw);
2227 MMX_OP2(pminsw);
2228 MMX_OP2(por);
2229 MMX_OP2(paddsb);
2230 MMX_OP2(paddsw);
2231 MMX_OP2(pmaxsw);
2232 MMX_OP2(pxor);
2233 MMX_OP2(pmuludq);
2234 MMX_OP2(pmaddwd);
2235 MMX_OP2(psadbw);
2236 MMX_OP2(psubb);
2237 MMX_OP2(psubw);
2238 MMX_OP2(psubd);
2239 MMX_OP2(psubq);
2240 MMX_OP2(paddb);
2241 MMX_OP2(paddw);
2242 MMX_OP2(paddd);
2243
2244 MMX_OP2(pavgb);
2245 MMX_OP2(pavgw);
2246
2247 asm volatile ("pinsrw $1, %1, %0" : "=y" (r.q[0]) : "r" (0x12345678));
776f2227 2248 printf("%-9s: r=" FMT64X "\n", "pinsrw", r.q[0]);
085339a1
FB		 2249
2250 asm volatile ("pinsrw $5, %1, %0" : "=x" (r.dq) : "r" (0x12345678));
776f2227 2251 printf("%-9s: r=" FMT64X "" FMT64X "\n", "pinsrw", r.q[1], r.q[0]);
085339a1
FB		 2252
2253 a.q[0] = test_values[0][0];
2254 a.q[1] = test_values[0][1];
2255 asm volatile ("pextrw $1, %1, %0" : "=r" (r.l[0]) : "y" (a.q[0]));
2256 printf("%-9s: r=%08x\n", "pextrw", r.l[0]);
2257
2258 asm volatile ("pextrw $5, %1, %0" : "=r" (r.l[0]) : "x" (a.dq));
2259 printf("%-9s: r=%08x\n", "pextrw", r.l[0]);
2260
2261 asm volatile ("pmovmskb %1, %0" : "=r" (r.l[0]) : "y" (a.q[0]));
2262 printf("%-9s: r=%08x\n", "pmovmskb", r.l[0]);
2263
2264 asm volatile ("pmovmskb %1, %0" : "=r" (r.l[0]) : "x" (a.dq));
2265 printf("%-9s: r=%08x\n", "pmovmskb", r.l[0]);
2266
97ed14ae
FB		 2267 {
2268 r.q[0] = -1;
2269 r.q[1] = -1;
2270
2271 a.q[0] = test_values[0][0];
2272 a.q[1] = test_values[0][1];
2273 b.q[0] = test_values[1][0];
2274 b.q[1] = test_values[1][1];
2275 asm volatile("maskmovq %1, %0" :
2276 : "y" (a.q[0]), "y" (b.q[0]), "D" (&r)
2277 : "memory");
776f2227 2278 printf("%-9s: r=" FMT64X " a=" FMT64X " b=" FMT64X "\n",
97ed14ae
FB		 2279 "maskmov",
2280 r.q[0],
2281 a.q[0],
2282 b.q[0]);
2283 asm volatile("maskmovdqu %1, %0" :
2284 : "x" (a.dq), "x" (b.dq), "D" (&r)
2285 : "memory");
776f2227 2286 printf("%-9s: r=" FMT64X "" FMT64X " a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X "\n",
97ed14ae
FB		 2287 "maskmov",
2288 r.q[1], r.q[0],
2289 a.q[1], a.q[0],
2290 b.q[1], b.q[0]);
2291 }
2292
085339a1
FB		 2293 asm volatile ("emms");
2294
2295 SSE_OP2(punpcklqdq);
2296 SSE_OP2(punpckhqdq);
2297 SSE_OP2(andps);
2298 SSE_OP2(andpd);
2299 SSE_OP2(andnps);
2300 SSE_OP2(andnpd);
2301 SSE_OP2(orps);
2302 SSE_OP2(orpd);
2303 SSE_OP2(xorps);
2304 SSE_OP2(xorpd);
2305
2306 SSE_OP2(unpcklps);
2307 SSE_OP2(unpcklpd);
2308 SSE_OP2(unpckhps);
2309 SSE_OP2(unpckhpd);
2310
97ed14ae
FB		 2311 SHUF_OP(shufps, 0x78);
2312 SHUF_OP(shufpd, 0x02);
085339a1
FB		 2313
2314 PSHUF_OP(pshufd, 0x78);
2315 PSHUF_OP(pshuflw, 0x78);
2316 PSHUF_OP(pshufhw, 0x78);
2317
2318 SHIFT_OP(psrlw, 7);
2319 SHIFT_OP(psrlw, 16);
2320 SHIFT_OP(psraw, 7);
2321 SHIFT_OP(psraw, 16);
2322 SHIFT_OP(psllw, 7);
2323 SHIFT_OP(psllw, 16);
2324
2325 SHIFT_OP(psrld, 7);
2326 SHIFT_OP(psrld, 32);
2327 SHIFT_OP(psrad, 7);
2328 SHIFT_OP(psrad, 32);
2329 SHIFT_OP(pslld, 7);
2330 SHIFT_OP(pslld, 32);
2331
2332 SHIFT_OP(psrlq, 7);
2333 SHIFT_OP(psrlq, 32);
2334 SHIFT_OP(psllq, 7);
2335 SHIFT_OP(psllq, 32);
2336
2337 SHIFT_IM(psrldq, 16);
2338 SHIFT_IM(psrldq, 7);
2339 SHIFT_IM(pslldq, 16);
2340 SHIFT_IM(pslldq, 7);
2341
2342 MOVMSK(movmskps);
2343 MOVMSK(movmskpd);
2344
2345 /* FPU specific ops */
2346
2347 {
2348 uint32_t mxcsr;
2349 asm volatile("stmxcsr %0" : "=m" (mxcsr));
2350 printf("mxcsr=%08x\n", mxcsr & 0x1f80);
2351 asm volatile("ldmxcsr %0" : : "m" (mxcsr));
2352 }
2353
2354 test_sse_comi(2, -1);
2355 test_sse_comi(2, 2);
2356 test_sse_comi(2, 3);
2357
2358 a.s[0] = 2.7;
2359 a.s[1] = 3.4;
2360 a.s[2] = 4;
2361 a.s[3] = -6.3;
2362 b.s[0] = 45.7;
2363 b.s[1] = 353.4;
2364 b.s[2] = 4;
2365 b.s[3] = 56.3;
2366 SSE_OPS(add);
2367 SSE_OPS(mul);
2368 SSE_OPS(sub);
2369 SSE_OPS(min);
2370 SSE_OPS(div);
2371 SSE_OPS(max);
2372 SSE_OPS(sqrt);
2373 SSE_OPS(cmpeq);
2374 SSE_OPS(cmplt);
2375 SSE_OPS(cmple);
2376 SSE_OPS(cmpunord);
2377 SSE_OPS(cmpneq);
2378 SSE_OPS(cmpnlt);
2379 SSE_OPS(cmpnle);
2380 SSE_OPS(cmpord);
2381
2382 a.d[0] = 2.7;
2383 a.d[1] = -3.4;
2384 b.d[0] = 45.7;
2385 b.d[1] = -53.4;
2386 SSE_OPD(add);
2387 SSE_OPD(mul);
2388 SSE_OPD(sub);
2389 SSE_OPD(min);
2390 SSE_OPD(div);
2391 SSE_OPD(max);
2392 SSE_OPD(sqrt);
2393 SSE_OPD(cmpeq);
2394 SSE_OPD(cmplt);
2395 SSE_OPD(cmple);
2396 SSE_OPD(cmpunord);
2397 SSE_OPD(cmpneq);
2398 SSE_OPD(cmpnlt);
2399 SSE_OPD(cmpnle);
2400 SSE_OPD(cmpord);
2401
2402 /* float to float/int */
2403 a.s[0] = 2.7;
2404 a.s[1] = 3.4;
2405 a.s[2] = 4;
2406 a.s[3] = -6.3;
2407 CVT_OP_XMM(cvtps2pd);
2408 CVT_OP_XMM(cvtss2sd);
2409 CVT_OP_XMM2MMX(cvtps2pi);
2410 CVT_OP_XMM2MMX(cvttps2pi);
2411 CVT_OP_XMM2REG(cvtss2si);
2412 CVT_OP_XMM2REG(cvttss2si);
2413 CVT_OP_XMM(cvtps2dq);
2414 CVT_OP_XMM(cvttps2dq);
2415
2416 a.d[0] = 2.6;
2417 a.d[1] = -3.4;
2418 CVT_OP_XMM(cvtpd2ps);
2419 CVT_OP_XMM(cvtsd2ss);
2420 CVT_OP_XMM2MMX(cvtpd2pi);
2421 CVT_OP_XMM2MMX(cvttpd2pi);
2422 CVT_OP_XMM2REG(cvtsd2si);
2423 CVT_OP_XMM2REG(cvttsd2si);
2424 CVT_OP_XMM(cvtpd2dq);
2425 CVT_OP_XMM(cvttpd2dq);
2426
2427 /* int to float */
2428 a.l[0] = -6;
2429 a.l[1] = 2;
2430 a.l[2] = 100;
2431 a.l[3] = -60000;
2432 CVT_OP_MMX2XMM(cvtpi2ps);
2433 CVT_OP_MMX2XMM(cvtpi2pd);
2434 CVT_OP_REG2XMM(cvtsi2ss);
2435 CVT_OP_REG2XMM(cvtsi2sd);
2436 CVT_OP_XMM(cvtdq2ps);
2437 CVT_OP_XMM(cvtdq2pd);
2438
2439 /* XXX: test PNI insns */
2440#if 0
2441 SSE_OP2(movshdup);
2442#endif
a4682cc2 2443 asm volatile ("emms");
085339a1
FB		 2444}
2445
2446#endif
2447
776f2227
FB		 2448extern void *__start_initcall;
2449extern void *__stop_initcall;
2450
4d1135e4
FB		 2451
2452int main(int argc, char **argv)
2453{
2454 void **ptr;
2455 void (*func)(void);
4b74fe1f 2456
776f2227
FB		 2457 ptr = &__start_initcall;
2458 while (ptr != &__stop_initcall) {
4d1135e4
FB		 2459 func = *ptr++;
2460 func();
2461 }
9d8e9c09 2462 test_bsx();
d57c4e01 2463 test_mul();
4d1135e4 2464 test_jcc();
9d8e9c09 2465 test_floats();
776f2227 2466#if !defined(__x86_64__)
55480af8 2467 test_bcd();
776f2227 2468#endif
1a9353d2 2469 test_xchg();
e1d4294a
FB		 2470 test_string();
2471 test_misc();
6dbad63e 2472 test_lea();
776f2227 2473#ifdef TEST_SEGS
6dbad63e 2474 test_segs();
e5918247 2475 test_code16();
776f2227 2476#endif
acae4681 2477#ifdef TEST_VM86
3a27ad0b 2478 test_vm86();
acae4681 2479#endif
3a27ad0b 2480 test_exceptions();
776f2227 2481#if !defined(__x86_64__)
3a27ad0b 2482 test_self_modifying_code();
3ff0631e 2483 test_single_step();
776f2227 2484#endif
61a8c4ec 2485 test_enter();
085339a1
FB		 2486#ifdef TEST_SSE
2487 test_sse();
a4682cc2 2488 test_fxsave();
085339a1 2489#endif
4d1135e4
FB		 2490 return 0;
2491}
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