[qemu.git] / hw / intc / arm_gic_kvm.c

/*
 * ARM Generic Interrupt Controller using KVM in-kernel support
 *
 * Copyright (c) 2012 Linaro Limited
 * Written by Peter Maydell
 * Save/Restore logic added by Christoffer Dall.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/sysbus.h"
#include "migration/migration.h"
#include "sysemu/kvm.h"
#include "kvm_arm.h"
#include "gic_internal.h"
#include "vgic_common.h"

//#define DEBUG_GIC_KVM

#ifdef DEBUG_GIC_KVM
static const int debug_gic_kvm = 1;
#else
static const int debug_gic_kvm = 0;
#endif

#define DPRINTF(fmt, ...) do { \
        if (debug_gic_kvm) { \
            printf("arm_gic: " fmt , ## __VA_ARGS__); \
        } \
    } while (0)

#define TYPE_KVM_ARM_GIC "kvm-arm-gic"
#define KVM_ARM_GIC(obj) \
     OBJECT_CHECK(GICState, (obj), TYPE_KVM_ARM_GIC)
#define KVM_ARM_GIC_CLASS(klass) \
     OBJECT_CLASS_CHECK(KVMARMGICClass, (klass), TYPE_KVM_ARM_GIC)
#define KVM_ARM_GIC_GET_CLASS(obj) \
     OBJECT_GET_CLASS(KVMARMGICClass, (obj), TYPE_KVM_ARM_GIC)

typedef struct KVMARMGICClass {
    ARMGICCommonClass parent_class;
    DeviceRealize parent_realize;
    void (*parent_reset)(DeviceState *dev);
} KVMARMGICClass;

void kvm_arm_gic_set_irq(uint32_t num_irq, int irq, int level)
{
    /* Meaning of the 'irq' parameter:
     *  [0..N-1] : external interrupts
     *  [N..N+31] : PPI (internal) interrupts for CPU 0
     *  [N+32..N+63] : PPI (internal interrupts for CPU 1
     *  ...
     * Convert this to the kernel's desired encoding, which
     * has separate fields in the irq number for type,
     * CPU number and interrupt number.
     */
    int kvm_irq, irqtype, cpu;

    if (irq < (num_irq - GIC_INTERNAL)) {
        /* External interrupt. The kernel numbers these like the GIC
         * hardware, with external interrupt IDs starting after the
         * internal ones.
         */
        irqtype = KVM_ARM_IRQ_TYPE_SPI;
        cpu = 0;
        irq += GIC_INTERNAL;
    } else {
        /* Internal interrupt: decode into (cpu, interrupt id) */
        irqtype = KVM_ARM_IRQ_TYPE_PPI;
        irq -= (num_irq - GIC_INTERNAL);
        cpu = irq / GIC_INTERNAL;
        irq %= GIC_INTERNAL;
    }
    kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT)
        | (cpu << KVM_ARM_IRQ_VCPU_SHIFT) | irq;

    kvm_set_irq(kvm_state, kvm_irq, !!level);
}

static void kvm_arm_gicv2_set_irq(void *opaque, int irq, int level)
{
    GICState *s = (GICState *)opaque;

    kvm_arm_gic_set_irq(s->num_irq, irq, level);
}

static bool kvm_arm_gic_can_save_restore(GICState *s)
{
    return s->dev_fd >= 0;
}

#define KVM_VGIC_ATTR(offset, cpu) \
    ((((uint64_t)(cpu) << KVM_DEV_ARM_VGIC_CPUID_SHIFT) & \
      KVM_DEV_ARM_VGIC_CPUID_MASK) | \
     (((uint64_t)(offset) << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) & \
      KVM_DEV_ARM_VGIC_OFFSET_MASK))

static void kvm_gicd_access(GICState *s, int offset, int cpu,
                            uint32_t *val, bool write)
{
    kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
                      KVM_VGIC_ATTR(offset, cpu), val, write);
}

static void kvm_gicc_access(GICState *s, int offset, int cpu,
                            uint32_t *val, bool write)
{
    kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_REGS,
                      KVM_VGIC_ATTR(offset, cpu), val, write);
}

#define for_each_irq_reg(_ctr, _max_irq, _field_width) \
    for (_ctr = 0; _ctr < ((_max_irq) / (32 / (_field_width))); _ctr++)

/*
 * Translate from the in-kernel field for an IRQ value to/from the qemu
 * representation.
 */
typedef void (*vgic_translate_fn)(GICState *s, int irq, int cpu,
                                  uint32_t *field, bool to_kernel);

/* synthetic translate function used for clear/set registers to completely
 * clear a setting using a clear-register before setting the remaining bits
 * using a set-register */
static void translate_clear(GICState *s, int irq, int cpu,
                            uint32_t *field, bool to_kernel)
{
    if (to_kernel) {
        *field = ~0;
    } else {
        /* does not make sense: qemu model doesn't use set/clear regs */
        abort();
    }
}

static void translate_group(GICState *s, int irq, int cpu,
                            uint32_t *field, bool to_kernel)
{
    int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;

    if (to_kernel) {
        *field = GIC_TEST_GROUP(irq, cm);
    } else {
        if (*field & 1) {
            GIC_SET_GROUP(irq, cm);
        }
    }
}

static void translate_enabled(GICState *s, int irq, int cpu,
                              uint32_t *field, bool to_kernel)
{
    int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;

    if (to_kernel) {
        *field = GIC_TEST_ENABLED(irq, cm);
    } else {
        if (*field & 1) {
            GIC_SET_ENABLED(irq, cm);
        }
    }
}

static void translate_pending(GICState *s, int irq, int cpu,
                              uint32_t *field, bool to_kernel)
{
    int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;

    if (to_kernel) {
        *field = gic_test_pending(s, irq, cm);
    } else {
        if (*field & 1) {
            GIC_SET_PENDING(irq, cm);
            /* TODO: Capture is level-line is held high in the kernel */
        }
    }
}

static void translate_active(GICState *s, int irq, int cpu,
                             uint32_t *field, bool to_kernel)
{
    int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;

    if (to_kernel) {
        *field = GIC_TEST_ACTIVE(irq, cm);
    } else {
        if (*field & 1) {
            GIC_SET_ACTIVE(irq, cm);
        }
    }
}

static void translate_trigger(GICState *s, int irq, int cpu,
                              uint32_t *field, bool to_kernel)
{
    if (to_kernel) {
        *field = (GIC_TEST_EDGE_TRIGGER(irq)) ? 0x2 : 0x0;
    } else {
        if (*field & 0x2) {
            GIC_SET_EDGE_TRIGGER(irq);
        }
    }
}

static void translate_priority(GICState *s, int irq, int cpu,
                               uint32_t *field, bool to_kernel)
{
    if (to_kernel) {
        *field = GIC_GET_PRIORITY(irq, cpu) & 0xff;
    } else {
        gic_set_priority(s, cpu, irq, *field & 0xff, MEMTXATTRS_UNSPECIFIED);
    }
}

static void translate_targets(GICState *s, int irq, int cpu,
                              uint32_t *field, bool to_kernel)
{
    if (to_kernel) {
        *field = s->irq_target[irq] & 0xff;
    } else {
        s->irq_target[irq] = *field & 0xff;
    }
}

static void translate_sgisource(GICState *s, int irq, int cpu,
                                uint32_t *field, bool to_kernel)
{
    if (to_kernel) {
        *field = s->sgi_pending[irq][cpu] & 0xff;
    } else {
        s->sgi_pending[irq][cpu] = *field & 0xff;
    }
}

/* Read a register group from the kernel VGIC */
static void kvm_dist_get(GICState *s, uint32_t offset, int width,
                         int maxirq, vgic_translate_fn translate_fn)
{
    uint32_t reg;
    int i;
    int j;
    int irq;
    int cpu;
    int regsz = 32 / width; /* irqs per kernel register */
    uint32_t field;

    for_each_irq_reg(i, maxirq, width) {
        irq = i * regsz;
        cpu = 0;
        while ((cpu < s->num_cpu && irq < GIC_INTERNAL) || cpu == 0) {
            kvm_gicd_access(s, offset, cpu, &reg, false);
            for (j = 0; j < regsz; j++) {
                field = extract32(reg, j * width, width);
                translate_fn(s, irq + j, cpu, &field, false);
            }

            cpu++;
        }
        offset += 4;
    }
}

/* Write a register group to the kernel VGIC */
static void kvm_dist_put(GICState *s, uint32_t offset, int width,
                         int maxirq, vgic_translate_fn translate_fn)
{
    uint32_t reg;
    int i;
    int j;
    int irq;
    int cpu;
    int regsz = 32 / width; /* irqs per kernel register */
    uint32_t field;

    for_each_irq_reg(i, maxirq, width) {
        irq = i * regsz;
        cpu = 0;
        while ((cpu < s->num_cpu && irq < GIC_INTERNAL) || cpu == 0) {
            reg = 0;
            for (j = 0; j < regsz; j++) {
                translate_fn(s, irq + j, cpu, &field, true);
                reg = deposit32(reg, j * width, width, field);
            }
            kvm_gicd_access(s, offset, cpu, &reg, true);

            cpu++;
        }
        offset += 4;
    }
}

static void kvm_arm_gic_put(GICState *s)
{
    uint32_t reg;
    int i;
    int cpu;
    int num_cpu;
    int num_irq;

    /* Note: We do the restore in a slightly different order than the save
     * (where the order doesn't matter and is simply ordered according to the
     * register offset values */

    /*****************************************************************
     * Distributor State
     */

    /* s->ctlr -> GICD_CTLR */
    reg = s->ctlr;
    kvm_gicd_access(s, 0x0, 0, &reg, true);

    /* Sanity checking on GICD_TYPER and s->num_irq, s->num_cpu */
    kvm_gicd_access(s, 0x4, 0, &reg, false);
    num_irq = ((reg & 0x1f) + 1) * 32;
    num_cpu = ((reg & 0xe0) >> 5) + 1;

    if (num_irq < s->num_irq) {
            fprintf(stderr, "Restoring %u IRQs, but kernel supports max %d\n",
                    s->num_irq, num_irq);
            abort();
    } else if (num_cpu != s->num_cpu) {
            fprintf(stderr, "Restoring %u CPU interfaces, kernel only has %d\n",
                    s->num_cpu, num_cpu);
            /* Did we not create the VCPUs in the kernel yet? */
            abort();
    }

    /* TODO: Consider checking compatibility with the IIDR ? */

    /* irq_state[n].enabled -> GICD_ISENABLERn */
    kvm_dist_put(s, 0x180, 1, s->num_irq, translate_clear);
    kvm_dist_put(s, 0x100, 1, s->num_irq, translate_enabled);

    /* irq_state[n].group -> GICD_IGROUPRn */
    kvm_dist_put(s, 0x80, 1, s->num_irq, translate_group);

    /* s->irq_target[irq] -> GICD_ITARGETSRn
     * (restore targets before pending to ensure the pending state is set on
     * the appropriate CPU interfaces in the kernel) */
    kvm_dist_put(s, 0x800, 8, s->num_irq, translate_targets);

    /* irq_state[n].trigger -> GICD_ICFGRn
     * (restore configuration registers before pending IRQs so we treat
     * level/edge correctly) */
    kvm_dist_put(s, 0xc00, 2, s->num_irq, translate_trigger);

    /* irq_state[n].pending + irq_state[n].level -> GICD_ISPENDRn */
    kvm_dist_put(s, 0x280, 1, s->num_irq, translate_clear);
    kvm_dist_put(s, 0x200, 1, s->num_irq, translate_pending);

    /* irq_state[n].active -> GICD_ISACTIVERn */
    kvm_dist_put(s, 0x380, 1, s->num_irq, translate_clear);
    kvm_dist_put(s, 0x300, 1, s->num_irq, translate_active);


    /* s->priorityX[irq] -> ICD_IPRIORITYRn */
    kvm_dist_put(s, 0x400, 8, s->num_irq, translate_priority);

    /* s->sgi_pending -> ICD_CPENDSGIRn */
    kvm_dist_put(s, 0xf10, 8, GIC_NR_SGIS, translate_clear);
    kvm_dist_put(s, 0xf20, 8, GIC_NR_SGIS, translate_sgisource);


    /*****************************************************************
     * CPU Interface(s) State
     */

    for (cpu = 0; cpu < s->num_cpu; cpu++) {
        /* s->cpu_ctlr[cpu] -> GICC_CTLR */
        reg = s->cpu_ctlr[cpu];
        kvm_gicc_access(s, 0x00, cpu, &reg, true);

        /* s->priority_mask[cpu] -> GICC_PMR */
        reg = (s->priority_mask[cpu] & 0xff);
        kvm_gicc_access(s, 0x04, cpu, &reg, true);

        /* s->bpr[cpu] -> GICC_BPR */
        reg = (s->bpr[cpu] & 0x7);
        kvm_gicc_access(s, 0x08, cpu, &reg, true);

        /* s->abpr[cpu] -> GICC_ABPR */
        reg = (s->abpr[cpu] & 0x7);
        kvm_gicc_access(s, 0x1c, cpu, &reg, true);

        /* s->apr[n][cpu] -> GICC_APRn */
        for (i = 0; i < 4; i++) {
            reg = s->apr[i][cpu];
            kvm_gicc_access(s, 0xd0 + i * 4, cpu, &reg, true);
        }
    }
}

static void kvm_arm_gic_get(GICState *s)
{
    uint32_t reg;
    int i;
    int cpu;

    /*****************************************************************
     * Distributor State
     */

    /* GICD_CTLR -> s->ctlr */
    kvm_gicd_access(s, 0x0, 0, &reg, false);
    s->ctlr = reg;

    /* Sanity checking on GICD_TYPER -> s->num_irq, s->num_cpu */
    kvm_gicd_access(s, 0x4, 0, &reg, false);
    s->num_irq = ((reg & 0x1f) + 1) * 32;
    s->num_cpu = ((reg & 0xe0) >> 5) + 1;

    if (s->num_irq > GIC_MAXIRQ) {
            fprintf(stderr, "Too many IRQs reported from the kernel: %d\n",
                    s->num_irq);
            abort();
    }

    /* GICD_IIDR -> ? */
    kvm_gicd_access(s, 0x8, 0, &reg, false);

    /* Clear all the IRQ settings */
    for (i = 0; i < s->num_irq; i++) {
        memset(&s->irq_state[i], 0, sizeof(s->irq_state[0]));
    }

    /* GICD_IGROUPRn -> irq_state[n].group */
    kvm_dist_get(s, 0x80, 1, s->num_irq, translate_group);

    /* GICD_ISENABLERn -> irq_state[n].enabled */
    kvm_dist_get(s, 0x100, 1, s->num_irq, translate_enabled);

    /* GICD_ISPENDRn -> irq_state[n].pending + irq_state[n].level */
    kvm_dist_get(s, 0x200, 1, s->num_irq, translate_pending);

    /* GICD_ISACTIVERn -> irq_state[n].active */
    kvm_dist_get(s, 0x300, 1, s->num_irq, translate_active);

    /* GICD_ICFRn -> irq_state[n].trigger */
    kvm_dist_get(s, 0xc00, 2, s->num_irq, translate_trigger);

    /* GICD_IPRIORITYRn -> s->priorityX[irq] */
    kvm_dist_get(s, 0x400, 8, s->num_irq, translate_priority);

    /* GICD_ITARGETSRn -> s->irq_target[irq] */
    kvm_dist_get(s, 0x800, 8, s->num_irq, translate_targets);

    /* GICD_CPENDSGIRn -> s->sgi_pending */
    kvm_dist_get(s, 0xf10, 8, GIC_NR_SGIS, translate_sgisource);


    /*****************************************************************
     * CPU Interface(s) State
     */

    for (cpu = 0; cpu < s->num_cpu; cpu++) {
        /* GICC_CTLR -> s->cpu_ctlr[cpu] */
        kvm_gicc_access(s, 0x00, cpu, &reg, false);
        s->cpu_ctlr[cpu] = reg;

        /* GICC_PMR -> s->priority_mask[cpu] */
        kvm_gicc_access(s, 0x04, cpu, &reg, false);
        s->priority_mask[cpu] = (reg & 0xff);

        /* GICC_BPR -> s->bpr[cpu] */
        kvm_gicc_access(s, 0x08, cpu, &reg, false);
        s->bpr[cpu] = (reg & 0x7);

        /* GICC_ABPR -> s->abpr[cpu] */
        kvm_gicc_access(s, 0x1c, cpu, &reg, false);
        s->abpr[cpu] = (reg & 0x7);

        /* GICC_APRn -> s->apr[n][cpu] */
        for (i = 0; i < 4; i++) {
            kvm_gicc_access(s, 0xd0 + i * 4, cpu, &reg, false);
            s->apr[i][cpu] = reg;
        }
    }
}

static void kvm_arm_gic_reset(DeviceState *dev)
{
    GICState *s = ARM_GIC_COMMON(dev);
    KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);

    kgc->parent_reset(dev);

    if (kvm_arm_gic_can_save_restore(s)) {
        kvm_arm_gic_put(s);
    }
}

static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
{
    int i;
    GICState *s = KVM_ARM_GIC(dev);
    KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
    Error *local_err = NULL;
    int ret;

    kgc->parent_realize(dev, &local_err);
    if (local_err) {
        error_propagate(errp, local_err);
        return;
    }

    if (s->security_extn) {
        error_setg(errp, "the in-kernel VGIC does not implement the "
                   "security extensions");
        return;
    }

    gic_init_irqs_and_mmio(s, kvm_arm_gicv2_set_irq, NULL);

    for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {
        qemu_irq irq = qdev_get_gpio_in(dev, i);
        kvm_irqchip_set_qemuirq_gsi(kvm_state, irq, i);
    }

    /* Try to create the device via the device control API */
    s->dev_fd = -1;
    ret = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V2, false);
    if (ret >= 0) {
        s->dev_fd = ret;

        /* Newstyle API is used, we may have attributes */
        if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0)) {
            uint32_t numirqs = s->num_irq;
            kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0,
                              &numirqs, true);
        }
        /* Tell the kernel to complete VGIC initialization now */
        if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
                                  KVM_DEV_ARM_VGIC_CTRL_INIT)) {
            kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
                              KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true);
        }
    } else if (ret != -ENODEV && ret != -ENOTSUP) {
        error_setg_errno(errp, -ret, "error creating in-kernel VGIC");
        return;
    }

    /* Distributor */
    kvm_arm_register_device(&s->iomem,
                            (KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)
                            | KVM_VGIC_V2_ADDR_TYPE_DIST,
                            KVM_DEV_ARM_VGIC_GRP_ADDR,
                            KVM_VGIC_V2_ADDR_TYPE_DIST,
                            s->dev_fd);
    /* CPU interface for current core. Unlike arm_gic, we don't
     * provide the "interface for core #N" memory regions, because
     * cores with a VGIC don't have those.
     */
    kvm_arm_register_device(&s->cpuiomem[0],
                            (KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)
                            | KVM_VGIC_V2_ADDR_TYPE_CPU,
                            KVM_DEV_ARM_VGIC_GRP_ADDR,
                            KVM_VGIC_V2_ADDR_TYPE_CPU,
                            s->dev_fd);

    if (!kvm_arm_gic_can_save_restore(s)) {
        error_setg(&s->migration_blocker, "This operating system kernel does "
                                          "not support vGICv2 migration");
        migrate_add_blocker(s->migration_blocker);
    }
}

static void kvm_arm_gic_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    ARMGICCommonClass *agcc = ARM_GIC_COMMON_CLASS(klass);
    KVMARMGICClass *kgc = KVM_ARM_GIC_CLASS(klass);

    agcc->pre_save = kvm_arm_gic_get;
    agcc->post_load = kvm_arm_gic_put;
    kgc->parent_realize = dc->realize;
    kgc->parent_reset = dc->reset;
    dc->realize = kvm_arm_gic_realize;
    dc->reset = kvm_arm_gic_reset;
}

static const TypeInfo kvm_arm_gic_info = {
    .name = TYPE_KVM_ARM_GIC,
    .parent = TYPE_ARM_GIC_COMMON,
    .instance_size = sizeof(GICState),
    .class_init = kvm_arm_gic_class_init,
    .class_size = sizeof(KVMARMGICClass),
};

static void kvm_arm_gic_register_types(void)
{
    type_register_static(&kvm_arm_gic_info);
}

type_init(kvm_arm_gic_register_types)
Commit	Line	Data
ed466761 PM	1	/*
	2	* ARM Generic Interrupt Controller using KVM in-kernel support
	3	*
	4	* Copyright (c) 2012 Linaro Limited
	5	* Written by Peter Maydell
855011be	6	* Save/Restore logic added by Christoffer Dall.
ed466761 PM	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation, either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License along
	19	* with this program; if not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
8ef94f0b	22	#include "qemu/osdep.h"
da34e65c	23	#include "qapi/error.h"
ed466761	24	#include "hw/sysbus.h"
24182fbc	25	#include "migration/migration.h"
ed466761 PM	26	#include "sysemu/kvm.h"
ed466761 PM	27	#include "kvm_arm.h"
47b43a1f	28	#include "gic_internal.h"
4b3cfe72	29	#include "vgic_common.h"
ed466761	30
855011be CD	31	//#define DEBUG_GIC_KVM
	32
	33	#ifdef DEBUG_GIC_KVM
	34	static const int debug_gic_kvm = 1;
	35	#else
	36	static const int debug_gic_kvm = 0;
	37	#endif
	38
	39	#define DPRINTF(fmt, ...) do { \
	40	if (debug_gic_kvm) { \
	41	printf("arm_gic: " fmt , ## __VA_ARGS__); \
	42	} \
	43	} while (0)
	44
ed466761 PM	45	#define TYPE_KVM_ARM_GIC "kvm-arm-gic"
	46	#define KVM_ARM_GIC(obj) \
	47	OBJECT_CHECK(GICState, (obj), TYPE_KVM_ARM_GIC)
	48	#define KVM_ARM_GIC_CLASS(klass) \
	49	OBJECT_CLASS_CHECK(KVMARMGICClass, (klass), TYPE_KVM_ARM_GIC)
	50	#define KVM_ARM_GIC_GET_CLASS(obj) \
	51	OBJECT_GET_CLASS(KVMARMGICClass, (obj), TYPE_KVM_ARM_GIC)
	52
	53	typedef struct KVMARMGICClass {
	54	ARMGICCommonClass parent_class;
	55	DeviceRealize parent_realize;
	56	void (parent_reset)(DeviceState dev);
	57	} KVMARMGICClass;
	58
4b3cfe72	59	void kvm_arm_gic_set_irq(uint32_t num_irq, int irq, int level)
ed466761 PM	60	{
	61	/* Meaning of the 'irq' parameter:
	62	* [0..N-1] : external interrupts
	63	* [N..N+31] : PPI (internal) interrupts for CPU 0
	64	* [N+32..N+63] : PPI (internal interrupts for CPU 1
	65	* ...
	66	* Convert this to the kernel's desired encoding, which
	67	* has separate fields in the irq number for type,
	68	* CPU number and interrupt number.
	69	*/
ed466761 PM	70	int kvm_irq, irqtype, cpu;
ed466761 PM	71
4b3cfe72	72	if (irq < (num_irq - GIC_INTERNAL)) {
ed466761 PM	73	/* External interrupt. The kernel numbers these like the GIC
	74	* hardware, with external interrupt IDs starting after the
	75	* internal ones.
	76	*/
	77	irqtype = KVM_ARM_IRQ_TYPE_SPI;
	78	cpu = 0;
	79	irq += GIC_INTERNAL;
	80	} else {
	81	/* Internal interrupt: decode into (cpu, interrupt id) */
	82	irqtype = KVM_ARM_IRQ_TYPE_PPI;
4b3cfe72	83	irq -= (num_irq - GIC_INTERNAL);
ed466761 PM	84	cpu = irq / GIC_INTERNAL;
	85	irq %= GIC_INTERNAL;
	86	}
	87	kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT)
	88	\| (cpu << KVM_ARM_IRQ_VCPU_SHIFT) \| irq;
	89
	90	kvm_set_irq(kvm_state, kvm_irq, !!level);
	91	}
	92
4b3cfe72	93	static void kvm_arm_gicv2_set_irq(void *opaque, int irq, int level)
72149414	94	{
4b3cfe72	95	GICState s = (GICState )opaque;
72149414	96
4b3cfe72	97	kvm_arm_gic_set_irq(s->num_irq, irq, level);
72149414 PM	98	}
72149414 PM	99
4b3cfe72	100	static bool kvm_arm_gic_can_save_restore(GICState *s)
855011be	101	{
4b3cfe72	102	return s->dev_fd >= 0;
855011be CD	103	}
855011be CD	104
4b3cfe72 PF	105	#define KVM_VGIC_ATTR(offset, cpu) \
	106	((((uint64_t)(cpu) << KVM_DEV_ARM_VGIC_CPUID_SHIFT) & \
	107	KVM_DEV_ARM_VGIC_CPUID_MASK) \| \
	108	(((uint64_t)(offset) << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) & \
	109	KVM_DEV_ARM_VGIC_OFFSET_MASK))
	110
855011be CD	111	static void kvm_gicd_access(GICState *s, int offset, int cpu,
	112	uint32_t *val, bool write)
	113	{
4b3cfe72 PF	114	kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
4b3cfe72 PF	115	KVM_VGIC_ATTR(offset, cpu), val, write);
855011be CD	116	}
	117
	118	static void kvm_gicc_access(GICState *s, int offset, int cpu,
	119	uint32_t *val, bool write)
	120	{
4b3cfe72 PF	121	kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_REGS,
4b3cfe72 PF	122	KVM_VGIC_ATTR(offset, cpu), val, write);
855011be CD	123	}
	124
	125	#define for_each_irq_reg(_ctr, _max_irq, _field_width) \
	126	for (_ctr = 0; _ctr < ((_max_irq) / (32 / (_field_width))); _ctr++)
	127
	128	/*
	129	* Translate from the in-kernel field for an IRQ value to/from the qemu
	130	* representation.
	131	*/
	132	typedef void (vgic_translate_fn)(GICState s, int irq, int cpu,
	133	uint32_t *field, bool to_kernel);
	134
	135	/* synthetic translate function used for clear/set registers to completely
3b163b01	136	* clear a setting using a clear-register before setting the remaining bits
855011be CD	137	* using a set-register */
	138	static void translate_clear(GICState *s, int irq, int cpu,
	139	uint32_t *field, bool to_kernel)
	140	{
	141	if (to_kernel) {
	142	*field = ~0;
	143	} else {
	144	/* does not make sense: qemu model doesn't use set/clear regs */
	145	abort();
	146	}
	147	}
	148
eb8b9530 PM	149	static void translate_group(GICState *s, int irq, int cpu,
	150	uint32_t *field, bool to_kernel)
	151	{
	152	int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
	153
	154	if (to_kernel) {
	155	*field = GIC_TEST_GROUP(irq, cm);
	156	} else {
	157	if (*field & 1) {
	158	GIC_SET_GROUP(irq, cm);
	159	}
	160	}
	161	}
	162
855011be CD	163	static void translate_enabled(GICState *s, int irq, int cpu,
	164	uint32_t *field, bool to_kernel)
	165	{
	166	int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
	167
	168	if (to_kernel) {
	169	*field = GIC_TEST_ENABLED(irq, cm);
	170	} else {
	171	if (*field & 1) {
	172	GIC_SET_ENABLED(irq, cm);
	173	}
	174	}
	175	}
	176
	177	static void translate_pending(GICState *s, int irq, int cpu,
	178	uint32_t *field, bool to_kernel)
	179	{
	180	int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
	181
	182	if (to_kernel) {
	183	*field = gic_test_pending(s, irq, cm);
	184	} else {
	185	if (*field & 1) {
	186	GIC_SET_PENDING(irq, cm);
	187	/* TODO: Capture is level-line is held high in the kernel */
	188	}
	189	}
	190	}
	191
	192	static void translate_active(GICState *s, int irq, int cpu,
	193	uint32_t *field, bool to_kernel)
	194	{
	195	int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
	196
	197	if (to_kernel) {
	198	*field = GIC_TEST_ACTIVE(irq, cm);
	199	} else {
	200	if (*field & 1) {
	201	GIC_SET_ACTIVE(irq, cm);
	202	}
	203	}
	204	}
	205
	206	static void translate_trigger(GICState *s, int irq, int cpu,
	207	uint32_t *field, bool to_kernel)
	208	{
	209	if (to_kernel) {
	210	*field = (GIC_TEST_EDGE_TRIGGER(irq)) ? 0x2 : 0x0;
	211	} else {
	212	if (*field & 0x2) {
	213	GIC_SET_EDGE_TRIGGER(irq);
	214	}
	215	}
	216	}
	217
	218	static void translate_priority(GICState *s, int irq, int cpu,
	219	uint32_t *field, bool to_kernel)
	220	{
	221	if (to_kernel) {
	222	*field = GIC_GET_PRIORITY(irq, cpu) & 0xff;
	223	} else {
81508470	224	gic_set_priority(s, cpu, irq, *field & 0xff, MEMTXATTRS_UNSPECIFIED);
855011be CD	225	}
	226	}
	227
	228	static void translate_targets(GICState *s, int irq, int cpu,
	229	uint32_t *field, bool to_kernel)
	230	{
	231	if (to_kernel) {
	232	*field = s->irq_target[irq] & 0xff;
	233	} else {
	234	s->irq_target[irq] = *field & 0xff;
	235	}
	236	}
	237
	238	static void translate_sgisource(GICState *s, int irq, int cpu,
	239	uint32_t *field, bool to_kernel)
	240	{
	241	if (to_kernel) {
	242	*field = s->sgi_pending[irq][cpu] & 0xff;
	243	} else {
	244	s->sgi_pending[irq][cpu] = *field & 0xff;
	245	}
	246	}
	247
	248	/* Read a register group from the kernel VGIC */
	249	static void kvm_dist_get(GICState *s, uint32_t offset, int width,
	250	int maxirq, vgic_translate_fn translate_fn)
	251	{
	252	uint32_t reg;
	253	int i;
	254	int j;
	255	int irq;
	256	int cpu;
	257	int regsz = 32 / width; /* irqs per kernel register */
	258	uint32_t field;
	259
	260	for_each_irq_reg(i, maxirq, width) {
	261	irq = i * regsz;
	262	cpu = 0;
	263	while ((cpu < s->num_cpu && irq < GIC_INTERNAL) \|\| cpu == 0) {
	264	kvm_gicd_access(s, offset, cpu, &reg, false);
	265	for (j = 0; j < regsz; j++) {
	266	field = extract32(reg, j * width, width);
	267	translate_fn(s, irq + j, cpu, &field, false);
	268	}
	269
	270	cpu++;
	271	}
	272	offset += 4;
	273	}
	274	}
	275
	276	/* Write a register group to the kernel VGIC */
	277	static void kvm_dist_put(GICState *s, uint32_t offset, int width,
	278	int maxirq, vgic_translate_fn translate_fn)
	279	{
	280	uint32_t reg;
	281	int i;
	282	int j;
	283	int irq;
	284	int cpu;
	285	int regsz = 32 / width; /* irqs per kernel register */
	286	uint32_t field;
	287
	288	for_each_irq_reg(i, maxirq, width) {
289	irq = i * regsz;
290	cpu = 0;
291	while ((cpu < s->num_cpu && irq < GIC_INTERNAL) \|\| cpu == 0) {
292	reg = 0;
293	for (j = 0; j < regsz; j++) {
294	translate_fn(s, irq + j, cpu, &field, true);
295	reg = deposit32(reg, j * width, width, field);
296	}
297	kvm_gicd_access(s, offset, cpu, &reg, true);
298
299	cpu++;
300	}
301	offset += 4;
302	}
303	}
304
ed466761 PM	305	static void kvm_arm_gic_put(GICState *s)
ed466761 PM	306	{
855011be CD	307	uint32_t reg;
	308	int i;
	309	int cpu;
	310	int num_cpu;
	311	int num_irq;
	312
855011be CD	313	/* Note: We do the restore in a slightly different order than the save
	314	* (where the order doesn't matter and is simply ordered according to the
	315	* register offset values */
	316
	317	/*****************************************************************
	318	* Distributor State
	319	*/
	320
679aa175 FA	321	/* s->ctlr -> GICD_CTLR */
679aa175 FA	322	reg = s->ctlr;
855011be CD	323	kvm_gicd_access(s, 0x0, 0, &reg, true);
	324
	325	/* Sanity checking on GICD_TYPER and s->num_irq, s->num_cpu */
	326	kvm_gicd_access(s, 0x4, 0, &reg, false);
	327	num_irq = ((reg & 0x1f) + 1) * 32;
	328	num_cpu = ((reg & 0xe0) >> 5) + 1;
	329
	330	if (num_irq < s->num_irq) {
	331	fprintf(stderr, "Restoring %u IRQs, but kernel supports max %d\n",
	332	s->num_irq, num_irq);
	333	abort();
	334	} else if (num_cpu != s->num_cpu) {
	335	fprintf(stderr, "Restoring %u CPU interfaces, kernel only has %d\n",
	336	s->num_cpu, num_cpu);
	337	/* Did we not create the VCPUs in the kernel yet? */
	338	abort();
	339	}
	340
	341	/* TODO: Consider checking compatibility with the IIDR ? */
	342
	343	/* irq_state[n].enabled -> GICD_ISENABLERn */
	344	kvm_dist_put(s, 0x180, 1, s->num_irq, translate_clear);
	345	kvm_dist_put(s, 0x100, 1, s->num_irq, translate_enabled);
	346
eb8b9530 PM	347	/* irq_state[n].group -> GICD_IGROUPRn */
	348	kvm_dist_put(s, 0x80, 1, s->num_irq, translate_group);
	349
855011be CD	350	/* s->irq_target[irq] -> GICD_ITARGETSRn
	351	* (restore targets before pending to ensure the pending state is set on
	352	* the appropriate CPU interfaces in the kernel) */
	353	kvm_dist_put(s, 0x800, 8, s->num_irq, translate_targets);
	354
74fdb781 AB	355	/* irq_state[n].trigger -> GICD_ICFGRn
	356	* (restore configuration registers before pending IRQs so we treat
	357	* level/edge correctly) */
	358	kvm_dist_put(s, 0xc00, 2, s->num_irq, translate_trigger);
	359
855011be CD	360	/* irq_state[n].pending + irq_state[n].level -> GICD_ISPENDRn */
	361	kvm_dist_put(s, 0x280, 1, s->num_irq, translate_clear);
	362	kvm_dist_put(s, 0x200, 1, s->num_irq, translate_pending);
	363
	364	/* irq_state[n].active -> GICD_ISACTIVERn */
	365	kvm_dist_put(s, 0x380, 1, s->num_irq, translate_clear);
	366	kvm_dist_put(s, 0x300, 1, s->num_irq, translate_active);
	367
855011be CD	368
	369	/* s->priorityX[irq] -> ICD_IPRIORITYRn */
	370	kvm_dist_put(s, 0x400, 8, s->num_irq, translate_priority);
	371
	372	/* s->sgi_pending -> ICD_CPENDSGIRn */
	373	kvm_dist_put(s, 0xf10, 8, GIC_NR_SGIS, translate_clear);
	374	kvm_dist_put(s, 0xf20, 8, GIC_NR_SGIS, translate_sgisource);
	375
	376
	377	/*****************************************************************
	378	* CPU Interface(s) State
	379	*/
	380
	381	for (cpu = 0; cpu < s->num_cpu; cpu++) {
32951860 FA	382	/* s->cpu_ctlr[cpu] -> GICC_CTLR */
32951860 FA	383	reg = s->cpu_ctlr[cpu];
855011be CD	384	kvm_gicc_access(s, 0x00, cpu, &reg, true);
	385
	386	/* s->priority_mask[cpu] -> GICC_PMR */
	387	reg = (s->priority_mask[cpu] & 0xff);
	388	kvm_gicc_access(s, 0x04, cpu, &reg, true);
	389
	390	/* s->bpr[cpu] -> GICC_BPR */
	391	reg = (s->bpr[cpu] & 0x7);
	392	kvm_gicc_access(s, 0x08, cpu, &reg, true);
	393
	394	/* s->abpr[cpu] -> GICC_ABPR */
	395	reg = (s->abpr[cpu] & 0x7);
	396	kvm_gicc_access(s, 0x1c, cpu, &reg, true);
	397
	398	/* s->apr[n][cpu] -> GICC_APRn */
	399	for (i = 0; i < 4; i++) {
	400	reg = s->apr[i][cpu];
	401	kvm_gicc_access(s, 0xd0 + i * 4, cpu, &reg, true);
	402	}
	403	}
ed466761 PM	404	}
	405
	406	static void kvm_arm_gic_get(GICState *s)
	407	{
855011be CD	408	uint32_t reg;
	409	int i;
	410	int cpu;
	411
855011be CD	412	/*****************************************************************
	413	* Distributor State
	414	*/
	415
679aa175	416	/* GICD_CTLR -> s->ctlr */
855011be	417	kvm_gicd_access(s, 0x0, 0, &reg, false);
679aa175	418	s->ctlr = reg;
855011be CD	419
	420	/* Sanity checking on GICD_TYPER -> s->num_irq, s->num_cpu */
	421	kvm_gicd_access(s, 0x4, 0, &reg, false);
	422	s->num_irq = ((reg & 0x1f) + 1) * 32;
	423	s->num_cpu = ((reg & 0xe0) >> 5) + 1;
	424
	425	if (s->num_irq > GIC_MAXIRQ) {
	426	fprintf(stderr, "Too many IRQs reported from the kernel: %d\n",
	427	s->num_irq);
	428	abort();
	429	}
	430
	431	/* GICD_IIDR -> ? */
	432	kvm_gicd_access(s, 0x8, 0, &reg, false);
	433
855011be CD	434	/* Clear all the IRQ settings */
	435	for (i = 0; i < s->num_irq; i++) {
	436	memset(&s->irq_state[i], 0, sizeof(s->irq_state[0]));
	437	}
	438
eb8b9530 PM	439	/* GICD_IGROUPRn -> irq_state[n].group */
	440	kvm_dist_get(s, 0x80, 1, s->num_irq, translate_group);
	441
855011be CD	442	/* GICD_ISENABLERn -> irq_state[n].enabled */
	443	kvm_dist_get(s, 0x100, 1, s->num_irq, translate_enabled);
	444
	445	/* GICD_ISPENDRn -> irq_state[n].pending + irq_state[n].level */
	446	kvm_dist_get(s, 0x200, 1, s->num_irq, translate_pending);
	447
	448	/* GICD_ISACTIVERn -> irq_state[n].active */
	449	kvm_dist_get(s, 0x300, 1, s->num_irq, translate_active);
	450
	451	/* GICD_ICFRn -> irq_state[n].trigger */
	452	kvm_dist_get(s, 0xc00, 2, s->num_irq, translate_trigger);
	453
	454	/* GICD_IPRIORITYRn -> s->priorityX[irq] */
	455	kvm_dist_get(s, 0x400, 8, s->num_irq, translate_priority);
	456
	457	/* GICD_ITARGETSRn -> s->irq_target[irq] */
	458	kvm_dist_get(s, 0x800, 8, s->num_irq, translate_targets);
	459
	460	/* GICD_CPENDSGIRn -> s->sgi_pending */
	461	kvm_dist_get(s, 0xf10, 8, GIC_NR_SGIS, translate_sgisource);
	462
	463
	464	/*****************************************************************
	465	* CPU Interface(s) State
	466	*/
	467
	468	for (cpu = 0; cpu < s->num_cpu; cpu++) {
32951860	469	/* GICC_CTLR -> s->cpu_ctlr[cpu] */
855011be	470	kvm_gicc_access(s, 0x00, cpu, &reg, false);
32951860	471	s->cpu_ctlr[cpu] = reg;
855011be CD	472
	473	/* GICC_PMR -> s->priority_mask[cpu] */
	474	kvm_gicc_access(s, 0x04, cpu, &reg, false);
	475	s->priority_mask[cpu] = (reg & 0xff);
	476
	477	/* GICC_BPR -> s->bpr[cpu] */
	478	kvm_gicc_access(s, 0x08, cpu, &reg, false);
	479	s->bpr[cpu] = (reg & 0x7);
	480
	481	/* GICC_ABPR -> s->abpr[cpu] */
	482	kvm_gicc_access(s, 0x1c, cpu, &reg, false);
	483	s->abpr[cpu] = (reg & 0x7);
	484
	485	/* GICC_APRn -> s->apr[n][cpu] */
	486	for (i = 0; i < 4; i++) {
	487	kvm_gicc_access(s, 0xd0 + i * 4, cpu, &reg, false);
	488	s->apr[i][cpu] = reg;
	489	}
	490	}
ed466761 PM	491	}
	492
	493	static void kvm_arm_gic_reset(DeviceState *dev)
	494	{
	495	GICState *s = ARM_GIC_COMMON(dev);
	496	KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
	497
	498	kgc->parent_reset(dev);
24182fbc PF	499
	500	if (kvm_arm_gic_can_save_restore(s)) {
	501	kvm_arm_gic_put(s);
	502	}
ed466761 PM	503	}
	504
	505	static void kvm_arm_gic_realize(DeviceState dev, Error *errp)
	506	{
	507	int i;
	508	GICState *s = KVM_ARM_GIC(dev);
ed466761	509	KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
0175ba10	510	Error *local_err = NULL;
1da41cc1	511	int ret;
ed466761	512
0175ba10 MA	513	kgc->parent_realize(dev, &local_err);
	514	if (local_err) {
	515	error_propagate(errp, local_err);
ed466761 PM	516	return;
	517	}
	518
5543d1ab FA	519	if (s->security_extn) {
	520	error_setg(errp, "the in-kernel VGIC does not implement the "
	521	"security extensions");
	522	return;
	523	}
	524
4b3cfe72	525	gic_init_irqs_and_mmio(s, kvm_arm_gicv2_set_irq, NULL);
6a1a9cfa EA	526
	527	for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {
	528	qemu_irq irq = qdev_get_gpio_in(dev, i);
	529	kvm_irqchip_set_qemuirq_gsi(kvm_state, irq, i);
	530	}
	531
1da41cc1 CD	532	/* Try to create the device via the device control API */
	533	s->dev_fd = -1;
	534	ret = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V2, false);
	535	if (ret >= 0) {
	536	s->dev_fd = ret;
4b3cfe72 PF	537
	538	/* Newstyle API is used, we may have attributes */
	539	if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0)) {
	540	uint32_t numirqs = s->num_irq;
	541	kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0,
	542	&numirqs, true);
	543	}
	544	/* Tell the kernel to complete VGIC initialization now */
	545	if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
	546	KVM_DEV_ARM_VGIC_CTRL_INIT)) {
	547	kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
	548	KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true);
	549	}
1da41cc1 CD	550	} else if (ret != -ENODEV && ret != -ENOTSUP) {
	551	error_setg_errno(errp, -ret, "error creating in-kernel VGIC");
	552	return;
	553	}
	554
ed466761	555	/* Distributor */
ed466761 PM	556	kvm_arm_register_device(&s->iomem,
ed466761 PM	557	(KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)
1da41cc1 CD	558	\| KVM_VGIC_V2_ADDR_TYPE_DIST,
	559	KVM_DEV_ARM_VGIC_GRP_ADDR,
	560	KVM_VGIC_V2_ADDR_TYPE_DIST,
	561	s->dev_fd);
ed466761 PM	562	/* CPU interface for current core. Unlike arm_gic, we don't
	563	* provide the "interface for core #N" memory regions, because
	564	* cores with a VGIC don't have those.
	565	*/
ed466761 PM	566	kvm_arm_register_device(&s->cpuiomem[0],
ed466761 PM	567	(KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)
1da41cc1 CD	568	\| KVM_VGIC_V2_ADDR_TYPE_CPU,
	569	KVM_DEV_ARM_VGIC_GRP_ADDR,
	570	KVM_VGIC_V2_ADDR_TYPE_CPU,
	571	s->dev_fd);
24182fbc PF	572
	573	if (!kvm_arm_gic_can_save_restore(s)) {
	574	error_setg(&s->migration_blocker, "This operating system kernel does "
	575	"not support vGICv2 migration");
	576	migrate_add_blocker(s->migration_blocker);
	577	}
ed466761 PM	578	}
	579
	580	static void kvm_arm_gic_class_init(ObjectClass klass, void data)
	581	{
	582	DeviceClass *dc = DEVICE_CLASS(klass);
	583	ARMGICCommonClass *agcc = ARM_GIC_COMMON_CLASS(klass);
	584	KVMARMGICClass *kgc = KVM_ARM_GIC_CLASS(klass);
	585
	586	agcc->pre_save = kvm_arm_gic_get;
	587	agcc->post_load = kvm_arm_gic_put;
	588	kgc->parent_realize = dc->realize;
	589	kgc->parent_reset = dc->reset;
	590	dc->realize = kvm_arm_gic_realize;
	591	dc->reset = kvm_arm_gic_reset;
ed466761 PM	592	}
	593
	594	static const TypeInfo kvm_arm_gic_info = {
	595	.name = TYPE_KVM_ARM_GIC,
	596	.parent = TYPE_ARM_GIC_COMMON,
	597	.instance_size = sizeof(GICState),
	598	.class_init = kvm_arm_gic_class_init,
	599	.class_size = sizeof(KVMARMGICClass),
	600	};
	601
	602	static void kvm_arm_gic_register_types(void)
	603	{
	604	type_register_static(&kvm_arm_gic_info);
	605	}
	606
	607	type_init(kvm_arm_gic_register_types)