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[qemu.git] / hw / pxa2xx_lcd.c
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a171fe39
AZ		 1/*
2 * Intel XScale PXA255/270 LCDC emulation.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <[email protected]>
6 *
7 * This code is licensed under the GPLv2.
8 */
9
10#include "vl.h"
11
12typedef void (*drawfn)(uint32_t *, uint8_t *, const uint8_t *, int, int);
13
14struct pxa2xx_lcdc_s {
15 target_phys_addr_t base;
16 qemu_irq irq;
17 int irqlevel;
18
19 int invalidated;
20 DisplayState *ds;
21 drawfn *line_fn[2];
22 int dest_width;
23 int xres, yres;
24 int pal_for;
25 int transp;
26 enum {
27 pxa_lcdc_2bpp = 1,
28 pxa_lcdc_4bpp = 2,
29 pxa_lcdc_8bpp = 3,
30 pxa_lcdc_16bpp = 4,
31 pxa_lcdc_18bpp = 5,
32 pxa_lcdc_18pbpp = 6,
33 pxa_lcdc_19bpp = 7,
34 pxa_lcdc_19pbpp = 8,
35 pxa_lcdc_24bpp = 9,
36 pxa_lcdc_25bpp = 10,
37 } bpp;
38
39 uint32_t control[6];
40 uint32_t status[2];
41 uint32_t ovl1c[2];
42 uint32_t ovl2c[2];
43 uint32_t ccr;
44 uint32_t cmdcr;
45 uint32_t trgbr;
46 uint32_t tcr;
47 uint32_t liidr;
48 uint8_t bscntr;
49
50 struct {
51 target_phys_addr_t branch;
52 int up;
53 uint8_t palette[1024];
54 uint8_t pbuffer[1024];
55 void (*redraw)(struct pxa2xx_lcdc_s *s, uint8_t *fb,
56 int *miny, int *maxy);
57
58 target_phys_addr_t descriptor;
59 target_phys_addr_t source;
60 uint32_t id;
61 uint32_t command;
62 } dma_ch[7];
63
64 void (*vsync_cb)(void *opaque);
65 void *opaque;
66 int orientation;
67};
68
69struct __attribute__ ((__packed__)) pxa_frame_descriptor_s {
70 uint32_t fdaddr;
71 uint32_t fsaddr;
72 uint32_t fidr;
73 uint32_t ldcmd;
74};
75
76#define LCCR0 0x000 /* LCD Controller Control register 0 */
77#define LCCR1 0x004 /* LCD Controller Control register 1 */
78#define LCCR2 0x008 /* LCD Controller Control register 2 */
79#define LCCR3 0x00c /* LCD Controller Control register 3 */
80#define LCCR4 0x010 /* LCD Controller Control register 4 */
81#define LCCR5 0x014 /* LCD Controller Control register 5 */
82
83#define FBR0 0x020 /* DMA Channel 0 Frame Branch register */
84#define FBR1 0x024 /* DMA Channel 1 Frame Branch register */
85#define FBR2 0x028 /* DMA Channel 2 Frame Branch register */
86#define FBR3 0x02c /* DMA Channel 3 Frame Branch register */
87#define FBR4 0x030 /* DMA Channel 4 Frame Branch register */
88#define FBR5 0x110 /* DMA Channel 5 Frame Branch register */
89#define FBR6 0x114 /* DMA Channel 6 Frame Branch register */
90
91#define LCSR1 0x034 /* LCD Controller Status register 1 */
92#define LCSR0 0x038 /* LCD Controller Status register 0 */
93#define LIIDR 0x03c /* LCD Controller Interrupt ID register */
94
95#define TRGBR 0x040 /* TMED RGB Seed register */
96#define TCR 0x044 /* TMED Control register */
97
98#define OVL1C1 0x050 /* Overlay 1 Control register 1 */
99#define OVL1C2 0x060 /* Overlay 1 Control register 2 */
100#define OVL2C1 0x070 /* Overlay 2 Control register 1 */
101#define OVL2C2 0x080 /* Overlay 2 Control register 2 */
102#define CCR 0x090 /* Cursor Control register */
103
104#define CMDCR 0x100 /* Command Control register */
105#define PRSR 0x104 /* Panel Read Status register */
106
107#define PXA_LCDDMA_CHANS 7
108#define DMA_FDADR 0x00 /* Frame Descriptor Address register */
109#define DMA_FSADR 0x04 /* Frame Source Address register */
110#define DMA_FIDR 0x08 /* Frame ID register */
111#define DMA_LDCMD 0x0c /* Command register */
112
113/* LCD Buffer Strength Control register */
114#define BSCNTR 0x04000054
115
116/* Bitfield masks */
117#define LCCR0_ENB (1 << 0)
118#define LCCR0_CMS (1 << 1)
119#define LCCR0_SDS (1 << 2)
120#define LCCR0_LDM (1 << 3)
121#define LCCR0_SOFM0 (1 << 4)
122#define LCCR0_IUM (1 << 5)
123#define LCCR0_EOFM0 (1 << 6)
124#define LCCR0_PAS (1 << 7)
125#define LCCR0_DPD (1 << 9)
126#define LCCR0_DIS (1 << 10)
127#define LCCR0_QDM (1 << 11)
128#define LCCR0_PDD (0xff << 12)
129#define LCCR0_BSM0 (1 << 20)
130#define LCCR0_OUM (1 << 21)
131#define LCCR0_LCDT (1 << 22)
132#define LCCR0_RDSTM (1 << 23)
133#define LCCR0_CMDIM (1 << 24)
134#define LCCR0_OUC (1 << 25)
135#define LCCR0_LDDALT (1 << 26)
136#define LCCR1_PPL(x) ((x) & 0x3ff)
137#define LCCR2_LPP(x) ((x) & 0x3ff)
138#define LCCR3_API (15 << 16)
139#define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8))
140#define LCCR3_PDFOR(x) (((x) >> 30) & 3)
141#define LCCR4_K1(x) (((x) >> 0) & 7)
142#define LCCR4_K2(x) (((x) >> 3) & 7)
143#define LCCR4_K3(x) (((x) >> 6) & 7)
144#define LCCR4_PALFOR(x) (((x) >> 15) & 3)
145#define LCCR5_SOFM(ch) (1 << (ch - 1))
146#define LCCR5_EOFM(ch) (1 << (ch + 7))
147#define LCCR5_BSM(ch) (1 << (ch + 15))
148#define LCCR5_IUM(ch) (1 << (ch + 23))
149#define OVLC1_EN (1 << 31)
150#define CCR_CEN (1 << 31)
151#define FBR_BRA (1 << 0)
152#define FBR_BINT (1 << 1)
153#define FBR_SRCADDR (0xfffffff << 4)
154#define LCSR0_LDD (1 << 0)
155#define LCSR0_SOF0 (1 << 1)
156#define LCSR0_BER (1 << 2)
157#define LCSR0_ABC (1 << 3)
158#define LCSR0_IU0 (1 << 4)
159#define LCSR0_IU1 (1 << 5)
160#define LCSR0_OU (1 << 6)
161#define LCSR0_QD (1 << 7)
162#define LCSR0_EOF0 (1 << 8)
163#define LCSR0_BS0 (1 << 9)
164#define LCSR0_SINT (1 << 10)
165#define LCSR0_RDST (1 << 11)
166#define LCSR0_CMDINT (1 << 12)
167#define LCSR0_BERCH(x) (((x) & 7) << 28)
168#define LCSR1_SOF(ch) (1 << (ch - 1))
169#define LCSR1_EOF(ch) (1 << (ch + 7))
170#define LCSR1_BS(ch) (1 << (ch + 15))
171#define LCSR1_IU(ch) (1 << (ch + 23))
172#define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
173#define LDCMD_EOFINT (1 << 21)
174#define LDCMD_SOFINT (1 << 22)
175#define LDCMD_PAL (1 << 26)
176
177/* Route internal interrupt lines to the global IC */
178static void pxa2xx_lcdc_int_update(struct pxa2xx_lcdc_s *s)
179{
180 int level = 0;
181 level |= (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LDM);
182 level |= (s->status[0] & LCSR0_SOF0) && !(s->control[0] & LCCR0_SOFM0);
183 level |= (s->status[0] & LCSR0_IU0) && !(s->control[0] & LCCR0_IUM);
184 level |= (s->status[0] & LCSR0_IU1) && !(s->control[5] & LCCR5_IUM(1));
185 level |= (s->status[0] & LCSR0_OU) && !(s->control[0] & LCCR0_OUM);
186 level |= (s->status[0] & LCSR0_QD) && !(s->control[0] & LCCR0_QDM);
187 level |= (s->status[0] & LCSR0_EOF0) && !(s->control[0] & LCCR0_EOFM0);
188 level |= (s->status[0] & LCSR0_BS0) && !(s->control[0] & LCCR0_BSM0);
189 level |= (s->status[0] & LCSR0_RDST) && !(s->control[0] & LCCR0_RDSTM);
190 level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM);
191 level |= (s->status[1] & ~s->control[5]);
192
193 qemu_set_irq(s->irq, !!level);
194 s->irqlevel = level;
195}
196
197/* Set Branch Status interrupt high and poke associated registers */
198static inline void pxa2xx_dma_bs_set(struct pxa2xx_lcdc_s *s, int ch)
199{
200 int unmasked;
201 if (ch == 0) {
202 s->status[0] |= LCSR0_BS0;
203 unmasked = !(s->control[0] & LCCR0_BSM0);
204 } else {
205 s->status[1] |= LCSR1_BS(ch);
206 unmasked = !(s->control[5] & LCCR5_BSM(ch));
207 }
208
209 if (unmasked) {
210 if (s->irqlevel)
211 s->status[0] |= LCSR0_SINT;
212 else
213 s->liidr = s->dma_ch[ch].id;
214 }
215}
216
217/* Set Start Of Frame Status interrupt high and poke associated registers */
218static inline void pxa2xx_dma_sof_set(struct pxa2xx_lcdc_s *s, int ch)
219{
220 int unmasked;
221 if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
222 return;
223
224 if (ch == 0) {
225 s->status[0] |= LCSR0_SOF0;
226 unmasked = !(s->control[0] & LCCR0_SOFM0);
227 } else {
228 s->status[1] |= LCSR1_SOF(ch);
229 unmasked = !(s->control[5] & LCCR5_SOFM(ch));
230 }
231
232 if (unmasked) {
233 if (s->irqlevel)
234 s->status[0] |= LCSR0_SINT;
235 else
236 s->liidr = s->dma_ch[ch].id;
237 }
238}
239
240/* Set End Of Frame Status interrupt high and poke associated registers */
241static inline void pxa2xx_dma_eof_set(struct pxa2xx_lcdc_s *s, int ch)
242{
243 int unmasked;
244 if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
245 return;
246
247 if (ch == 0) {
248 s->status[0] |= LCSR0_EOF0;
249 unmasked = !(s->control[0] & LCCR0_EOFM0);
250 } else {
251 s->status[1] |= LCSR1_EOF(ch);
252 unmasked = !(s->control[5] & LCCR5_EOFM(ch));
253 }
254
255 if (unmasked) {
256 if (s->irqlevel)
257 s->status[0] |= LCSR0_SINT;
258 else
259 s->liidr = s->dma_ch[ch].id;
260 }
261}
262
263/* Set Bus Error Status interrupt high and poke associated registers */
264static inline void pxa2xx_dma_ber_set(struct pxa2xx_lcdc_s *s, int ch)
265{
266 s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
267 if (s->irqlevel)
268 s->status[0] |= LCSR0_SINT;
269 else
270 s->liidr = s->dma_ch[ch].id;
271}
272
273/* Set Read Status interrupt high and poke associated registers */
274static inline void pxa2xx_dma_rdst_set(struct pxa2xx_lcdc_s *s)
275{
276 s->status[0] |= LCSR0_RDST;
277 if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM))
278 s->status[0] |= LCSR0_SINT;
279}
280
281/* Load new Frame Descriptors from DMA */
282static void pxa2xx_descriptor_load(struct pxa2xx_lcdc_s *s)
283{
284 struct pxa_frame_descriptor_s *desc[PXA_LCDDMA_CHANS];
285 target_phys_addr_t descptr;
286 int i;
287
288 for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
289 desc[i] = 0;
290 s->dma_ch[i].source = 0;
291
292 if (!s->dma_ch[i].up)
293 continue;
294
295 if (s->dma_ch[i].branch & FBR_BRA) {
296 descptr = s->dma_ch[i].branch & FBR_SRCADDR;
297 if (s->dma_ch[i].branch & FBR_BINT)
298 pxa2xx_dma_bs_set(s, i);
299 s->dma_ch[i].branch &= ~FBR_BRA;
300 } else
301 descptr = s->dma_ch[i].descriptor;
302
d95b2f8d
AZ		 303 if (!(descptr >= PXA2XX_SDRAM_BASE && descptr +
304 sizeof(*desc[i]) <= PXA2XX_SDRAM_BASE + phys_ram_size))
a171fe39
AZ		 305 continue;
306
d95b2f8d 307 descptr -= PXA2XX_SDRAM_BASE;
a171fe39
AZ		 308 desc[i] = (struct pxa_frame_descriptor_s *) (phys_ram_base + descptr);
309 s->dma_ch[i].descriptor = desc[i]->fdaddr;
310 s->dma_ch[i].source = desc[i]->fsaddr;
311 s->dma_ch[i].id = desc[i]->fidr;
312 s->dma_ch[i].command = desc[i]->ldcmd;
313 }
314}
315
316static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset)
317{
318 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
319 int ch;
320 offset -= s->base;
321
322 switch (offset) {
323 case LCCR0:
324 return s->control[0];
325 case LCCR1:
326 return s->control[1];
327 case LCCR2:
328 return s->control[2];
329 case LCCR3:
330 return s->control[3];
331 case LCCR4:
332 return s->control[4];
333 case LCCR5:
334 return s->control[5];
335
336 case OVL1C1:
337 return s->ovl1c[0];
338 case OVL1C2:
339 return s->ovl1c[1];
340 case OVL2C1:
341 return s->ovl2c[0];
342 case OVL2C2:
343 return s->ovl2c[1];
344
345 case CCR:
346 return s->ccr;
347
348 case CMDCR:
349 return s->cmdcr;
350
351 case TRGBR:
352 return s->trgbr;
353 case TCR:
354 return s->tcr;
355
356 case 0x200 ... 0x1000: /* DMA per-channel registers */
357 ch = (offset - 0x200) >> 4;
358 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
359 goto fail;
360
361 switch (offset & 0xf) {
362 case DMA_FDADR:
363 return s->dma_ch[ch].descriptor;
364 case DMA_FSADR:
365 return s->dma_ch[ch].source;
366 case DMA_FIDR:
367 return s->dma_ch[ch].id;
368 case DMA_LDCMD:
369 return s->dma_ch[ch].command;
370 default:
371 goto fail;
372 }
373
374 case FBR0:
375 return s->dma_ch[0].branch;
376 case FBR1:
377 return s->dma_ch[1].branch;
378 case FBR2:
379 return s->dma_ch[2].branch;
380 case FBR3:
381 return s->dma_ch[3].branch;
382 case FBR4:
383 return s->dma_ch[4].branch;
384 case FBR5:
385 return s->dma_ch[5].branch;
386 case FBR6:
387 return s->dma_ch[6].branch;
388
389 case BSCNTR:
390 return s->bscntr;
391
392 case PRSR:
393 return 0;
394
395 case LCSR0:
396 return s->status[0];
397 case LCSR1:
398 return s->status[1];
399 case LIIDR:
400 return s->liidr;
401
402 default:
403 fail:
404 cpu_abort(cpu_single_env,
405 "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
406 }
407
408 return 0;
409}
410
411static void pxa2xx_lcdc_write(void *opaque,
412 target_phys_addr_t offset, uint32_t value)
413{
414 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
415 int ch;
416 offset -= s->base;
417
418 switch (offset) {
419 case LCCR0:
420 /* ACK Quick Disable done */
421 if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB))
422 s->status[0] |= LCSR0_QD;
423
424 if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT))
425 printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
426
427 if ((s->control[3] & LCCR3_API) &&
428 (value & LCCR0_ENB) && !(value & LCCR0_LCDT))
429 s->status[0] |= LCSR0_ABC;
430
431 s->control[0] = value & 0x07ffffff;
432 pxa2xx_lcdc_int_update(s);
433
434 s->dma_ch[0].up = !!(value & LCCR0_ENB);
435 s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS);
436 break;
437
438 case LCCR1:
439 s->control[1] = value;
440 break;
441
442 case LCCR2:
443 s->control[2] = value;
444 break;
445
446 case LCCR3:
447 s->control[3] = value & 0xefffffff;
448 s->bpp = LCCR3_BPP(value);
449 break;
450
451 case LCCR4:
452 s->control[4] = value & 0x83ff81ff;
453 break;
454
455 case LCCR5:
456 s->control[5] = value & 0x3f3f3f3f;
457 break;
458
459 case OVL1C1:
460 if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN))
461 printf("%s: Overlay 1 not supported\n", __FUNCTION__);
462
463 s->ovl1c[0] = value & 0x80ffffff;
464 s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS);
465 break;
466
467 case OVL1C2:
468 s->ovl1c[1] = value & 0x000fffff;
469 break;
470
471 case OVL2C1:
472 if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN))
473 printf("%s: Overlay 2 not supported\n", __FUNCTION__);
474
475 s->ovl2c[0] = value & 0x80ffffff;
476 s->dma_ch[2].up = !!(value & OVLC1_EN);
477 s->dma_ch[3].up = !!(value & OVLC1_EN);
478 s->dma_ch[4].up = !!(value & OVLC1_EN);
479 break;
480
481 case OVL2C2:
482 s->ovl2c[1] = value & 0x007fffff;
483 break;
484
485 case CCR:
486 if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
487 printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
488
489 s->ccr = value & 0x81ffffe7;
490 s->dma_ch[5].up = !!(value & CCR_CEN);
491 break;
492
493 case CMDCR:
494 s->cmdcr = value & 0xff;
495 break;
496
497 case TRGBR:
498 s->trgbr = value & 0x00ffffff;
499 break;
500
501 case TCR:
502 s->tcr = value & 0x7fff;
503 break;
504
505 case 0x200 ... 0x1000: /* DMA per-channel registers */
506 ch = (offset - 0x200) >> 4;
507 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
508 goto fail;
509
510 switch (offset & 0xf) {
511 case DMA_FDADR:
512 s->dma_ch[ch].descriptor = value & 0xfffffff0;
513 break;
514
515 default:
516 goto fail;
517 }
518 break;
519
520 case FBR0:
521 s->dma_ch[0].branch = value & 0xfffffff3;
522 break;
523 case FBR1:
524 s->dma_ch[1].branch = value & 0xfffffff3;
525 break;
526 case FBR2:
527 s->dma_ch[2].branch = value & 0xfffffff3;
528 break;
529 case FBR3:
530 s->dma_ch[3].branch = value & 0xfffffff3;
531 break;
532 case FBR4:
533 s->dma_ch[4].branch = value & 0xfffffff3;
534 break;
535 case FBR5:
536 s->dma_ch[5].branch = value & 0xfffffff3;
537 break;
538 case FBR6:
539 s->dma_ch[6].branch = value & 0xfffffff3;
540 break;
541
542 case BSCNTR:
543 s->bscntr = value & 0xf;
544 break;
545
546 case PRSR:
547 break;
548
549 case LCSR0:
550 s->status[0] &= ~(value & 0xfff);
551 if (value & LCSR0_BER)
552 s->status[0] &= ~LCSR0_BERCH(7);
553 break;
554
555 case LCSR1:
556 s->status[1] &= ~(value & 0x3e3f3f);
557 break;
558
559 default:
560 fail:
561 cpu_abort(cpu_single_env,
562 "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
563 }
564}
565
566static CPUReadMemoryFunc *pxa2xx_lcdc_readfn[] = {
567 pxa2xx_lcdc_read,
568 pxa2xx_lcdc_read,
569 pxa2xx_lcdc_read
570};
571
572static CPUWriteMemoryFunc *pxa2xx_lcdc_writefn[] = {
573 pxa2xx_lcdc_write,
574 pxa2xx_lcdc_write,
575 pxa2xx_lcdc_write
576};
577
578static inline
579uint32_t rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
580{
581 return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
582}
583
584static inline
585uint32_t rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
586{
587 return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
588}
589
590static inline
591uint32_t rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
592{
593 return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
594}
595
596static inline
597uint32_t rgb_to_pixel24(unsigned int r, unsigned int g, unsigned b)
598{
599 return (r << 16) | (g << 8) | b;
600}
601
602static inline
603uint32_t rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
604{
605 return (r << 16) | (g << 8) | b;
606}
607
608/* Load new palette for a given DMA channel, convert to internal format */
609static void pxa2xx_palette_parse(struct pxa2xx_lcdc_s *s, int ch, int bpp)
610{
611 int i, n, format, r, g, b, alpha;
612 uint32_t *dest, *src;
613 s->pal_for = LCCR4_PALFOR(s->control[4]);
614 format = s->pal_for;
615
616 switch (bpp) {
617 case pxa_lcdc_2bpp:
618 n = 4;
619 break;
620 case pxa_lcdc_4bpp:
621 n = 16;
622 break;
623 case pxa_lcdc_8bpp:
624 n = 256;
625 break;
626 default:
627 format = 0;
628 return;
629 }
630
631 src = (uint32_t *) s->dma_ch[ch].pbuffer;
632 dest = (uint32_t *) s->dma_ch[ch].palette;
633 alpha = r = g = b = 0;
634
635 for (i = 0; i < n; i ++) {
636 switch (format) {
637 case 0: /* 16 bpp, no transparency */
638 alpha = 0;
639 if (s->control[0] & LCCR0_CMS)
640 r = g = b = *src & 0xff;
641 else {
642 r = (*src & 0xf800) >> 8;
643 g = (*src & 0x07e0) >> 3;
644 b = (*src & 0x001f) << 3;
645 }
646 break;
647 case 1: /* 16 bpp plus transparency */
648 alpha = *src & (1 << 24);
649 if (s->control[0] & LCCR0_CMS)
650 r = g = b = *src & 0xff;
651 else {
652 r = (*src & 0xf800) >> 8;
653 g = (*src & 0x07e0) >> 3;
654 b = (*src & 0x001f) << 3;
655 }
656 break;
657 case 2: /* 18 bpp plus transparency */
658 alpha = *src & (1 << 24);
659 if (s->control[0] & LCCR0_CMS)
660 r = g = b = *src & 0xff;
661 else {
662 r = (*src & 0xf80000) >> 16;
663 g = (*src & 0x00fc00) >> 8;
664 b = (*src & 0x0000f8);
665 }
666 break;
667 case 3: /* 24 bpp plus transparency */
668 alpha = *src & (1 << 24);
669 if (s->control[0] & LCCR0_CMS)
670 r = g = b = *src & 0xff;
671 else {
672 r = (*src & 0xff0000) >> 16;
673 g = (*src & 0x00ff00) >> 8;
674 b = (*src & 0x0000ff);
675 }
676 break;
677 }
678 switch (s->ds->depth) {
679 case 8:
680 *dest = rgb_to_pixel8(r, g, b) | alpha;
681 break;
682 case 15:
683 *dest = rgb_to_pixel15(r, g, b) | alpha;
684 break;
685 case 16:
686 *dest = rgb_to_pixel16(r, g, b) | alpha;
687 break;
688 case 24:
689 *dest = rgb_to_pixel24(r, g, b) | alpha;
690 break;
691 case 32:
692 *dest = rgb_to_pixel32(r, g, b) | alpha;
693 break;
694 }
695 src ++;
696 dest ++;
697 }
698}
699
700static void pxa2xx_lcdc_dma0_redraw_horiz(struct pxa2xx_lcdc_s *s,
701 uint8_t *fb, int *miny, int *maxy)
702{
703 int y, src_width, dest_width, dirty[2];
704 uint8_t *src, *dest;
705 ram_addr_t x, addr, new_addr, start, end;
706 drawfn fn = 0;
707 if (s->dest_width)
708 fn = s->line_fn[s->transp][s->bpp];
709 if (!fn)
710 return;
711
712 src = fb;
713 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
714 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
715 src_width *= 3;
716 else if (s->bpp > pxa_lcdc_16bpp)
717 src_width *= 4;
718 else if (s->bpp > pxa_lcdc_8bpp)
719 src_width *= 2;
720
721 dest = s->ds->data;
722 dest_width = s->xres * s->dest_width;
723
724 addr = (ram_addr_t) (fb - phys_ram_base);
725 start = addr + s->yres * src_width;
726 end = addr;
727 dirty[0] = dirty[1] = cpu_physical_memory_get_dirty(start, VGA_DIRTY_FLAG);
728 for (y = 0; y < s->yres; y ++) {
729 new_addr = addr + src_width;
730 for (x = addr + TARGET_PAGE_SIZE; x < new_addr;
731 x += TARGET_PAGE_SIZE) {
732 dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
733 dirty[0] |= dirty[1];
734 }
735 if (dirty[0] || s->invalidated) {
736 fn((uint32_t *) s->dma_ch[0].palette,
737 dest, src, s->xres, s->dest_width);
738 if (addr < start)
739 start = addr;
740 if (new_addr > end)
741 end = new_addr;
742 if (y < *miny)
743 *miny = y;
744 if (y >= *maxy)
745 *maxy = y + 1;
746 }
747 addr = new_addr;
748 dirty[0] = dirty[1];
749 src += src_width;
750 dest += dest_width;
751 }
752
753 if (end > start)
754 cpu_physical_memory_reset_dirty(start, end, VGA_DIRTY_FLAG);
755}
756
757static void pxa2xx_lcdc_dma0_redraw_vert(struct pxa2xx_lcdc_s *s,
758 uint8_t *fb, int *miny, int *maxy)
759{
760 int y, src_width, dest_width, dirty[2];
761 uint8_t *src, *dest;
762 ram_addr_t x, addr, new_addr, start, end;
763 drawfn fn = 0;
764 if (s->dest_width)
765 fn = s->line_fn[s->transp][s->bpp];
766 if (!fn)
767 return;
768
769 src = fb;
770 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
771 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
772 src_width *= 3;
773 else if (s->bpp > pxa_lcdc_16bpp)
774 src_width *= 4;
775 else if (s->bpp > pxa_lcdc_8bpp)
776 src_width *= 2;
777
778 dest_width = s->yres * s->dest_width;
779 dest = s->ds->data + dest_width * (s->xres - 1);
780
781 addr = (ram_addr_t) (fb - phys_ram_base);
782 start = addr + s->yres * src_width;
783 end = addr;
784 dirty[0] = dirty[1] = cpu_physical_memory_get_dirty(start, VGA_DIRTY_FLAG);
785 for (y = 0; y < s->yres; y ++) {
786 new_addr = addr + src_width;
787 for (x = addr + TARGET_PAGE_SIZE; x < new_addr;
788 x += TARGET_PAGE_SIZE) {
789 dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
790 dirty[0] |= dirty[1];
791 }
792 if (dirty[0] || s->invalidated) {
793 fn((uint32_t *) s->dma_ch[0].palette,
794 dest, src, s->xres, -dest_width);
795 if (addr < start)
796 start = addr;
797 if (new_addr > end)
798 end = new_addr;
799 if (y < *miny)
800 *miny = y;
801 if (y >= *maxy)
802 *maxy = y + 1;
803 }
804 addr = new_addr;
805 dirty[0] = dirty[1];
806 src += src_width;
807 dest += s->dest_width;
808 }
809
810 if (end > start)
811 cpu_physical_memory_reset_dirty(start, end, VGA_DIRTY_FLAG);
812}
813
814static void pxa2xx_lcdc_resize(struct pxa2xx_lcdc_s *s)
815{
816 int width, height;
817 if (!(s->control[0] & LCCR0_ENB))
818 return;
819
820 width = LCCR1_PPL(s->control[1]) + 1;
821 height = LCCR2_LPP(s->control[2]) + 1;
822
823 if (width != s->xres || height != s->yres) {
824 if (s->orientation)
825 dpy_resize(s->ds, height, width);
826 else
827 dpy_resize(s->ds, width, height);
828 s->invalidated = 1;
829 s->xres = width;
830 s->yres = height;
831 }
832}
833
834static void pxa2xx_update_display(void *opaque)
835{
836 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
837 uint8_t *fb;
838 target_phys_addr_t fbptr;
839 int miny, maxy;
840 int ch;
841 if (!(s->control[0] & LCCR0_ENB))
842 return;
843
844 pxa2xx_descriptor_load(s);
845
846 pxa2xx_lcdc_resize(s);
847 miny = s->yres;
848 maxy = 0;
849 s->transp = s->dma_ch[2].up || s->dma_ch[3].up;
850 /* Note: With overlay planes the order depends on LCCR0 bit 25. */
851 for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++)
852 if (s->dma_ch[ch].up) {
853 if (!s->dma_ch[ch].source) {
854 pxa2xx_dma_ber_set(s, ch);
855 continue;
856 }
857 fbptr = s->dma_ch[ch].source;
d95b2f8d
AZ		 858 if (!(fbptr >= PXA2XX_SDRAM_BASE &&
859 fbptr <= PXA2XX_SDRAM_BASE + phys_ram_size)) {
a171fe39
AZ		 860 pxa2xx_dma_ber_set(s, ch);
861 continue;
862 }
d95b2f8d 863 fbptr -= PXA2XX_SDRAM_BASE;
a171fe39
AZ		 864 fb = phys_ram_base + fbptr;
865
866 if (s->dma_ch[ch].command & LDCMD_PAL) {
867 memcpy(s->dma_ch[ch].pbuffer, fb,
868 MAX(LDCMD_LENGTH(s->dma_ch[ch].command),
869 sizeof(s->dma_ch[ch].pbuffer)));
870 pxa2xx_palette_parse(s, ch, s->bpp);
871 } else {
872 /* Do we need to reparse palette */
873 if (LCCR4_PALFOR(s->control[4]) != s->pal_for)
874 pxa2xx_palette_parse(s, ch, s->bpp);
875
876 /* ACK frame start */
877 pxa2xx_dma_sof_set(s, ch);
878
879 s->dma_ch[ch].redraw(s, fb, &miny, &maxy);
880 s->invalidated = 0;
881
882 /* ACK frame completed */
883 pxa2xx_dma_eof_set(s, ch);
884 }
885 }
886
887 if (s->control[0] & LCCR0_DIS) {
888 /* ACK last frame completed */
889 s->control[0] &= ~LCCR0_ENB;
890 s->status[0] |= LCSR0_LDD;
891 }
892
893 if (s->orientation)
894 dpy_update(s->ds, miny, 0, maxy, s->xres);
895 else
896 dpy_update(s->ds, 0, miny, s->xres, maxy);
897 pxa2xx_lcdc_int_update(s);
898
899 if (s->vsync_cb)
900 s->vsync_cb(s->opaque);
901}
902
903static void pxa2xx_invalidate_display(void *opaque)
904{
905 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
906 s->invalidated = 1;
907}
908
909static void pxa2xx_screen_dump(void *opaque, const char *filename)
910{
911 /* TODO */
912}
913
914void pxa2xx_lcdc_orientation(void *opaque, int angle)
915{
916 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
917
918 if (angle) {
919 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_vert;
920 } else {
921 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_horiz;
922 }
923
924 s->orientation = angle;
925 s->xres = s->yres = -1;
926 pxa2xx_lcdc_resize(s);
927}
928
929#define BITS 8
930#include "pxa2xx_template.h"
931#define BITS 15
932#include "pxa2xx_template.h"
933#define BITS 16
934#include "pxa2xx_template.h"
935#define BITS 24
936#include "pxa2xx_template.h"
937#define BITS 32
938#include "pxa2xx_template.h"
939
940struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq,
941 DisplayState *ds)
942{
943 int iomemtype;
944 struct pxa2xx_lcdc_s *s;
945
946 s = (struct pxa2xx_lcdc_s *) qemu_mallocz(sizeof(struct pxa2xx_lcdc_s));
947 s->base = base;
948 s->invalidated = 1;
949 s->irq = irq;
950 s->ds = ds;
951
952 pxa2xx_lcdc_orientation(s, graphic_rotate);
953
954 iomemtype = cpu_register_io_memory(0, pxa2xx_lcdc_readfn,
955 pxa2xx_lcdc_writefn, s);
956 cpu_register_physical_memory(base, 0x000fffff, iomemtype);
957
958 graphic_console_init(ds, pxa2xx_update_display,
959 pxa2xx_invalidate_display, pxa2xx_screen_dump, s);
960
961 switch (s->ds->depth) {
962 case 0:
963 s->dest_width = 0;
964 break;
965 case 8:
966 s->line_fn[0] = pxa2xx_draw_fn_8;
967 s->line_fn[1] = pxa2xx_draw_fn_8t;
968 s->dest_width = 1;
969 break;
970 case 15:
971 s->line_fn[0] = pxa2xx_draw_fn_15;
972 s->line_fn[1] = pxa2xx_draw_fn_15t;
973 s->dest_width = 2;
974 break;
975 case 16:
976 s->line_fn[0] = pxa2xx_draw_fn_16;
977 s->line_fn[1] = pxa2xx_draw_fn_16t;
978 s->dest_width = 2;
979 break;
980 case 24:
981 s->line_fn[0] = pxa2xx_draw_fn_24;
982 s->line_fn[1] = pxa2xx_draw_fn_24t;
983 s->dest_width = 3;
984 break;
985 case 32:
986 s->line_fn[0] = pxa2xx_draw_fn_32;
987 s->line_fn[1] = pxa2xx_draw_fn_32t;
988 s->dest_width = 4;
989 break;
990 default:
991 fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
992 exit(1);
993 }
994 return s;
995}
996
997void pxa2xx_lcd_vsync_cb(struct pxa2xx_lcdc_s *s,
998 void (*cb)(void *opaque), void *opaque) {
999 s->vsync_cb = cb;
1000 s->opaque = opaque;
1001}
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