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e3c2613f
FB		 1/*
2 * QEMU AMD PC-Net II (Am79C970A) emulation
5fafdf24 3 *
e3c2613f 4 * Copyright (c) 2004 Antony T Curtis
5fafdf24 5 *
e3c2613f
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
5fafdf24 24
e3c2613f
FB		 25/* This software was written to be compatible with the specification:
26 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
27 * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
28 */
5fafdf24 29
91cc0295
FB		 30/*
31 * On Sparc32, this is the Lance (Am7990) part of chip STP2000 (Master I/O), also
32 * produced as NCR89C100. See
33 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
34 * and
35 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt
36 */
37
83c9f4ca 38#include "hw/qdev.h"
1422e32d 39#include "net/net.h"
1de7afc9
PB		 40#include "qemu/timer.h"
41#include "qemu/sockets.h"
9c17d615 42#include "sysemu/sysemu.h"
15cae340 43#include "trace.h"
e3c2613f 44
47b43a1f 45#include "pcnet.h"
94e1a912 46
e3c2613f
FB		 47//#define PCNET_DEBUG
48//#define PCNET_DEBUG_IO
49//#define PCNET_DEBUG_BCR
50//#define PCNET_DEBUG_CSR
51//#define PCNET_DEBUG_RMD
52//#define PCNET_DEBUG_TMD
53//#define PCNET_DEBUG_MATCH
54
55
219fb125
FB		 56struct qemu_ether_header {
57 uint8_t ether_dhost[6];
58 uint8_t ether_shost[6];
59 uint16_t ether_type;
60};
61
e3c2613f
FB		 62#define CSR_INIT(S) !!(((S)->csr[0])&0x0001)
63#define CSR_STRT(S) !!(((S)->csr[0])&0x0002)
64#define CSR_STOP(S) !!(((S)->csr[0])&0x0004)
65#define CSR_TDMD(S) !!(((S)->csr[0])&0x0008)
66#define CSR_TXON(S) !!(((S)->csr[0])&0x0010)
67#define CSR_RXON(S) !!(((S)->csr[0])&0x0020)
68#define CSR_INEA(S) !!(((S)->csr[0])&0x0040)
9b94dc32 69#define CSR_BSWP(S) !!(((S)->csr[3])&0x0004)
e3c2613f
FB		 70#define CSR_LAPPEN(S) !!(((S)->csr[3])&0x0020)
71#define CSR_DXSUFLO(S) !!(((S)->csr[3])&0x0040)
72#define CSR_ASTRP_RCV(S) !!(((S)->csr[4])&0x0800)
73#define CSR_DPOLL(S) !!(((S)->csr[4])&0x1000)
74#define CSR_SPND(S) !!(((S)->csr[5])&0x0001)
75#define CSR_LTINTEN(S) !!(((S)->csr[5])&0x4000)
76#define CSR_TOKINTD(S) !!(((S)->csr[5])&0x8000)
77#define CSR_DRX(S) !!(((S)->csr[15])&0x0001)
78#define CSR_DTX(S) !!(((S)->csr[15])&0x0002)
79#define CSR_LOOP(S) !!(((S)->csr[15])&0x0004)
89b190a2 80#define CSR_DXMTFCS(S) !!(((S)->csr[15])&0x0008)
ef45c914 81#define CSR_INTL(S) !!(((S)->csr[15])&0x0040)
e3c2613f
FB		 82#define CSR_DRCVPA(S) !!(((S)->csr[15])&0x2000)
83#define CSR_DRCVBC(S) !!(((S)->csr[15])&0x4000)
84#define CSR_PROM(S) !!(((S)->csr[15])&0x8000)
85
86#define CSR_CRBC(S) ((S)->csr[40])
87#define CSR_CRST(S) ((S)->csr[41])
88#define CSR_CXBC(S) ((S)->csr[42])
89#define CSR_CXST(S) ((S)->csr[43])
90#define CSR_NRBC(S) ((S)->csr[44])
91#define CSR_NRST(S) ((S)->csr[45])
92#define CSR_POLL(S) ((S)->csr[46])
93#define CSR_PINT(S) ((S)->csr[47])
94#define CSR_RCVRC(S) ((S)->csr[72])
95#define CSR_XMTRC(S) ((S)->csr[74])
96#define CSR_RCVRL(S) ((S)->csr[76])
97#define CSR_XMTRL(S) ((S)->csr[78])
98#define CSR_MISSC(S) ((S)->csr[112])
99
366c9332
MB		 100#define CSR_IADR(S) ((S)->csr[ 1] | ((uint32_t)(S)->csr[ 2] << 16))
101#define CSR_CRBA(S) ((S)->csr[18] | ((uint32_t)(S)->csr[19] << 16))
102#define CSR_CXBA(S) ((S)->csr[20] | ((uint32_t)(S)->csr[21] << 16))
103#define CSR_NRBA(S) ((S)->csr[22] | ((uint32_t)(S)->csr[23] << 16))
104#define CSR_BADR(S) ((S)->csr[24] | ((uint32_t)(S)->csr[25] << 16))
105#define CSR_NRDA(S) ((S)->csr[26] | ((uint32_t)(S)->csr[27] << 16))
106#define CSR_CRDA(S) ((S)->csr[28] | ((uint32_t)(S)->csr[29] << 16))
107#define CSR_BADX(S) ((S)->csr[30] | ((uint32_t)(S)->csr[31] << 16))
108#define CSR_NXDA(S) ((S)->csr[32] | ((uint32_t)(S)->csr[33] << 16))
109#define CSR_CXDA(S) ((S)->csr[34] | ((uint32_t)(S)->csr[35] << 16))
110#define CSR_NNRD(S) ((S)->csr[36] | ((uint32_t)(S)->csr[37] << 16))
111#define CSR_NNXD(S) ((S)->csr[38] | ((uint32_t)(S)->csr[39] << 16))
112#define CSR_PXDA(S) ((S)->csr[60] | ((uint32_t)(S)->csr[61] << 16))
113#define CSR_NXBA(S) ((S)->csr[64] | ((uint32_t)(S)->csr[65] << 16))
e3c2613f
FB		 114
115#define PHYSADDR(S,A) \
366c9332 116 (BCR_SSIZE32(S) ? (A) : (A) | ((0xff00 & (uint32_t)(S)->csr[2])<<16))
e3c2613f
FB		 117
118struct pcnet_initblk16 {
119 uint16_t mode;
91cc0295
FB		 120 uint16_t padr[3];
121 uint16_t ladrf[4];
122 uint32_t rdra;
123 uint32_t tdra;
e3c2613f
FB		 124};
125
126struct pcnet_initblk32 {
127 uint16_t mode;
91cc0295
FB		 128 uint8_t rlen;
129 uint8_t tlen;
130 uint16_t padr[3];
e3c2613f 131 uint16_t _res;
91cc0295 132 uint16_t ladrf[4];
e3c2613f
FB		 133 uint32_t rdra;
134 uint32_t tdra;
135};
136
137struct pcnet_TMD {
6d2980f5
TS		 138 uint32_t tbadr;
139 int16_t length;
140 int16_t status;
141 uint32_t misc;
142 uint32_t res;
e3c2613f
FB		 143};
144
6d2980f5
TS		 145#define TMDL_BCNT_MASK 0x0fff
146#define TMDL_BCNT_SH 0
147#define TMDL_ONES_MASK 0xf000
148#define TMDL_ONES_SH 12
149
150#define TMDS_BPE_MASK 0x0080
151#define TMDS_BPE_SH 7
152#define TMDS_ENP_MASK 0x0100
153#define TMDS_ENP_SH 8
154#define TMDS_STP_MASK 0x0200
155#define TMDS_STP_SH 9
156#define TMDS_DEF_MASK 0x0400
157#define TMDS_DEF_SH 10
158#define TMDS_ONE_MASK 0x0800
159#define TMDS_ONE_SH 11
160#define TMDS_LTINT_MASK 0x1000
161#define TMDS_LTINT_SH 12
162#define TMDS_NOFCS_MASK 0x2000
163#define TMDS_NOFCS_SH 13
89b190a2
AJ		 164#define TMDS_ADDFCS_MASK TMDS_NOFCS_MASK
165#define TMDS_ADDFCS_SH TMDS_NOFCS_SH
6d2980f5
TS		 166#define TMDS_ERR_MASK 0x4000
167#define TMDS_ERR_SH 14
168#define TMDS_OWN_MASK 0x8000
169#define TMDS_OWN_SH 15
170
171#define TMDM_TRC_MASK 0x0000000f
172#define TMDM_TRC_SH 0
173#define TMDM_TDR_MASK 0x03ff0000
174#define TMDM_TDR_SH 16
175#define TMDM_RTRY_MASK 0x04000000
176#define TMDM_RTRY_SH 26
177#define TMDM_LCAR_MASK 0x08000000
178#define TMDM_LCAR_SH 27
179#define TMDM_LCOL_MASK 0x10000000
180#define TMDM_LCOL_SH 28
181#define TMDM_EXDEF_MASK 0x20000000
182#define TMDM_EXDEF_SH 29
183#define TMDM_UFLO_MASK 0x40000000
184#define TMDM_UFLO_SH 30
185#define TMDM_BUFF_MASK 0x80000000
186#define TMDM_BUFF_SH 31
187
e3c2613f 188struct pcnet_RMD {
6d2980f5
TS		 189 uint32_t rbadr;
190 int16_t buf_length;
191 int16_t status;
192 uint32_t msg_length;
193 uint32_t res;
e3c2613f
FB		 194};
195
6d2980f5
TS		 196#define RMDL_BCNT_MASK 0x0fff
197#define RMDL_BCNT_SH 0
198#define RMDL_ONES_MASK 0xf000
199#define RMDL_ONES_SH 12
200
201#define RMDS_BAM_MASK 0x0010
202#define RMDS_BAM_SH 4
203#define RMDS_LFAM_MASK 0x0020
204#define RMDS_LFAM_SH 5
205#define RMDS_PAM_MASK 0x0040
206#define RMDS_PAM_SH 6
207#define RMDS_BPE_MASK 0x0080
208#define RMDS_BPE_SH 7
209#define RMDS_ENP_MASK 0x0100
210#define RMDS_ENP_SH 8
211#define RMDS_STP_MASK 0x0200
212#define RMDS_STP_SH 9
213#define RMDS_BUFF_MASK 0x0400
214#define RMDS_BUFF_SH 10
215#define RMDS_CRC_MASK 0x0800
216#define RMDS_CRC_SH 11
217#define RMDS_OFLO_MASK 0x1000
218#define RMDS_OFLO_SH 12
219#define RMDS_FRAM_MASK 0x2000
220#define RMDS_FRAM_SH 13
221#define RMDS_ERR_MASK 0x4000
222#define RMDS_ERR_SH 14
223#define RMDS_OWN_MASK 0x8000
224#define RMDS_OWN_SH 15
225
226#define RMDM_MCNT_MASK 0x00000fff
227#define RMDM_MCNT_SH 0
228#define RMDM_ZEROS_MASK 0x0000f000
229#define RMDM_ZEROS_SH 12
230#define RMDM_RPC_MASK 0x00ff0000
231#define RMDM_RPC_SH 16
232#define RMDM_RCC_MASK 0xff000000
233#define RMDM_RCC_SH 24
234
235#define SET_FIELD(regp, name, field, value) \
236 (*(regp) = (*(regp) & ~(name ## _ ## field ## _MASK)) \
237 | ((value) << name ## _ ## field ## _SH))
238
239#define GET_FIELD(reg, name, field) \
240 (((reg) & name ## _ ## field ## _MASK) >> name ## _ ## field ## _SH)
241
242#define PRINT_TMD(T) printf( \
243 "TMD0 : TBADR=0x%08x\n" \
e3c2613f
FB		 244 "TMD1 : OWN=%d, ERR=%d, FCS=%d, LTI=%d, " \
245 "ONE=%d, DEF=%d, STP=%d, ENP=%d,\n" \
246 " BPE=%d, BCNT=%d\n" \
247 "TMD2 : BUF=%d, UFL=%d, EXD=%d, LCO=%d, " \
248 "LCA=%d, RTR=%d,\n" \
249 " TDR=%d, TRC=%d\n", \
6d2980f5
TS		 250 (T)->tbadr, \
251 GET_FIELD((T)->status, TMDS, OWN), \
252 GET_FIELD((T)->status, TMDS, ERR), \
253 GET_FIELD((T)->status, TMDS, NOFCS), \
254 GET_FIELD((T)->status, TMDS, LTINT), \
255 GET_FIELD((T)->status, TMDS, ONE), \
256 GET_FIELD((T)->status, TMDS, DEF), \
257 GET_FIELD((T)->status, TMDS, STP), \
258 GET_FIELD((T)->status, TMDS, ENP), \
259 GET_FIELD((T)->status, TMDS, BPE), \
260 4096-GET_FIELD((T)->length, TMDL, BCNT), \
261 GET_FIELD((T)->misc, TMDM, BUFF), \
262 GET_FIELD((T)->misc, TMDM, UFLO), \
263 GET_FIELD((T)->misc, TMDM, EXDEF), \
264 GET_FIELD((T)->misc, TMDM, LCOL), \
265 GET_FIELD((T)->misc, TMDM, LCAR), \
266 GET_FIELD((T)->misc, TMDM, RTRY), \
267 GET_FIELD((T)->misc, TMDM, TDR), \
268 GET_FIELD((T)->misc, TMDM, TRC))
269
270#define PRINT_RMD(R) printf( \
271 "RMD0 : RBADR=0x%08x\n" \
e3c2613f
FB		 272 "RMD1 : OWN=%d, ERR=%d, FRAM=%d, OFLO=%d, " \
273 "CRC=%d, BUFF=%d, STP=%d, ENP=%d,\n " \
6d2980f5 274 "BPE=%d, PAM=%d, LAFM=%d, BAM=%d, ONES=%d, BCNT=%d\n" \
e3c2613f 275 "RMD2 : RCC=%d, RPC=%d, MCNT=%d, ZEROS=%d\n", \
6d2980f5
TS		 276 (R)->rbadr, \
277 GET_FIELD((R)->status, RMDS, OWN), \
278 GET_FIELD((R)->status, RMDS, ERR), \
279 GET_FIELD((R)->status, RMDS, FRAM), \
280 GET_FIELD((R)->status, RMDS, OFLO), \
281 GET_FIELD((R)->status, RMDS, CRC), \
282 GET_FIELD((R)->status, RMDS, BUFF), \
283 GET_FIELD((R)->status, RMDS, STP), \
284 GET_FIELD((R)->status, RMDS, ENP), \
285 GET_FIELD((R)->status, RMDS, BPE), \
286 GET_FIELD((R)->status, RMDS, PAM), \
287 GET_FIELD((R)->status, RMDS, LFAM), \
288 GET_FIELD((R)->status, RMDS, BAM), \
289 GET_FIELD((R)->buf_length, RMDL, ONES), \
290 4096-GET_FIELD((R)->buf_length, RMDL, BCNT), \
291 GET_FIELD((R)->msg_length, RMDM, RCC), \
292 GET_FIELD((R)->msg_length, RMDM, RPC), \
293 GET_FIELD((R)->msg_length, RMDM, MCNT), \
294 GET_FIELD((R)->msg_length, RMDM, ZEROS))
295
296static inline void pcnet_tmd_load(PCNetState *s, struct pcnet_TMD *tmd,
a8170e5e 297 hwaddr addr)
e3c2613f 298{
6d2980f5
TS		 299 if (!BCR_SSIZE32(s)) {
300 struct {
301 uint32_t tbadr;
302 int16_t length;
303 int16_t status;
304 } xda;
305 s->phys_mem_read(s->dma_opaque, addr, (void *)&xda, sizeof(xda), 0);
306 tmd->tbadr = le32_to_cpu(xda.tbadr) & 0xffffff;
307 tmd->length = le16_to_cpu(xda.length);
308 tmd->status = (le32_to_cpu(xda.tbadr) >> 16) & 0xff00;
309 tmd->misc = le16_to_cpu(xda.status) << 16;
310 tmd->res = 0;
03c18475 311 } else {
6d2980f5
TS		 312 s->phys_mem_read(s->dma_opaque, addr, (void *)tmd, sizeof(*tmd), 0);
313 le32_to_cpus(&tmd->tbadr);
69b34976
TS		 314 le16_to_cpus((uint16_t *)&tmd->length);
315 le16_to_cpus((uint16_t *)&tmd->status);
6d2980f5
TS		 316 le32_to_cpus(&tmd->misc);
317 le32_to_cpus(&tmd->res);
318 if (BCR_SWSTYLE(s) == 3) {
319 uint32_t tmp = tmd->tbadr;
320 tmd->tbadr = tmd->misc;
321 tmd->misc = tmp;
03c18475 322 }
e3c2613f
FB		 323 }
324}
325
6d2980f5 326static inline void pcnet_tmd_store(PCNetState *s, const struct pcnet_TMD *tmd,
a8170e5e 327 hwaddr addr)
e3c2613f 328{
6d2980f5
TS		 329 if (!BCR_SSIZE32(s)) {
330 struct {
331 uint32_t tbadr;
332 int16_t length;
333 int16_t status;
334 } xda;
335 xda.tbadr = cpu_to_le32((tmd->tbadr & 0xffffff) |
336 ((tmd->status & 0xff00) << 16));
337 xda.length = cpu_to_le16(tmd->length);
338 xda.status = cpu_to_le16(tmd->misc >> 16);
339 s->phys_mem_write(s->dma_opaque, addr, (void *)&xda, sizeof(xda), 0);
03c18475 340 } else {
6d2980f5
TS		 341 struct {
342 uint32_t tbadr;
343 int16_t length;
344 int16_t status;
345 uint32_t misc;
346 uint32_t res;
347 } xda;
348 xda.tbadr = cpu_to_le32(tmd->tbadr);
349 xda.length = cpu_to_le16(tmd->length);
350 xda.status = cpu_to_le16(tmd->status);
351 xda.misc = cpu_to_le32(tmd->misc);
352 xda.res = cpu_to_le32(tmd->res);
353 if (BCR_SWSTYLE(s) == 3) {
354 uint32_t tmp = xda.tbadr;
355 xda.tbadr = xda.misc;
356 xda.misc = tmp;
03c18475 357 }
6d2980f5 358 s->phys_mem_write(s->dma_opaque, addr, (void *)&xda, sizeof(xda), 0);
e3c2613f
FB		 359 }
360}
361
6d2980f5 362static inline void pcnet_rmd_load(PCNetState *s, struct pcnet_RMD *rmd,
a8170e5e 363 hwaddr addr)
e3c2613f 364{
6d2980f5
TS		 365 if (!BCR_SSIZE32(s)) {
366 struct {
367 uint32_t rbadr;
368 int16_t buf_length;
369 int16_t msg_length;
370 } rda;
371 s->phys_mem_read(s->dma_opaque, addr, (void *)&rda, sizeof(rda), 0);
372 rmd->rbadr = le32_to_cpu(rda.rbadr) & 0xffffff;
373 rmd->buf_length = le16_to_cpu(rda.buf_length);
374 rmd->status = (le32_to_cpu(rda.rbadr) >> 16) & 0xff00;
375 rmd->msg_length = le16_to_cpu(rda.msg_length);
376 rmd->res = 0;
03c18475 377 } else {
6d2980f5
TS		 378 s->phys_mem_read(s->dma_opaque, addr, (void *)rmd, sizeof(*rmd), 0);
379 le32_to_cpus(&rmd->rbadr);
69b34976
TS		 380 le16_to_cpus((uint16_t *)&rmd->buf_length);
381 le16_to_cpus((uint16_t *)&rmd->status);
6d2980f5
TS		 382 le32_to_cpus(&rmd->msg_length);
383 le32_to_cpus(&rmd->res);
384 if (BCR_SWSTYLE(s) == 3) {
385 uint32_t tmp = rmd->rbadr;
386 rmd->rbadr = rmd->msg_length;
387 rmd->msg_length = tmp;
03c18475 388 }
e3c2613f
FB		 389 }
390}
391
6d2980f5 392static inline void pcnet_rmd_store(PCNetState *s, struct pcnet_RMD *rmd,
a8170e5e 393 hwaddr addr)
e3c2613f 394{
6d2980f5
TS		 395 if (!BCR_SSIZE32(s)) {
396 struct {
397 uint32_t rbadr;
398 int16_t buf_length;
399 int16_t msg_length;
400 } rda;
401 rda.rbadr = cpu_to_le32((rmd->rbadr & 0xffffff) |
402 ((rmd->status & 0xff00) << 16));
403 rda.buf_length = cpu_to_le16(rmd->buf_length);
404 rda.msg_length = cpu_to_le16(rmd->msg_length);
405 s->phys_mem_write(s->dma_opaque, addr, (void *)&rda, sizeof(rda), 0);
03c18475 406 } else {
6d2980f5
TS		 407 struct {
408 uint32_t rbadr;
409 int16_t buf_length;
410 int16_t status;
411 uint32_t msg_length;
412 uint32_t res;
413 } rda;
414 rda.rbadr = cpu_to_le32(rmd->rbadr);
415 rda.buf_length = cpu_to_le16(rmd->buf_length);
416 rda.status = cpu_to_le16(rmd->status);
417 rda.msg_length = cpu_to_le32(rmd->msg_length);
418 rda.res = cpu_to_le32(rmd->res);
419 if (BCR_SWSTYLE(s) == 3) {
420 uint32_t tmp = rda.rbadr;
421 rda.rbadr = rda.msg_length;
422 rda.msg_length = tmp;
e3c2613f 423 }
6d2980f5 424 s->phys_mem_write(s->dma_opaque, addr, (void *)&rda, sizeof(rda), 0);
e3c2613f
FB		 425 }
426}
427
428
429#define TMDLOAD(TMD,ADDR) pcnet_tmd_load(s,TMD,ADDR)
430
431#define TMDSTORE(TMD,ADDR) pcnet_tmd_store(s,TMD,ADDR)
432
433#define RMDLOAD(RMD,ADDR) pcnet_rmd_load(s,RMD,ADDR)
434
435#define RMDSTORE(RMD,ADDR) pcnet_rmd_store(s,RMD,ADDR)
436
437#if 1
438
439#define CHECK_RMD(ADDR,RES) do { \
440 struct pcnet_RMD rmd; \
441 RMDLOAD(&rmd,(ADDR)); \
6d2980f5
TS		 442 (RES) |= (GET_FIELD(rmd.buf_length, RMDL, ONES) != 15) \
443 || (GET_FIELD(rmd.msg_length, RMDM, ZEROS) != 0); \
e3c2613f
FB		 444} while (0)
445
446#define CHECK_TMD(ADDR,RES) do { \
447 struct pcnet_TMD tmd; \
448 TMDLOAD(&tmd,(ADDR)); \
6d2980f5 449 (RES) |= (GET_FIELD(tmd.length, TMDL, ONES) != 15); \
e3c2613f
FB		 450} while (0)
451
452#else
453
454#define CHECK_RMD(ADDR,RES) do { \
455 switch (BCR_SWSTYLE(s)) { \
456 case 0x00: \
457 do { \
458 uint16_t rda[4]; \
6d2980f5
TS		 459 s->phys_mem_read(s->dma_opaque, (ADDR), \
460 (void *)&rda[0], sizeof(rda), 0); \
e3c2613f
FB		 461 (RES) |= (rda[2] & 0xf000)!=0xf000; \
462 (RES) |= (rda[3] & 0xf000)!=0x0000; \
463 } while (0); \
464 break; \
465 case 0x01: \
466 case 0x02: \
467 do { \
468 uint32_t rda[4]; \
6d2980f5 469 s->phys_mem_read(s->dma_opaque, (ADDR), \
9b94dc32 470 (void *)&rda[0], sizeof(rda), 0); \
e3c2613f
FB		 471 (RES) |= (rda[1] & 0x0000f000L)!=0x0000f000L; \
472 (RES) |= (rda[2] & 0x0000f000L)!=0x00000000L; \
473 } while (0); \
474 break; \
475 case 0x03: \
476 do { \
477 uint32_t rda[4]; \
6d2980f5 478 s->phys_mem_read(s->dma_opaque, (ADDR), \
9b94dc32 479 (void *)&rda[0], sizeof(rda), 0); \
e3c2613f
FB		 480 (RES) |= (rda[0] & 0x0000f000L)!=0x00000000L; \
481 (RES) |= (rda[1] & 0x0000f000L)!=0x0000f000L; \
482 } while (0); \
483 break; \
484 } \
485} while (0)
486
487#define CHECK_TMD(ADDR,RES) do { \
488 switch (BCR_SWSTYLE(s)) { \
489 case 0x00: \
490 do { \
491 uint16_t xda[4]; \
6d2980f5
TS		 492 s->phys_mem_read(s->dma_opaque, (ADDR), \
493 (void *)&xda[0], sizeof(xda), 0); \
494 (RES) |= (xda[2] & 0xf000)!=0xf000; \
e3c2613f
FB		 495 } while (0); \
496 break; \
497 case 0x01: \
498 case 0x02: \
499 case 0x03: \
500 do { \
501 uint32_t xda[4]; \
6d2980f5
TS		 502 s->phys_mem_read(s->dma_opaque, (ADDR), \
503 (void *)&xda[0], sizeof(xda), 0); \
e3c2613f
FB		 504 (RES) |= (xda[1] & 0x0000f000L)!=0x0000f000L; \
505 } while (0); \
506 break; \
507 } \
508} while (0)
509
510#endif
511
512#define PRINT_PKTHDR(BUF) do { \
6d2980f5
TS		 513 struct qemu_ether_header *hdr = (void *)(BUF); \
514 printf("packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, " \
515 "shost=%02x:%02x:%02x:%02x:%02x:%02x, " \
516 "type=0x%04x\n", \
e3c2613f
FB		 517 hdr->ether_dhost[0],hdr->ether_dhost[1],hdr->ether_dhost[2], \
518 hdr->ether_dhost[3],hdr->ether_dhost[4],hdr->ether_dhost[5], \
519 hdr->ether_shost[0],hdr->ether_shost[1],hdr->ether_shost[2], \
520 hdr->ether_shost[3],hdr->ether_shost[4],hdr->ether_shost[5], \
6d2980f5 521 be16_to_cpu(hdr->ether_type)); \
e3c2613f
FB		 522} while (0)
523
524#define MULTICAST_FILTER_LEN 8
525
526static inline uint32_t lnc_mchash(const uint8_t *ether_addr)
527{
528#define LNC_POLYNOMIAL 0xEDB88320UL
529 uint32_t crc = 0xFFFFFFFF;
530 int idx, bit;
531 uint8_t data;
532
219fb125 533 for (idx = 0; idx < 6; idx++) {
e3c2613f
FB		 534 for (data = *ether_addr++, bit = 0; bit < MULTICAST_FILTER_LEN; bit++) {
535 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LNC_POLYNOMIAL : 0);
536 data >>= 1;
537 }
538 }
539 return crc;
540#undef LNC_POLYNOMIAL
541}
542
543#define CRC(crc, ch) (crc = (crc >> 8) ^ crctab[(crc ^ (ch)) & 0xff])
544
545/* generated using the AUTODIN II polynomial
546 * x^32 + x^26 + x^23 + x^22 + x^16 +
547 * x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
548 */
549static const uint32_t crctab[256] = {
550 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,
551 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
552 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
553 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
554 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
555 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
556 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,
557 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
558 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
559 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
560 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,
561 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
562 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,
563 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
564 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
565 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
566 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,
567 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
568 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,
569 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
570 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
571 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
572 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,
573 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
574 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
575 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
576 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
577 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
578 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,
579 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
580 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,
581 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
582 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
583 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,
584 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
585 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
586 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,
587 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
588 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
589 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
590 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,
591 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
592 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,
593 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
594 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
595 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
596 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,
597 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
598 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,
599 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
600 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
601 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,
602 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,
603 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
604 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
605 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
606 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
607 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
608 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,
609 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
610 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,
611 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
612 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
613 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
614};
615
616static inline int padr_match(PCNetState *s, const uint8_t *buf, int size)
617{
219fb125 618 struct qemu_ether_header *hdr = (void *)buf;
5fafdf24 619 uint8_t padr[6] = {
e3c2613f
FB		 620 s->csr[12] & 0xff, s->csr[12] >> 8,
621 s->csr[13] & 0xff, s->csr[13] >> 8,
5fafdf24 622 s->csr[14] & 0xff, s->csr[14] >> 8
e3c2613f 623 };
29b9a345 624 int result = (!CSR_DRCVPA(s)) && !memcmp(hdr->ether_dhost, padr, 6);
e3c2613f
FB		 625#ifdef PCNET_DEBUG_MATCH
626 printf("packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, "
627 "padr=%02x:%02x:%02x:%02x:%02x:%02x\n",
628 hdr->ether_dhost[0],hdr->ether_dhost[1],hdr->ether_dhost[2],
629 hdr->ether_dhost[3],hdr->ether_dhost[4],hdr->ether_dhost[5],
630 padr[0],padr[1],padr[2],padr[3],padr[4],padr[5]);
631 printf("padr_match result=%d\n", result);
632#endif
633 return result;
634}
635
636static inline int padr_bcast(PCNetState *s, const uint8_t *buf, int size)
637{
9b94dc32 638 static const uint8_t BCAST[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
219fb125 639 struct qemu_ether_header *hdr = (void *)buf;
29b9a345 640 int result = !CSR_DRCVBC(s) && !memcmp(hdr->ether_dhost, BCAST, 6);
e3c2613f
FB		 641#ifdef PCNET_DEBUG_MATCH
642 printf("padr_bcast result=%d\n", result);
643#endif
644 return result;
645}
646
647static inline int ladr_match(PCNetState *s, const uint8_t *buf, int size)
648{
219fb125 649 struct qemu_ether_header *hdr = (void *)buf;
5fafdf24 650 if ((*(hdr->ether_dhost)&0x01) &&
e3c2613f 651 ((uint64_t *)&s->csr[8])[0] != 0LL) {
5fafdf24 652 uint8_t ladr[8] = {
e3c2613f
FB		 653 s->csr[8] & 0xff, s->csr[8] >> 8,
654 s->csr[9] & 0xff, s->csr[9] >> 8,
5fafdf24
TS		 655 s->csr[10] & 0xff, s->csr[10] >> 8,
656 s->csr[11] & 0xff, s->csr[11] >> 8
e3c2613f
FB		 657 };
658 int index = lnc_mchash(hdr->ether_dhost) >> 26;
659 return !!(ladr[index >> 3] & (1 << (index & 7)));
660 }
661 return 0;
662}
663
a8170e5e 664static inline hwaddr pcnet_rdra_addr(PCNetState *s, int idx)
e3c2613f
FB		 665{
666 while (idx < 1) idx += CSR_RCVRL(s);
667 return s->rdra + ((CSR_RCVRL(s) - idx) * (BCR_SWSTYLE(s) ? 16 : 8));
668}
669
670static inline int64_t pcnet_get_next_poll_time(PCNetState *s, int64_t current_time)
671{
5fafdf24
TS		 672 int64_t next_time = current_time +
673 muldiv64(65536 - (CSR_SPND(s) ? 0 : CSR_POLL(s)),
6ee093c9 674 get_ticks_per_sec(), 33000000L);
e3c2613f
FB		 675 if (next_time <= current_time)
676 next_time = current_time + 1;
677 return next_time;
678}
679
680static void pcnet_poll(PCNetState *s);
681static void pcnet_poll_timer(void *opaque);
682
683static uint32_t pcnet_csr_readw(PCNetState *s, uint32_t rap);
684static void pcnet_csr_writew(PCNetState *s, uint32_t rap, uint32_t new_value);
685static void pcnet_bcr_writew(PCNetState *s, uint32_t rap, uint32_t val);
e3c2613f
FB		 686
687static void pcnet_s_reset(PCNetState *s)
688{
15cae340 689 trace_pcnet_s_reset(s);
e3c2613f 690
e3c2613f
FB		 691 s->rdra = 0;
692 s->tdra = 0;
693 s->rap = 0;
3b46e624 694
e3c2613f
FB		 695 s->bcr[BCR_BSBC] &= ~0x0080;
696
697 s->csr[0] = 0x0004;
698 s->csr[3] = 0x0000;
699 s->csr[4] = 0x0115;
700 s->csr[5] = 0x0000;
701 s->csr[6] = 0x0000;
702 s->csr[8] = 0;
703 s->csr[9] = 0;
704 s->csr[10] = 0;
705 s->csr[11] = 0;
706 s->csr[12] = le16_to_cpu(((uint16_t *)&s->prom[0])[0]);
707 s->csr[13] = le16_to_cpu(((uint16_t *)&s->prom[0])[1]);
708 s->csr[14] = le16_to_cpu(((uint16_t *)&s->prom[0])[2]);
709 s->csr[15] &= 0x21c4;
710 s->csr[72] = 1;
711 s->csr[74] = 1;
712 s->csr[76] = 1;
713 s->csr[78] = 1;
714 s->csr[80] = 0x1410;
715 s->csr[88] = 0x1003;
716 s->csr[89] = 0x0262;
717 s->csr[94] = 0x0000;
718 s->csr[100] = 0x0200;
719 s->csr[103] = 0x0105;
e3c2613f
FB		 720 s->csr[112] = 0x0000;
721 s->csr[114] = 0x0000;
722 s->csr[122] = 0x0000;
723 s->csr[124] = 0x0000;
ec607da7
FB		 724
725 s->tx_busy = 0;
e3c2613f
FB		 726}
727
728static void pcnet_update_irq(PCNetState *s)
729{
730 int isr = 0;
731 s->csr[0] &= ~0x0080;
3b46e624 732
e3c2613f
FB		 733#if 1
734 if (((s->csr[0] & ~s->csr[3]) & 0x5f00) ||
735 (((s->csr[4]>>1) & ~s->csr[4]) & 0x0115) ||
736 (((s->csr[5]>>1) & s->csr[5]) & 0x0048))
737#else
738 if ((!(s->csr[3] & 0x4000) && !!(s->csr[0] & 0x4000)) /* BABL */ ||
739 (!(s->csr[3] & 0x1000) && !!(s->csr[0] & 0x1000)) /* MISS */ ||
740 (!(s->csr[3] & 0x0100) && !!(s->csr[0] & 0x0100)) /* IDON */ ||
741 (!(s->csr[3] & 0x0200) && !!(s->csr[0] & 0x0200)) /* TINT */ ||
742 (!(s->csr[3] & 0x0400) && !!(s->csr[0] & 0x0400)) /* RINT */ ||
743 (!(s->csr[3] & 0x0800) && !!(s->csr[0] & 0x0800)) /* MERR */ ||
744 (!(s->csr[4] & 0x0001) && !!(s->csr[4] & 0x0002)) /* JAB */ ||
745 (!(s->csr[4] & 0x0004) && !!(s->csr[4] & 0x0008)) /* TXSTRT */ ||
746 (!(s->csr[4] & 0x0010) && !!(s->csr[4] & 0x0020)) /* RCVO */ ||
747 (!(s->csr[4] & 0x0100) && !!(s->csr[4] & 0x0200)) /* MFCO */ ||
748 (!!(s->csr[5] & 0x0040) && !!(s->csr[5] & 0x0080)) /* EXDINT */ ||
749 (!!(s->csr[5] & 0x0008) && !!(s->csr[5] & 0x0010)) /* MPINT */)
750#endif
751 {
3b46e624 752
e3c2613f
FB		 753 isr = CSR_INEA(s);
754 s->csr[0] |= 0x0080;
755 }
3b46e624 756
e3c2613f
FB		 757 if (!!(s->csr[4] & 0x0080) && CSR_INEA(s)) { /* UINT */
758 s->csr[4] &= ~0x0080;
759 s->csr[4] |= 0x0040;
760 s->csr[0] |= 0x0080;
761 isr = 1;
15cae340 762 trace_pcnet_user_int(s);
e3c2613f
FB		 763 }
764
765#if 1
5fafdf24 766 if (((s->csr[5]>>1) & s->csr[5]) & 0x0500)
e3c2613f
FB		 767#else
768 if ((!!(s->csr[5] & 0x0400) && !!(s->csr[5] & 0x0800)) /* SINT */ ||
769 (!!(s->csr[5] & 0x0100) && !!(s->csr[5] & 0x0200)) /* SLPINT */ )
770#endif
771 {
772 isr = 1;
773 s->csr[0] |= 0x0080;
774 }
775
776 if (isr != s->isr) {
15cae340 777 trace_pcnet_isr_change(s, isr, s->isr);
e3c2613f 778 }
d537cf6c 779 qemu_set_irq(s->irq, isr);
91cc0295 780 s->isr = isr;
e3c2613f
FB		 781}
782
783static void pcnet_init(PCNetState *s)
784{
91cc0295 785 int rlen, tlen;
6d2980f5 786 uint16_t padr[3], ladrf[4], mode;
91cc0295
FB		 787 uint32_t rdra, tdra;
788
15cae340 789 trace_pcnet_init(s, PHYSADDR(s, CSR_IADR(s)));
3b46e624 790
e3c2613f
FB		 791 if (BCR_SSIZE32(s)) {
792 struct pcnet_initblk32 initblk;
91cc0295 793 s->phys_mem_read(s->dma_opaque, PHYSADDR(s,CSR_IADR(s)),
9b94dc32 794 (uint8_t *)&initblk, sizeof(initblk), 0);
6d2980f5 795 mode = le16_to_cpu(initblk.mode);
91cc0295
FB		 796 rlen = initblk.rlen >> 4;
797 tlen = initblk.tlen >> 4;
6d2980f5
TS		 798 ladrf[0] = le16_to_cpu(initblk.ladrf[0]);
799 ladrf[1] = le16_to_cpu(initblk.ladrf[1]);
800 ladrf[2] = le16_to_cpu(initblk.ladrf[2]);
801 ladrf[3] = le16_to_cpu(initblk.ladrf[3]);
802 padr[0] = le16_to_cpu(initblk.padr[0]);
803 padr[1] = le16_to_cpu(initblk.padr[1]);
804 padr[2] = le16_to_cpu(initblk.padr[2]);
9b94dc32
FB		 805 rdra = le32_to_cpu(initblk.rdra);
806 tdra = le32_to_cpu(initblk.tdra);
e3c2613f
FB		 807 } else {
808 struct pcnet_initblk16 initblk;
91cc0295 809 s->phys_mem_read(s->dma_opaque, PHYSADDR(s,CSR_IADR(s)),
9b94dc32 810 (uint8_t *)&initblk, sizeof(initblk), 0);
6d2980f5
TS		 811 mode = le16_to_cpu(initblk.mode);
812 ladrf[0] = le16_to_cpu(initblk.ladrf[0]);
813 ladrf[1] = le16_to_cpu(initblk.ladrf[1]);
814 ladrf[2] = le16_to_cpu(initblk.ladrf[2]);
815 ladrf[3] = le16_to_cpu(initblk.ladrf[3]);
816 padr[0] = le16_to_cpu(initblk.padr[0]);
817 padr[1] = le16_to_cpu(initblk.padr[1]);
818 padr[2] = le16_to_cpu(initblk.padr[2]);
9b94dc32
FB		 819 rdra = le32_to_cpu(initblk.rdra);
820 tdra = le32_to_cpu(initblk.tdra);
91cc0295
FB		 821 rlen = rdra >> 29;
822 tlen = tdra >> 29;
823 rdra &= 0x00ffffff;
824 tdra &= 0x00ffffff;
825 }
6d2980f5 826
15cae340 827 trace_pcnet_rlen_tlen(s, rlen, tlen);
6d2980f5 828
91cc0295
FB		 829 CSR_RCVRL(s) = (rlen < 9) ? (1 << rlen) : 512;
830 CSR_XMTRL(s) = (tlen < 9) ? (1 << tlen) : 512;
831 s->csr[ 6] = (tlen << 12) | (rlen << 8);
6d2980f5
TS		 832 s->csr[15] = mode;
833 s->csr[ 8] = ladrf[0];
834 s->csr[ 9] = ladrf[1];
835 s->csr[10] = ladrf[2];
836 s->csr[11] = ladrf[3];
837 s->csr[12] = padr[0];
838 s->csr[13] = padr[1];
839 s->csr[14] = padr[2];
91cc0295
FB		 840 s->rdra = PHYSADDR(s, rdra);
841 s->tdra = PHYSADDR(s, tdra);
e3c2613f
FB		 842
843 CSR_RCVRC(s) = CSR_RCVRL(s);
844 CSR_XMTRC(s) = CSR_XMTRL(s);
845
15cae340
DK		 846 trace_pcnet_ss32_rdra_tdra(s, BCR_SSIZE32(s),
847 s->rdra, CSR_RCVRL(s), s->tdra, CSR_XMTRL(s));
e3c2613f 848
3b46e624 849 s->csr[0] |= 0x0101;
e3c2613f 850 s->csr[0] &= ~0x0004; /* clear STOP bit */
ee76c1f8
JK		 851
852 qemu_flush_queued_packets(qemu_get_queue(s->nic));
e3c2613f
FB		 853}
854
855static void pcnet_start(PCNetState *s)
856{
857#ifdef PCNET_DEBUG
858 printf("pcnet_start\n");
859#endif
860
861 if (!CSR_DTX(s))
862 s->csr[0] |= 0x0010; /* set TXON */
3b46e624 863
e3c2613f
FB		 864 if (!CSR_DRX(s))
865 s->csr[0] |= 0x0020; /* set RXON */
866
867 s->csr[0] &= ~0x0004; /* clear STOP bit */
868 s->csr[0] |= 0x0002;
ad323081 869 pcnet_poll_timer(s);
ee76c1f8
JK		 870
871 qemu_flush_queued_packets(qemu_get_queue(s->nic));
e3c2613f
FB		 872}
873
874static void pcnet_stop(PCNetState *s)
875{
876#ifdef PCNET_DEBUG
877 printf("pcnet_stop\n");
878#endif
6655124d 879 s->csr[0] &= ~0xffeb;
e3c2613f
FB		 880 s->csr[0] |= 0x0014;
881 s->csr[4] &= ~0x02c2;
882 s->csr[5] &= ~0x0011;
883 pcnet_poll_timer(s);
884}
885
886static void pcnet_rdte_poll(PCNetState *s)
887{
888 s->csr[28] = s->csr[29] = 0;
889 if (s->rdra) {
890 int bad = 0;
891#if 1
a8170e5e
AK		 892 hwaddr crda = pcnet_rdra_addr(s, CSR_RCVRC(s));
893 hwaddr nrda = pcnet_rdra_addr(s, -1 + CSR_RCVRC(s));
894 hwaddr nnrd = pcnet_rdra_addr(s, -2 + CSR_RCVRC(s));
e3c2613f 895#else
a8170e5e 896 hwaddr crda = s->rdra +
e3c2613f
FB		 897 (CSR_RCVRL(s) - CSR_RCVRC(s)) *
898 (BCR_SWSTYLE(s) ? 16 : 8 );
899 int nrdc = CSR_RCVRC(s)<=1 ? CSR_RCVRL(s) : CSR_RCVRC(s)-1;
a8170e5e 900 hwaddr nrda = s->rdra +
e3c2613f
FB		 901 (CSR_RCVRL(s) - nrdc) *
902 (BCR_SWSTYLE(s) ? 16 : 8 );
903 int nnrc = nrdc<=1 ? CSR_RCVRL(s) : nrdc-1;
a8170e5e 904 hwaddr nnrd = s->rdra +
e3c2613f
FB		 905 (CSR_RCVRL(s) - nnrc) *
906 (BCR_SWSTYLE(s) ? 16 : 8 );
907#endif
908
f1afe02a 909 CHECK_RMD(crda, bad);
e3c2613f 910 if (!bad) {
f1afe02a 911 CHECK_RMD(nrda, bad);
e3c2613f 912 if (bad || (nrda == crda)) nrda = 0;
f1afe02a 913 CHECK_RMD(nnrd, bad);
e3c2613f
FB		 914 if (bad || (nnrd == crda)) nnrd = 0;
915
916 s->csr[28] = crda & 0xffff;
917 s->csr[29] = crda >> 16;
918 s->csr[26] = nrda & 0xffff;
919 s->csr[27] = nrda >> 16;
920 s->csr[36] = nnrd & 0xffff;
921 s->csr[37] = nnrd >> 16;
922#ifdef PCNET_DEBUG
923 if (bad) {
cb3df91a 924 printf("pcnet: BAD RMD RECORDS AFTER 0x" TARGET_FMT_plx "\n",
f1afe02a 925 crda);
e3c2613f
FB		 926 }
927 } else {
cb3df91a 928 printf("pcnet: BAD RMD RDA=0x" TARGET_FMT_plx "\n",
f1afe02a 929 crda);
e3c2613f
FB		 930#endif
931 }
932 }
3b46e624 933
e3c2613f
FB		 934 if (CSR_CRDA(s)) {
935 struct pcnet_RMD rmd;
936 RMDLOAD(&rmd, PHYSADDR(s,CSR_CRDA(s)));
6d2980f5
TS		 937 CSR_CRBC(s) = GET_FIELD(rmd.buf_length, RMDL, BCNT);
938 CSR_CRST(s) = rmd.status;
e3c2613f 939#ifdef PCNET_DEBUG_RMD_X
6d2980f5 940 printf("CRDA=0x%08x CRST=0x%04x RCVRC=%d RMDL=0x%04x RMDS=0x%04x RMDM=0x%08x\n",
e3c2613f 941 PHYSADDR(s,CSR_CRDA(s)), CSR_CRST(s), CSR_RCVRC(s),
6d2980f5 942 rmd.buf_length, rmd.status, rmd.msg_length);
e3c2613f
FB		 943 PRINT_RMD(&rmd);
944#endif
945 } else {
946 CSR_CRBC(s) = CSR_CRST(s) = 0;
947 }
3b46e624 948
e3c2613f
FB		 949 if (CSR_NRDA(s)) {
950 struct pcnet_RMD rmd;
951 RMDLOAD(&rmd, PHYSADDR(s,CSR_NRDA(s)));
6d2980f5
TS		 952 CSR_NRBC(s) = GET_FIELD(rmd.buf_length, RMDL, BCNT);
953 CSR_NRST(s) = rmd.status;
e3c2613f
FB		 954 } else {
955 CSR_NRBC(s) = CSR_NRST(s) = 0;
956 }
957
958}
959
960static int pcnet_tdte_poll(PCNetState *s)
961{
962 s->csr[34] = s->csr[35] = 0;
963 if (s->tdra) {
a8170e5e 964 hwaddr cxda = s->tdra +
e3c2613f 965 (CSR_XMTRL(s) - CSR_XMTRC(s)) *
6d2980f5 966 (BCR_SWSTYLE(s) ? 16 : 8);
e3c2613f 967 int bad = 0;
f1afe02a 968 CHECK_TMD(cxda, bad);
e3c2613f
FB		 969 if (!bad) {
970 if (CSR_CXDA(s) != cxda) {
971 s->csr[60] = s->csr[34];
972 s->csr[61] = s->csr[35];
973 s->csr[62] = CSR_CXBC(s);
974 s->csr[63] = CSR_CXST(s);
975 }
976 s->csr[34] = cxda & 0xffff;
977 s->csr[35] = cxda >> 16;
6d2980f5 978#ifdef PCNET_DEBUG_X
f1afe02a 979 printf("pcnet: BAD TMD XDA=0x%08x\n", cxda);
e3c2613f
FB		 980#endif
981 }
982 }
983
984 if (CSR_CXDA(s)) {
985 struct pcnet_TMD tmd;
986
3b46e624 987 TMDLOAD(&tmd, PHYSADDR(s,CSR_CXDA(s)));
e3c2613f 988
6d2980f5
TS		 989 CSR_CXBC(s) = GET_FIELD(tmd.length, TMDL, BCNT);
990 CSR_CXST(s) = tmd.status;
e3c2613f
FB		 991 } else {
992 CSR_CXBC(s) = CSR_CXST(s) = 0;
993 }
3b46e624 994
e3c2613f
FB		 995 return !!(CSR_CXST(s) & 0x8000);
996}
997
e3c2613f
FB		 998#define MIN_BUF_SIZE 60
999
4e68f7a0 1000ssize_t pcnet_receive(NetClientState *nc, const uint8_t *buf, size_t size_)
e3c2613f 1001{
cc1f0f45 1002 PCNetState *s = qemu_get_nic_opaque(nc);
e3c2613f
FB		 1003 int is_padr = 0, is_bcast = 0, is_ladr = 0;
1004 uint8_t buf1[60];
89b190a2
AJ		 1005 int remaining;
1006 int crc_err = 0;
4f1c942b 1007 int size = size_;
e3c2613f 1008
c1ded3dc
JK		 1009 if (CSR_DRX(s) || CSR_STOP(s) || CSR_SPND(s) || !size ||
1010 (CSR_LOOP(s) && !s->looptest)) {
4f1c942b 1011 return -1;
c1ded3dc 1012 }
e3c2613f
FB		 1013#ifdef PCNET_DEBUG
1014 printf("pcnet_receive size=%d\n", size);
1015#endif
1016
1017 /* if too small buffer, then expand it */
1018 if (size < MIN_BUF_SIZE) {
1019 memcpy(buf1, buf, size);
1020 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
1021 buf = buf1;
1022 size = MIN_BUF_SIZE;
1023 }
1024
5fafdf24
TS		 1025 if (CSR_PROM(s)
1026 || (is_padr=padr_match(s, buf, size))
e3c2613f
FB		 1027 || (is_bcast=padr_bcast(s, buf, size))
1028 || (is_ladr=ladr_match(s, buf, size))) {
1029
1030 pcnet_rdte_poll(s);
1031
1032 if (!(CSR_CRST(s) & 0x8000) && s->rdra) {
1033 struct pcnet_RMD rmd;
1034 int rcvrc = CSR_RCVRC(s)-1,i;
a8170e5e 1035 hwaddr nrda;
e3c2613f
FB		 1036 for (i = CSR_RCVRL(s)-1; i > 0; i--, rcvrc--) {
1037 if (rcvrc <= 1)
1038 rcvrc = CSR_RCVRL(s);
1039 nrda = s->rdra +
1040 (CSR_RCVRL(s) - rcvrc) *
1041 (BCR_SWSTYLE(s) ? 16 : 8 );
f1afe02a 1042 RMDLOAD(&rmd, nrda);
6d2980f5 1043 if (GET_FIELD(rmd.status, RMDS, OWN)) {
e3c2613f 1044#ifdef PCNET_DEBUG_RMD
5fafdf24 1045 printf("pcnet - scan buffer: RCVRC=%d PREV_RCVRC=%d\n",
e3c2613f
FB		 1046 rcvrc, CSR_RCVRC(s));
1047#endif
1048 CSR_RCVRC(s) = rcvrc;
1049 pcnet_rdte_poll(s);
1050 break;
1051 }
1052 }
1053 }
1054
1055 if (!(CSR_CRST(s) & 0x8000)) {
1056#ifdef PCNET_DEBUG_RMD
1057 printf("pcnet - no buffer: RCVRC=%d\n", CSR_RCVRC(s));
1058#endif
1059 s->csr[0] |= 0x1000; /* Set MISS flag */
1060 CSR_MISSC(s)++;
1061 } else {
89b190a2 1062 uint8_t *src = s->buffer;
a8170e5e 1063 hwaddr crda = CSR_CRDA(s);
e3c2613f
FB		 1064 struct pcnet_RMD rmd;
1065 int pktcount = 0;
1066
89b190a2
AJ		 1067 if (!s->looptest) {
1068 memcpy(src, buf, size);
1069 /* no need to compute the CRC */
1070 src[size] = 0;
1071 src[size + 1] = 0;
1072 src[size + 2] = 0;
1073 src[size + 3] = 0;
1074 size += 4;
1075 } else if (s->looptest == PCNET_LOOPTEST_CRC ||
1076 !CSR_DXMTFCS(s) || size < MIN_BUF_SIZE+4) {
e3c2613f 1077 uint32_t fcs = ~0;
e3c2613f 1078 uint8_t *p = src;
e3c2613f 1079
89b190a2
AJ		 1080 while (p != &src[size])
1081 CRC(fcs, *p++);
1082 *(uint32_t *)p = htonl(fcs);
1083 size += 4;
1084 } else {
1085 uint32_t fcs = ~0;
1086 uint8_t *p = src;
3b46e624 1087
89b190a2 1088 while (p != &src[size-4])
e3c2613f 1089 CRC(fcs, *p++);
89b190a2
AJ		 1090 crc_err = (*(uint32_t *)p != htonl(fcs));
1091 }
e3c2613f
FB		 1092
1093#ifdef PCNET_DEBUG_MATCH
1094 PRINT_PKTHDR(buf);
1095#endif
1096
1097 RMDLOAD(&rmd, PHYSADDR(s,crda));
1098 /*if (!CSR_LAPPEN(s))*/
6d2980f5 1099 SET_FIELD(&rmd.status, RMDS, STP, 1);
e3c2613f
FB		 1100
1101#define PCNET_RECV_STORE() do { \
89b190a2 1102 int count = MIN(4096 - GET_FIELD(rmd.buf_length, RMDL, BCNT),remaining); \
a8170e5e 1103 hwaddr rbadr = PHYSADDR(s, rmd.rbadr); \
6d2980f5 1104 s->phys_mem_write(s->dma_opaque, rbadr, src, count, CSR_BSWP(s)); \
89b190a2 1105 src += count; remaining -= count; \
6d2980f5 1106 SET_FIELD(&rmd.status, RMDS, OWN, 0); \
e3c2613f
FB		 1107 RMDSTORE(&rmd, PHYSADDR(s,crda)); \
1108 pktcount++; \
1109} while (0)
1110
89b190a2 1111 remaining = size;
e3c2613f 1112 PCNET_RECV_STORE();
89b190a2 1113 if ((remaining > 0) && CSR_NRDA(s)) {
a8170e5e 1114 hwaddr nrda = CSR_NRDA(s);
89b190a2
AJ		 1115#ifdef PCNET_DEBUG_RMD
1116 PRINT_RMD(&rmd);
1117#endif
e3c2613f 1118 RMDLOAD(&rmd, PHYSADDR(s,nrda));
6d2980f5 1119 if (GET_FIELD(rmd.status, RMDS, OWN)) {
e3c2613f
FB		 1120 crda = nrda;
1121 PCNET_RECV_STORE();
89b190a2
AJ		 1122#ifdef PCNET_DEBUG_RMD
1123 PRINT_RMD(&rmd);
1124#endif
1125 if ((remaining > 0) && (nrda=CSR_NNRD(s))) {
e3c2613f 1126 RMDLOAD(&rmd, PHYSADDR(s,nrda));
6d2980f5 1127 if (GET_FIELD(rmd.status, RMDS, OWN)) {
e3c2613f
FB		 1128 crda = nrda;
1129 PCNET_RECV_STORE();
1130 }
1131 }
3b46e624 1132 }
e3c2613f
FB		 1133 }
1134
1135#undef PCNET_RECV_STORE
1136
1137 RMDLOAD(&rmd, PHYSADDR(s,crda));
89b190a2
AJ		 1138 if (remaining == 0) {
1139 SET_FIELD(&rmd.msg_length, RMDM, MCNT, size);
6d2980f5
TS		 1140 SET_FIELD(&rmd.status, RMDS, ENP, 1);
1141 SET_FIELD(&rmd.status, RMDS, PAM, !CSR_PROM(s) && is_padr);
1142 SET_FIELD(&rmd.status, RMDS, LFAM, !CSR_PROM(s) && is_ladr);
1143 SET_FIELD(&rmd.status, RMDS, BAM, !CSR_PROM(s) && is_bcast);
89b190a2
AJ		 1144 if (crc_err) {
1145 SET_FIELD(&rmd.status, RMDS, CRC, 1);
1146 SET_FIELD(&rmd.status, RMDS, ERR, 1);
1147 }
e3c2613f 1148 } else {
6d2980f5
TS		 1149 SET_FIELD(&rmd.status, RMDS, OFLO, 1);
1150 SET_FIELD(&rmd.status, RMDS, BUFF, 1);
1151 SET_FIELD(&rmd.status, RMDS, ERR, 1);
e3c2613f
FB		 1152 }
1153 RMDSTORE(&rmd, PHYSADDR(s,crda));
1154 s->csr[0] |= 0x0400;
1155
1156#ifdef PCNET_DEBUG
5fafdf24 1157 printf("RCVRC=%d CRDA=0x%08x BLKS=%d\n",
e3c2613f
FB		 1158 CSR_RCVRC(s), PHYSADDR(s,CSR_CRDA(s)), pktcount);
1159#endif
1160#ifdef PCNET_DEBUG_RMD
1161 PRINT_RMD(&rmd);
3b46e624 1162#endif
e3c2613f
FB		 1163
1164 while (pktcount--) {
1165 if (CSR_RCVRC(s) <= 1)
1166 CSR_RCVRC(s) = CSR_RCVRL(s);
1167 else
3b46e624 1168 CSR_RCVRC(s)--;
e3c2613f 1169 }
3b46e624 1170
e3c2613f
FB		 1171 pcnet_rdte_poll(s);
1172
3b46e624 1173 }
e3c2613f
FB		 1174 }
1175
1176 pcnet_poll(s);
3b46e624 1177 pcnet_update_irq(s);
4f1c942b
MM		 1178
1179 return size_;
e3c2613f
FB		 1180}
1181
4e68f7a0 1182void pcnet_set_link_status(NetClientState *nc)
e1c2008a 1183{
cc1f0f45 1184 PCNetState *d = qemu_get_nic_opaque(nc);
e1c2008a
JK		 1185
1186 d->lnkst = nc->link_down ? 0 : 0x40;
1187}
1188
e3c2613f
FB		 1189static void pcnet_transmit(PCNetState *s)
1190{
a8170e5e 1191 hwaddr xmit_cxda = 0;
e3c2613f 1192 int count = CSR_XMTRL(s)-1;
89b190a2 1193 int add_crc = 0;
7b50d009 1194 int bcnt;
e3c2613f 1195 s->xmit_pos = -1;
3b46e624 1196
e3c2613f
FB		 1197 if (!CSR_TXON(s)) {
1198 s->csr[0] &= ~0x0008;
1199 return;
1200 }
ec607da7
FB		 1201
1202 s->tx_busy = 1;
1203
e3c2613f
FB		 1204 txagain:
1205 if (pcnet_tdte_poll(s)) {
1206 struct pcnet_TMD tmd;
1207
6d2980f5 1208 TMDLOAD(&tmd, PHYSADDR(s,CSR_CXDA(s)));
e3c2613f
FB		 1209
1210#ifdef PCNET_DEBUG_TMD
1211 printf(" TMDLOAD 0x%08x\n", PHYSADDR(s,CSR_CXDA(s)));
1212 PRINT_TMD(&tmd);
1213#endif
6d2980f5
TS		 1214 if (GET_FIELD(tmd.status, TMDS, STP)) {
1215 s->xmit_pos = 0;
e3c2613f 1216 xmit_cxda = PHYSADDR(s,CSR_CXDA(s));
89b190a2
AJ		 1217 if (BCR_SWSTYLE(s) != 1)
1218 add_crc = GET_FIELD(tmd.status, TMDS, ADDFCS);
e3c2613f 1219 }
ef45c914
JK		 1220 if (s->lnkst == 0 &&
1221 (!CSR_LOOP(s) || (!CSR_INTL(s) && !BCR_TMAULOOP(s)))) {
1222 SET_FIELD(&tmd.misc, TMDM, LCAR, 1);
1223 SET_FIELD(&tmd.status, TMDS, ERR, 1);
1224 SET_FIELD(&tmd.status, TMDS, OWN, 0);
1225 s->csr[0] |= 0xa000; /* ERR | CERR */
1226 s->xmit_pos = -1;
1227 goto txdone;
1228 }
7b50d009
GA		 1229
1230 if (s->xmit_pos < 0) {
1231 goto txdone;
1232 }
1233
1234 bcnt = 4096 - GET_FIELD(tmd.length, TMDL, BCNT);
9f7c594c
PM		 1235
1236 /* if multi-tmd packet outsizes s->buffer then skip it silently.
1237 Note: this is not what real hw does */
1238 if (s->xmit_pos + bcnt > sizeof(s->buffer)) {
1239 s->xmit_pos = -1;
1240 goto txdone;
1241 }
1242
7b50d009
GA		 1243 s->phys_mem_read(s->dma_opaque, PHYSADDR(s, tmd.tbadr),
1244 s->buffer + s->xmit_pos, bcnt, CSR_BSWP(s));
1245 s->xmit_pos += bcnt;
1246
9bd0d294 1247 if (!GET_FIELD(tmd.status, TMDS, ENP)) {
7b50d009
GA		 1248 goto txdone;
1249 }
1250
e3c2613f 1251#ifdef PCNET_DEBUG
7b50d009 1252 printf("pcnet_transmit size=%d\n", s->xmit_pos);
6d2980f5 1253#endif
7b50d009
GA		 1254 if (CSR_LOOP(s)) {
1255 if (BCR_SWSTYLE(s) == 1)
1256 add_crc = !GET_FIELD(tmd.status, TMDS, NOFCS);
1257 s->looptest = add_crc ? PCNET_LOOPTEST_CRC : PCNET_LOOPTEST_NOCRC;
1258 pcnet_receive(qemu_get_queue(s->nic), s->buffer, s->xmit_pos);
1259 s->looptest = 0;
1260 } else {
1261 if (s->nic) {
1262 qemu_send_packet(qemu_get_queue(s->nic), s->buffer,
1263 s->xmit_pos);
1264 }
e3c2613f
FB		 1265 }
1266
7b50d009
GA		 1267 s->csr[0] &= ~0x0008; /* clear TDMD */
1268 s->csr[4] |= 0x0004; /* set TXSTRT */
1269 s->xmit_pos = -1;
1270
ef45c914 1271 txdone:
6d2980f5 1272 SET_FIELD(&tmd.status, TMDS, OWN, 0);
e3c2613f 1273 TMDSTORE(&tmd, PHYSADDR(s,CSR_CXDA(s)));
6d2980f5 1274 if (!CSR_TOKINTD(s) || (CSR_LTINTEN(s) && GET_FIELD(tmd.status, TMDS, LTINT)))
e3c2613f
FB		 1275 s->csr[0] |= 0x0200; /* set TINT */
1276
1277 if (CSR_XMTRC(s)<=1)
1278 CSR_XMTRC(s) = CSR_XMTRL(s);
1279 else
1280 CSR_XMTRC(s)--;
1281 if (count--)
1282 goto txagain;
1283
5fafdf24 1284 } else
e3c2613f
FB		 1285 if (s->xmit_pos >= 0) {
1286 struct pcnet_TMD tmd;
f1afe02a 1287 TMDLOAD(&tmd, xmit_cxda);
6d2980f5
TS		 1288 SET_FIELD(&tmd.misc, TMDM, BUFF, 1);
1289 SET_FIELD(&tmd.misc, TMDM, UFLO, 1);
1290 SET_FIELD(&tmd.status, TMDS, ERR, 1);
1291 SET_FIELD(&tmd.status, TMDS, OWN, 0);
f1afe02a 1292 TMDSTORE(&tmd, xmit_cxda);
e3c2613f
FB		 1293 s->csr[0] |= 0x0200; /* set TINT */
1294 if (!CSR_DXSUFLO(s)) {
1295 s->csr[0] &= ~0x0010;
1296 } else
1297 if (count--)
1298 goto txagain;
1299 }
ec607da7
FB		 1300
1301 s->tx_busy = 0;
e3c2613f
FB		 1302}
1303
1304static void pcnet_poll(PCNetState *s)
1305{
1306 if (CSR_RXON(s)) {
1307 pcnet_rdte_poll(s);
1308 }
1309
5fafdf24 1310 if (CSR_TDMD(s) ||
e3c2613f 1311 (CSR_TXON(s) && !CSR_DPOLL(s) && pcnet_tdte_poll(s)))
ec607da7
FB		 1312 {
1313 /* prevent recursion */
1314 if (s->tx_busy)
1315 return;
1316
e3c2613f 1317 pcnet_transmit(s);
ec607da7 1318 }
e3c2613f
FB		 1319}
1320
1321static void pcnet_poll_timer(void *opaque)
1322{
1323 PCNetState *s = opaque;
1324
bc72ad67 1325 timer_del(s->poll_timer);
e3c2613f
FB		 1326
1327 if (CSR_TDMD(s)) {
1328 pcnet_transmit(s);
1329 }
1330
3b46e624 1331 pcnet_update_irq(s);
e3c2613f
FB		 1332
1333 if (!CSR_STOP(s) && !CSR_SPND(s) && !CSR_DPOLL(s)) {
bc72ad67 1334 uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) * 33;
e3c2613f
FB		 1335 if (!s->timer || !now)
1336 s->timer = now;
1337 else {
1338 uint64_t t = now - s->timer + CSR_POLL(s);
1339 if (t > 0xffffLL) {
1340 pcnet_poll(s);
1341 CSR_POLL(s) = CSR_PINT(s);
1342 } else
1343 CSR_POLL(s) = t;
1344 }
bc72ad67
AB		 1345 timer_mod(s->poll_timer,
1346 pcnet_get_next_poll_time(s,qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)));
e3c2613f
FB		 1347 }
1348}
1349
1350
1351static void pcnet_csr_writew(PCNetState *s, uint32_t rap, uint32_t new_value)
1352{
1353 uint16_t val = new_value;
1354#ifdef PCNET_DEBUG_CSR
1355 printf("pcnet_csr_writew rap=%d val=0x%04x\n", rap, val);
1356#endif
1357 switch (rap) {
1358 case 0:
1359 s->csr[0] &= ~(val & 0x7f00); /* Clear any interrupt flags */
1360
1361 s->csr[0] = (s->csr[0] & ~0x0040) | (val & 0x0048);
1362
1363 val = (val & 0x007f) | (s->csr[0] & 0x7f00);
1364
1365 /* IFF STOP, STRT and INIT are set, clear STRT and INIT */
1366 if ((val&7) == 7)
1367 val &= ~3;
1368
1369 if (!CSR_STOP(s) && (val & 4))
1370 pcnet_stop(s);
1371
1372 if (!CSR_INIT(s) && (val & 1))
1373 pcnet_init(s);
1374
1375 if (!CSR_STRT(s) && (val & 2))
1376 pcnet_start(s);
1377
5fafdf24 1378 if (CSR_TDMD(s))
e3c2613f
FB		 1379 pcnet_transmit(s);
1380
1381 return;
1382 case 1:
1383 case 2:
1384 case 8:
1385 case 9:
1386 case 10:
1387 case 11:
1388 case 12:
1389 case 13:
1390 case 14:
1391 case 15:
1392 case 18: /* CRBAL */
1393 case 19: /* CRBAU */
1394 case 20: /* CXBAL */
1395 case 21: /* CXBAU */
1396 case 22: /* NRBAU */
1397 case 23: /* NRBAU */
1398 case 24:
1399 case 25:
1400 case 26:
1401 case 27:
1402 case 28:
1403 case 29:
1404 case 30:
1405 case 31:
1406 case 32:
1407 case 33:
1408 case 34:
1409 case 35:
1410 case 36:
1411 case 37:
1412 case 38:
1413 case 39:
1414 case 40: /* CRBC */
1415 case 41:
1416 case 42: /* CXBC */
1417 case 43:
1418 case 44:
1419 case 45:
1420 case 46: /* POLL */
1421 case 47: /* POLLINT */
1422 case 72:
1423 case 74:
1424 case 76: /* RCVRL */
1425 case 78: /* XMTRL */
1426 case 112:
1427 if (CSR_STOP(s) || CSR_SPND(s))
1428 break;
1429 return;
1430 case 3:
1431 break;
1432 case 4:
5fafdf24 1433 s->csr[4] &= ~(val & 0x026a);
e3c2613f
FB		 1434 val &= ~0x026a; val |= s->csr[4] & 0x026a;
1435 break;
1436 case 5:
5fafdf24 1437 s->csr[5] &= ~(val & 0x0a90);
e3c2613f
FB		 1438 val &= ~0x0a90; val |= s->csr[5] & 0x0a90;
1439 break;
1440 case 16:
1441 pcnet_csr_writew(s,1,val);
1442 return;
1443 case 17:
1444 pcnet_csr_writew(s,2,val);
1445 return;
1446 case 58:
1447 pcnet_bcr_writew(s,BCR_SWS,val);
1448 break;
1449 default:
1450 return;
1451 }
1452 s->csr[rap] = val;
1453}
1454
1455static uint32_t pcnet_csr_readw(PCNetState *s, uint32_t rap)
1456{
1457 uint32_t val;
1458 switch (rap) {
1459 case 0:
1460 pcnet_update_irq(s);
1461 val = s->csr[0];
1462 val |= (val & 0x7800) ? 0x8000 : 0;
1463 break;
1464 case 16:
1465 return pcnet_csr_readw(s,1);
1466 case 17:
1467 return pcnet_csr_readw(s,2);
1468 case 58:
1469 return pcnet_bcr_readw(s,BCR_SWS);
1470 case 88:
1471 val = s->csr[89];
1472 val <<= 16;
1473 val |= s->csr[88];
1474 break;
1475 default:
1476 val = s->csr[rap];
1477 }
1478#ifdef PCNET_DEBUG_CSR
1479 printf("pcnet_csr_readw rap=%d val=0x%04x\n", rap, val);
1480#endif
1481 return val;
1482}
1483
1484static void pcnet_bcr_writew(PCNetState *s, uint32_t rap, uint32_t val)
1485{
1486 rap &= 127;
1487#ifdef PCNET_DEBUG_BCR
1488 printf("pcnet_bcr_writew rap=%d val=0x%04x\n", rap, val);
1489#endif
1490 switch (rap) {
1491 case BCR_SWS:
1492 if (!(CSR_STOP(s) || CSR_SPND(s)))
1493 return;
1494 val &= ~0x0300;
1495 switch (val & 0x00ff) {
1496 case 0:
1497 val |= 0x0200;
1498 break;
1499 case 1:
1500 val |= 0x0100;
1501 break;
1502 case 2:
1503 case 3:
1504 val |= 0x0300;
1505 break;
1506 default:
1507 printf("Bad SWSTYLE=0x%02x\n", val & 0xff);
1508 val = 0x0200;
1509 break;
1510 }
1511#ifdef PCNET_DEBUG
1512 printf("BCR_SWS=0x%04x\n", val);
1513#endif
0b0404bf 1514 /* fall through */
e3c2613f
FB		 1515 case BCR_LNKST:
1516 case BCR_LED1:
1517 case BCR_LED2:
1518 case BCR_LED3:
1519 case BCR_MC:
1520 case BCR_FDC:
1521 case BCR_BSBC:
1522 case BCR_EECAS:
1523 case BCR_PLAT:
1524 s->bcr[rap] = val;
1525 break;
1526 default:
1527 break;
1528 }
1529}
1530
a4c75a21 1531uint32_t pcnet_bcr_readw(PCNetState *s, uint32_t rap)
e3c2613f
FB		 1532{
1533 uint32_t val;
1534 rap &= 127;
1535 switch (rap) {
1536 case BCR_LNKST:
1537 case BCR_LED1:
1538 case BCR_LED2:
1539 case BCR_LED3:
1540 val = s->bcr[rap] & ~0x8000;
1541 val |= (val & 0x017f & s->lnkst) ? 0x8000 : 0;
1542 break;
1543 default:
1544 val = rap < 32 ? s->bcr[rap] : 0;
1545 break;
1546 }
1547#ifdef PCNET_DEBUG_BCR
1548 printf("pcnet_bcr_readw rap=%d val=0x%04x\n", rap, val);
1549#endif
1550 return val;
1551}
1552
94e1a912 1553void pcnet_h_reset(void *opaque)
e3c2613f 1554{
91cc0295 1555 PCNetState *s = opaque;
e3c2613f
FB		 1556
1557 s->bcr[BCR_MSRDA] = 0x0005;
1558 s->bcr[BCR_MSWRA] = 0x0005;
1559 s->bcr[BCR_MC ] = 0x0002;
1560 s->bcr[BCR_LNKST] = 0x00c0;
1561 s->bcr[BCR_LED1 ] = 0x0084;
1562 s->bcr[BCR_LED2 ] = 0x0088;
1563 s->bcr[BCR_LED3 ] = 0x0090;
1564 s->bcr[BCR_FDC ] = 0x0000;
1565 s->bcr[BCR_BSBC ] = 0x9001;
1566 s->bcr[BCR_EECAS] = 0x0002;
1567 s->bcr[BCR_SWS ] = 0x0200;
1568 s->bcr[BCR_PLAT ] = 0xff06;
1569
1570 pcnet_s_reset(s);
de41ac92
JK		 1571 pcnet_update_irq(s);
1572 pcnet_poll_timer(s);
e3c2613f
FB		 1573}
1574
94e1a912 1575void pcnet_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
e3c2613f
FB		 1576{
1577 PCNetState *s = opaque;
1578 pcnet_poll_timer(s);
1579#ifdef PCNET_DEBUG_IO
1580 printf("pcnet_ioport_writew addr=0x%08x val=0x%04x\n", addr, val);
1581#endif
1582 if (!BCR_DWIO(s)) {
1583 switch (addr & 0x0f) {
1584 case 0x00: /* RDP */
1585 pcnet_csr_writew(s, s->rap, val);
1586 break;
1587 case 0x02:
1588 s->rap = val & 0x7f;
1589 break;
1590 case 0x06:
1591 pcnet_bcr_writew(s, s->rap, val);
1592 break;
1593 }
1594 }
1595 pcnet_update_irq(s);
1596}
1597
94e1a912 1598uint32_t pcnet_ioport_readw(void *opaque, uint32_t addr)
e3c2613f
FB		 1599{
1600 PCNetState *s = opaque;
1601 uint32_t val = -1;
1602 pcnet_poll_timer(s);
1603 if (!BCR_DWIO(s)) {
1604 switch (addr & 0x0f) {
1605 case 0x00: /* RDP */
1606 val = pcnet_csr_readw(s, s->rap);
1607 break;
1608 case 0x02:
1609 val = s->rap;
1610 break;
1611 case 0x04:
1612 pcnet_s_reset(s);
1613 val = 0;
1614 break;
1615 case 0x06:
1616 val = pcnet_bcr_readw(s, s->rap);
1617 break;
1618 }
1619 }
1620 pcnet_update_irq(s);
1621#ifdef PCNET_DEBUG_IO
1622 printf("pcnet_ioport_readw addr=0x%08x val=0x%04x\n", addr, val & 0xffff);
1623#endif
1624 return val;
1625}
1626
a4c75a21 1627void pcnet_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
e3c2613f
FB		 1628{
1629 PCNetState *s = opaque;
1630 pcnet_poll_timer(s);
1631#ifdef PCNET_DEBUG_IO
1632 printf("pcnet_ioport_writel addr=0x%08x val=0x%08x\n", addr, val);
1633#endif
1634 if (BCR_DWIO(s)) {
1635 switch (addr & 0x0f) {
1636 case 0x00: /* RDP */
1637 pcnet_csr_writew(s, s->rap, val & 0xffff);
1638 break;
1639 case 0x04:
1640 s->rap = val & 0x7f;
1641 break;
1642 case 0x0c:
1643 pcnet_bcr_writew(s, s->rap, val & 0xffff);
1644 break;
1645 }
1646 } else
1647 if ((addr & 0x0f) == 0) {
1648 /* switch device to dword i/o mode */
1649 pcnet_bcr_writew(s, BCR_BSBC, pcnet_bcr_readw(s, BCR_BSBC) | 0x0080);
1650#ifdef PCNET_DEBUG_IO
1651 printf("device switched into dword i/o mode\n");
3b46e624 1652#endif
e3c2613f
FB		 1653 }
1654 pcnet_update_irq(s);
1655}
1656
a4c75a21 1657uint32_t pcnet_ioport_readl(void *opaque, uint32_t addr)
e3c2613f
FB		 1658{
1659 PCNetState *s = opaque;
1660 uint32_t val = -1;
1661 pcnet_poll_timer(s);
3b46e624 1662 if (BCR_DWIO(s)) {
e3c2613f
FB		 1663 switch (addr & 0x0f) {
1664 case 0x00: /* RDP */
1665 val = pcnet_csr_readw(s, s->rap);
1666 break;
1667 case 0x04:
1668 val = s->rap;
1669 break;
1670 case 0x08:
1671 pcnet_s_reset(s);
1672 val = 0;
1673 break;
1674 case 0x0c:
1675 val = pcnet_bcr_readw(s, s->rap);
1676 break;
1677 }
1678 }
1679 pcnet_update_irq(s);
1680#ifdef PCNET_DEBUG_IO
1681 printf("pcnet_ioport_readl addr=0x%08x val=0x%08x\n", addr, val);
1682#endif
1683 return val;
1684}
1685
3d865059 1686static bool is_version_2(void *opaque, int version_id)
91cc0295 1687{
3d865059 1688 return version_id == 2;
91cc0295
FB		 1689}
1690
3d865059
JQ		 1691const VMStateDescription vmstate_pcnet = {
1692 .name = "pcnet",
1693 .version_id = 3,
1694 .minimum_version_id = 2,
d49805ae 1695 .fields = (VMStateField[]) {
3d865059
JQ		 1696 VMSTATE_INT32(rap, PCNetState),
1697 VMSTATE_INT32(isr, PCNetState),
1698 VMSTATE_INT32(lnkst, PCNetState),
1699 VMSTATE_UINT32(rdra, PCNetState),
1700 VMSTATE_UINT32(tdra, PCNetState),
1701 VMSTATE_BUFFER(prom, PCNetState),
1702 VMSTATE_UINT16_ARRAY(csr, PCNetState, 128),
1703 VMSTATE_UINT16_ARRAY(bcr, PCNetState, 32),
1704 VMSTATE_UINT64(timer, PCNetState),
1705 VMSTATE_INT32(xmit_pos, PCNetState),
1706 VMSTATE_BUFFER(buffer, PCNetState),
1707 VMSTATE_UNUSED_TEST(is_version_2, 4),
1708 VMSTATE_INT32(tx_busy, PCNetState),
e720677e 1709 VMSTATE_TIMER_PTR(poll_timer, PCNetState),
3d865059 1710 VMSTATE_END_OF_LIST()
efb56cf7 1711 }
3d865059 1712};
0abaa7c1 1713
4c3b2245 1714void pcnet_common_init(DeviceState *dev, PCNetState *s, NetClientInfo *info)
91cc0295 1715{
7165448a
WD		 1716 int i;
1717 uint16_t checksum;
1718
bc72ad67 1719 s->poll_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pcnet_poll_timer, s);
9d07d757 1720
76224833 1721 qemu_macaddr_default_if_unset(&s->conf.macaddr);
f79f2bfc 1722 s->nic = qemu_new_nic(info, &s->conf, object_get_typename(OBJECT(dev)), dev->id, s);
b356f76d 1723 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1ca4d09a 1724
7165448a
WD		 1725 /* Initialize the PROM */
1726
1727 /*
1728 Datasheet: http://pdfdata.datasheetsite.com/web/24528/AM79C970A.pdf
1729 page 95
1730 */
1731 memcpy(s->prom, s->conf.macaddr.a, 6);
1732 /* Reserved Location: must be 00h */
1733 s->prom[6] = s->prom[7] = 0x00;
1734 /* Reserved Location: must be 00h */
1735 s->prom[8] = 0x00;
1736 /* Hardware ID: must be 11h if compatibility to AMD drivers is desired */
1737 s->prom[9] = 0x11;
1738 /* User programmable space, init with 0 */
1739 s->prom[10] = s->prom[11] = 0x00;
1740 /* LSByte of two-byte checksum, which is the sum of bytes 00h-0Bh
1741 and bytes 0Eh and 0Fh, must therefore be initialized with 0! */
1742 s->prom[12] = s->prom[13] = 0x00;
1743 /* Must be ASCII W (57h) if compatibility to AMD
1744 driver software is desired */
1745 s->prom[14] = s->prom[15] = 0x57;
1746
1747 for (i = 0, checksum = 0; i < 16; i++) {
1748 checksum += s->prom[i];
1749 }
1750 *(uint16_t *)&s->prom[12] = cpu_to_le16(checksum);
1751
9f2a8d7a 1752 s->lnkst = 0x40; /* initial link state: up */
91cc0295 1753}
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