]> Git Repo - qemu.git/blame - target/xtensa/core-de212/xtensa-modules.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Use #include "..." for our own headers, <...> for others
[qemu.git] / target / xtensa / core-de212 / xtensa-modules.c
CommitLineData
7ddaee6d
MF		 1/* Xtensa configuration-specific ISA information.
2
3 Copyright (c) 2003-2015 Tensilica Inc.
4
5 Permission is hereby granted, free of charge, to any person obtaining
6 a copy of this software and associated documentation files (the
7 "Software"), to deal in the Software without restriction, including
8 without limitation the rights to use, copy, modify, merge, publish,
9 distribute, sublicense, and/or sell copies of the Software, and to
10 permit persons to whom the Software is furnished to do so, subject to
11 the following conditions:
12
13 The above copyright notice and this permission notice shall be included
14 in all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
20 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
d8e39b70 24#include "xtensa-isa.h"
7ddaee6d
MF		 25#include "xtensa-isa-internal.h"
26
27\f
28/* Sysregs. */
29
30static xtensa_sysreg_internal sysregs[] = {
31 { "LBEG", 0, 0 },
32 { "LEND", 1, 0 },
33 { "LCOUNT", 2, 0 },
34 { "ACCLO", 16, 0 },
35 { "ACCHI", 17, 0 },
36 { "M0", 32, 0 },
37 { "M1", 33, 0 },
38 { "M2", 34, 0 },
39 { "M3", 35, 0 },
40 { "MMID", 89, 0 },
41 { "DDR", 104, 0 },
42 { "CONFIGID0", 176, 0 },
43 { "CONFIGID1", 208, 0 },
44 { "INTERRUPT", 226, 0 },
45 { "INTCLEAR", 227, 0 },
46 { "CCOUNT", 234, 0 },
47 { "PRID", 235, 0 },
48 { "ICOUNT", 236, 0 },
49 { "CCOMPARE0", 240, 0 },
50 { "CCOMPARE1", 241, 0 },
51 { "CCOMPARE2", 242, 0 },
52 { "VECBASE", 231, 0 },
53 { "EPC1", 177, 0 },
54 { "EPC2", 178, 0 },
55 { "EPC3", 179, 0 },
56 { "EPC4", 180, 0 },
57 { "EPC5", 181, 0 },
58 { "EPC6", 182, 0 },
59 { "EPC7", 183, 0 },
60 { "EXCSAVE1", 209, 0 },
61 { "EXCSAVE2", 210, 0 },
62 { "EXCSAVE3", 211, 0 },
63 { "EXCSAVE4", 212, 0 },
64 { "EXCSAVE5", 213, 0 },
65 { "EXCSAVE6", 214, 0 },
66 { "EXCSAVE7", 215, 0 },
67 { "EPS2", 194, 0 },
68 { "EPS3", 195, 0 },
69 { "EPS4", 196, 0 },
70 { "EPS5", 197, 0 },
71 { "EPS6", 198, 0 },
72 { "EPS7", 199, 0 },
73 { "EXCCAUSE", 232, 0 },
74 { "DEPC", 192, 0 },
75 { "EXCVADDR", 238, 0 },
76 { "WINDOWBASE", 72, 0 },
77 { "WINDOWSTART", 73, 0 },
78 { "SAR", 3, 0 },
79 { "PS", 230, 0 },
80 { "MISC0", 244, 0 },
81 { "MISC1", 245, 0 },
82 { "INTENABLE", 228, 0 },
83 { "DBREAKA0", 144, 0 },
84 { "DBREAKC0", 160, 0 },
85 { "DBREAKA1", 145, 0 },
86 { "DBREAKC1", 161, 0 },
87 { "IBREAKA0", 128, 0 },
88 { "IBREAKA1", 129, 0 },
89 { "IBREAKENABLE", 96, 0 },
90 { "ICOUNTLEVEL", 237, 0 },
91 { "DEBUGCAUSE", 233, 0 },
92 { "SCOMPARE1", 12, 0 },
93 { "ATOMCTL", 99, 0 },
94 { "EXPSTATE", 230, 1 }
95};
96
97#define NUM_SYSREGS 64
98#define MAX_SPECIAL_REG 245
99#define MAX_USER_REG 230
100
101\f
102/* Processor states. */
103
104static xtensa_state_internal states[] = {
105 { "LCOUNT", 32, 0 },
106 { "PC", 32, 0 },
107 { "ICOUNT", 32, 0 },
108 { "DDR", 32, 0 },
109 { "INTERRUPT", 22, 0 },
110 { "CCOUNT", 32, 0 },
111 { "XTSYNC", 1, 0 },
112 { "VECBASE", 22, 0 },
113 { "EPC1", 32, 0 },
114 { "EPC2", 32, 0 },
115 { "EPC3", 32, 0 },
116 { "EPC4", 32, 0 },
117 { "EPC5", 32, 0 },
118 { "EPC6", 32, 0 },
119 { "EPC7", 32, 0 },
120 { "EXCSAVE1", 32, 0 },
121 { "EXCSAVE2", 32, 0 },
122 { "EXCSAVE3", 32, 0 },
123 { "EXCSAVE4", 32, 0 },
124 { "EXCSAVE5", 32, 0 },
125 { "EXCSAVE6", 32, 0 },
126 { "EXCSAVE7", 32, 0 },
127 { "EPS2", 13, 0 },
128 { "EPS3", 13, 0 },
129 { "EPS4", 13, 0 },
130 { "EPS5", 13, 0 },
131 { "EPS6", 13, 0 },
132 { "EPS7", 13, 0 },
133 { "EXCCAUSE", 6, 0 },
134 { "PSINTLEVEL", 4, 0 },
135 { "PSUM", 1, 0 },
136 { "PSWOE", 1, 0 },
137 { "PSEXCM", 1, 0 },
138 { "DEPC", 32, 0 },
139 { "EXCVADDR", 32, 0 },
140 { "WindowBase", 3, 0 },
141 { "WindowStart", 8, 0 },
142 { "PSCALLINC", 2, 0 },
143 { "PSOWB", 4, 0 },
144 { "LBEG", 32, 0 },
145 { "LEND", 32, 0 },
146 { "SAR", 6, 0 },
147 { "MISC0", 32, 0 },
148 { "MISC1", 32, 0 },
149 { "ACC", 40, 0 },
150 { "InOCDMode", 1, 0 },
151 { "INTENABLE", 22, 0 },
152 { "DBREAKA0", 32, 0 },
153 { "DBREAKC0", 8, 0 },
154 { "DBREAKA1", 32, 0 },
155 { "DBREAKC1", 8, 0 },
156 { "IBREAKA0", 32, 0 },
157 { "IBREAKA1", 32, 0 },
158 { "IBREAKENABLE", 2, 0 },
159 { "ICOUNTLEVEL", 4, 0 },
160 { "DEBUGCAUSE", 6, 0 },
161 { "DBNUM", 4, 0 },
162 { "CCOMPARE0", 32, 0 },
163 { "CCOMPARE1", 32, 0 },
164 { "CCOMPARE2", 32, 0 },
165 { "SCOMPARE1", 32, 0 },
166 { "ATOMCTL", 6, 0 },
167 { "ERI_RAW_INTERLOCK", 1, 0 },
168 { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
169};
170
171#define NUM_STATES 64
172
173enum xtensa_state_id {
174 STATE_LCOUNT,
175 STATE_PC,
176 STATE_ICOUNT,
177 STATE_DDR,
178 STATE_INTERRUPT,
179 STATE_CCOUNT,
180 STATE_XTSYNC,
181 STATE_VECBASE,
182 STATE_EPC1,
183 STATE_EPC2,
184 STATE_EPC3,
185 STATE_EPC4,
186 STATE_EPC5,
187 STATE_EPC6,
188 STATE_EPC7,
189 STATE_EXCSAVE1,
190 STATE_EXCSAVE2,
191 STATE_EXCSAVE3,
192 STATE_EXCSAVE4,
193 STATE_EXCSAVE5,
194 STATE_EXCSAVE6,
195 STATE_EXCSAVE7,
196 STATE_EPS2,
197 STATE_EPS3,
198 STATE_EPS4,
199 STATE_EPS5,
200 STATE_EPS6,
201 STATE_EPS7,
202 STATE_EXCCAUSE,
203 STATE_PSINTLEVEL,
204 STATE_PSUM,
205 STATE_PSWOE,
206 STATE_PSEXCM,
207 STATE_DEPC,
208 STATE_EXCVADDR,
209 STATE_WindowBase,
210 STATE_WindowStart,
211 STATE_PSCALLINC,
212 STATE_PSOWB,
213 STATE_LBEG,
214 STATE_LEND,
215 STATE_SAR,
216 STATE_MISC0,
217 STATE_MISC1,
218 STATE_ACC,
219 STATE_InOCDMode,
220 STATE_INTENABLE,
221 STATE_DBREAKA0,
222 STATE_DBREAKC0,
223 STATE_DBREAKA1,
224 STATE_DBREAKC1,
225 STATE_IBREAKA0,
226 STATE_IBREAKA1,
227 STATE_IBREAKENABLE,
228 STATE_ICOUNTLEVEL,
229 STATE_DEBUGCAUSE,
230 STATE_DBNUM,
231 STATE_CCOMPARE0,
232 STATE_CCOMPARE1,
233 STATE_CCOMPARE2,
234 STATE_SCOMPARE1,
235 STATE_ATOMCTL,
236 STATE_ERI_RAW_INTERLOCK,
237 STATE_EXPSTATE
238};
239
240\f
241/* Field definitions. */
242
243static unsigned
244Field_t_Slot_inst_get (const xtensa_insnbuf insn)
245{
246 unsigned tie_t = 0;
247 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
248 return tie_t;
249}
250
251static void
252Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
253{
254 uint32 tie_t;
255 tie_t = (val << 28) >> 28;
256 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
257}
258
259static unsigned
260Field_s_Slot_inst_get (const xtensa_insnbuf insn)
261{
262 unsigned tie_t = 0;
263 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
264 return tie_t;
265}
266
267static void
268Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
269{
270 uint32 tie_t;
271 tie_t = (val << 28) >> 28;
272 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
273}
274
275static unsigned
276Field_r_Slot_inst_get (const xtensa_insnbuf insn)
277{
278 unsigned tie_t = 0;
279 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
280 return tie_t;
281}
282
283static void
284Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
285{
286 uint32 tie_t;
287 tie_t = (val << 28) >> 28;
288 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
289}
290
291static unsigned
292Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
293{
294 unsigned tie_t = 0;
295 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
296 return tie_t;
297}
298
299static void
300Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
301{
302 uint32 tie_t;
303 tie_t = (val << 28) >> 28;
304 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
305}
306
307static unsigned
308Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
309{
310 unsigned tie_t = 0;
311 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
312 return tie_t;
313}
314
315static void
316Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
317{
318 uint32 tie_t;
319 tie_t = (val << 28) >> 28;
320 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
321}
322
323static unsigned
324Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
325{
326 unsigned tie_t = 0;
327 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
328 return tie_t;
329}
330
331static void
332Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
333{
334 uint32 tie_t;
335 tie_t = (val << 28) >> 28;
336 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
337}
338
339static unsigned
340Field_n_Slot_inst_get (const xtensa_insnbuf insn)
341{
342 unsigned tie_t = 0;
343 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
344 return tie_t;
345}
346
347static void
348Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
349{
350 uint32 tie_t;
351 tie_t = (val << 30) >> 30;
352 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
353}
354
355static unsigned
356Field_m_Slot_inst_get (const xtensa_insnbuf insn)
357{
358 unsigned tie_t = 0;
359 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
360 return tie_t;
361}
362
363static void
364Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
365{
366 uint32 tie_t;
367 tie_t = (val << 30) >> 30;
368 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
369}
370
371static unsigned
372Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
373{
374 unsigned tie_t = 0;
375 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
376 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
377 return tie_t;
378}
379
380static void
381Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
382{
383 uint32 tie_t;
384 tie_t = (val << 28) >> 28;
385 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
386 tie_t = (val << 24) >> 28;
387 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
388}
389
390static unsigned
391Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
392{
393 unsigned tie_t = 0;
394 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
395 return tie_t;
396}
397
398static void
399Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
400{
401 uint32 tie_t;
402 tie_t = (val << 29) >> 29;
403 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
404}
405
406static unsigned
407Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
408{
409 unsigned tie_t = 0;
410 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
411 return tie_t;
412}
413
414static void
415Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
416{
417 uint32 tie_t;
418 tie_t = (val << 31) >> 31;
419 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
420}
421
422static unsigned
423Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
424{
425 unsigned tie_t = 0;
426 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
427 return tie_t;
428}
429
430static void
431Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
432{
433 uint32 tie_t;
434 tie_t = (val << 30) >> 30;
435 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
436}
437
438static unsigned
439Field_w_Slot_inst_get (const xtensa_insnbuf insn)
440{
441 unsigned tie_t = 0;
442 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
443 return tie_t;
444}
445
446static void
447Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
448{
449 uint32 tie_t;
450 tie_t = (val << 30) >> 30;
451 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
452}
453
454static unsigned
455Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
456{
457 unsigned tie_t = 0;
458 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
459 return tie_t;
460}
461
462static void
463Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
464{
465 uint32 tie_t;
466 tie_t = (val << 31) >> 31;
467 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
468}
469
470static unsigned
471Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
472{
473 unsigned tie_t = 0;
474 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
475 return tie_t;
476}
477
478static void
479Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
480{
481 uint32 tie_t;
482 tie_t = (val << 30) >> 30;
483 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
484}
485
486static unsigned
487Field_st_Slot_inst_get (const xtensa_insnbuf insn)
488{
489 unsigned tie_t = 0;
490 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
491 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
492 return tie_t;
493}
494
495static void
496Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
497{
498 uint32 tie_t;
499 tie_t = (val << 28) >> 28;
500 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
501 tie_t = (val << 24) >> 28;
502 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
503}
504
505static unsigned
506Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
507{
508 unsigned tie_t = 0;
509 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
510 return tie_t;
511}
512
513static void
514Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
515{
516 uint32 tie_t;
517 tie_t = (val << 29) >> 29;
518 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
519}
520
521static unsigned
522Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
523{
524 unsigned tie_t = 0;
525 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
526 return tie_t;
527}
528
529static void
530Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
531{
532 uint32 tie_t;
533 tie_t = (val << 28) >> 28;
534 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
535}
536
537static unsigned
538Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
539{
540 unsigned tie_t = 0;
541 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
542 return tie_t;
543}
544
545static void
546Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
547{
548 uint32 tie_t;
549 tie_t = (val << 28) >> 28;
550 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
551}
552
553static unsigned
554Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
555{
556 unsigned tie_t = 0;
557 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
558 return tie_t;
559}
560
561static void
562Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
563{
564 uint32 tie_t;
565 tie_t = (val << 28) >> 28;
566 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
567}
568
569static unsigned
570Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
571{
572 unsigned tie_t = 0;
573 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
574 return tie_t;
575}
576
577static void
578Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
579{
580 uint32 tie_t;
581 tie_t = (val << 28) >> 28;
582 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
583}
584
585static unsigned
586Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
587{
588 unsigned tie_t = 0;
589 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
590 return tie_t;
591}
592
593static void
594Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
595{
596 uint32 tie_t;
597 tie_t = (val << 31) >> 31;
598 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
599}
600
601static unsigned
602Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
603{
604 unsigned tie_t = 0;
605 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
606 return tie_t;
607}
608
609static void
610Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
611{
612 uint32 tie_t;
613 tie_t = (val << 31) >> 31;
614 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
615}
616
617static unsigned
618Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
619{
620 unsigned tie_t = 0;
621 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
622 return tie_t;
623}
624
625static void
626Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
627{
628 uint32 tie_t;
629 tie_t = (val << 28) >> 28;
630 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
631}
632
633static unsigned
634Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
635{
636 unsigned tie_t = 0;
637 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
638 return tie_t;
639}
640
641static void
642Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
643{
644 uint32 tie_t;
645 tie_t = (val << 28) >> 28;
646 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
647}
648
649static unsigned
650Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
651{
652 unsigned tie_t = 0;
653 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
654 return tie_t;
655}
656
657static void
658Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
659{
660 uint32 tie_t;
661 tie_t = (val << 31) >> 31;
662 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
663}
664
665static unsigned
666Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
667{
668 unsigned tie_t = 0;
669 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
670 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
671 return tie_t;
672}
673
674static void
675Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
676{
677 uint32 tie_t;
678 tie_t = (val << 28) >> 28;
679 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
680 tie_t = (val << 27) >> 31;
681 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
682}
683
684static unsigned
685Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
686{
687 unsigned tie_t = 0;
688 tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
689 return tie_t;
690}
691
692static void
693Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
694{
695 uint32 tie_t;
696 tie_t = (val << 20) >> 20;
697 insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
698}
699
700static unsigned
701Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
702{
703 unsigned tie_t = 0;
704 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
705 return tie_t;
706}
707
708static void
709Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
710{
711 uint32 tie_t;
712 tie_t = (val << 24) >> 24;
713 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
714}
715
716static unsigned
717Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
718{
719 unsigned tie_t = 0;
720 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
721 return tie_t;
722}
723
724static void
725Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
726{
727 uint32 tie_t;
728 tie_t = (val << 28) >> 28;
729 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
730}
731
732static unsigned
733Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
734{
735 unsigned tie_t = 0;
736 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
737 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
738 return tie_t;
739}
740
741static void
742Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
743{
744 uint32 tie_t;
745 tie_t = (val << 24) >> 24;
746 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
747 tie_t = (val << 20) >> 28;
748 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
749}
750
751static unsigned
752Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
753{
754 unsigned tie_t = 0;
755 tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
756 return tie_t;
757}
758
759static void
760Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
761{
762 uint32 tie_t;
763 tie_t = (val << 16) >> 16;
764 insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
765}
766
767static unsigned
768Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
769{
770 unsigned tie_t = 0;
771 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
772 return tie_t;
773}
774
775static void
776Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
777{
778 uint32 tie_t;
779 tie_t = (val << 14) >> 14;
780 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
781}
782
783static unsigned
784Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
785{
786 unsigned tie_t = 0;
787 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
788 return tie_t;
789}
790
791static void
792Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
793{
794 uint32 tie_t;
795 tie_t = (val << 28) >> 28;
796 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
797}
798
799static unsigned
800Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
801{
802 unsigned tie_t = 0;
803 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
804 return tie_t;
805}
806
807static void
808Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
809{
810 uint32 tie_t;
811 tie_t = (val << 31) >> 31;
812 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
813}
814
815static unsigned
816Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
817{
818 unsigned tie_t = 0;
819 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
820 return tie_t;
821}
822
823static void
824Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
825{
826 uint32 tie_t;
827 tie_t = (val << 31) >> 31;
828 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
829}
830
831static unsigned
832Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
833{
834 unsigned tie_t = 0;
835 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
836 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
837 return tie_t;
838}
839
840static void
841Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
842{
843 uint32 tie_t;
844 tie_t = (val << 28) >> 28;
845 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
846 tie_t = (val << 27) >> 31;
847 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
848}
849
850static unsigned
851Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
852{
853 unsigned tie_t = 0;
854 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
855 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
856 return tie_t;
857}
858
859static void
860Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
861{
862 uint32 tie_t;
863 tie_t = (val << 28) >> 28;
864 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
865 tie_t = (val << 27) >> 31;
866 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
867}
868
869static unsigned
870Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
871{
872 unsigned tie_t = 0;
873 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
874 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
875 return tie_t;
876}
877
878static void
879Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
880{
881 uint32 tie_t;
882 tie_t = (val << 28) >> 28;
883 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
884 tie_t = (val << 27) >> 31;
885 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
886}
887
888static unsigned
889Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
890{
891 unsigned tie_t = 0;
892 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
893 return tie_t;
894}
895
896static void
897Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
898{
899 uint32 tie_t;
900 tie_t = (val << 31) >> 31;
901 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
902}
903
904static unsigned
905Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
906{
907 unsigned tie_t = 0;
908 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
909 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
910 return tie_t;
911}
912
913static void
914Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
915{
916 uint32 tie_t;
917 tie_t = (val << 28) >> 28;
918 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
919 tie_t = (val << 27) >> 31;
920 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
921}
922
923static unsigned
924Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
925{
926 unsigned tie_t = 0;
927 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
928 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
929 return tie_t;
930}
931
932static void
933Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
934{
935 uint32 tie_t;
936 tie_t = (val << 28) >> 28;
937 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
938 tie_t = (val << 24) >> 28;
939 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
940}
941
942static unsigned
943Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
944{
945 unsigned tie_t = 0;
946 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
947 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
948 return tie_t;
949}
950
951static void
952Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
953{
954 uint32 tie_t;
955 tie_t = (val << 28) >> 28;
956 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
957 tie_t = (val << 24) >> 28;
958 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
959}
960
961static unsigned
962Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
963{
964 unsigned tie_t = 0;
965 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
966 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
967 return tie_t;
968}
969
970static void
971Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
972{
973 uint32 tie_t;
974 tie_t = (val << 28) >> 28;
975 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
976 tie_t = (val << 24) >> 28;
977 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
978}
979
980static unsigned
981Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
982{
983 unsigned tie_t = 0;
984 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
985 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
986 return tie_t;
987}
988
989static void
990Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
991{
992 uint32 tie_t;
993 tie_t = (val << 28) >> 28;
994 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
995 tie_t = (val << 24) >> 28;
996 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
997}
998
999static unsigned
1000Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
1001{
1002 unsigned tie_t = 0;
1003 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1004 return tie_t;
1005}
1006
1007static void
1008Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1009{
1010 uint32 tie_t;
1011 tie_t = (val << 28) >> 28;
1012 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1013}
1014
1015static unsigned
1016Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
1017{
1018 unsigned tie_t = 0;
1019 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1020 return tie_t;
1021}
1022
1023static void
1024Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1025{
1026 uint32 tie_t;
1027 tie_t = (val << 28) >> 28;
1028 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1029}
1030
1031static unsigned
1032Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
1033{
1034 unsigned tie_t = 0;
1035 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1036 return tie_t;
1037}
1038
1039static void
1040Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1041{
1042 uint32 tie_t;
1043 tie_t = (val << 28) >> 28;
1044 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1045}
1046
1047static unsigned
1048Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
1049{
1050 unsigned tie_t = 0;
1051 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
1052 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1053 return tie_t;
1054}
1055
1056static void
1057Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1058{
1059 uint32 tie_t;
1060 tie_t = (val << 30) >> 30;
1061 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1062 tie_t = (val << 28) >> 30;
1063 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
1064}
1065
1066static unsigned
1067Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
1068{
1069 unsigned tie_t = 0;
1070 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1071 return tie_t;
1072}
1073
1074static void
1075Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1076{
1077 uint32 tie_t;
1078 tie_t = (val << 31) >> 31;
1079 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1080}
1081
1082static unsigned
1083Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1084{
1085 unsigned tie_t = 0;
1086 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1087 return tie_t;
1088}
1089
1090static void
1091Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1092{
1093 uint32 tie_t;
1094 tie_t = (val << 28) >> 28;
1095 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1096}
1097
1098static unsigned
1099Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1100{
1101 unsigned tie_t = 0;
1102 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1103 return tie_t;
1104}
1105
1106static void
1107Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1108{
1109 uint32 tie_t;
1110 tie_t = (val << 28) >> 28;
1111 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1112}
1113
1114static unsigned
1115Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1116{
1117 unsigned tie_t = 0;
1118 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1119 return tie_t;
1120}
1121
1122static void
1123Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1124{
1125 uint32 tie_t;
1126 tie_t = (val << 30) >> 30;
1127 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1128}
1129
1130static unsigned
1131Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1132{
1133 unsigned tie_t = 0;
1134 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1135 return tie_t;
1136}
1137
1138static void
1139Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1140{
1141 uint32 tie_t;
1142 tie_t = (val << 30) >> 30;
1143 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1144}
1145
1146static unsigned
1147Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1148{
1149 unsigned tie_t = 0;
1150 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1151 return tie_t;
1152}
1153
1154static void
1155Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1156{
1157 uint32 tie_t;
1158 tie_t = (val << 28) >> 28;
1159 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1160}
1161
1162static unsigned
1163Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1164{
1165 unsigned tie_t = 0;
1166 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1167 return tie_t;
1168}
1169
1170static void
1171Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1172{
1173 uint32 tie_t;
1174 tie_t = (val << 28) >> 28;
1175 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1176}
1177
1178static unsigned
1179Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1180{
1181 unsigned tie_t = 0;
1182 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1183 return tie_t;
1184}
1185
1186static void
1187Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1188{
1189 uint32 tie_t;
1190 tie_t = (val << 29) >> 29;
1191 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1192}
1193
1194static unsigned
1195Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1196{
1197 unsigned tie_t = 0;
1198 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1199 return tie_t;
1200}
1201
1202static void
1203Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1204{
1205 uint32 tie_t;
1206 tie_t = (val << 29) >> 29;
1207 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1208}
1209
1210static unsigned
1211Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
1212{
1213 unsigned tie_t = 0;
1214 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1215 return tie_t;
1216}
1217
1218static void
1219Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1220{
1221 uint32 tie_t;
1222 tie_t = (val << 31) >> 31;
1223 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1224}
1225
1226static unsigned
1227Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
1228{
1229 unsigned tie_t = 0;
1230 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1231 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1232 return tie_t;
1233}
1234
1235static void
1236Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1237{
1238 uint32 tie_t;
1239 tie_t = (val << 28) >> 28;
1240 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1241 tie_t = (val << 26) >> 30;
1242 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1243}
1244
1245static unsigned
1246Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
1247{
1248 unsigned tie_t = 0;
1249 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1250 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1251 return tie_t;
1252}
1253
1254static void
1255Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1256{
1257 uint32 tie_t;
1258 tie_t = (val << 28) >> 28;
1259 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1260 tie_t = (val << 26) >> 30;
1261 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1262}
1263
1264static unsigned
1265Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
1266{
1267 unsigned tie_t = 0;
1268 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1269 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1270 return tie_t;
1271}
1272
1273static void
1274Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1275{
1276 uint32 tie_t;
1277 tie_t = (val << 28) >> 28;
1278 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1279 tie_t = (val << 25) >> 29;
1280 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1281}
1282
1283static unsigned
1284Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
1285{
1286 unsigned tie_t = 0;
1287 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1288 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1289 return tie_t;
1290}
1291
1292static void
1293Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1294{
1295 uint32 tie_t;
1296 tie_t = (val << 28) >> 28;
1297 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1298 tie_t = (val << 25) >> 29;
1299 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1300}
1301
1302static unsigned
1303Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
1304{
1305 unsigned tie_t = 0;
1306 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1307 return tie_t;
1308}
1309
1310static void
1311Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1312{
1313 uint32 tie_t;
1314 tie_t = (val << 31) >> 31;
1315 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1316}
1317
1318static unsigned
1319Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
1320{
1321 unsigned tie_t = 0;
1322 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1323 return tie_t;
1324}
1325
1326static void
1327Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1328{
1329 uint32 tie_t;
1330 tie_t = (val << 31) >> 31;
1331 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1332}
1333
1334static unsigned
1335Field_y_Slot_inst_get (const xtensa_insnbuf insn)
1336{
1337 unsigned tie_t = 0;
1338 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1339 return tie_t;
1340}
1341
1342static void
1343Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1344{
1345 uint32 tie_t;
1346 tie_t = (val << 31) >> 31;
1347 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1348}
1349
1350static unsigned
1351Field_x_Slot_inst_get (const xtensa_insnbuf insn)
1352{
1353 unsigned tie_t = 0;
1354 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1355 return tie_t;
1356}
1357
1358static void
1359Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1360{
1361 uint32 tie_t;
1362 tie_t = (val << 31) >> 31;
1363 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1364}
1365
1366static unsigned
1367Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
1368{
1369 unsigned tie_t = 0;
1370 tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
1371 return tie_t;
1372}
1373
1374static void
1375Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1376{
1377 uint32 tie_t;
1378 tie_t = (val << 17) >> 17;
1379 insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
1380}
1381
1382static unsigned
1383Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
1384{
1385 unsigned tie_t = 0;
1386 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
1387 return tie_t;
1388}
1389
1390static void
1391Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1392{
1393 uint32 tie_t;
1394 tie_t = (val << 14) >> 14;
1395 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
1396}
1397
1398static unsigned
1399Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
1400{
1401 unsigned tie_t = 0;
1402 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1403 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1404 return tie_t;
1405}
1406
1407static void
1408Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1409{
1410 uint32 tie_t;
1411 tie_t = (val << 28) >> 28;
1412 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1413 tie_t = (val << 27) >> 31;
1414 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1415}
1416
1417static unsigned
1418Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
1419{
1420 unsigned tie_t = 0;
1421 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1422 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1423 return tie_t;
1424}
1425
1426static void
1427Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1428{
1429 uint32 tie_t;
1430 tie_t = (val << 28) >> 28;
1431 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1432 tie_t = (val << 27) >> 31;
1433 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1434}
1435
1436static unsigned
1437Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
1438{
1439 unsigned tie_t = 0;
1440 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1441 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1442 return tie_t;
1443}
1444
1445static void
1446Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1447{
1448 uint32 tie_t;
1449 tie_t = (val << 28) >> 28;
1450 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1451 tie_t = (val << 27) >> 31;
1452 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1453}
1454
1455static unsigned
1456Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
1457{
1458 unsigned tie_t = 0;
1459 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1460 return tie_t;
1461}
1462
1463static void
1464Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1465{
1466 uint32 tie_t;
1467 tie_t = (val << 29) >> 29;
1468 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1469}
1470
1471static unsigned
1472Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
1473{
1474 unsigned tie_t = 0;
1475 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1476 return tie_t;
1477}
1478
1479static void
1480Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1481{
1482 uint32 tie_t;
1483 tie_t = (val << 29) >> 29;
1484 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1485}
1486
1487static void
1488Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
1489 uint32 val ATTRIBUTE_UNUSED)
1490{
1491 /* Do nothing. */
1492}
1493
1494static unsigned
1495Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1496{
1497 return 0;
1498}
1499
1500static unsigned
1501Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1502{
1503 return 4;
1504}
1505
1506static unsigned
1507Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1508{
1509 return 8;
1510}
1511
1512static unsigned
1513Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1514{
1515 return 12;
1516}
1517
1518static unsigned
1519Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1520{
1521 return 0;
1522}
1523
1524static unsigned
1525Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1526{
1527 return 1;
1528}
1529
1530static unsigned
1531Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1532{
1533 return 2;
1534}
1535
1536static unsigned
1537Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1538{
1539 return 3;
1540}
1541
1542enum xtensa_field_id {
1543 FIELD_t,
1544 FIELD_bbi4,
1545 FIELD_bbi,
1546 FIELD_imm12,
1547 FIELD_imm8,
1548 FIELD_s,
1549 FIELD_imm12b,
1550 FIELD_imm16,
1551 FIELD_m,
1552 FIELD_n,
1553 FIELD_offset,
1554 FIELD_op0,
1555 FIELD_op1,
1556 FIELD_op2,
1557 FIELD_r,
1558 FIELD_sa4,
1559 FIELD_sae4,
1560 FIELD_sae,
1561 FIELD_sal,
1562 FIELD_sargt,
1563 FIELD_sas4,
1564 FIELD_sas,
1565 FIELD_sr,
1566 FIELD_st,
1567 FIELD_thi3,
1568 FIELD_imm4,
1569 FIELD_mn,
1570 FIELD_i,
1571 FIELD_imm6lo,
1572 FIELD_imm6hi,
1573 FIELD_imm7lo,
1574 FIELD_imm7hi,
1575 FIELD_z,
1576 FIELD_imm6,
1577 FIELD_imm7,
1578 FIELD_r3,
1579 FIELD_rbit2,
1580 FIELD_rhi,
1581 FIELD_t3,
1582 FIELD_tbit2,
1583 FIELD_tlo,
1584 FIELD_w,
1585 FIELD_y,
1586 FIELD_x,
1587 FIELD_xt_wbr15_imm,
1588 FIELD_xt_wbr18_imm,
1589 FIELD_bitindex,
1590 FIELD_s3to1,
1591 FIELD__ar0,
1592 FIELD__ar4,
1593 FIELD__ar8,
1594 FIELD__ar12,
1595 FIELD__mr0,
1596 FIELD__mr1,
1597 FIELD__mr2,
1598 FIELD__mr3
1599};
1600
1601\f
1602/* Functional units. */
1603
1604#define funcUnits 0
1605
1606\f
1607/* Register files. */
1608
1609enum xtensa_regfile_id {
1610 REGFILE_AR,
1611 REGFILE_MR
1612};
1613
1614static xtensa_regfile_internal regfiles[] = {
1615 { "AR", "a", REGFILE_AR, 32, 32 },
1616 { "MR", "m", REGFILE_MR, 32, 4 }
1617};
1618
1619\f
1620/* Interfaces. */
1621
1622static xtensa_interface_internal interfaces[] = {
1623 { "ERI_RD_Out", 14, 0, 0, 'o' },
1624 { "ERI_RD_In", 32, 0, 1, 'i' },
1625 { "ERI_RD_Rdy", 1, 0, 0, 'i' },
1626 { "ERI_WR_Out", 46, 0, 2, 'o' },
1627 { "ERI_WR_In", 1, 0, 3, 'i' },
1628 { "IMPWIRE", 32, 0, 4, 'i' }
1629};
1630
1631enum xtensa_interface_id {
1632 INTERFACE_ERI_RD_Out,
1633 INTERFACE_ERI_RD_In,
1634 INTERFACE_ERI_RD_Rdy,
1635 INTERFACE_ERI_WR_Out,
1636 INTERFACE_ERI_WR_In,
1637 INTERFACE_IMPWIRE
1638};
1639
1640
1641/* Constant tables. */
1642
1643/* constant table ai4c */
1644static const unsigned CONST_TBL_ai4c_0[] = {
1645 0xffffffff,
1646 0x1,
1647 0x2,
1648 0x3,
1649 0x4,
1650 0x5,
1651 0x6,
1652 0x7,
1653 0x8,
1654 0x9,
1655 0xa,
1656 0xb,
1657 0xc,
1658 0xd,
1659 0xe,
1660 0xf,
1661 0
1662};
1663
1664/* constant table b4c */
1665static const unsigned CONST_TBL_b4c_0[] = {
1666 0xffffffff,
1667 0x1,
1668 0x2,
1669 0x3,
1670 0x4,
1671 0x5,
1672 0x6,
1673 0x7,
1674 0x8,
1675 0xa,
1676 0xc,
1677 0x10,
1678 0x20,
1679 0x40,
1680 0x80,
1681 0x100,
1682 0
1683};
1684
1685/* constant table b4cu */
1686static const unsigned CONST_TBL_b4cu_0[] = {
1687 0x8000,
1688 0x10000,
1689 0x2,
1690 0x3,
1691 0x4,
1692 0x5,
1693 0x6,
1694 0x7,
1695 0x8,
1696 0xa,
1697 0xc,
1698 0x10,
1699 0x20,
1700 0x40,
1701 0x80,
1702 0x100,
1703 0
1704};
1705
1706\f
1707/* Instruction operands. */
1708
1709static int
1710OperandSem_opnd_sem_MR_0_decode (uint32 *valp)
1711{
1712 *valp += 2;
1713 return 0;
1714}
1715
1716static int
1717OperandSem_opnd_sem_MR_0_encode (uint32 *valp)
1718{
1719 int error;
1720 error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
1721 *valp = *valp & 1;
1722 return error;
1723}
1724
1725static int
1726OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
1727{
1728 unsigned soffsetx4_out_0;
1729 unsigned soffsetx4_in_0;
1730 soffsetx4_in_0 = *valp & 0x3ffff;
1731 soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
1732 *valp = soffsetx4_out_0;
1733 return 0;
1734}
1735
1736static int
1737OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
1738{
1739 unsigned soffsetx4_in_0;
1740 unsigned soffsetx4_out_0;
1741 soffsetx4_out_0 = *valp;
1742 soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
1743 *valp = soffsetx4_in_0;
1744 return 0;
1745}
1746
1747static int
1748OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
1749{
1750 unsigned uimm12x8_out_0;
1751 unsigned uimm12x8_in_0;
1752 uimm12x8_in_0 = *valp & 0xfff;
1753 uimm12x8_out_0 = uimm12x8_in_0 << 3;
1754 *valp = uimm12x8_out_0;
1755 return 0;
1756}
1757
1758static int
1759OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
1760{
1761 unsigned uimm12x8_in_0;
1762 unsigned uimm12x8_out_0;
1763 uimm12x8_out_0 = *valp;
1764 uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
1765 *valp = uimm12x8_in_0;
1766 return 0;
1767}
1768
1769static int
1770OperandSem_opnd_sem_simm4_decode (uint32 *valp)
1771{
1772 unsigned simm4_out_0;
1773 unsigned simm4_in_0;
1774 simm4_in_0 = *valp & 0xf;
1775 simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
1776 *valp = simm4_out_0;
1777 return 0;
1778}
1779
1780static int
1781OperandSem_opnd_sem_simm4_encode (uint32 *valp)
1782{
1783 unsigned simm4_in_0;
1784 unsigned simm4_out_0;
1785 simm4_out_0 = *valp;
1786 simm4_in_0 = (simm4_out_0 & 0xf);
1787 *valp = simm4_in_0;
1788 return 0;
1789}
1790
1791static int
1792OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
1793{
1794 return 0;
1795}
1796
1797static int
1798OperandSem_opnd_sem_AR_encode (uint32 *valp)
1799{
1800 int error;
1801 error = (*valp >= 32);
1802 return error;
1803}
1804
1805static int
1806OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
1807{
1808 return 0;
1809}
1810
1811static int
1812OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
1813{
1814 int error;
1815 error = (*valp >= 32);
1816 return error;
1817}
1818
1819static int
1820OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
1821{
1822 return 0;
1823}
1824
1825static int
1826OperandSem_opnd_sem_AR_1_encode (uint32 *valp)
1827{
1828 int error;
1829 error = (*valp >= 32);
1830 return error;
1831}
1832
1833static int
1834OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
1835{
1836 return 0;
1837}
1838
1839static int
1840OperandSem_opnd_sem_AR_2_encode (uint32 *valp)
1841{
1842 int error;
1843 error = (*valp >= 32);
1844 return error;
1845}
1846
1847static int
1848OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
1849{
1850 return 0;
1851}
1852
1853static int
1854OperandSem_opnd_sem_AR_3_encode (uint32 *valp)
1855{
1856 int error;
1857 error = (*valp >= 32);
1858 return error;
1859}
1860
1861static int
1862OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
1863{
1864 return 0;
1865}
1866
1867static int
1868OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
1869{
1870 int error;
1871 error = (*valp >= 32);
1872 return error;
1873}
1874
1875static int
1876OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
1877{
1878 unsigned immrx4_out_0;
1879 unsigned immrx4_in_0;
1880 immrx4_in_0 = *valp & 0xf;
1881 immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
1882 *valp = immrx4_out_0;
1883 return 0;
1884}
1885
1886static int
1887OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
1888{
1889 unsigned immrx4_in_0;
1890 unsigned immrx4_out_0;
1891 immrx4_out_0 = *valp;
1892 immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
1893 *valp = immrx4_in_0;
1894 return 0;
1895}
1896
1897static int
1898OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
1899{
1900 unsigned lsi4x4_out_0;
1901 unsigned lsi4x4_in_0;
1902 lsi4x4_in_0 = *valp & 0xf;
1903 lsi4x4_out_0 = lsi4x4_in_0 << 2;
1904 *valp = lsi4x4_out_0;
1905 return 0;
1906}
1907
1908static int
1909OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
1910{
1911 unsigned lsi4x4_in_0;
1912 unsigned lsi4x4_out_0;
1913 lsi4x4_out_0 = *valp;
1914 lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
1915 *valp = lsi4x4_in_0;
1916 return 0;
1917}
1918
1919static int
1920OperandSem_opnd_sem_simm7_decode (uint32 *valp)
1921{
1922 unsigned simm7_out_0;
1923 unsigned simm7_in_0;
1924 simm7_in_0 = *valp & 0x7f;
1925 simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
1926 *valp = simm7_out_0;
1927 return 0;
1928}
1929
1930static int
1931OperandSem_opnd_sem_simm7_encode (uint32 *valp)
1932{
1933 unsigned simm7_in_0;
1934 unsigned simm7_out_0;
1935 simm7_out_0 = *valp;
1936 simm7_in_0 = (simm7_out_0 & 0x7f);
1937 *valp = simm7_in_0;
1938 return 0;
1939}
1940
1941static int
1942OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
1943{
1944 unsigned uimm6_out_0;
1945 unsigned uimm6_in_0;
1946 uimm6_in_0 = *valp & 0x3f;
1947 uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
1948 *valp = uimm6_out_0;
1949 return 0;
1950}
1951
1952static int
1953OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
1954{
1955 unsigned uimm6_in_0;
1956 unsigned uimm6_out_0;
1957 uimm6_out_0 = *valp;
1958 uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
1959 *valp = uimm6_in_0;
1960 return 0;
1961}
1962
1963static int
1964OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
1965{
1966 unsigned ai4const_out_0;
1967 unsigned ai4const_in_0;
1968 ai4const_in_0 = *valp & 0xf;
1969 ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
1970 *valp = ai4const_out_0;
1971 return 0;
1972}
1973
1974static int
1975OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
1976{
1977 unsigned ai4const_in_0;
1978 unsigned ai4const_out_0;
1979 ai4const_out_0 = *valp;
1980 switch (ai4const_out_0)
1981 {
1982 case 0xffffffff: ai4const_in_0 = 0; break;
1983 case 0x1: ai4const_in_0 = 0x1; break;
1984 case 0x2: ai4const_in_0 = 0x2; break;
1985 case 0x3: ai4const_in_0 = 0x3; break;
1986 case 0x4: ai4const_in_0 = 0x4; break;
1987 case 0x5: ai4const_in_0 = 0x5; break;
1988 case 0x6: ai4const_in_0 = 0x6; break;
1989 case 0x7: ai4const_in_0 = 0x7; break;
1990 case 0x8: ai4const_in_0 = 0x8; break;
1991 case 0x9: ai4const_in_0 = 0x9; break;
1992 case 0xa: ai4const_in_0 = 0xa; break;
1993 case 0xb: ai4const_in_0 = 0xb; break;
1994 case 0xc: ai4const_in_0 = 0xc; break;
1995 case 0xd: ai4const_in_0 = 0xd; break;
1996 case 0xe: ai4const_in_0 = 0xe; break;
1997 default: ai4const_in_0 = 0xf; break;
1998 }
1999 *valp = ai4const_in_0;
2000 return 0;
2001}
2002
2003static int
2004OperandSem_opnd_sem_b4const_decode (uint32 *valp)
2005{
2006 unsigned b4const_out_0;
2007 unsigned b4const_in_0;
2008 b4const_in_0 = *valp & 0xf;
2009 b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
2010 *valp = b4const_out_0;
2011 return 0;
2012}
2013
2014static int
2015OperandSem_opnd_sem_b4const_encode (uint32 *valp)
2016{
2017 unsigned b4const_in_0;
2018 unsigned b4const_out_0;
2019 b4const_out_0 = *valp;
2020 switch (b4const_out_0)
2021 {
2022 case 0xffffffff: b4const_in_0 = 0; break;
2023 case 0x1: b4const_in_0 = 0x1; break;
2024 case 0x2: b4const_in_0 = 0x2; break;
2025 case 0x3: b4const_in_0 = 0x3; break;
2026 case 0x4: b4const_in_0 = 0x4; break;
2027 case 0x5: b4const_in_0 = 0x5; break;
2028 case 0x6: b4const_in_0 = 0x6; break;
2029 case 0x7: b4const_in_0 = 0x7; break;
2030 case 0x8: b4const_in_0 = 0x8; break;
2031 case 0xa: b4const_in_0 = 0x9; break;
2032 case 0xc: b4const_in_0 = 0xa; break;
2033 case 0x10: b4const_in_0 = 0xb; break;
2034 case 0x20: b4const_in_0 = 0xc; break;
2035 case 0x40: b4const_in_0 = 0xd; break;
2036 case 0x80: b4const_in_0 = 0xe; break;
2037 default: b4const_in_0 = 0xf; break;
2038 }
2039 *valp = b4const_in_0;
2040 return 0;
2041}
2042
2043static int
2044OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
2045{
2046 unsigned b4constu_out_0;
2047 unsigned b4constu_in_0;
2048 b4constu_in_0 = *valp & 0xf;
2049 b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
2050 *valp = b4constu_out_0;
2051 return 0;
2052}
2053
2054static int
2055OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
2056{
2057 unsigned b4constu_in_0;
2058 unsigned b4constu_out_0;
2059 b4constu_out_0 = *valp;
2060 switch (b4constu_out_0)
2061 {
2062 case 0x8000: b4constu_in_0 = 0; break;
2063 case 0x10000: b4constu_in_0 = 0x1; break;
2064 case 0x2: b4constu_in_0 = 0x2; break;
2065 case 0x3: b4constu_in_0 = 0x3; break;
2066 case 0x4: b4constu_in_0 = 0x4; break;
2067 case 0x5: b4constu_in_0 = 0x5; break;
2068 case 0x6: b4constu_in_0 = 0x6; break;
2069 case 0x7: b4constu_in_0 = 0x7; break;
2070 case 0x8: b4constu_in_0 = 0x8; break;
2071 case 0xa: b4constu_in_0 = 0x9; break;
2072 case 0xc: b4constu_in_0 = 0xa; break;
2073 case 0x10: b4constu_in_0 = 0xb; break;
2074 case 0x20: b4constu_in_0 = 0xc; break;
2075 case 0x40: b4constu_in_0 = 0xd; break;
2076 case 0x80: b4constu_in_0 = 0xe; break;
2077 default: b4constu_in_0 = 0xf; break;
2078 }
2079 *valp = b4constu_in_0;
2080 return 0;
2081}
2082
2083static int
2084OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
2085{
2086 unsigned uimm8_out_0;
2087 unsigned uimm8_in_0;
2088 uimm8_in_0 = *valp & 0xff;
2089 uimm8_out_0 = uimm8_in_0;
2090 *valp = uimm8_out_0;
2091 return 0;
2092}
2093
2094static int
2095OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
2096{
2097 unsigned uimm8_in_0;
2098 unsigned uimm8_out_0;
2099 uimm8_out_0 = *valp;
2100 uimm8_in_0 = (uimm8_out_0 & 0xff);
2101 *valp = uimm8_in_0;
2102 return 0;
2103}
2104
2105static int
2106OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
2107{
2108 unsigned uimm8x2_out_0;
2109 unsigned uimm8x2_in_0;
2110 uimm8x2_in_0 = *valp & 0xff;
2111 uimm8x2_out_0 = uimm8x2_in_0 << 1;
2112 *valp = uimm8x2_out_0;
2113 return 0;
2114}
2115
2116static int
2117OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
2118{
2119 unsigned uimm8x2_in_0;
2120 unsigned uimm8x2_out_0;
2121 uimm8x2_out_0 = *valp;
2122 uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
2123 *valp = uimm8x2_in_0;
2124 return 0;
2125}
2126
2127static int
2128OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
2129{
2130 unsigned uimm8x4_out_0;
2131 unsigned uimm8x4_in_0;
2132 uimm8x4_in_0 = *valp & 0xff;
2133 uimm8x4_out_0 = uimm8x4_in_0 << 2;
2134 *valp = uimm8x4_out_0;
2135 return 0;
2136}
2137
2138static int
2139OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
2140{
2141 unsigned uimm8x4_in_0;
2142 unsigned uimm8x4_out_0;
2143 uimm8x4_out_0 = *valp;
2144 uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
2145 *valp = uimm8x4_in_0;
2146 return 0;
2147}
2148
2149static int
2150OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
2151{
2152 unsigned uimm4x16_out_0;
2153 unsigned uimm4x16_in_0;
2154 uimm4x16_in_0 = *valp & 0xf;
2155 uimm4x16_out_0 = uimm4x16_in_0 << 4;
2156 *valp = uimm4x16_out_0;
2157 return 0;
2158}
2159
2160static int
2161OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
2162{
2163 unsigned uimm4x16_in_0;
2164 unsigned uimm4x16_out_0;
2165 uimm4x16_out_0 = *valp;
2166 uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
2167 *valp = uimm4x16_in_0;
2168 return 0;
2169}
2170
2171static int
2172OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp)
2173{
2174 unsigned uimmrx4_out_0;
2175 unsigned uimmrx4_in_0;
2176 uimmrx4_in_0 = *valp & 0xf;
2177 uimmrx4_out_0 = uimmrx4_in_0 << 2;
2178 *valp = uimmrx4_out_0;
2179 return 0;
2180}
2181
2182static int
2183OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp)
2184{
2185 unsigned uimmrx4_in_0;
2186 unsigned uimmrx4_out_0;
2187 uimmrx4_out_0 = *valp;
2188 uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf);
2189 *valp = uimmrx4_in_0;
2190 return 0;
2191}
2192
2193static int
2194OperandSem_opnd_sem_simm8_decode (uint32 *valp)
2195{
2196 unsigned simm8_out_0;
2197 unsigned simm8_in_0;
2198 simm8_in_0 = *valp & 0xff;
2199 simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
2200 *valp = simm8_out_0;
2201 return 0;
2202}
2203
2204static int
2205OperandSem_opnd_sem_simm8_encode (uint32 *valp)
2206{
2207 unsigned simm8_in_0;
2208 unsigned simm8_out_0;
2209 simm8_out_0 = *valp;
2210 simm8_in_0 = (simm8_out_0 & 0xff);
2211 *valp = simm8_in_0;
2212 return 0;
2213}
2214
2215static int
2216OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
2217{
2218 unsigned simm8x256_out_0;
2219 unsigned simm8x256_in_0;
2220 simm8x256_in_0 = *valp & 0xff;
2221 simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
2222 *valp = simm8x256_out_0;
2223 return 0;
2224}
2225
2226static int
2227OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
2228{
2229 unsigned simm8x256_in_0;
2230 unsigned simm8x256_out_0;
2231 simm8x256_out_0 = *valp;
2232 simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
2233 *valp = simm8x256_in_0;
2234 return 0;
2235}
2236
2237static int
2238OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
2239{
2240 unsigned simm12b_out_0;
2241 unsigned simm12b_in_0;
2242 simm12b_in_0 = *valp & 0xfff;
2243 simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
2244 *valp = simm12b_out_0;
2245 return 0;
2246}
2247
2248static int
2249OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
2250{
2251 unsigned simm12b_in_0;
2252 unsigned simm12b_out_0;
2253 simm12b_out_0 = *valp;
2254 simm12b_in_0 = (simm12b_out_0 & 0xfff);
2255 *valp = simm12b_in_0;
2256 return 0;
2257}
2258
2259static int
2260OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
2261{
2262 unsigned msalp32_out_0;
2263 unsigned msalp32_in_0;
2264 msalp32_in_0 = *valp & 0x1f;
2265 msalp32_out_0 = 0x20 - msalp32_in_0;
2266 *valp = msalp32_out_0;
2267 return 0;
2268}
2269
2270static int
2271OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
2272{
2273 unsigned msalp32_in_0;
2274 unsigned msalp32_out_0;
2275 msalp32_out_0 = *valp;
2276 msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
2277 *valp = msalp32_in_0;
2278 return 0;
2279}
2280
2281static int
2282OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
2283{
2284 unsigned op2p1_out_0;
2285 unsigned op2p1_in_0;
2286 op2p1_in_0 = *valp & 0xf;
2287 op2p1_out_0 = op2p1_in_0 + 0x1;
2288 *valp = op2p1_out_0;
2289 return 0;
2290}
2291
2292static int
2293OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
2294{
2295 unsigned op2p1_in_0;
2296 unsigned op2p1_out_0;
2297 op2p1_out_0 = *valp;
2298 op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
2299 *valp = op2p1_in_0;
2300 return 0;
2301}
2302
2303static int
2304OperandSem_opnd_sem_label8_decode (uint32 *valp)
2305{
2306 unsigned label8_out_0;
2307 unsigned label8_in_0;
2308 label8_in_0 = *valp & 0xff;
2309 label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
2310 *valp = label8_out_0;
2311 return 0;
2312}
2313
2314static int
2315OperandSem_opnd_sem_label8_encode (uint32 *valp)
2316{
2317 unsigned label8_in_0;
2318 unsigned label8_out_0;
2319 label8_out_0 = *valp;
2320 label8_in_0 = (label8_out_0 - 0x4) & 0xff;
2321 *valp = label8_in_0;
2322 return 0;
2323}
2324
2325static int
2326OperandSem_opnd_sem_ulabel8_decode (uint32 *valp)
2327{
2328 unsigned ulabel8_out_0;
2329 unsigned ulabel8_in_0;
2330 ulabel8_in_0 = *valp & 0xff;
2331 ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0);
2332 *valp = ulabel8_out_0;
2333 return 0;
2334}
2335
2336static int
2337OperandSem_opnd_sem_ulabel8_encode (uint32 *valp)
2338{
2339 unsigned ulabel8_in_0;
2340 unsigned ulabel8_out_0;
2341 ulabel8_out_0 = *valp;
2342 ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff;
2343 *valp = ulabel8_in_0;
2344 return 0;
2345}
2346
2347static int
2348OperandSem_opnd_sem_label12_decode (uint32 *valp)
2349{
2350 unsigned label12_out_0;
2351 unsigned label12_in_0;
2352 label12_in_0 = *valp & 0xfff;
2353 label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
2354 *valp = label12_out_0;
2355 return 0;
2356}
2357
2358static int
2359OperandSem_opnd_sem_label12_encode (uint32 *valp)
2360{
2361 unsigned label12_in_0;
2362 unsigned label12_out_0;
2363 label12_out_0 = *valp;
2364 label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
2365 *valp = label12_in_0;
2366 return 0;
2367}
2368
2369static int
2370OperandSem_opnd_sem_soffset_decode (uint32 *valp)
2371{
2372 unsigned soffset_out_0;
2373 unsigned soffset_in_0;
2374 soffset_in_0 = *valp & 0x3ffff;
2375 soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
2376 *valp = soffset_out_0;
2377 return 0;
2378}
2379
2380static int
2381OperandSem_opnd_sem_soffset_encode (uint32 *valp)
2382{
2383 unsigned soffset_in_0;
2384 unsigned soffset_out_0;
2385 soffset_out_0 = *valp;
2386 soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
2387 *valp = soffset_in_0;
2388 return 0;
2389}
2390
2391static int
2392OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
2393{
2394 unsigned uimm16x4_out_0;
2395 unsigned uimm16x4_in_0;
2396 uimm16x4_in_0 = *valp & 0xffff;
2397 uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
2398 *valp = uimm16x4_out_0;
2399 return 0;
2400}
2401
2402static int
2403OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
2404{
2405 unsigned uimm16x4_in_0;
2406 unsigned uimm16x4_out_0;
2407 uimm16x4_out_0 = *valp;
2408 uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
2409 *valp = uimm16x4_in_0;
2410 return 0;
2411}
2412
2413static int
2414OperandSem_opnd_sem_bbi_decode (uint32 *valp)
2415{
2416 unsigned bbi_out_0;
2417 unsigned bbi_in_0;
2418 bbi_in_0 = *valp & 0x1f;
2419 bbi_out_0 = (0 << 5) | bbi_in_0;
2420 *valp = bbi_out_0;
2421 return 0;
2422}
2423
2424static int
2425OperandSem_opnd_sem_bbi_encode (uint32 *valp)
2426{
2427 unsigned bbi_in_0;
2428 unsigned bbi_out_0;
2429 bbi_out_0 = *valp;
2430 bbi_in_0 = (bbi_out_0 & 0x1f);
2431 *valp = bbi_in_0;
2432 return 0;
2433}
2434
2435static int
2436OperandSem_opnd_sem_s_decode (uint32 *valp)
2437{
2438 unsigned s_out_0;
2439 unsigned s_in_0;
2440 s_in_0 = *valp & 0xf;
2441 s_out_0 = (0 << 4) | s_in_0;
2442 *valp = s_out_0;
2443 return 0;
2444}
2445
2446static int
2447OperandSem_opnd_sem_s_encode (uint32 *valp)
2448{
2449 unsigned s_in_0;
2450 unsigned s_out_0;
2451 s_out_0 = *valp;
2452 s_in_0 = (s_out_0 & 0xf);
2453 *valp = s_in_0;
2454 return 0;
2455}
2456
2457static int
2458OperandSem_opnd_sem_MR_decode (uint32 *valp ATTRIBUTE_UNUSED)
2459{
2460 return 0;
2461}
2462
2463static int
2464OperandSem_opnd_sem_MR_encode (uint32 *valp)
2465{
2466 int error;
2467 error = (*valp >= 4);
2468 return error;
2469}
2470
2471static int
2472OperandSem_opnd_sem_MR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
2473{
2474 return 0;
2475}
2476
2477static int
2478OperandSem_opnd_sem_MR_1_encode (uint32 *valp)
2479{
2480 int error;
2481 error = (*valp >= 4);
2482 return error;
2483}
2484
2485static int
2486OperandSem_opnd_sem_MR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
2487{
2488 return 0;
2489}
2490
2491static int
2492OperandSem_opnd_sem_MR_2_encode (uint32 *valp)
2493{
2494 int error;
2495 error = (*valp >= 4);
2496 return error;
2497}
2498
2499static int
2500OperandSem_opnd_sem_MR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
2501{
2502 return 0;
2503}
2504
2505static int
2506OperandSem_opnd_sem_MR_3_encode (uint32 *valp)
2507{
2508 int error;
2509 error = (*valp >= 4);
2510 return error;
2511}
2512
2513static int
2514OperandSem_opnd_sem_MR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
2515{
2516 return 0;
2517}
2518
2519static int
2520OperandSem_opnd_sem_MR_4_encode (uint32 *valp)
2521{
2522 int error;
2523 error = (*valp >= 4);
2524 return error;
2525}
2526
2527static int
2528OperandSem_opnd_sem_MR_5_decode (uint32 *valp ATTRIBUTE_UNUSED)
2529{
2530 return 0;
2531}
2532
2533static int
2534OperandSem_opnd_sem_MR_5_encode (uint32 *valp)
2535{
2536 int error;
2537 error = (*valp >= 4);
2538 return error;
2539}
2540
2541static int
2542OperandSem_opnd_sem_immt_decode (uint32 *valp)
2543{
2544 unsigned immt_out_0;
2545 unsigned immt_in_0;
2546 immt_in_0 = *valp & 0xf;
2547 immt_out_0 = immt_in_0;
2548 *valp = immt_out_0;
2549 return 0;
2550}
2551
2552static int
2553OperandSem_opnd_sem_immt_encode (uint32 *valp)
2554{
2555 unsigned immt_in_0;
2556 unsigned immt_out_0;
2557 immt_out_0 = *valp;
2558 immt_in_0 = immt_out_0 & 0xf;
2559 *valp = immt_in_0;
2560 return 0;
2561}
2562
2563static int
2564OperandSem_opnd_sem_tp7_decode (uint32 *valp)
2565{
2566 unsigned tp7_out_0;
2567 unsigned tp7_in_0;
2568 tp7_in_0 = *valp & 0xf;
2569 tp7_out_0 = tp7_in_0 + 0x7;
2570 *valp = tp7_out_0;
2571 return 0;
2572}
2573
2574static int
2575OperandSem_opnd_sem_tp7_encode (uint32 *valp)
2576{
2577 unsigned tp7_in_0;
2578 unsigned tp7_out_0;
2579 tp7_out_0 = *valp;
2580 tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
2581 *valp = tp7_in_0;
2582 return 0;
2583}
2584
2585static int
2586OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
2587{
2588 unsigned xt_wbr15_label_out_0;
2589 unsigned xt_wbr15_label_in_0;
2590 xt_wbr15_label_in_0 = *valp & 0x7fff;
2591 xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
2592 *valp = xt_wbr15_label_out_0;
2593 return 0;
2594}
2595
2596static int
2597OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
2598{
2599 unsigned xt_wbr15_label_in_0;
2600 unsigned xt_wbr15_label_out_0;
2601 xt_wbr15_label_out_0 = *valp;
2602 xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
2603 *valp = xt_wbr15_label_in_0;
2604 return 0;
2605}
2606
2607static int
2608OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp)
2609{
2610 unsigned xt_wbr18_label_out_0;
2611 unsigned xt_wbr18_label_in_0;
2612 xt_wbr18_label_in_0 = *valp & 0x3ffff;
2613 xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14);
2614 *valp = xt_wbr18_label_out_0;
2615 return 0;
2616}
2617
2618static int
2619OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp)
2620{
2621 unsigned xt_wbr18_label_in_0;
2622 unsigned xt_wbr18_label_out_0;
2623 xt_wbr18_label_out_0 = *valp;
2624 xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff;
2625 *valp = xt_wbr18_label_in_0;
2626 return 0;
2627}
2628
2629static int
2630OperandSem_opnd_sem_bitindex_decode (uint32 *valp)
2631{
2632 unsigned bitindex_out_0;
2633 unsigned bitindex_in_0;
2634 bitindex_in_0 = *valp & 0x1f;
2635 bitindex_out_0 = (0 << 5) | bitindex_in_0;
2636 *valp = bitindex_out_0;
2637 return 0;
2638}
2639
2640static int
2641OperandSem_opnd_sem_bitindex_encode (uint32 *valp)
2642{
2643 unsigned bitindex_in_0;
2644 unsigned bitindex_out_0;
2645 bitindex_out_0 = *valp;
2646 bitindex_in_0 = (bitindex_out_0 & 0x1f);
2647 *valp = bitindex_in_0;
2648 return 0;
2649}
2650
2651static int
2652Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
2653{
2654 *valp -= (pc & ~0x3);
2655 return 0;
2656}
2657
2658static int
2659Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
2660{
2661 *valp += (pc & ~0x3);
2662 return 0;
2663}
2664
2665static int
2666Operand_uimm6_ator (uint32 *valp, uint32 pc)
2667{
2668 *valp -= pc;
2669 return 0;
2670}
2671
2672static int
2673Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
2674{
2675 *valp += pc;
2676 return 0;
2677}
2678
2679static int
2680Operand_label8_ator (uint32 *valp, uint32 pc)
2681{
2682 *valp -= pc;
2683 return 0;
2684}
2685
2686static int
2687Operand_label8_rtoa (uint32 *valp, uint32 pc)
2688{
2689 *valp += pc;
2690 return 0;
2691}
2692
2693static int
2694Operand_ulabel8_ator (uint32 *valp, uint32 pc)
2695{
2696 *valp -= pc;
2697 return 0;
2698}
2699
2700static int
2701Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
2702{
2703 *valp += pc;
2704 return 0;
2705}
2706
2707static int
2708Operand_label12_ator (uint32 *valp, uint32 pc)
2709{
2710 *valp -= pc;
2711 return 0;
2712}
2713
2714static int
2715Operand_label12_rtoa (uint32 *valp, uint32 pc)
2716{
2717 *valp += pc;
2718 return 0;
2719}
2720
2721static int
2722Operand_soffset_ator (uint32 *valp, uint32 pc)
2723{
2724 *valp -= pc;
2725 return 0;
2726}
2727
2728static int
2729Operand_soffset_rtoa (uint32 *valp, uint32 pc)
2730{
2731 *valp += pc;
2732 return 0;
2733}
2734
2735static int
2736Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
2737{
2738 *valp -= ((pc + 3) & ~0x3);
2739 return 0;
2740}
2741
2742static int
2743Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
2744{
2745 *valp += ((pc + 3) & ~0x3);
2746 return 0;
2747}
2748
2749static int
2750Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
2751{
2752 *valp -= pc;
2753 return 0;
2754}
2755
2756static int
2757Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
2758{
2759 *valp += pc;
2760 return 0;
2761}
2762
2763static int
2764Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
2765{
2766 *valp -= pc;
2767 return 0;
2768}
2769
2770static int
2771Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
2772{
2773 *valp += pc;
2774 return 0;
2775}
2776
2777static xtensa_operand_internal operands[] = {
2778 { "soffsetx4", FIELD_offset, -1, 0,
2779 XTENSA_OPERAND_IS_PCRELATIVE,
2780 OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
2781 Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
2782 { "uimm12x8", FIELD_imm12, -1, 0,
2783 0,
2784 OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
2785 0, 0 },
2786 { "simm4", FIELD_mn, -1, 0,
2787 0,
2788 OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
2789 0, 0 },
2790 { "arr", FIELD_r, REGFILE_AR, 1,
2791 XTENSA_OPERAND_IS_REGISTER,
2792 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
2793 0, 0 },
2794 { "ars", FIELD_s, REGFILE_AR, 1,
2795 XTENSA_OPERAND_IS_REGISTER,
2796 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
2797 0, 0 },
2798 { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
2799 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2800 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
2801 0, 0 },
2802 { "art", FIELD_t, REGFILE_AR, 1,
2803 XTENSA_OPERAND_IS_REGISTER,
2804 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
2805 0, 0 },
2806 { "ar0", FIELD__ar0, REGFILE_AR, 1,
2807 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2808 OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
2809 0, 0 },
2810 { "ar4", FIELD__ar4, REGFILE_AR, 1,
2811 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2812 OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode,
2813 0, 0 },
2814 { "ar8", FIELD__ar8, REGFILE_AR, 1,
2815 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2816 OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode,
2817 0, 0 },
2818 { "ar12", FIELD__ar12, REGFILE_AR, 1,
2819 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2820 OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode,
2821 0, 0 },
2822 { "ars_entry", FIELD_s, REGFILE_AR, 1,
2823 XTENSA_OPERAND_IS_REGISTER,
2824 OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
2825 0, 0 },
2826 { "immrx4", FIELD_r, -1, 0,
2827 0,
2828 OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
2829 0, 0 },
2830 { "lsi4x4", FIELD_r, -1, 0,
2831 0,
2832 OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
2833 0, 0 },
2834 { "simm7", FIELD_imm7, -1, 0,
2835 0,
2836 OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
2837 0, 0 },
2838 { "uimm6", FIELD_imm6, -1, 0,
2839 XTENSA_OPERAND_IS_PCRELATIVE,
2840 OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
2841 Operand_uimm6_ator, Operand_uimm6_rtoa },
2842 { "ai4const", FIELD_t, -1, 0,
2843 0,
2844 OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
2845 0, 0 },
2846 { "b4const", FIELD_r, -1, 0,
2847 0,
2848 OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
2849 0, 0 },
2850 { "b4constu", FIELD_r, -1, 0,
2851 0,
2852 OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
2853 0, 0 },
2854 { "uimm8", FIELD_imm8, -1, 0,
2855 0,
2856 OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
2857 0, 0 },
2858 { "uimm8x2", FIELD_imm8, -1, 0,
2859 0,
2860 OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
2861 0, 0 },
2862 { "uimm8x4", FIELD_imm8, -1, 0,
2863 0,
2864 OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
2865 0, 0 },
2866 { "uimm4x16", FIELD_op2, -1, 0,
2867 0,
2868 OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
2869 0, 0 },
2870 { "uimmrx4", FIELD_r, -1, 0,
2871 0,
2872 OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode,
2873 0, 0 },
2874 { "simm8", FIELD_imm8, -1, 0,
2875 0,
2876 OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
2877 0, 0 },
2878 { "simm8x256", FIELD_imm8, -1, 0,
2879 0,
2880 OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
2881 0, 0 },
2882 { "simm12b", FIELD_imm12b, -1, 0,
2883 0,
2884 OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
2885 0, 0 },
2886 { "msalp32", FIELD_sal, -1, 0,
2887 0,
2888 OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
2889 0, 0 },
2890 { "op2p1", FIELD_op2, -1, 0,
2891 0,
2892 OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
2893 0, 0 },
2894 { "label8", FIELD_imm8, -1, 0,
2895 XTENSA_OPERAND_IS_PCRELATIVE,
2896 OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
2897 Operand_label8_ator, Operand_label8_rtoa },
2898 { "ulabel8", FIELD_imm8, -1, 0,
2899 XTENSA_OPERAND_IS_PCRELATIVE,
2900 OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode,
2901 Operand_ulabel8_ator, Operand_ulabel8_rtoa },
2902 { "label12", FIELD_imm12, -1, 0,
2903 XTENSA_OPERAND_IS_PCRELATIVE,
2904 OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
2905 Operand_label12_ator, Operand_label12_rtoa },
2906 { "soffset", FIELD_offset, -1, 0,
2907 XTENSA_OPERAND_IS_PCRELATIVE,
2908 OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
2909 Operand_soffset_ator, Operand_soffset_rtoa },
2910 { "uimm16x4", FIELD_imm16, -1, 0,
2911 XTENSA_OPERAND_IS_PCRELATIVE,
2912 OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
2913 Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
2914 { "bbi", FIELD_bbi, -1, 0,
2915 0,
2916 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
2917 0, 0 },
2918 { "sae", FIELD_sae, -1, 0,
2919 0,
2920 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
2921 0, 0 },
2922 { "sas", FIELD_sas, -1, 0,
2923 0,
2924 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
2925 0, 0 },
2926 { "sargt", FIELD_sargt, -1, 0,
2927 0,
2928 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
2929 0, 0 },
2930 { "s", FIELD_s, -1, 0,
2931 0,
2932 OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
2933 0, 0 },
2934 { "mx", FIELD_x, REGFILE_MR, 1,
2935 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
2936 OperandSem_opnd_sem_MR_encode, OperandSem_opnd_sem_MR_decode,
2937 0, 0 },
2938 { "my", FIELD_y, REGFILE_MR, 1,
2939 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
2940 OperandSem_opnd_sem_MR_0_encode, OperandSem_opnd_sem_MR_0_decode,
2941 0, 0 },
2942 { "mw", FIELD_w, REGFILE_MR, 1,
2943 XTENSA_OPERAND_IS_REGISTER,
2944 OperandSem_opnd_sem_MR_1_encode, OperandSem_opnd_sem_MR_1_decode,
2945 0, 0 },
2946 { "mr0", FIELD__mr0, REGFILE_MR, 1,
2947 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2948 OperandSem_opnd_sem_MR_2_encode, OperandSem_opnd_sem_MR_2_decode,
2949 0, 0 },
2950 { "mr1", FIELD__mr1, REGFILE_MR, 1,
2951 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2952 OperandSem_opnd_sem_MR_3_encode, OperandSem_opnd_sem_MR_3_decode,
2953 0, 0 },
2954 { "mr2", FIELD__mr2, REGFILE_MR, 1,
2955 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2956 OperandSem_opnd_sem_MR_4_encode, OperandSem_opnd_sem_MR_4_decode,
2957 0, 0 },
2958 { "mr3", FIELD__mr3, REGFILE_MR, 1,
2959 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2960 OperandSem_opnd_sem_MR_5_encode, OperandSem_opnd_sem_MR_5_decode,
2961 0, 0 },
2962 { "immt", FIELD_t, -1, 0,
2963 0,
2964 OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
2965 0, 0 },
2966 { "imms", FIELD_s, -1, 0,
2967 0,
2968 OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
2969 0, 0 },
2970 { "tp7", FIELD_t, -1, 0,
2971 0,
2972 OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
2973 0, 0 },
2974 { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
2975 XTENSA_OPERAND_IS_PCRELATIVE,
2976 OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
2977 Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
2978 { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
2979 XTENSA_OPERAND_IS_PCRELATIVE,
2980 OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode,
2981 Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
2982 { "bitindex", FIELD_bitindex, -1, 0,
2983 0,
2984 OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode,
2985 0, 0 },
2986 { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
2987 { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
2988 { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
2989 { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
2990 { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
2991 { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
2992 { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
2993 { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
2994 { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
2995 { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
2996 { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
2997 { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
2998 { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
2999 { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
3000 { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
3001 { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
3002 { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
3003 { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
3004 { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
3005 { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
3006 { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
3007 { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
3008 { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
3009 { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
3010 { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
3011 { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
3012 { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
3013 { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
3014 { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
3015 { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
3016 { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 },
3017 { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 },
3018 { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 },
3019 { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 },
3020 { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 },
3021 { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 },
3022 { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 },
3023 { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 },
3024 { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 },
3025 { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
3026 { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
3027 { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
3028};
3029
3030enum xtensa_operand_id {
3031 OPERAND_soffsetx4,
3032 OPERAND_uimm12x8,
3033 OPERAND_simm4,
3034 OPERAND_arr,
3035 OPERAND_ars,
3036 OPERAND__ars_invisible,
3037 OPERAND_art,
3038 OPERAND_ar0,
3039 OPERAND_ar4,
3040 OPERAND_ar8,
3041 OPERAND_ar12,
3042 OPERAND_ars_entry,
3043 OPERAND_immrx4,
3044 OPERAND_lsi4x4,
3045 OPERAND_simm7,
3046 OPERAND_uimm6,
3047 OPERAND_ai4const,
3048 OPERAND_b4const,
3049 OPERAND_b4constu,
3050 OPERAND_uimm8,
3051 OPERAND_uimm8x2,
3052 OPERAND_uimm8x4,
3053 OPERAND_uimm4x16,
3054 OPERAND_uimmrx4,
3055 OPERAND_simm8,
3056 OPERAND_simm8x256,
3057 OPERAND_simm12b,
3058 OPERAND_msalp32,
3059 OPERAND_op2p1,
3060 OPERAND_label8,
3061 OPERAND_ulabel8,
3062 OPERAND_label12,
3063 OPERAND_soffset,
3064 OPERAND_uimm16x4,
3065 OPERAND_bbi,
3066 OPERAND_sae,
3067 OPERAND_sas,
3068 OPERAND_sargt,
3069 OPERAND_s,
3070 OPERAND_mx,
3071 OPERAND_my,
3072 OPERAND_mw,
3073 OPERAND_mr0,
3074 OPERAND_mr1,
3075 OPERAND_mr2,
3076 OPERAND_mr3,
3077 OPERAND_immt,
3078 OPERAND_imms,
3079 OPERAND_tp7,
3080 OPERAND_xt_wbr15_label,
3081 OPERAND_xt_wbr18_label,
3082 OPERAND_bitindex,
3083 OPERAND_t,
3084 OPERAND_bbi4,
3085 OPERAND_imm12,
3086 OPERAND_imm8,
3087 OPERAND_imm12b,
3088 OPERAND_imm16,
3089 OPERAND_m,
3090 OPERAND_n,
3091 OPERAND_offset,
3092 OPERAND_op0,
3093 OPERAND_op1,
3094 OPERAND_op2,
3095 OPERAND_r,
3096 OPERAND_sa4,
3097 OPERAND_sae4,
3098 OPERAND_sal,
3099 OPERAND_sas4,
3100 OPERAND_sr,
3101 OPERAND_st,
3102 OPERAND_thi3,
3103 OPERAND_imm4,
3104 OPERAND_mn,
3105 OPERAND_i,
3106 OPERAND_imm6lo,
3107 OPERAND_imm6hi,
3108 OPERAND_imm7lo,
3109 OPERAND_imm7hi,
3110 OPERAND_z,
3111 OPERAND_imm6,
3112 OPERAND_imm7,
3113 OPERAND_r3,
3114 OPERAND_rbit2,
3115 OPERAND_rhi,
3116 OPERAND_t3,
3117 OPERAND_tbit2,
3118 OPERAND_tlo,
3119 OPERAND_w,
3120 OPERAND_y,
3121 OPERAND_x,
3122 OPERAND_xt_wbr15_imm,
3123 OPERAND_xt_wbr18_imm,
3124 OPERAND_s3to1
3125};
3126
3127\f
3128/* Iclass table. */
3129
3130static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
3131 { { STATE_PSEXCM }, 'o' },
3132 { { STATE_EPC1 }, 'i' }
3133};
3134
3135static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
3136 { { STATE_DEPC }, 'i' }
3137};
3138
3139static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
3140 { { OPERAND_soffsetx4 }, 'i' },
3141 { { OPERAND_ar12 }, 'o' }
3142};
3143
3144static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
3145 { { STATE_PSCALLINC }, 'o' }
3146};
3147
3148static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
3149 { { OPERAND_soffsetx4 }, 'i' },
3150 { { OPERAND_ar8 }, 'o' }
3151};
3152
3153static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
3154 { { STATE_PSCALLINC }, 'o' }
3155};
3156
3157static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
3158 { { OPERAND_soffsetx4 }, 'i' },
3159 { { OPERAND_ar4 }, 'o' }
3160};
3161
3162static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
3163 { { STATE_PSCALLINC }, 'o' }
3164};
3165
3166static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
3167 { { OPERAND_ars }, 'i' },
3168 { { OPERAND_ar12 }, 'o' }
3169};
3170
3171static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
3172 { { STATE_PSCALLINC }, 'o' }
3173};
3174
3175static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
3176 { { OPERAND_ars }, 'i' },
3177 { { OPERAND_ar8 }, 'o' }
3178};
3179
3180static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
3181 { { STATE_PSCALLINC }, 'o' }
3182};
3183
3184static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
3185 { { OPERAND_ars }, 'i' },
3186 { { OPERAND_ar4 }, 'o' }
3187};
3188
3189static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
3190 { { STATE_PSCALLINC }, 'o' }
3191};
3192
3193static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
3194 { { OPERAND_ars_entry }, 's' },
3195 { { OPERAND_ars }, 'i' },
3196 { { OPERAND_uimm12x8 }, 'i' }
3197};
3198
3199static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
3200 { { STATE_PSCALLINC }, 'i' },
3201 { { STATE_PSEXCM }, 'i' },
3202 { { STATE_PSWOE }, 'i' },
3203 { { STATE_WindowBase }, 'm' },
3204 { { STATE_WindowStart }, 'm' }
3205};
3206
3207static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
3208 { { OPERAND_art }, 'o' },
3209 { { OPERAND_ars }, 'i' }
3210};
3211
3212static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
3213 { { STATE_WindowBase }, 'i' },
3214 { { STATE_WindowStart }, 'i' }
3215};
3216
3217static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
3218 { { OPERAND_simm4 }, 'i' }
3219};
3220
3221static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
3222 { { STATE_WindowBase }, 'm' }
3223};
3224
3225static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
3226 { { OPERAND__ars_invisible }, 'i' }
3227};
3228
3229static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
3230 { { STATE_WindowBase }, 'm' },
3231 { { STATE_WindowStart }, 'm' },
3232 { { STATE_PSCALLINC }, 'o' },
3233 { { STATE_PSEXCM }, 'i' },
3234 { { STATE_PSWOE }, 'i' }
3235};
3236
3237static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
3238 { { STATE_EPC1 }, 'i' },
3239 { { STATE_PSEXCM }, 'o' },
3240 { { STATE_WindowBase }, 'm' },
3241 { { STATE_WindowStart }, 'm' },
3242 { { STATE_PSOWB }, 'i' }
3243};
3244
3245static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
3246 { { OPERAND_art }, 'o' },
3247 { { OPERAND_ars }, 'i' },
3248 { { OPERAND_immrx4 }, 'i' }
3249};
3250
3251static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
3252 { { OPERAND_art }, 'i' },
3253 { { OPERAND_ars }, 'i' },
3254 { { OPERAND_immrx4 }, 'i' }
3255};
3256
3257static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
3258 { { OPERAND_art }, 'o' }
3259};
3260
3261static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
3262 { { STATE_WindowBase }, 'i' }
3263};
3264
3265static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
3266 { { OPERAND_art }, 'i' }
3267};
3268
3269static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
3270 { { STATE_WindowBase }, 'o' }
3271};
3272
3273static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
3274 { { OPERAND_art }, 'm' }
3275};
3276
3277static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
3278 { { STATE_WindowBase }, 'm' }
3279};
3280
3281static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
3282 { { OPERAND_art }, 'o' }
3283};
3284
3285static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
3286 { { STATE_WindowStart }, 'i' }
3287};
3288
3289static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
3290 { { OPERAND_art }, 'i' }
3291};
3292
3293static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
3294 { { STATE_WindowStart }, 'o' }
3295};
3296
3297static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
3298 { { OPERAND_art }, 'm' }
3299};
3300
3301static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
3302 { { STATE_WindowStart }, 'm' }
3303};
3304
3305static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
3306 { { OPERAND_arr }, 'o' },
3307 { { OPERAND_ars }, 'i' },
3308 { { OPERAND_art }, 'i' }
3309};
3310
3311static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
3312 { { OPERAND_arr }, 'o' },
3313 { { OPERAND_ars }, 'i' },
3314 { { OPERAND_ai4const }, 'i' }
3315};
3316
3317static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
3318 { { OPERAND_ars }, 'i' },
3319 { { OPERAND_uimm6 }, 'i' }
3320};
3321
3322static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
3323 { { OPERAND_art }, 'o' },
3324 { { OPERAND_ars }, 'i' },
3325 { { OPERAND_lsi4x4 }, 'i' }
3326};
3327
3328static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
3329 { { OPERAND_art }, 'o' },
3330 { { OPERAND_ars }, 'i' }
3331};
3332
3333static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
3334 { { OPERAND_ars }, 'o' },
3335 { { OPERAND_simm7 }, 'i' }
3336};
3337
3338static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
3339 { { OPERAND__ars_invisible }, 'i' }
3340};
3341
3342static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
3343 { { OPERAND_art }, 'i' },
3344 { { OPERAND_ars }, 'i' },
3345 { { OPERAND_lsi4x4 }, 'i' }
3346};
3347
3348static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
3349 { { OPERAND_art }, 'o' },
3350 { { OPERAND_ars }, 'i' },
3351 { { OPERAND_simm8 }, 'i' }
3352};
3353
3354static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
3355 { { OPERAND_art }, 'o' },
3356 { { OPERAND_ars }, 'i' },
3357 { { OPERAND_simm8x256 }, 'i' }
3358};
3359
3360static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
3361 { { OPERAND_arr }, 'o' },
3362 { { OPERAND_ars }, 'i' },
3363 { { OPERAND_art }, 'i' }
3364};
3365
3366static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
3367 { { OPERAND_arr }, 'o' },
3368 { { OPERAND_ars }, 'i' },
3369 { { OPERAND_art }, 'i' }
3370};
3371
3372static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
3373 { { OPERAND_ars }, 'i' },
3374 { { OPERAND_b4const }, 'i' },
3375 { { OPERAND_label8 }, 'i' }
3376};
3377
3378static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
3379 { { OPERAND_ars }, 'i' },
3380 { { OPERAND_bbi }, 'i' },
3381 { { OPERAND_label8 }, 'i' }
3382};
3383
3384static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
3385 { { OPERAND_ars }, 'i' },
3386 { { OPERAND_b4constu }, 'i' },
3387 { { OPERAND_label8 }, 'i' }
3388};
3389
3390static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
3391 { { OPERAND_ars }, 'i' },
3392 { { OPERAND_art }, 'i' },
3393 { { OPERAND_label8 }, 'i' }
3394};
3395
3396static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
3397 { { OPERAND_ars }, 'i' },
3398 { { OPERAND_label12 }, 'i' }
3399};
3400
3401static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
3402 { { OPERAND_soffsetx4 }, 'i' },
3403 { { OPERAND_ar0 }, 'o' }
3404};
3405
3406static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
3407 { { OPERAND_ars }, 'i' },
3408 { { OPERAND_ar0 }, 'o' }
3409};
3410
3411static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
3412 { { OPERAND_arr }, 'o' },
3413 { { OPERAND_art }, 'i' },
3414 { { OPERAND_sae }, 'i' },
3415 { { OPERAND_op2p1 }, 'i' }
3416};
3417
3418static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
3419 { { OPERAND_soffset }, 'i' }
3420};
3421
3422static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
3423 { { OPERAND_ars }, 'i' }
3424};
3425
3426static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
3427 { { OPERAND_art }, 'o' },
3428 { { OPERAND_ars }, 'i' },
3429 { { OPERAND_uimm8x2 }, 'i' }
3430};
3431
3432static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
3433 { { OPERAND_art }, 'o' },
3434 { { OPERAND_ars }, 'i' },
3435 { { OPERAND_uimm8x2 }, 'i' }
3436};
3437
3438static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
3439 { { OPERAND_art }, 'o' },
3440 { { OPERAND_ars }, 'i' },
3441 { { OPERAND_uimm8x4 }, 'i' }
3442};
3443
3444static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
3445 { { OPERAND_art }, 'o' },
3446 { { OPERAND_uimm16x4 }, 'i' }
3447};
3448
3449static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
3450 { { OPERAND_art }, 'o' },
3451 { { OPERAND_ars }, 'i' },
3452 { { OPERAND_uimm8 }, 'i' }
3453};
3454
3455static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
3456 { { OPERAND_ars }, 'i' },
3457 { { OPERAND_ulabel8 }, 'i' }
3458};
3459
3460static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
3461 { { STATE_LBEG }, 'o' },
3462 { { STATE_LEND }, 'o' },
3463 { { STATE_LCOUNT }, 'o' }
3464};
3465
3466static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
3467 { { OPERAND_ars }, 'i' },
3468 { { OPERAND_ulabel8 }, 'i' }
3469};
3470
3471static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
3472 { { STATE_LBEG }, 'o' },
3473 { { STATE_LEND }, 'o' },
3474 { { STATE_LCOUNT }, 'o' }
3475};
3476
3477static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
3478 { { OPERAND_art }, 'o' },
3479 { { OPERAND_simm12b }, 'i' }
3480};
3481
3482static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
3483 { { OPERAND_arr }, 'm' },
3484 { { OPERAND_ars }, 'i' },
3485 { { OPERAND_art }, 'i' }
3486};
3487
3488static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
3489 { { OPERAND_arr }, 'o' },
3490 { { OPERAND_art }, 'i' }
3491};
3492
3493static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
3494 { { OPERAND__ars_invisible }, 'i' }
3495};
3496
3497static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
3498 { { OPERAND_art }, 'i' },
3499 { { OPERAND_ars }, 'i' },
3500 { { OPERAND_uimm8x2 }, 'i' }
3501};
3502
3503static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
3504 { { OPERAND_art }, 'i' },
3505 { { OPERAND_ars }, 'i' },
3506 { { OPERAND_uimm8x4 }, 'i' }
3507};
3508
3509static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = {
3510 { { OPERAND_art }, 'i' },
3511 { { OPERAND_ars }, 'i' },
3512 { { OPERAND_uimmrx4 }, 'i' }
3513};
3514
3515static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
3516 { { OPERAND_art }, 'i' },
3517 { { OPERAND_ars }, 'i' },
3518 { { OPERAND_uimm8 }, 'i' }
3519};
3520
3521static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
3522 { { OPERAND_ars }, 'i' }
3523};
3524
3525static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
3526 { { STATE_SAR }, 'o' }
3527};
3528
3529static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
3530 { { OPERAND_sas }, 'i' }
3531};
3532
3533static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
3534 { { STATE_SAR }, 'o' }
3535};
3536
3537static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
3538 { { OPERAND_arr }, 'o' },
3539 { { OPERAND_ars }, 'i' }
3540};
3541
3542static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
3543 { { STATE_SAR }, 'i' }
3544};
3545
3546static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
3547 { { OPERAND_arr }, 'o' },
3548 { { OPERAND_ars }, 'i' },
3549 { { OPERAND_art }, 'i' }
3550};
3551
3552static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
3553 { { STATE_SAR }, 'i' }
3554};
3555
3556static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
3557 { { OPERAND_arr }, 'o' },
3558 { { OPERAND_art }, 'i' }
3559};
3560
3561static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
3562 { { STATE_SAR }, 'i' }
3563};
3564
3565static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
3566 { { OPERAND_arr }, 'o' },
3567 { { OPERAND_ars }, 'i' },
3568 { { OPERAND_msalp32 }, 'i' }
3569};
3570
3571static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
3572 { { OPERAND_arr }, 'o' },
3573 { { OPERAND_art }, 'i' },
3574 { { OPERAND_sargt }, 'i' }
3575};
3576
3577static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
3578 { { OPERAND_arr }, 'o' },
3579 { { OPERAND_art }, 'i' },
3580 { { OPERAND_s }, 'i' }
3581};
3582
3583static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
3584 { { STATE_XTSYNC }, 'i' }
3585};
3586
3587static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
3588 { { OPERAND_art }, 'o' },
3589 { { OPERAND_s }, 'i' }
3590};
3591
3592static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
3593 { { STATE_PSWOE }, 'i' },
3594 { { STATE_PSCALLINC }, 'i' },
3595 { { STATE_PSOWB }, 'i' },
3596 { { STATE_PSUM }, 'i' },
3597 { { STATE_PSEXCM }, 'i' },
3598 { { STATE_PSINTLEVEL }, 'm' }
3599};
3600
3601static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
3602 { { OPERAND_art }, 'o' }
3603};
3604
3605static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
3606 { { STATE_LEND }, 'i' }
3607};
3608
3609static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
3610 { { OPERAND_art }, 'i' }
3611};
3612
3613static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
3614 { { STATE_LEND }, 'o' }
3615};
3616
3617static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
3618 { { OPERAND_art }, 'm' }
3619};
3620
3621static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
3622 { { STATE_LEND }, 'm' }
3623};
3624
3625static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
3626 { { OPERAND_art }, 'o' }
3627};
3628
3629static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
3630 { { STATE_LCOUNT }, 'i' }
3631};
3632
3633static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
3634 { { OPERAND_art }, 'i' }
3635};
3636
3637static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
3638 { { STATE_XTSYNC }, 'o' },
3639 { { STATE_LCOUNT }, 'o' }
3640};
3641
3642static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
3643 { { OPERAND_art }, 'm' }
3644};
3645
3646static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
3647 { { STATE_XTSYNC }, 'o' },
3648 { { STATE_LCOUNT }, 'm' }
3649};
3650
3651static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
3652 { { OPERAND_art }, 'o' }
3653};
3654
3655static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
3656 { { STATE_LBEG }, 'i' }
3657};
3658
3659static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
3660 { { OPERAND_art }, 'i' }
3661};
3662
3663static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
3664 { { STATE_LBEG }, 'o' }
3665};
3666
3667static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
3668 { { OPERAND_art }, 'm' }
3669};
3670
3671static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
3672 { { STATE_LBEG }, 'm' }
3673};
3674
3675static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
3676 { { OPERAND_art }, 'o' }
3677};
3678
3679static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
3680 { { STATE_SAR }, 'i' }
3681};
3682
3683static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
3684 { { OPERAND_art }, 'i' }
3685};
3686
3687static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
3688 { { STATE_SAR }, 'o' },
3689 { { STATE_XTSYNC }, 'o' }
3690};
3691
3692static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
3693 { { OPERAND_art }, 'm' }
3694};
3695
3696static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
3697 { { STATE_SAR }, 'm' }
3698};
3699
3700static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = {
3701 { { OPERAND_art }, 'o' }
3702};
3703
3704static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = {
3705 { { OPERAND_art }, 'i' }
3706};
3707
3708static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = {
3709 { { OPERAND_art }, 'm' }
3710};
3711
3712static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
3713 { { OPERAND_art }, 'o' }
3714};
3715
3716static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
3717 { { OPERAND_art }, 'i' }
3718};
3719
3720static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
3721 { { OPERAND_art }, 'm' }
3722};
3723
3724static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
3725 { { OPERAND_art }, 'o' }
3726};
3727
3728static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
3729 { { OPERAND_art }, 'i' }
3730};
3731
3732static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
3733 { { OPERAND_art }, 'o' }
3734};
3735
3736static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
3737 { { OPERAND_art }, 'o' }
3738};
3739
3740static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
3741 { { STATE_PSWOE }, 'i' },
3742 { { STATE_PSCALLINC }, 'i' },
3743 { { STATE_PSOWB }, 'i' },
3744 { { STATE_PSUM }, 'i' },
3745 { { STATE_PSEXCM }, 'i' },
3746 { { STATE_PSINTLEVEL }, 'i' }
3747};
3748
3749static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
3750 { { OPERAND_art }, 'i' }
3751};
3752
3753static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
3754 { { STATE_PSWOE }, 'o' },
3755 { { STATE_PSCALLINC }, 'o' },
3756 { { STATE_PSOWB }, 'o' },
3757 { { STATE_PSUM }, 'o' },
3758 { { STATE_PSEXCM }, 'o' },
3759 { { STATE_PSINTLEVEL }, 'o' }
3760};
3761
3762static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
3763 { { OPERAND_art }, 'm' }
3764};
3765
3766static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
3767 { { STATE_PSWOE }, 'm' },
3768 { { STATE_PSCALLINC }, 'm' },
3769 { { STATE_PSOWB }, 'm' },
3770 { { STATE_PSUM }, 'm' },
3771 { { STATE_PSEXCM }, 'm' },
3772 { { STATE_PSINTLEVEL }, 'm' }
3773};
3774
3775static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
3776 { { OPERAND_art }, 'o' }
3777};
3778
3779static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
3780 { { STATE_EPC1 }, 'i' }
3781};
3782
3783static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
3784 { { OPERAND_art }, 'i' }
3785};
3786
3787static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
3788 { { STATE_EPC1 }, 'o' }
3789};
3790
3791static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
3792 { { OPERAND_art }, 'm' }
3793};
3794
3795static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
3796 { { STATE_EPC1 }, 'm' }
3797};
3798
3799static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
3800 { { OPERAND_art }, 'o' }
3801};
3802
3803static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
3804 { { STATE_EXCSAVE1 }, 'i' }
3805};
3806
3807static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
3808 { { OPERAND_art }, 'i' }
3809};
3810
3811static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
3812 { { STATE_EXCSAVE1 }, 'o' }
3813};
3814
3815static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
3816 { { OPERAND_art }, 'm' }
3817};
3818
3819static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
3820 { { STATE_EXCSAVE1 }, 'm' }
3821};
3822
3823static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
3824 { { OPERAND_art }, 'o' }
3825};
3826
3827static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
3828 { { STATE_EPC2 }, 'i' }
3829};
3830
3831static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
3832 { { OPERAND_art }, 'i' }
3833};
3834
3835static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
3836 { { STATE_EPC2 }, 'o' }
3837};
3838
3839static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
3840 { { OPERAND_art }, 'm' }
3841};
3842
3843static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
3844 { { STATE_EPC2 }, 'm' }
3845};
3846
3847static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
3848 { { OPERAND_art }, 'o' }
3849};
3850
3851static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
3852 { { STATE_EXCSAVE2 }, 'i' }
3853};
3854
3855static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
3856 { { OPERAND_art }, 'i' }
3857};
3858
3859static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
3860 { { STATE_EXCSAVE2 }, 'o' }
3861};
3862
3863static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
3864 { { OPERAND_art }, 'm' }
3865};
3866
3867static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
3868 { { STATE_EXCSAVE2 }, 'm' }
3869};
3870
3871static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
3872 { { OPERAND_art }, 'o' }
3873};
3874
3875static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
3876 { { STATE_EPC3 }, 'i' }
3877};
3878
3879static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
3880 { { OPERAND_art }, 'i' }
3881};
3882
3883static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
3884 { { STATE_EPC3 }, 'o' }
3885};
3886
3887static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
3888 { { OPERAND_art }, 'm' }
3889};
3890
3891static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
3892 { { STATE_EPC3 }, 'm' }
3893};
3894
3895static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
3896 { { OPERAND_art }, 'o' }
3897};
3898
3899static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
3900 { { STATE_EXCSAVE3 }, 'i' }
3901};
3902
3903static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
3904 { { OPERAND_art }, 'i' }
3905};
3906
3907static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
3908 { { STATE_EXCSAVE3 }, 'o' }
3909};
3910
3911static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
3912 { { OPERAND_art }, 'm' }
3913};
3914
3915static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
3916 { { STATE_EXCSAVE3 }, 'm' }
3917};
3918
3919static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
3920 { { OPERAND_art }, 'o' }
3921};
3922
3923static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
3924 { { STATE_EPC4 }, 'i' }
3925};
3926
3927static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
3928 { { OPERAND_art }, 'i' }
3929};
3930
3931static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
3932 { { STATE_EPC4 }, 'o' }
3933};
3934
3935static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
3936 { { OPERAND_art }, 'm' }
3937};
3938
3939static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
3940 { { STATE_EPC4 }, 'm' }
3941};
3942
3943static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
3944 { { OPERAND_art }, 'o' }
3945};
3946
3947static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
3948 { { STATE_EXCSAVE4 }, 'i' }
3949};
3950
3951static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
3952 { { OPERAND_art }, 'i' }
3953};
3954
3955static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
3956 { { STATE_EXCSAVE4 }, 'o' }
3957};
3958
3959static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
3960 { { OPERAND_art }, 'm' }
3961};
3962
3963static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
3964 { { STATE_EXCSAVE4 }, 'm' }
3965};
3966
3967static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
3968 { { OPERAND_art }, 'o' }
3969};
3970
3971static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
3972 { { STATE_EPC5 }, 'i' }
3973};
3974
3975static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
3976 { { OPERAND_art }, 'i' }
3977};
3978
3979static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
3980 { { STATE_EPC5 }, 'o' }
3981};
3982
3983static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
3984 { { OPERAND_art }, 'm' }
3985};
3986
3987static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
3988 { { STATE_EPC5 }, 'm' }
3989};
3990
3991static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
3992 { { OPERAND_art }, 'o' }
3993};
3994
3995static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
3996 { { STATE_EXCSAVE5 }, 'i' }
3997};
3998
3999static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
4000 { { OPERAND_art }, 'i' }
4001};
4002
4003static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
4004 { { STATE_EXCSAVE5 }, 'o' }
4005};
4006
4007static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
4008 { { OPERAND_art }, 'm' }
4009};
4010
4011static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
4012 { { STATE_EXCSAVE5 }, 'm' }
4013};
4014
4015static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
4016 { { OPERAND_art }, 'o' }
4017};
4018
4019static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
4020 { { STATE_EPC6 }, 'i' }
4021};
4022
4023static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
4024 { { OPERAND_art }, 'i' }
4025};
4026
4027static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
4028 { { STATE_EPC6 }, 'o' }
4029};
4030
4031static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
4032 { { OPERAND_art }, 'm' }
4033};
4034
4035static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
4036 { { STATE_EPC6 }, 'm' }
4037};
4038
4039static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
4040 { { OPERAND_art }, 'o' }
4041};
4042
4043static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
4044 { { STATE_EXCSAVE6 }, 'i' }
4045};
4046
4047static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
4048 { { OPERAND_art }, 'i' }
4049};
4050
4051static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
4052 { { STATE_EXCSAVE6 }, 'o' }
4053};
4054
4055static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
4056 { { OPERAND_art }, 'm' }
4057};
4058
4059static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
4060 { { STATE_EXCSAVE6 }, 'm' }
4061};
4062
4063static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
4064 { { OPERAND_art }, 'o' }
4065};
4066
4067static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
4068 { { STATE_EPC7 }, 'i' }
4069};
4070
4071static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
4072 { { OPERAND_art }, 'i' }
4073};
4074
4075static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
4076 { { STATE_EPC7 }, 'o' }
4077};
4078
4079static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
4080 { { OPERAND_art }, 'm' }
4081};
4082
4083static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
4084 { { STATE_EPC7 }, 'm' }
4085};
4086
4087static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
4088 { { OPERAND_art }, 'o' }
4089};
4090
4091static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
4092 { { STATE_EXCSAVE7 }, 'i' }
4093};
4094
4095static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
4096 { { OPERAND_art }, 'i' }
4097};
4098
4099static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
4100 { { STATE_EXCSAVE7 }, 'o' }
4101};
4102
4103static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
4104 { { OPERAND_art }, 'm' }
4105};
4106
4107static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
4108 { { STATE_EXCSAVE7 }, 'm' }
4109};
4110
4111static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
4112 { { OPERAND_art }, 'o' }
4113};
4114
4115static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
4116 { { STATE_EPS2 }, 'i' }
4117};
4118
4119static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
4120 { { OPERAND_art }, 'i' }
4121};
4122
4123static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
4124 { { STATE_EPS2 }, 'o' }
4125};
4126
4127static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
4128 { { OPERAND_art }, 'm' }
4129};
4130
4131static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
4132 { { STATE_EPS2 }, 'm' }
4133};
4134
4135static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
4136 { { OPERAND_art }, 'o' }
4137};
4138
4139static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
4140 { { STATE_EPS3 }, 'i' }
4141};
4142
4143static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
4144 { { OPERAND_art }, 'i' }
4145};
4146
4147static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
4148 { { STATE_EPS3 }, 'o' }
4149};
4150
4151static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
4152 { { OPERAND_art }, 'm' }
4153};
4154
4155static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
4156 { { STATE_EPS3 }, 'm' }
4157};
4158
4159static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
4160 { { OPERAND_art }, 'o' }
4161};
4162
4163static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
4164 { { STATE_EPS4 }, 'i' }
4165};
4166
4167static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
4168 { { OPERAND_art }, 'i' }
4169};
4170
4171static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
4172 { { STATE_EPS4 }, 'o' }
4173};
4174
4175static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
4176 { { OPERAND_art }, 'm' }
4177};
4178
4179static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
4180 { { STATE_EPS4 }, 'm' }
4181};
4182
4183static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
4184 { { OPERAND_art }, 'o' }
4185};
4186
4187static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
4188 { { STATE_EPS5 }, 'i' }
4189};
4190
4191static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
4192 { { OPERAND_art }, 'i' }
4193};
4194
4195static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
4196 { { STATE_EPS5 }, 'o' }
4197};
4198
4199static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
4200 { { OPERAND_art }, 'm' }
4201};
4202
4203static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
4204 { { STATE_EPS5 }, 'm' }
4205};
4206
4207static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
4208 { { OPERAND_art }, 'o' }
4209};
4210
4211static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
4212 { { STATE_EPS6 }, 'i' }
4213};
4214
4215static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
4216 { { OPERAND_art }, 'i' }
4217};
4218
4219static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
4220 { { STATE_EPS6 }, 'o' }
4221};
4222
4223static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
4224 { { OPERAND_art }, 'm' }
4225};
4226
4227static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
4228 { { STATE_EPS6 }, 'm' }
4229};
4230
4231static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
4232 { { OPERAND_art }, 'o' }
4233};
4234
4235static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
4236 { { STATE_EPS7 }, 'i' }
4237};
4238
4239static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
4240 { { OPERAND_art }, 'i' }
4241};
4242
4243static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
4244 { { STATE_EPS7 }, 'o' }
4245};
4246
4247static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
4248 { { OPERAND_art }, 'm' }
4249};
4250
4251static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
4252 { { STATE_EPS7 }, 'm' }
4253};
4254
4255static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
4256 { { OPERAND_art }, 'o' }
4257};
4258
4259static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
4260 { { STATE_EXCVADDR }, 'i' }
4261};
4262
4263static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
4264 { { OPERAND_art }, 'i' }
4265};
4266
4267static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
4268 { { STATE_EXCVADDR }, 'o' }
4269};
4270
4271static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
4272 { { OPERAND_art }, 'm' }
4273};
4274
4275static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
4276 { { STATE_EXCVADDR }, 'm' }
4277};
4278
4279static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
4280 { { OPERAND_art }, 'o' }
4281};
4282
4283static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
4284 { { STATE_DEPC }, 'i' }
4285};
4286
4287static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
4288 { { OPERAND_art }, 'i' }
4289};
4290
4291static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
4292 { { STATE_DEPC }, 'o' }
4293};
4294
4295static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
4296 { { OPERAND_art }, 'm' }
4297};
4298
4299static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
4300 { { STATE_DEPC }, 'm' }
4301};
4302
4303static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
4304 { { OPERAND_art }, 'o' }
4305};
4306
4307static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
4308 { { STATE_EXCCAUSE }, 'i' },
4309 { { STATE_XTSYNC }, 'i' }
4310};
4311
4312static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
4313 { { OPERAND_art }, 'i' }
4314};
4315
4316static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
4317 { { STATE_EXCCAUSE }, 'o' }
4318};
4319
4320static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
4321 { { OPERAND_art }, 'm' }
4322};
4323
4324static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
4325 { { STATE_EXCCAUSE }, 'm' }
4326};
4327
4328static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
4329 { { OPERAND_art }, 'o' }
4330};
4331
4332static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
4333 { { STATE_MISC0 }, 'i' }
4334};
4335
4336static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
4337 { { OPERAND_art }, 'i' }
4338};
4339
4340static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
4341 { { STATE_MISC0 }, 'o' }
4342};
4343
4344static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
4345 { { OPERAND_art }, 'm' }
4346};
4347
4348static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
4349 { { STATE_MISC0 }, 'm' }
4350};
4351
4352static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
4353 { { OPERAND_art }, 'o' }
4354};
4355
4356static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
4357 { { STATE_MISC1 }, 'i' }
4358};
4359
4360static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
4361 { { OPERAND_art }, 'i' }
4362};
4363
4364static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
4365 { { STATE_MISC1 }, 'o' }
4366};
4367
4368static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
4369 { { OPERAND_art }, 'm' }
4370};
4371
4372static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
4373 { { STATE_MISC1 }, 'm' }
4374};
4375
4376static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
4377 { { OPERAND_art }, 'o' }
4378};
4379
4380static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
4381 { { OPERAND_art }, 'o' }
4382};
4383
4384static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
4385 { { STATE_VECBASE }, 'i' }
4386};
4387
4388static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
4389 { { OPERAND_art }, 'i' }
4390};
4391
4392static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
4393 { { STATE_VECBASE }, 'o' }
4394};
4395
4396static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
4397 { { OPERAND_art }, 'm' }
4398};
4399
4400static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
4401 { { STATE_VECBASE }, 'm' }
4402};
4403
4404static xtensa_arg_internal Iclass_xt_mul16_args[] = {
4405 { { OPERAND_arr }, 'o' },
4406 { { OPERAND_ars }, 'i' },
4407 { { OPERAND_art }, 'i' }
4408};
4409
4410static xtensa_arg_internal Iclass_xt_mul32_args[] = {
4411 { { OPERAND_arr }, 'o' },
4412 { { OPERAND_ars }, 'i' },
4413 { { OPERAND_art }, 'i' }
4414};
4415
4416static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
4417 { { OPERAND_ars }, 'i' },
4418 { { OPERAND_art }, 'i' }
4419};
4420
4421static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
4422 { { STATE_ACC }, 'o' }
4423};
4424
4425static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
4426 { { OPERAND_ars }, 'i' },
4427 { { OPERAND_my }, 'i' }
4428};
4429
4430static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
4431 { { STATE_ACC }, 'o' }
4432};
4433
4434static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
4435 { { OPERAND_mx }, 'i' },
4436 { { OPERAND_art }, 'i' }
4437};
4438
4439static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
4440 { { STATE_ACC }, 'o' }
4441};
4442
4443static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
4444 { { OPERAND_mx }, 'i' },
4445 { { OPERAND_my }, 'i' }
4446};
4447
4448static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
4449 { { STATE_ACC }, 'o' }
4450};
4451
4452static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
4453 { { OPERAND_ars }, 'i' },
4454 { { OPERAND_art }, 'i' }
4455};
4456
4457static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
4458 { { STATE_ACC }, 'm' }
4459};
4460
4461static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
4462 { { OPERAND_ars }, 'i' },
4463 { { OPERAND_my }, 'i' }
4464};
4465
4466static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
4467 { { STATE_ACC }, 'm' }
4468};
4469
4470static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
4471 { { OPERAND_mx }, 'i' },
4472 { { OPERAND_art }, 'i' }
4473};
4474
4475static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
4476 { { STATE_ACC }, 'm' }
4477};
4478
4479static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
4480 { { OPERAND_mx }, 'i' },
4481 { { OPERAND_my }, 'i' }
4482};
4483
4484static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
4485 { { STATE_ACC }, 'm' }
4486};
4487
4488static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
4489 { { OPERAND_mw }, 'o' },
4490 { { OPERAND_ars }, 'm' },
4491 { { OPERAND_mx }, 'i' },
4492 { { OPERAND_art }, 'i' }
4493};
4494
4495static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
4496 { { STATE_ACC }, 'm' }
4497};
4498
4499static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
4500 { { OPERAND_mw }, 'o' },
4501 { { OPERAND_ars }, 'm' },
4502 { { OPERAND_mx }, 'i' },
4503 { { OPERAND_my }, 'i' }
4504};
4505
4506static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
4507 { { STATE_ACC }, 'm' }
4508};
4509
4510static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
4511 { { OPERAND_mw }, 'o' },
4512 { { OPERAND_ars }, 'm' }
4513};
4514
4515static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
4516 { { OPERAND_art }, 'o' },
4517 { { OPERAND_mr0 }, 'i' }
4518};
4519
4520static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
4521 { { OPERAND_art }, 'i' },
4522 { { OPERAND_mr0 }, 'o' }
4523};
4524
4525static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
4526 { { OPERAND_art }, 'm' },
4527 { { OPERAND_mr0 }, 'm' }
4528};
4529
4530static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
4531 { { OPERAND_art }, 'o' },
4532 { { OPERAND_mr1 }, 'i' }
4533};
4534
4535static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
4536 { { OPERAND_art }, 'i' },
4537 { { OPERAND_mr1 }, 'o' }
4538};
4539
4540static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
4541 { { OPERAND_art }, 'm' },
4542 { { OPERAND_mr1 }, 'm' }
4543};
4544
4545static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
4546 { { OPERAND_art }, 'o' },
4547 { { OPERAND_mr2 }, 'i' }
4548};
4549
4550static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
4551 { { OPERAND_art }, 'i' },
4552 { { OPERAND_mr2 }, 'o' }
4553};
4554
4555static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
4556 { { OPERAND_art }, 'm' },
4557 { { OPERAND_mr2 }, 'm' }
4558};
4559
4560static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
4561 { { OPERAND_art }, 'o' },
4562 { { OPERAND_mr3 }, 'i' }
4563};
4564
4565static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
4566 { { OPERAND_art }, 'i' },
4567 { { OPERAND_mr3 }, 'o' }
4568};
4569
4570static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
4571 { { OPERAND_art }, 'm' },
4572 { { OPERAND_mr3 }, 'm' }
4573};
4574
4575static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
4576 { { OPERAND_art }, 'o' }
4577};
4578
4579static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
4580 { { STATE_ACC }, 'i' }
4581};
4582
4583static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
4584 { { OPERAND_art }, 'i' }
4585};
4586
4587static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
4588 { { STATE_ACC }, 'm' }
4589};
4590
4591static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
4592 { { OPERAND_art }, 'm' }
4593};
4594
4595static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
4596 { { STATE_ACC }, 'm' }
4597};
4598
4599static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
4600 { { OPERAND_art }, 'o' }
4601};
4602
4603static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
4604 { { STATE_ACC }, 'i' }
4605};
4606
4607static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
4608 { { OPERAND_art }, 'i' }
4609};
4610
4611static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
4612 { { STATE_ACC }, 'm' }
4613};
4614
4615static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
4616 { { OPERAND_art }, 'm' }
4617};
4618
4619static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
4620 { { STATE_ACC }, 'm' }
4621};
4622
4623static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
4624 { { OPERAND_s }, 'i' }
4625};
4626
4627static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
4628 { { STATE_PSWOE }, 'o' },
4629 { { STATE_PSCALLINC }, 'o' },
4630 { { STATE_PSOWB }, 'o' },
4631 { { STATE_PSUM }, 'o' },
4632 { { STATE_PSEXCM }, 'o' },
4633 { { STATE_PSINTLEVEL }, 'o' },
4634 { { STATE_EPC1 }, 'i' },
4635 { { STATE_EPC2 }, 'i' },
4636 { { STATE_EPC3 }, 'i' },
4637 { { STATE_EPC4 }, 'i' },
4638 { { STATE_EPC5 }, 'i' },
4639 { { STATE_EPC6 }, 'i' },
4640 { { STATE_EPC7 }, 'i' },
4641 { { STATE_EPS2 }, 'i' },
4642 { { STATE_EPS3 }, 'i' },
4643 { { STATE_EPS4 }, 'i' },
4644 { { STATE_EPS5 }, 'i' },
4645 { { STATE_EPS6 }, 'i' },
4646 { { STATE_EPS7 }, 'i' },
4647 { { STATE_InOCDMode }, 'm' }
4648};
4649
4650static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
4651 { { OPERAND_s }, 'i' }
4652};
4653
4654static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
4655 { { STATE_PSINTLEVEL }, 'o' }
4656};
4657
4658static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
4659 { { OPERAND_art }, 'o' }
4660};
4661
4662static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
4663 { { STATE_INTERRUPT }, 'i' }
4664};
4665
4666static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
4667 { { OPERAND_art }, 'i' }
4668};
4669
4670static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
4671 { { STATE_XTSYNC }, 'o' },
4672 { { STATE_INTERRUPT }, 'm' }
4673};
4674
4675static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
4676 { { OPERAND_art }, 'i' }
4677};
4678
4679static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
4680 { { STATE_XTSYNC }, 'o' },
4681 { { STATE_INTERRUPT }, 'm' }
4682};
4683
4684static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
4685 { { OPERAND_art }, 'o' }
4686};
4687
4688static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
4689 { { STATE_INTENABLE }, 'i' }
4690};
4691
4692static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
4693 { { OPERAND_art }, 'i' }
4694};
4695
4696static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
4697 { { STATE_INTENABLE }, 'o' }
4698};
4699
4700static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
4701 { { OPERAND_art }, 'm' }
4702};
4703
4704static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
4705 { { STATE_INTENABLE }, 'm' }
4706};
4707
4708static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
4709 { { OPERAND_imms }, 'i' },
4710 { { OPERAND_immt }, 'i' }
4711};
4712
4713static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
4714 { { STATE_PSEXCM }, 'i' },
4715 { { STATE_PSINTLEVEL }, 'i' }
4716};
4717
4718static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
4719 { { OPERAND_imms }, 'i' }
4720};
4721
4722static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
4723 { { STATE_PSEXCM }, 'i' },
4724 { { STATE_PSINTLEVEL }, 'i' }
4725};
4726
4727static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
4728 { { OPERAND_art }, 'o' }
4729};
4730
4731static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
4732 { { STATE_DBREAKA0 }, 'i' }
4733};
4734
4735static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
4736 { { OPERAND_art }, 'i' }
4737};
4738
4739static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
4740 { { STATE_DBREAKA0 }, 'o' },
4741 { { STATE_XTSYNC }, 'o' }
4742};
4743
4744static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
4745 { { OPERAND_art }, 'm' }
4746};
4747
4748static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
4749 { { STATE_DBREAKA0 }, 'm' },
4750 { { STATE_XTSYNC }, 'o' }
4751};
4752
4753static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
4754 { { OPERAND_art }, 'o' }
4755};
4756
4757static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
4758 { { STATE_DBREAKC0 }, 'i' }
4759};
4760
4761static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
4762 { { OPERAND_art }, 'i' }
4763};
4764
4765static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
4766 { { STATE_DBREAKC0 }, 'o' },
4767 { { STATE_XTSYNC }, 'o' }
4768};
4769
4770static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
4771 { { OPERAND_art }, 'm' }
4772};
4773
4774static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
4775 { { STATE_DBREAKC0 }, 'm' },
4776 { { STATE_XTSYNC }, 'o' }
4777};
4778
4779static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
4780 { { OPERAND_art }, 'o' }
4781};
4782
4783static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
4784 { { STATE_DBREAKA1 }, 'i' }
4785};
4786
4787static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
4788 { { OPERAND_art }, 'i' }
4789};
4790
4791static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
4792 { { STATE_DBREAKA1 }, 'o' },
4793 { { STATE_XTSYNC }, 'o' }
4794};
4795
4796static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
4797 { { OPERAND_art }, 'm' }
4798};
4799
4800static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
4801 { { STATE_DBREAKA1 }, 'm' },
4802 { { STATE_XTSYNC }, 'o' }
4803};
4804
4805static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
4806 { { OPERAND_art }, 'o' }
4807};
4808
4809static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
4810 { { STATE_DBREAKC1 }, 'i' }
4811};
4812
4813static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
4814 { { OPERAND_art }, 'i' }
4815};
4816
4817static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
4818 { { STATE_DBREAKC1 }, 'o' },
4819 { { STATE_XTSYNC }, 'o' }
4820};
4821
4822static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
4823 { { OPERAND_art }, 'm' }
4824};
4825
4826static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
4827 { { STATE_DBREAKC1 }, 'm' },
4828 { { STATE_XTSYNC }, 'o' }
4829};
4830
4831static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
4832 { { OPERAND_art }, 'o' }
4833};
4834
4835static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
4836 { { STATE_IBREAKA0 }, 'i' }
4837};
4838
4839static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
4840 { { OPERAND_art }, 'i' }
4841};
4842
4843static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
4844 { { STATE_IBREAKA0 }, 'o' }
4845};
4846
4847static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
4848 { { OPERAND_art }, 'm' }
4849};
4850
4851static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
4852 { { STATE_IBREAKA0 }, 'm' }
4853};
4854
4855static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
4856 { { OPERAND_art }, 'o' }
4857};
4858
4859static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
4860 { { STATE_IBREAKA1 }, 'i' }
4861};
4862
4863static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
4864 { { OPERAND_art }, 'i' }
4865};
4866
4867static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
4868 { { STATE_IBREAKA1 }, 'o' }
4869};
4870
4871static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
4872 { { OPERAND_art }, 'm' }
4873};
4874
4875static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
4876 { { STATE_IBREAKA1 }, 'm' }
4877};
4878
4879static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
4880 { { OPERAND_art }, 'o' }
4881};
4882
4883static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
4884 { { STATE_IBREAKENABLE }, 'i' }
4885};
4886
4887static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
4888 { { OPERAND_art }, 'i' }
4889};
4890
4891static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
4892 { { STATE_IBREAKENABLE }, 'o' }
4893};
4894
4895static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
4896 { { OPERAND_art }, 'm' }
4897};
4898
4899static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
4900 { { STATE_IBREAKENABLE }, 'm' }
4901};
4902
4903static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
4904 { { OPERAND_art }, 'o' }
4905};
4906
4907static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
4908 { { STATE_DEBUGCAUSE }, 'i' },
4909 { { STATE_DBNUM }, 'i' }
4910};
4911
4912static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
4913 { { OPERAND_art }, 'i' }
4914};
4915
4916static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
4917 { { STATE_DEBUGCAUSE }, 'o' },
4918 { { STATE_DBNUM }, 'o' }
4919};
4920
4921static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
4922 { { OPERAND_art }, 'm' }
4923};
4924
4925static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
4926 { { STATE_DEBUGCAUSE }, 'm' },
4927 { { STATE_DBNUM }, 'm' }
4928};
4929
4930static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
4931 { { OPERAND_art }, 'o' }
4932};
4933
4934static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
4935 { { STATE_ICOUNT }, 'i' }
4936};
4937
4938static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
4939 { { OPERAND_art }, 'i' }
4940};
4941
4942static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
4943 { { STATE_XTSYNC }, 'o' },
4944 { { STATE_ICOUNT }, 'o' }
4945};
4946
4947static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
4948 { { OPERAND_art }, 'm' }
4949};
4950
4951static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
4952 { { STATE_XTSYNC }, 'o' },
4953 { { STATE_ICOUNT }, 'm' }
4954};
4955
4956static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
4957 { { OPERAND_art }, 'o' }
4958};
4959
4960static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
4961 { { STATE_ICOUNTLEVEL }, 'i' }
4962};
4963
4964static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
4965 { { OPERAND_art }, 'i' }
4966};
4967
4968static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
4969 { { STATE_ICOUNTLEVEL }, 'o' }
4970};
4971
4972static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
4973 { { OPERAND_art }, 'm' }
4974};
4975
4976static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
4977 { { STATE_ICOUNTLEVEL }, 'm' }
4978};
4979
4980static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
4981 { { OPERAND_art }, 'o' }
4982};
4983
4984static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
4985 { { STATE_DDR }, 'i' }
4986};
4987
4988static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
4989 { { OPERAND_art }, 'i' }
4990};
4991
4992static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
4993 { { STATE_XTSYNC }, 'o' },
4994 { { STATE_DDR }, 'o' }
4995};
4996
4997static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
4998 { { OPERAND_art }, 'm' }
4999};
5000
5001static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
5002 { { STATE_XTSYNC }, 'o' },
5003 { { STATE_DDR }, 'm' }
5004};
5005
5006static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = {
5007 { { OPERAND_ars }, 'm' }
5008};
5009
5010static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = {
5011 { { STATE_XTSYNC }, 'o' },
5012 { { STATE_InOCDMode }, 'i' },
5013 { { STATE_DDR }, 'o' }
5014};
5015
5016static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = {
5017 { { OPERAND_ars }, 'm' }
5018};
5019
5020static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = {
5021 { { STATE_InOCDMode }, 'i' },
5022 { { STATE_DDR }, 'i' }
5023};
5024
5025static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
5026 { { OPERAND_imms }, 'i' }
5027};
5028
5029static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
5030 { { STATE_InOCDMode }, 'm' },
5031 { { STATE_EPC6 }, 'i' },
5032 { { STATE_PSWOE }, 'o' },
5033 { { STATE_PSCALLINC }, 'o' },
5034 { { STATE_PSOWB }, 'o' },
5035 { { STATE_PSUM }, 'o' },
5036 { { STATE_PSEXCM }, 'o' },
5037 { { STATE_PSINTLEVEL }, 'o' },
5038 { { STATE_EPS6 }, 'i' }
5039};
5040
5041static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
5042 { { STATE_InOCDMode }, 'm' }
5043};
5044
5045static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
5046 { { OPERAND_art }, 'i' }
5047};
5048
5049static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
5050 { { STATE_XTSYNC }, 'o' }
5051};
5052
5053static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
5054 { { OPERAND_art }, 'o' }
5055};
5056
5057static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
5058 { { STATE_CCOUNT }, 'i' }
5059};
5060
5061static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
5062 { { OPERAND_art }, 'i' }
5063};
5064
5065static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
5066 { { STATE_XTSYNC }, 'o' },
5067 { { STATE_CCOUNT }, 'o' }
5068};
5069
5070static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
5071 { { OPERAND_art }, 'm' }
5072};
5073
5074static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
5075 { { STATE_XTSYNC }, 'o' },
5076 { { STATE_CCOUNT }, 'm' }
5077};
5078
5079static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
5080 { { OPERAND_art }, 'o' }
5081};
5082
5083static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
5084 { { STATE_CCOMPARE0 }, 'i' }
5085};
5086
5087static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
5088 { { OPERAND_art }, 'i' }
5089};
5090
5091static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
5092 { { STATE_CCOMPARE0 }, 'o' },
5093 { { STATE_INTERRUPT }, 'm' }
5094};
5095
5096static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
5097 { { OPERAND_art }, 'm' }
5098};
5099
5100static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
5101 { { STATE_CCOMPARE0 }, 'm' },
5102 { { STATE_INTERRUPT }, 'm' }
5103};
5104
5105static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
5106 { { OPERAND_art }, 'o' }
5107};
5108
5109static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
5110 { { STATE_CCOMPARE1 }, 'i' }
5111};
5112
5113static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
5114 { { OPERAND_art }, 'i' }
5115};
5116
5117static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
5118 { { STATE_CCOMPARE1 }, 'o' },
5119 { { STATE_INTERRUPT }, 'm' }
5120};
5121
5122static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
5123 { { OPERAND_art }, 'm' }
5124};
5125
5126static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
5127 { { STATE_CCOMPARE1 }, 'm' },
5128 { { STATE_INTERRUPT }, 'm' }
5129};
5130
5131static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
5132 { { OPERAND_art }, 'o' }
5133};
5134
5135static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
5136 { { STATE_CCOMPARE2 }, 'i' }
5137};
5138
5139static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
5140 { { OPERAND_art }, 'i' }
5141};
5142
5143static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
5144 { { STATE_CCOMPARE2 }, 'o' },
5145 { { STATE_INTERRUPT }, 'm' }
5146};
5147
5148static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
5149 { { OPERAND_art }, 'm' }
5150};
5151
5152static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
5153 { { STATE_CCOMPARE2 }, 'm' },
5154 { { STATE_INTERRUPT }, 'm' }
5155};
5156
5157static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
5158 { { OPERAND_ars }, 'i' },
5159 { { OPERAND_uimm8x4 }, 'i' }
5160};
5161
5162static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
5163 { { OPERAND_ars }, 'i' },
5164 { { OPERAND_uimm4x16 }, 'i' }
5165};
5166
5167static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
5168 { { OPERAND_ars }, 'i' },
5169 { { OPERAND_uimm8x4 }, 'i' }
5170};
5171
5172static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
5173 { { OPERAND_art }, 'o' },
5174 { { OPERAND_ars }, 'i' }
5175};
5176
5177static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
5178 { { OPERAND_art }, 'i' },
5179 { { OPERAND_ars }, 'i' }
5180};
5181
5182static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
5183 { { OPERAND_ars }, 'i' },
5184 { { OPERAND_uimm8x4 }, 'i' }
5185};
5186
5187static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = {
5188 { { OPERAND_ars }, 'm' }
5189};
5190
5191static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
5192 { { OPERAND_ars }, 'i' },
5193 { { OPERAND_uimm4x16 }, 'i' }
5194};
5195
5196static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
5197 { { OPERAND_ars }, 'i' },
5198 { { OPERAND_uimm8x4 }, 'i' }
5199};
5200
5201static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
5202 { { OPERAND_ars }, 'i' },
5203 { { OPERAND_uimm8x4 }, 'i' }
5204};
5205
5206static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
5207 { { OPERAND_ars }, 'i' },
5208 { { OPERAND_uimm4x16 }, 'i' }
5209};
5210
5211static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
5212 { { OPERAND_art }, 'i' },
5213 { { OPERAND_ars }, 'i' }
5214};
5215
5216static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
5217 { { OPERAND_art }, 'o' },
5218 { { OPERAND_ars }, 'i' }
5219};
5220
5221static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
5222 { { OPERAND_ars }, 'i' }
5223};
5224
5225static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
5226 { { STATE_XTSYNC }, 'o' }
5227};
5228
5229static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
5230 { { OPERAND_art }, 'o' },
5231 { { OPERAND_ars }, 'i' }
5232};
5233
5234static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
5235 { { OPERAND_art }, 'i' },
5236 { { OPERAND_ars }, 'i' }
5237};
5238
5239static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
5240 { { STATE_XTSYNC }, 'o' }
5241};
5242
5243static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
5244 { { OPERAND_ars }, 'i' }
5245};
5246
5247static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
5248 { { OPERAND_art }, 'o' },
5249 { { OPERAND_ars }, 'i' }
5250};
5251
5252static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
5253 { { OPERAND_art }, 'i' },
5254 { { OPERAND_ars }, 'i' }
5255};
5256
5257static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
5258 { { OPERAND_arr }, 'o' },
5259 { { OPERAND_ars }, 'i' },
5260 { { OPERAND_tp7 }, 'i' }
5261};
5262
5263static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
5264 { { OPERAND_arr }, 'o' },
5265 { { OPERAND_ars }, 'i' },
5266 { { OPERAND_art }, 'i' }
5267};
5268
5269static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
5270 { { OPERAND_art }, 'o' },
5271 { { OPERAND_ars }, 'i' }
5272};
5273
5274static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
5275 { { OPERAND_arr }, 'o' },
5276 { { OPERAND_ars }, 'i' },
5277 { { OPERAND_tp7 }, 'i' }
5278};
5279
5280static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
5281 { { OPERAND_art }, 'o' },
5282 { { OPERAND_ars }, 'i' },
5283 { { OPERAND_uimm8x4 }, 'i' }
5284};
5285
5286static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
5287 { { OPERAND_art }, 'i' },
5288 { { OPERAND_ars }, 'i' },
5289 { { OPERAND_uimm8x4 }, 'i' }
5290};
5291
5292static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
5293 { { OPERAND_art }, 'm' },
5294 { { OPERAND_ars }, 'i' },
5295 { { OPERAND_uimm8x4 }, 'i' }
5296};
5297
5298static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
5299 { { STATE_SCOMPARE1 }, 'i' },
5300 { { STATE_XTSYNC }, 'i' },
5301 { { STATE_SCOMPARE1 }, 'i' }
5302};
5303
5304static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
5305 { { OPERAND_art }, 'o' }
5306};
5307
5308static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
5309 { { STATE_SCOMPARE1 }, 'i' }
5310};
5311
5312static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
5313 { { OPERAND_art }, 'i' }
5314};
5315
5316static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
5317 { { STATE_SCOMPARE1 }, 'o' }
5318};
5319
5320static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
5321 { { OPERAND_art }, 'm' }
5322};
5323
5324static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
5325 { { STATE_SCOMPARE1 }, 'm' }
5326};
5327
5328static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
5329 { { OPERAND_art }, 'o' }
5330};
5331
5332static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
5333 { { STATE_ATOMCTL }, 'i' }
5334};
5335
5336static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
5337 { { OPERAND_art }, 'i' }
5338};
5339
5340static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
5341 { { STATE_ATOMCTL }, 'o' },
5342 { { STATE_XTSYNC }, 'o' }
5343};
5344
5345static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
5346 { { OPERAND_art }, 'm' }
5347};
5348
5349static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
5350 { { STATE_ATOMCTL }, 'm' },
5351 { { STATE_XTSYNC }, 'o' }
5352};
5353
5354static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
5355 { { OPERAND_arr }, 'o' },
5356 { { OPERAND_ars }, 'i' },
5357 { { OPERAND_art }, 'i' }
5358};
5359
5360static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
5361 { { OPERAND_art }, 'o' },
5362 { { OPERAND_ars }, 'i' }
5363};
5364
5365static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = {
5366 { { STATE_ERI_RAW_INTERLOCK }, 'i' }
5367};
5368
5369static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = {
5370 INTERFACE_ERI_RD_In,
5371 INTERFACE_ERI_RD_Out
5372};
5373
5374static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
5375 { { OPERAND_art }, 'i' },
5376 { { OPERAND_ars }, 'i' }
5377};
5378
5379static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = {
5380 { { STATE_ERI_RAW_INTERLOCK }, 'o' }
5381};
5382
5383static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = {
5384 INTERFACE_ERI_WR_In,
5385 INTERFACE_ERI_WR_Out
5386};
5387
5388static xtensa_arg_internal Iclass_rur_expstate_args[] = {
5389 { { OPERAND_arr }, 'o' }
5390};
5391
5392static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
5393 { { STATE_EXPSTATE }, 'i' }
5394};
5395
5396static xtensa_arg_internal Iclass_wur_expstate_args[] = {
5397 { { OPERAND_art }, 'i' }
5398};
5399
5400static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
5401 { { STATE_EXPSTATE }, 'o' }
5402};
5403
5404static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
5405 { { OPERAND_art }, 'o' }
5406};
5407
5408static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = {
5409 INTERFACE_IMPWIRE
5410};
5411
5412static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
5413 { { OPERAND_bitindex }, 'i' }
5414};
5415
5416static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
5417 { { STATE_EXPSTATE }, 'm' }
5418};
5419
5420static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
5421 { { OPERAND_bitindex }, 'i' }
5422};
5423
5424static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
5425 { { STATE_EXPSTATE }, 'm' }
5426};
5427
5428static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
5429 { { OPERAND_art }, 'i' },
5430 { { OPERAND_ars }, 'i' }
5431};
5432
5433static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {
5434 { { STATE_EXPSTATE }, 'm' }
5435};
5436
5437static xtensa_iclass_internal iclasses[] = {
5438 { 0, 0 /* xt_iclass_excw */,
5439 0, 0, 0, 0 },
5440 { 0, 0 /* xt_iclass_rfe */,
5441 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
5442 { 0, 0 /* xt_iclass_rfde */,
5443 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
5444 { 0, 0 /* xt_iclass_syscall */,
5445 0, 0, 0, 0 },
5446 { 2, Iclass_xt_iclass_call12_args,
5447 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
5448 { 2, Iclass_xt_iclass_call8_args,
5449 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
5450 { 2, Iclass_xt_iclass_call4_args,
5451 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
5452 { 2, Iclass_xt_iclass_callx12_args,
5453 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
5454 { 2, Iclass_xt_iclass_callx8_args,
5455 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
5456 { 2, Iclass_xt_iclass_callx4_args,
5457 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
5458 { 3, Iclass_xt_iclass_entry_args,
5459 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
5460 { 2, Iclass_xt_iclass_movsp_args,
5461 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
5462 { 1, Iclass_xt_iclass_rotw_args,
5463 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
5464 { 1, Iclass_xt_iclass_retw_args,
5465 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
5466 { 0, 0 /* xt_iclass_rfwou */,
5467 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
5468 { 3, Iclass_xt_iclass_l32e_args,
5469 0, 0, 0, 0 },
5470 { 3, Iclass_xt_iclass_s32e_args,
5471 0, 0, 0, 0 },
5472 { 1, Iclass_xt_iclass_rsr_windowbase_args,
5473 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
5474 { 1, Iclass_xt_iclass_wsr_windowbase_args,
5475 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
5476 { 1, Iclass_xt_iclass_xsr_windowbase_args,
5477 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
5478 { 1, Iclass_xt_iclass_rsr_windowstart_args,
5479 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
5480 { 1, Iclass_xt_iclass_wsr_windowstart_args,
5481 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
5482 { 1, Iclass_xt_iclass_xsr_windowstart_args,
5483 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
5484 { 3, Iclass_xt_iclass_add_n_args,
5485 0, 0, 0, 0 },
5486 { 3, Iclass_xt_iclass_addi_n_args,
5487 0, 0, 0, 0 },
5488 { 2, Iclass_xt_iclass_bz6_args,
5489 0, 0, 0, 0 },
5490 { 0, 0 /* xt_iclass_ill_n */,
5491 0, 0, 0, 0 },
5492 { 3, Iclass_xt_iclass_loadi4_args,
5493 0, 0, 0, 0 },
5494 { 2, Iclass_xt_iclass_mov_n_args,
5495 0, 0, 0, 0 },
5496 { 2, Iclass_xt_iclass_movi_n_args,
5497 0, 0, 0, 0 },
5498 { 0, 0 /* xt_iclass_nopn */,
5499 0, 0, 0, 0 },
5500 { 1, Iclass_xt_iclass_retn_args,
5501 0, 0, 0, 0 },
5502 { 3, Iclass_xt_iclass_storei4_args,
5503 0, 0, 0, 0 },
5504 { 3, Iclass_xt_iclass_addi_args,
5505 0, 0, 0, 0 },
5506 { 3, Iclass_xt_iclass_addmi_args,
5507 0, 0, 0, 0 },
5508 { 3, Iclass_xt_iclass_addsub_args,
5509 0, 0, 0, 0 },
5510 { 3, Iclass_xt_iclass_bit_args,
5511 0, 0, 0, 0 },
5512 { 3, Iclass_xt_iclass_bsi8_args,
5513 0, 0, 0, 0 },
5514 { 3, Iclass_xt_iclass_bsi8b_args,
5515 0, 0, 0, 0 },
5516 { 3, Iclass_xt_iclass_bsi8u_args,
5517 0, 0, 0, 0 },
5518 { 3, Iclass_xt_iclass_bst8_args,
5519 0, 0, 0, 0 },
5520 { 2, Iclass_xt_iclass_bsz12_args,
5521 0, 0, 0, 0 },
5522 { 2, Iclass_xt_iclass_call0_args,
5523 0, 0, 0, 0 },
5524 { 2, Iclass_xt_iclass_callx0_args,
5525 0, 0, 0, 0 },
5526 { 4, Iclass_xt_iclass_exti_args,
5527 0, 0, 0, 0 },
5528 { 0, 0 /* xt_iclass_ill */,
5529 0, 0, 0, 0 },
5530 { 1, Iclass_xt_iclass_jump_args,
5531 0, 0, 0, 0 },
5532 { 1, Iclass_xt_iclass_jumpx_args,
5533 0, 0, 0, 0 },
5534 { 3, Iclass_xt_iclass_l16ui_args,
5535 0, 0, 0, 0 },
5536 { 3, Iclass_xt_iclass_l16si_args,
5537 0, 0, 0, 0 },
5538 { 3, Iclass_xt_iclass_l32i_args,
5539 0, 0, 0, 0 },
5540 { 2, Iclass_xt_iclass_l32r_args,
5541 0, 0, 0, 0 },
5542 { 3, Iclass_xt_iclass_l8i_args,
5543 0, 0, 0, 0 },
5544 { 2, Iclass_xt_iclass_loop_args,
5545 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
5546 { 2, Iclass_xt_iclass_loopz_args,
5547 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
5548 { 2, Iclass_xt_iclass_movi_args,
5549 0, 0, 0, 0 },
5550 { 3, Iclass_xt_iclass_movz_args,
5551 0, 0, 0, 0 },
5552 { 2, Iclass_xt_iclass_neg_args,
5553 0, 0, 0, 0 },
5554 { 0, 0 /* xt_iclass_nop */,
5555 0, 0, 0, 0 },
5556 { 1, Iclass_xt_iclass_return_args,
5557 0, 0, 0, 0 },
5558 { 0, 0 /* xt_iclass_simcall */,
5559 0, 0, 0, 0 },
5560 { 3, Iclass_xt_iclass_s16i_args,
5561 0, 0, 0, 0 },
5562 { 3, Iclass_xt_iclass_s32i_args,
5563 0, 0, 0, 0 },
5564 { 3, Iclass_xt_iclass_s32nb_args,
5565 0, 0, 0, 0 },
5566 { 3, Iclass_xt_iclass_s8i_args,
5567 0, 0, 0, 0 },
5568 { 1, Iclass_xt_iclass_sar_args,
5569 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
5570 { 1, Iclass_xt_iclass_sari_args,
5571 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
5572 { 2, Iclass_xt_iclass_shifts_args,
5573 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
5574 { 3, Iclass_xt_iclass_shiftst_args,
5575 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
5576 { 2, Iclass_xt_iclass_shiftt_args,
5577 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
5578 { 3, Iclass_xt_iclass_slli_args,
5579 0, 0, 0, 0 },
5580 { 3, Iclass_xt_iclass_srai_args,
5581 0, 0, 0, 0 },
5582 { 3, Iclass_xt_iclass_srli_args,
5583 0, 0, 0, 0 },
5584 { 0, 0 /* xt_iclass_memw */,
5585 0, 0, 0, 0 },
5586 { 0, 0 /* xt_iclass_extw */,
5587 0, 0, 0, 0 },
5588 { 0, 0 /* xt_iclass_isync */,
5589 0, 0, 0, 0 },
5590 { 0, 0 /* xt_iclass_sync */,
5591 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
5592 { 2, Iclass_xt_iclass_rsil_args,
5593 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
5594 { 1, Iclass_xt_iclass_rsr_lend_args,
5595 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
5596 { 1, Iclass_xt_iclass_wsr_lend_args,
5597 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
5598 { 1, Iclass_xt_iclass_xsr_lend_args,
5599 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
5600 { 1, Iclass_xt_iclass_rsr_lcount_args,
5601 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
5602 { 1, Iclass_xt_iclass_wsr_lcount_args,
5603 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
5604 { 1, Iclass_xt_iclass_xsr_lcount_args,
5605 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
5606 { 1, Iclass_xt_iclass_rsr_lbeg_args,
5607 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
5608 { 1, Iclass_xt_iclass_wsr_lbeg_args,
5609 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
5610 { 1, Iclass_xt_iclass_xsr_lbeg_args,
5611 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
5612 { 1, Iclass_xt_iclass_rsr_sar_args,
5613 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
5614 { 1, Iclass_xt_iclass_wsr_sar_args,
5615 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
5616 { 1, Iclass_xt_iclass_xsr_sar_args,
5617 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
5618 { 1, Iclass_xt_iclass_rsr_memctl_args,
5619 0, 0, 0, 0 },
5620 { 1, Iclass_xt_iclass_wsr_memctl_args,
5621 0, 0, 0, 0 },
5622 { 1, Iclass_xt_iclass_xsr_memctl_args,
5623 0, 0, 0, 0 },
5624 { 1, Iclass_xt_iclass_rsr_litbase_args,
5625 0, 0, 0, 0 },
5626 { 1, Iclass_xt_iclass_wsr_litbase_args,
5627 0, 0, 0, 0 },
5628 { 1, Iclass_xt_iclass_xsr_litbase_args,
5629 0, 0, 0, 0 },
5630 { 1, Iclass_xt_iclass_rsr_configid0_args,
5631 0, 0, 0, 0 },
5632 { 1, Iclass_xt_iclass_wsr_configid0_args,
5633 0, 0, 0, 0 },
5634 { 1, Iclass_xt_iclass_rsr_configid1_args,
5635 0, 0, 0, 0 },
5636 { 1, Iclass_xt_iclass_rsr_ps_args,
5637 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
5638 { 1, Iclass_xt_iclass_wsr_ps_args,
5639 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
5640 { 1, Iclass_xt_iclass_xsr_ps_args,
5641 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
5642 { 1, Iclass_xt_iclass_rsr_epc1_args,
5643 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
5644 { 1, Iclass_xt_iclass_wsr_epc1_args,
5645 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
5646 { 1, Iclass_xt_iclass_xsr_epc1_args,
5647 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
5648 { 1, Iclass_xt_iclass_rsr_excsave1_args,
5649 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
5650 { 1, Iclass_xt_iclass_wsr_excsave1_args,
5651 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
5652 { 1, Iclass_xt_iclass_xsr_excsave1_args,
5653 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
5654 { 1, Iclass_xt_iclass_rsr_epc2_args,
5655 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
5656 { 1, Iclass_xt_iclass_wsr_epc2_args,
5657 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
5658 { 1, Iclass_xt_iclass_xsr_epc2_args,
5659 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
5660 { 1, Iclass_xt_iclass_rsr_excsave2_args,
5661 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
5662 { 1, Iclass_xt_iclass_wsr_excsave2_args,
5663 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
5664 { 1, Iclass_xt_iclass_xsr_excsave2_args,
5665 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
5666 { 1, Iclass_xt_iclass_rsr_epc3_args,
5667 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
5668 { 1, Iclass_xt_iclass_wsr_epc3_args,
5669 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
5670 { 1, Iclass_xt_iclass_xsr_epc3_args,
5671 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
5672 { 1, Iclass_xt_iclass_rsr_excsave3_args,
5673 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
5674 { 1, Iclass_xt_iclass_wsr_excsave3_args,
5675 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
5676 { 1, Iclass_xt_iclass_xsr_excsave3_args,
5677 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
5678 { 1, Iclass_xt_iclass_rsr_epc4_args,
5679 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
5680 { 1, Iclass_xt_iclass_wsr_epc4_args,
5681 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
5682 { 1, Iclass_xt_iclass_xsr_epc4_args,
5683 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
5684 { 1, Iclass_xt_iclass_rsr_excsave4_args,
5685 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
5686 { 1, Iclass_xt_iclass_wsr_excsave4_args,
5687 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
5688 { 1, Iclass_xt_iclass_xsr_excsave4_args,
5689 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
5690 { 1, Iclass_xt_iclass_rsr_epc5_args,
5691 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
5692 { 1, Iclass_xt_iclass_wsr_epc5_args,
5693 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
5694 { 1, Iclass_xt_iclass_xsr_epc5_args,
5695 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
5696 { 1, Iclass_xt_iclass_rsr_excsave5_args,
5697 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
5698 { 1, Iclass_xt_iclass_wsr_excsave5_args,
5699 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
5700 { 1, Iclass_xt_iclass_xsr_excsave5_args,
5701 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
5702 { 1, Iclass_xt_iclass_rsr_epc6_args,
5703 1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
5704 { 1, Iclass_xt_iclass_wsr_epc6_args,
5705 1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
5706 { 1, Iclass_xt_iclass_xsr_epc6_args,
5707 1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
5708 { 1, Iclass_xt_iclass_rsr_excsave6_args,
5709 1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
5710 { 1, Iclass_xt_iclass_wsr_excsave6_args,
5711 1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
5712 { 1, Iclass_xt_iclass_xsr_excsave6_args,
5713 1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
5714 { 1, Iclass_xt_iclass_rsr_epc7_args,
5715 1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
5716 { 1, Iclass_xt_iclass_wsr_epc7_args,
5717 1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
5718 { 1, Iclass_xt_iclass_xsr_epc7_args,
5719 1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
5720 { 1, Iclass_xt_iclass_rsr_excsave7_args,
5721 1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
5722 { 1, Iclass_xt_iclass_wsr_excsave7_args,
5723 1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
5724 { 1, Iclass_xt_iclass_xsr_excsave7_args,
5725 1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
5726 { 1, Iclass_xt_iclass_rsr_eps2_args,
5727 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
5728 { 1, Iclass_xt_iclass_wsr_eps2_args,
5729 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
5730 { 1, Iclass_xt_iclass_xsr_eps2_args,
5731 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
5732 { 1, Iclass_xt_iclass_rsr_eps3_args,
5733 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
5734 { 1, Iclass_xt_iclass_wsr_eps3_args,
5735 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
5736 { 1, Iclass_xt_iclass_xsr_eps3_args,
5737 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
5738 { 1, Iclass_xt_iclass_rsr_eps4_args,
5739 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
5740 { 1, Iclass_xt_iclass_wsr_eps4_args,
5741 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
5742 { 1, Iclass_xt_iclass_xsr_eps4_args,
5743 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
5744 { 1, Iclass_xt_iclass_rsr_eps5_args,
5745 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
5746 { 1, Iclass_xt_iclass_wsr_eps5_args,
5747 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
5748 { 1, Iclass_xt_iclass_xsr_eps5_args,
5749 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
5750 { 1, Iclass_xt_iclass_rsr_eps6_args,
5751 1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
5752 { 1, Iclass_xt_iclass_wsr_eps6_args,
5753 1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
5754 { 1, Iclass_xt_iclass_xsr_eps6_args,
5755 1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
5756 { 1, Iclass_xt_iclass_rsr_eps7_args,
5757 1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
5758 { 1, Iclass_xt_iclass_wsr_eps7_args,
5759 1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
5760 { 1, Iclass_xt_iclass_xsr_eps7_args,
5761 1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
5762 { 1, Iclass_xt_iclass_rsr_excvaddr_args,
5763 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
5764 { 1, Iclass_xt_iclass_wsr_excvaddr_args,
5765 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
5766 { 1, Iclass_xt_iclass_xsr_excvaddr_args,
5767 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
5768 { 1, Iclass_xt_iclass_rsr_depc_args,
5769 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
5770 { 1, Iclass_xt_iclass_wsr_depc_args,
5771 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
5772 { 1, Iclass_xt_iclass_xsr_depc_args,
5773 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
5774 { 1, Iclass_xt_iclass_rsr_exccause_args,
5775 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
5776 { 1, Iclass_xt_iclass_wsr_exccause_args,
5777 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
5778 { 1, Iclass_xt_iclass_xsr_exccause_args,
5779 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
5780 { 1, Iclass_xt_iclass_rsr_misc0_args,
5781 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
5782 { 1, Iclass_xt_iclass_wsr_misc0_args,
5783 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
5784 { 1, Iclass_xt_iclass_xsr_misc0_args,
5785 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
5786 { 1, Iclass_xt_iclass_rsr_misc1_args,
5787 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
5788 { 1, Iclass_xt_iclass_wsr_misc1_args,
5789 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
5790 { 1, Iclass_xt_iclass_xsr_misc1_args,
5791 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
5792 { 1, Iclass_xt_iclass_rsr_prid_args,
5793 0, 0, 0, 0 },
5794 { 1, Iclass_xt_iclass_rsr_vecbase_args,
5795 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
5796 { 1, Iclass_xt_iclass_wsr_vecbase_args,
5797 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
5798 { 1, Iclass_xt_iclass_xsr_vecbase_args,
5799 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
5800 { 3, Iclass_xt_mul16_args,
5801 0, 0, 0, 0 },
5802 { 3, Iclass_xt_mul32_args,
5803 0, 0, 0, 0 },
5804 { 2, Iclass_xt_iclass_mac16_aa_args,
5805 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
5806 { 2, Iclass_xt_iclass_mac16_ad_args,
5807 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
5808 { 2, Iclass_xt_iclass_mac16_da_args,
5809 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
5810 { 2, Iclass_xt_iclass_mac16_dd_args,
5811 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
5812 { 2, Iclass_xt_iclass_mac16a_aa_args,
5813 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
5814 { 2, Iclass_xt_iclass_mac16a_ad_args,
5815 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
5816 { 2, Iclass_xt_iclass_mac16a_da_args,
5817 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
5818 { 2, Iclass_xt_iclass_mac16a_dd_args,
5819 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
5820 { 4, Iclass_xt_iclass_mac16al_da_args,
5821 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
5822 { 4, Iclass_xt_iclass_mac16al_dd_args,
5823 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
5824 { 2, Iclass_xt_iclass_mac16_l_args,
5825 0, 0, 0, 0 },
5826 { 2, Iclass_xt_iclass_rsr_m0_args,
5827 0, 0, 0, 0 },
5828 { 2, Iclass_xt_iclass_wsr_m0_args,
5829 0, 0, 0, 0 },
5830 { 2, Iclass_xt_iclass_xsr_m0_args,
5831 0, 0, 0, 0 },
5832 { 2, Iclass_xt_iclass_rsr_m1_args,
5833 0, 0, 0, 0 },
5834 { 2, Iclass_xt_iclass_wsr_m1_args,
5835 0, 0, 0, 0 },
5836 { 2, Iclass_xt_iclass_xsr_m1_args,
5837 0, 0, 0, 0 },
5838 { 2, Iclass_xt_iclass_rsr_m2_args,
5839 0, 0, 0, 0 },
5840 { 2, Iclass_xt_iclass_wsr_m2_args,
5841 0, 0, 0, 0 },
5842 { 2, Iclass_xt_iclass_xsr_m2_args,
5843 0, 0, 0, 0 },
5844 { 2, Iclass_xt_iclass_rsr_m3_args,
5845 0, 0, 0, 0 },
5846 { 2, Iclass_xt_iclass_wsr_m3_args,
5847 0, 0, 0, 0 },
5848 { 2, Iclass_xt_iclass_xsr_m3_args,
5849 0, 0, 0, 0 },
5850 { 1, Iclass_xt_iclass_rsr_acclo_args,
5851 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
5852 { 1, Iclass_xt_iclass_wsr_acclo_args,
5853 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
5854 { 1, Iclass_xt_iclass_xsr_acclo_args,
5855 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
5856 { 1, Iclass_xt_iclass_rsr_acchi_args,
5857 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
5858 { 1, Iclass_xt_iclass_wsr_acchi_args,
5859 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
5860 { 1, Iclass_xt_iclass_xsr_acchi_args,
5861 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
5862 { 1, Iclass_xt_iclass_rfi_args,
5863 20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
5864 { 1, Iclass_xt_iclass_wait_args,
5865 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
5866 { 1, Iclass_xt_iclass_rsr_interrupt_args,
5867 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
5868 { 1, Iclass_xt_iclass_wsr_intset_args,
5869 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
5870 { 1, Iclass_xt_iclass_wsr_intclear_args,
5871 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
5872 { 1, Iclass_xt_iclass_rsr_intenable_args,
5873 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
5874 { 1, Iclass_xt_iclass_wsr_intenable_args,
5875 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
5876 { 1, Iclass_xt_iclass_xsr_intenable_args,
5877 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
5878 { 2, Iclass_xt_iclass_break_args,
5879 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
5880 { 1, Iclass_xt_iclass_break_n_args,
5881 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
5882 { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
5883 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
5884 { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
5885 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
5886 { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
5887 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
5888 { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
5889 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
5890 { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
5891 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
5892 { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
5893 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
5894 { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
5895 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
5896 { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
5897 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
5898 { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
5899 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
5900 { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
5901 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
5902 { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
5903 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
5904 { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
5905 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
5906 { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
5907 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
5908 { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
5909 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
5910 { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
5911 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
5912 { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
5913 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
5914 { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
5915 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
5916 { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
5917 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
5918 { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
5919 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
5920 { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
5921 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
5922 { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
5923 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
5924 { 1, Iclass_xt_iclass_rsr_debugcause_args,
5925 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
5926 { 1, Iclass_xt_iclass_wsr_debugcause_args,
5927 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
5928 { 1, Iclass_xt_iclass_xsr_debugcause_args,
5929 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
5930 { 1, Iclass_xt_iclass_rsr_icount_args,
5931 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
5932 { 1, Iclass_xt_iclass_wsr_icount_args,
5933 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
5934 { 1, Iclass_xt_iclass_xsr_icount_args,
5935 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
5936 { 1, Iclass_xt_iclass_rsr_icountlevel_args,
5937 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
5938 { 1, Iclass_xt_iclass_wsr_icountlevel_args,
5939 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
5940 { 1, Iclass_xt_iclass_xsr_icountlevel_args,
5941 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
5942 { 1, Iclass_xt_iclass_rsr_ddr_args,
5943 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
5944 { 1, Iclass_xt_iclass_wsr_ddr_args,
5945 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
5946 { 1, Iclass_xt_iclass_xsr_ddr_args,
5947 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
5948 { 1, Iclass_xt_iclass_lddr32_p_args,
5949 3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 },
5950 { 1, Iclass_xt_iclass_sddr32_p_args,
5951 2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 },
5952 { 1, Iclass_xt_iclass_rfdo_args,
5953 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
5954 { 0, 0 /* xt_iclass_rfdd */,
5955 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
5956 { 1, Iclass_xt_iclass_wsr_mmid_args,
5957 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
5958 { 1, Iclass_xt_iclass_rsr_ccount_args,
5959 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
5960 { 1, Iclass_xt_iclass_wsr_ccount_args,
5961 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
5962 { 1, Iclass_xt_iclass_xsr_ccount_args,
5963 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
5964 { 1, Iclass_xt_iclass_rsr_ccompare0_args,
5965 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
5966 { 1, Iclass_xt_iclass_wsr_ccompare0_args,
5967 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
5968 { 1, Iclass_xt_iclass_xsr_ccompare0_args,
5969 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
5970 { 1, Iclass_xt_iclass_rsr_ccompare1_args,
5971 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
5972 { 1, Iclass_xt_iclass_wsr_ccompare1_args,
5973 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
5974 { 1, Iclass_xt_iclass_xsr_ccompare1_args,
5975 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
5976 { 1, Iclass_xt_iclass_rsr_ccompare2_args,
5977 1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
5978 { 1, Iclass_xt_iclass_wsr_ccompare2_args,
5979 2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
5980 { 1, Iclass_xt_iclass_xsr_ccompare2_args,
5981 2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
5982 { 2, Iclass_xt_iclass_icache_args,
5983 0, 0, 0, 0 },
5984 { 2, Iclass_xt_iclass_icache_lock_args,
5985 0, 0, 0, 0 },
5986 { 2, Iclass_xt_iclass_icache_inv_args,
5987 0, 0, 0, 0 },
5988 { 2, Iclass_xt_iclass_licx_args,
5989 0, 0, 0, 0 },
5990 { 2, Iclass_xt_iclass_sicx_args,
5991 0, 0, 0, 0 },
5992 { 2, Iclass_xt_iclass_dcache_args,
5993 0, 0, 0, 0 },
5994 { 1, Iclass_xt_iclass_dcache_dyn_args,
5995 0, 0, 0, 0 },
5996 { 2, Iclass_xt_iclass_dcache_ind_args,
5997 0, 0, 0, 0 },
5998 { 2, Iclass_xt_iclass_dcache_inv_args,
5999 0, 0, 0, 0 },
6000 { 2, Iclass_xt_iclass_dpf_args,
6001 0, 0, 0, 0 },
6002 { 2, Iclass_xt_iclass_dcache_lock_args,
6003 0, 0, 0, 0 },
6004 { 2, Iclass_xt_iclass_sdct_args,
6005 0, 0, 0, 0 },
6006 { 2, Iclass_xt_iclass_ldct_args,
6007 0, 0, 0, 0 },
6008 { 1, Iclass_xt_iclass_idtlb_args,
6009 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
6010 { 2, Iclass_xt_iclass_rdtlb_args,
6011 0, 0, 0, 0 },
6012 { 2, Iclass_xt_iclass_wdtlb_args,
6013 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
6014 { 1, Iclass_xt_iclass_iitlb_args,
6015 0, 0, 0, 0 },
6016 { 2, Iclass_xt_iclass_ritlb_args,
6017 0, 0, 0, 0 },
6018 { 2, Iclass_xt_iclass_witlb_args,
6019 0, 0, 0, 0 },
6020 { 3, Iclass_xt_iclass_clamp_args,
6021 0, 0, 0, 0 },
6022 { 3, Iclass_xt_iclass_minmax_args,
6023 0, 0, 0, 0 },
6024 { 2, Iclass_xt_iclass_nsa_args,
6025 0, 0, 0, 0 },
6026 { 3, Iclass_xt_iclass_sx_args,
6027 0, 0, 0, 0 },
6028 { 3, Iclass_xt_iclass_l32ai_args,
6029 0, 0, 0, 0 },
6030 { 3, Iclass_xt_iclass_s32ri_args,
6031 0, 0, 0, 0 },
6032 { 3, Iclass_xt_iclass_s32c1i_args,
6033 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
6034 { 1, Iclass_xt_iclass_rsr_scompare1_args,
6035 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
6036 { 1, Iclass_xt_iclass_wsr_scompare1_args,
6037 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
6038 { 1, Iclass_xt_iclass_xsr_scompare1_args,
6039 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
6040 { 1, Iclass_xt_iclass_rsr_atomctl_args,
6041 1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
6042 { 1, Iclass_xt_iclass_wsr_atomctl_args,
6043 2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
6044 { 1, Iclass_xt_iclass_xsr_atomctl_args,
6045 2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
6046 { 3, Iclass_xt_iclass_div_args,
6047 0, 0, 0, 0 },
6048 { 2, Iclass_xt_iclass_rer_args,
6049 1, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs },
6050 { 2, Iclass_xt_iclass_wer_args,
6051 1, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs },
6052 { 1, Iclass_rur_expstate_args,
6053 1, Iclass_rur_expstate_stateArgs, 0, 0 },
6054 { 1, Iclass_wur_expstate_args,
6055 1, Iclass_wur_expstate_stateArgs, 0, 0 },
6056 { 1, Iclass_iclass_READ_IMPWIRE_args,
6057 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
6058 { 1, Iclass_iclass_SETB_EXPSTATE_args,
6059 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
6060 { 1, Iclass_iclass_CLRB_EXPSTATE_args,
6061 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
6062 { 2, Iclass_iclass_WRMSK_EXPSTATE_args,
6063 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
6064};
6065
6066enum xtensa_iclass_id {
6067 ICLASS_xt_iclass_excw,
6068 ICLASS_xt_iclass_rfe,
6069 ICLASS_xt_iclass_rfde,
6070 ICLASS_xt_iclass_syscall,
6071 ICLASS_xt_iclass_call12,
6072 ICLASS_xt_iclass_call8,
6073 ICLASS_xt_iclass_call4,
6074 ICLASS_xt_iclass_callx12,
6075 ICLASS_xt_iclass_callx8,
6076 ICLASS_xt_iclass_callx4,
6077 ICLASS_xt_iclass_entry,
6078 ICLASS_xt_iclass_movsp,
6079 ICLASS_xt_iclass_rotw,
6080 ICLASS_xt_iclass_retw,
6081 ICLASS_xt_iclass_rfwou,
6082 ICLASS_xt_iclass_l32e,
6083 ICLASS_xt_iclass_s32e,
6084 ICLASS_xt_iclass_rsr_windowbase,
6085 ICLASS_xt_iclass_wsr_windowbase,
6086 ICLASS_xt_iclass_xsr_windowbase,
6087 ICLASS_xt_iclass_rsr_windowstart,
6088 ICLASS_xt_iclass_wsr_windowstart,
6089 ICLASS_xt_iclass_xsr_windowstart,
6090 ICLASS_xt_iclass_add_n,
6091 ICLASS_xt_iclass_addi_n,
6092 ICLASS_xt_iclass_bz6,
6093 ICLASS_xt_iclass_ill_n,
6094 ICLASS_xt_iclass_loadi4,
6095 ICLASS_xt_iclass_mov_n,
6096 ICLASS_xt_iclass_movi_n,
6097 ICLASS_xt_iclass_nopn,
6098 ICLASS_xt_iclass_retn,
6099 ICLASS_xt_iclass_storei4,
6100 ICLASS_xt_iclass_addi,
6101 ICLASS_xt_iclass_addmi,
6102 ICLASS_xt_iclass_addsub,
6103 ICLASS_xt_iclass_bit,
6104 ICLASS_xt_iclass_bsi8,
6105 ICLASS_xt_iclass_bsi8b,
6106 ICLASS_xt_iclass_bsi8u,
6107 ICLASS_xt_iclass_bst8,
6108 ICLASS_xt_iclass_bsz12,
6109 ICLASS_xt_iclass_call0,
6110 ICLASS_xt_iclass_callx0,
6111 ICLASS_xt_iclass_exti,
6112 ICLASS_xt_iclass_ill,
6113 ICLASS_xt_iclass_jump,
6114 ICLASS_xt_iclass_jumpx,
6115 ICLASS_xt_iclass_l16ui,
6116 ICLASS_xt_iclass_l16si,
6117 ICLASS_xt_iclass_l32i,
6118 ICLASS_xt_iclass_l32r,
6119 ICLASS_xt_iclass_l8i,
6120 ICLASS_xt_iclass_loop,
6121 ICLASS_xt_iclass_loopz,
6122 ICLASS_xt_iclass_movi,
6123 ICLASS_xt_iclass_movz,
6124 ICLASS_xt_iclass_neg,
6125 ICLASS_xt_iclass_nop,
6126 ICLASS_xt_iclass_return,
6127 ICLASS_xt_iclass_simcall,
6128 ICLASS_xt_iclass_s16i,
6129 ICLASS_xt_iclass_s32i,
6130 ICLASS_xt_iclass_s32nb,
6131 ICLASS_xt_iclass_s8i,
6132 ICLASS_xt_iclass_sar,
6133 ICLASS_xt_iclass_sari,
6134 ICLASS_xt_iclass_shifts,
6135 ICLASS_xt_iclass_shiftst,
6136 ICLASS_xt_iclass_shiftt,
6137 ICLASS_xt_iclass_slli,
6138 ICLASS_xt_iclass_srai,
6139 ICLASS_xt_iclass_srli,
6140 ICLASS_xt_iclass_memw,
6141 ICLASS_xt_iclass_extw,
6142 ICLASS_xt_iclass_isync,
6143 ICLASS_xt_iclass_sync,
6144 ICLASS_xt_iclass_rsil,
6145 ICLASS_xt_iclass_rsr_lend,
6146 ICLASS_xt_iclass_wsr_lend,
6147 ICLASS_xt_iclass_xsr_lend,
6148 ICLASS_xt_iclass_rsr_lcount,
6149 ICLASS_xt_iclass_wsr_lcount,
6150 ICLASS_xt_iclass_xsr_lcount,
6151 ICLASS_xt_iclass_rsr_lbeg,
6152 ICLASS_xt_iclass_wsr_lbeg,
6153 ICLASS_xt_iclass_xsr_lbeg,
6154 ICLASS_xt_iclass_rsr_sar,
6155 ICLASS_xt_iclass_wsr_sar,
6156 ICLASS_xt_iclass_xsr_sar,
6157 ICLASS_xt_iclass_rsr_memctl,
6158 ICLASS_xt_iclass_wsr_memctl,
6159 ICLASS_xt_iclass_xsr_memctl,
6160 ICLASS_xt_iclass_rsr_litbase,
6161 ICLASS_xt_iclass_wsr_litbase,
6162 ICLASS_xt_iclass_xsr_litbase,
6163 ICLASS_xt_iclass_rsr_configid0,
6164 ICLASS_xt_iclass_wsr_configid0,
6165 ICLASS_xt_iclass_rsr_configid1,
6166 ICLASS_xt_iclass_rsr_ps,
6167 ICLASS_xt_iclass_wsr_ps,
6168 ICLASS_xt_iclass_xsr_ps,
6169 ICLASS_xt_iclass_rsr_epc1,
6170 ICLASS_xt_iclass_wsr_epc1,
6171 ICLASS_xt_iclass_xsr_epc1,
6172 ICLASS_xt_iclass_rsr_excsave1,
6173 ICLASS_xt_iclass_wsr_excsave1,
6174 ICLASS_xt_iclass_xsr_excsave1,
6175 ICLASS_xt_iclass_rsr_epc2,
6176 ICLASS_xt_iclass_wsr_epc2,
6177 ICLASS_xt_iclass_xsr_epc2,
6178 ICLASS_xt_iclass_rsr_excsave2,
6179 ICLASS_xt_iclass_wsr_excsave2,
6180 ICLASS_xt_iclass_xsr_excsave2,
6181 ICLASS_xt_iclass_rsr_epc3,
6182 ICLASS_xt_iclass_wsr_epc3,
6183 ICLASS_xt_iclass_xsr_epc3,
6184 ICLASS_xt_iclass_rsr_excsave3,
6185 ICLASS_xt_iclass_wsr_excsave3,
6186 ICLASS_xt_iclass_xsr_excsave3,
6187 ICLASS_xt_iclass_rsr_epc4,
6188 ICLASS_xt_iclass_wsr_epc4,
6189 ICLASS_xt_iclass_xsr_epc4,
6190 ICLASS_xt_iclass_rsr_excsave4,
6191 ICLASS_xt_iclass_wsr_excsave4,
6192 ICLASS_xt_iclass_xsr_excsave4,
6193 ICLASS_xt_iclass_rsr_epc5,
6194 ICLASS_xt_iclass_wsr_epc5,
6195 ICLASS_xt_iclass_xsr_epc5,
6196 ICLASS_xt_iclass_rsr_excsave5,
6197 ICLASS_xt_iclass_wsr_excsave5,
6198 ICLASS_xt_iclass_xsr_excsave5,
6199 ICLASS_xt_iclass_rsr_epc6,
6200 ICLASS_xt_iclass_wsr_epc6,
6201 ICLASS_xt_iclass_xsr_epc6,
6202 ICLASS_xt_iclass_rsr_excsave6,
6203 ICLASS_xt_iclass_wsr_excsave6,
6204 ICLASS_xt_iclass_xsr_excsave6,
6205 ICLASS_xt_iclass_rsr_epc7,
6206 ICLASS_xt_iclass_wsr_epc7,
6207 ICLASS_xt_iclass_xsr_epc7,
6208 ICLASS_xt_iclass_rsr_excsave7,
6209 ICLASS_xt_iclass_wsr_excsave7,
6210 ICLASS_xt_iclass_xsr_excsave7,
6211 ICLASS_xt_iclass_rsr_eps2,
6212 ICLASS_xt_iclass_wsr_eps2,
6213 ICLASS_xt_iclass_xsr_eps2,
6214 ICLASS_xt_iclass_rsr_eps3,
6215 ICLASS_xt_iclass_wsr_eps3,
6216 ICLASS_xt_iclass_xsr_eps3,
6217 ICLASS_xt_iclass_rsr_eps4,
6218 ICLASS_xt_iclass_wsr_eps4,
6219 ICLASS_xt_iclass_xsr_eps4,
6220 ICLASS_xt_iclass_rsr_eps5,
6221 ICLASS_xt_iclass_wsr_eps5,
6222 ICLASS_xt_iclass_xsr_eps5,
6223 ICLASS_xt_iclass_rsr_eps6,
6224 ICLASS_xt_iclass_wsr_eps6,
6225 ICLASS_xt_iclass_xsr_eps6,
6226 ICLASS_xt_iclass_rsr_eps7,
6227 ICLASS_xt_iclass_wsr_eps7,
6228 ICLASS_xt_iclass_xsr_eps7,
6229 ICLASS_xt_iclass_rsr_excvaddr,
6230 ICLASS_xt_iclass_wsr_excvaddr,
6231 ICLASS_xt_iclass_xsr_excvaddr,
6232 ICLASS_xt_iclass_rsr_depc,
6233 ICLASS_xt_iclass_wsr_depc,
6234 ICLASS_xt_iclass_xsr_depc,
6235 ICLASS_xt_iclass_rsr_exccause,
6236 ICLASS_xt_iclass_wsr_exccause,
6237 ICLASS_xt_iclass_xsr_exccause,
6238 ICLASS_xt_iclass_rsr_misc0,
6239 ICLASS_xt_iclass_wsr_misc0,
6240 ICLASS_xt_iclass_xsr_misc0,
6241 ICLASS_xt_iclass_rsr_misc1,
6242 ICLASS_xt_iclass_wsr_misc1,
6243 ICLASS_xt_iclass_xsr_misc1,
6244 ICLASS_xt_iclass_rsr_prid,
6245 ICLASS_xt_iclass_rsr_vecbase,
6246 ICLASS_xt_iclass_wsr_vecbase,
6247 ICLASS_xt_iclass_xsr_vecbase,
6248 ICLASS_xt_mul16,
6249 ICLASS_xt_mul32,
6250 ICLASS_xt_iclass_mac16_aa,
6251 ICLASS_xt_iclass_mac16_ad,
6252 ICLASS_xt_iclass_mac16_da,
6253 ICLASS_xt_iclass_mac16_dd,
6254 ICLASS_xt_iclass_mac16a_aa,
6255 ICLASS_xt_iclass_mac16a_ad,
6256 ICLASS_xt_iclass_mac16a_da,
6257 ICLASS_xt_iclass_mac16a_dd,
6258 ICLASS_xt_iclass_mac16al_da,
6259 ICLASS_xt_iclass_mac16al_dd,
6260 ICLASS_xt_iclass_mac16_l,
6261 ICLASS_xt_iclass_rsr_m0,
6262 ICLASS_xt_iclass_wsr_m0,
6263 ICLASS_xt_iclass_xsr_m0,
6264 ICLASS_xt_iclass_rsr_m1,
6265 ICLASS_xt_iclass_wsr_m1,
6266 ICLASS_xt_iclass_xsr_m1,
6267 ICLASS_xt_iclass_rsr_m2,
6268 ICLASS_xt_iclass_wsr_m2,
6269 ICLASS_xt_iclass_xsr_m2,
6270 ICLASS_xt_iclass_rsr_m3,
6271 ICLASS_xt_iclass_wsr_m3,
6272 ICLASS_xt_iclass_xsr_m3,
6273 ICLASS_xt_iclass_rsr_acclo,
6274 ICLASS_xt_iclass_wsr_acclo,
6275 ICLASS_xt_iclass_xsr_acclo,
6276 ICLASS_xt_iclass_rsr_acchi,
6277 ICLASS_xt_iclass_wsr_acchi,
6278 ICLASS_xt_iclass_xsr_acchi,
6279 ICLASS_xt_iclass_rfi,
6280 ICLASS_xt_iclass_wait,
6281 ICLASS_xt_iclass_rsr_interrupt,
6282 ICLASS_xt_iclass_wsr_intset,
6283 ICLASS_xt_iclass_wsr_intclear,
6284 ICLASS_xt_iclass_rsr_intenable,
6285 ICLASS_xt_iclass_wsr_intenable,
6286 ICLASS_xt_iclass_xsr_intenable,
6287 ICLASS_xt_iclass_break,
6288 ICLASS_xt_iclass_break_n,
6289 ICLASS_xt_iclass_rsr_dbreaka0,
6290 ICLASS_xt_iclass_wsr_dbreaka0,
6291 ICLASS_xt_iclass_xsr_dbreaka0,
6292 ICLASS_xt_iclass_rsr_dbreakc0,
6293 ICLASS_xt_iclass_wsr_dbreakc0,
6294 ICLASS_xt_iclass_xsr_dbreakc0,
6295 ICLASS_xt_iclass_rsr_dbreaka1,
6296 ICLASS_xt_iclass_wsr_dbreaka1,
6297 ICLASS_xt_iclass_xsr_dbreaka1,
6298 ICLASS_xt_iclass_rsr_dbreakc1,
6299 ICLASS_xt_iclass_wsr_dbreakc1,
6300 ICLASS_xt_iclass_xsr_dbreakc1,
6301 ICLASS_xt_iclass_rsr_ibreaka0,
6302 ICLASS_xt_iclass_wsr_ibreaka0,
6303 ICLASS_xt_iclass_xsr_ibreaka0,
6304 ICLASS_xt_iclass_rsr_ibreaka1,
6305 ICLASS_xt_iclass_wsr_ibreaka1,
6306 ICLASS_xt_iclass_xsr_ibreaka1,
6307 ICLASS_xt_iclass_rsr_ibreakenable,
6308 ICLASS_xt_iclass_wsr_ibreakenable,
6309 ICLASS_xt_iclass_xsr_ibreakenable,
6310 ICLASS_xt_iclass_rsr_debugcause,
6311 ICLASS_xt_iclass_wsr_debugcause,
6312 ICLASS_xt_iclass_xsr_debugcause,
6313 ICLASS_xt_iclass_rsr_icount,
6314 ICLASS_xt_iclass_wsr_icount,
6315 ICLASS_xt_iclass_xsr_icount,
6316 ICLASS_xt_iclass_rsr_icountlevel,
6317 ICLASS_xt_iclass_wsr_icountlevel,
6318 ICLASS_xt_iclass_xsr_icountlevel,
6319 ICLASS_xt_iclass_rsr_ddr,
6320 ICLASS_xt_iclass_wsr_ddr,
6321 ICLASS_xt_iclass_xsr_ddr,
6322 ICLASS_xt_iclass_lddr32_p,
6323 ICLASS_xt_iclass_sddr32_p,
6324 ICLASS_xt_iclass_rfdo,
6325 ICLASS_xt_iclass_rfdd,
6326 ICLASS_xt_iclass_wsr_mmid,
6327 ICLASS_xt_iclass_rsr_ccount,
6328 ICLASS_xt_iclass_wsr_ccount,
6329 ICLASS_xt_iclass_xsr_ccount,
6330 ICLASS_xt_iclass_rsr_ccompare0,
6331 ICLASS_xt_iclass_wsr_ccompare0,
6332 ICLASS_xt_iclass_xsr_ccompare0,
6333 ICLASS_xt_iclass_rsr_ccompare1,
6334 ICLASS_xt_iclass_wsr_ccompare1,
6335 ICLASS_xt_iclass_xsr_ccompare1,
6336 ICLASS_xt_iclass_rsr_ccompare2,
6337 ICLASS_xt_iclass_wsr_ccompare2,
6338 ICLASS_xt_iclass_xsr_ccompare2,
6339 ICLASS_xt_iclass_icache,
6340 ICLASS_xt_iclass_icache_lock,
6341 ICLASS_xt_iclass_icache_inv,
6342 ICLASS_xt_iclass_licx,
6343 ICLASS_xt_iclass_sicx,
6344 ICLASS_xt_iclass_dcache,
6345 ICLASS_xt_iclass_dcache_dyn,
6346 ICLASS_xt_iclass_dcache_ind,
6347 ICLASS_xt_iclass_dcache_inv,
6348 ICLASS_xt_iclass_dpf,
6349 ICLASS_xt_iclass_dcache_lock,
6350 ICLASS_xt_iclass_sdct,
6351 ICLASS_xt_iclass_ldct,
6352 ICLASS_xt_iclass_idtlb,
6353 ICLASS_xt_iclass_rdtlb,
6354 ICLASS_xt_iclass_wdtlb,
6355 ICLASS_xt_iclass_iitlb,
6356 ICLASS_xt_iclass_ritlb,
6357 ICLASS_xt_iclass_witlb,
6358 ICLASS_xt_iclass_clamp,
6359 ICLASS_xt_iclass_minmax,
6360 ICLASS_xt_iclass_nsa,
6361 ICLASS_xt_iclass_sx,
6362 ICLASS_xt_iclass_l32ai,
6363 ICLASS_xt_iclass_s32ri,
6364 ICLASS_xt_iclass_s32c1i,
6365 ICLASS_xt_iclass_rsr_scompare1,
6366 ICLASS_xt_iclass_wsr_scompare1,
6367 ICLASS_xt_iclass_xsr_scompare1,
6368 ICLASS_xt_iclass_rsr_atomctl,
6369 ICLASS_xt_iclass_wsr_atomctl,
6370 ICLASS_xt_iclass_xsr_atomctl,
6371 ICLASS_xt_iclass_div,
6372 ICLASS_xt_iclass_rer,
6373 ICLASS_xt_iclass_wer,
6374 ICLASS_rur_expstate,
6375 ICLASS_wur_expstate,
6376 ICLASS_iclass_READ_IMPWIRE,
6377 ICLASS_iclass_SETB_EXPSTATE,
6378 ICLASS_iclass_CLRB_EXPSTATE,
6379 ICLASS_iclass_WRMSK_EXPSTATE
6380};
6381
6382\f
6383/* Opcode encodings. */
6384
6385static void
6386Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
6387{
6388 slotbuf[0] = 0x2080;
6389}
6390
6391static void
6392Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
6393{
6394 slotbuf[0] = 0x3000;
6395}
6396
6397static void
6398Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
6399{
6400 slotbuf[0] = 0x3200;
6401}
6402
6403static void
6404Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
6405{
6406 slotbuf[0] = 0x5000;
6407}
6408
6409static void
6410Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
6411{
6412 slotbuf[0] = 0x35;
6413}
6414
6415static void
6416Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
6417{
6418 slotbuf[0] = 0x25;
6419}
6420
6421static void
6422Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6423{
6424 slotbuf[0] = 0x15;
6425}
6426
6427static void
6428Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
6429{
6430 slotbuf[0] = 0xf0;
6431}
6432
6433static void
6434Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
6435{
6436 slotbuf[0] = 0xe0;
6437}
6438
6439static void
6440Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6441{
6442 slotbuf[0] = 0xd0;
6443}
6444
6445static void
6446Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
6447{
6448 slotbuf[0] = 0x36;
6449}
6450
6451static void
6452Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
6453{
6454 slotbuf[0] = 0x1000;
6455}
6456
6457static void
6458Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
6459{
6460 slotbuf[0] = 0x408000;
6461}
6462
6463static void
6464Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
6465{
6466 slotbuf[0] = 0x90;
6467}
6468
6469static void
6470Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6471{
6472 slotbuf[0] = 0xf01d;
6473}
6474
6475static void
6476Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
6477{
6478 slotbuf[0] = 0x3400;
6479}
6480
6481static void
6482Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
6483{
6484 slotbuf[0] = 0x3500;
6485}
6486
6487static void
6488Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
6489{
6490 slotbuf[0] = 0x90000;
6491}
6492
6493static void
6494Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
6495{
6496 slotbuf[0] = 0x490000;
6497}
6498
6499static void
6500Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
6501{
6502 slotbuf[0] = 0x34800;
6503}
6504
6505static void
6506Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
6507{
6508 slotbuf[0] = 0x134800;
6509}
6510
6511static void
6512Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
6513{
6514 slotbuf[0] = 0x614800;
6515}
6516
6517static void
6518Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
6519{
6520 slotbuf[0] = 0x34900;
6521}
6522
6523static void
6524Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
6525{
6526 slotbuf[0] = 0x134900;
6527}
6528
6529static void
6530Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
6531{
6532 slotbuf[0] = 0x614900;
6533}
6534
6535static void
6536Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
6537{
6538 slotbuf[0] = 0xa;
6539}
6540
6541static void
6542Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
6543{
6544 slotbuf[0] = 0xb;
6545}
6546
6547static void
6548Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6549{
6550 slotbuf[0] = 0x8c;
6551}
6552
6553static void
6554Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6555{
6556 slotbuf[0] = 0xcc;
6557}
6558
6559static void
6560Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6561{
6562 slotbuf[0] = 0xf06d;
6563}
6564
6565static void
6566Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
6567{
6568 slotbuf[0] = 0x8;
6569}
6570
6571static void
6572Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6573{
6574 slotbuf[0] = 0xd;
6575}
6576
6577static void
6578Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6579{
6580 slotbuf[0] = 0xc;
6581}
6582
6583static void
6584Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6585{
6586 slotbuf[0] = 0xf03d;
6587}
6588
6589static void
6590Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6591{
6592 slotbuf[0] = 0xf00d;
6593}
6594
6595static void
6596Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
6597{
6598 slotbuf[0] = 0x9;
6599}
6600
6601static void
6602Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6603{
6604 slotbuf[0] = 0xc002;
6605}
6606
6607static void
6608Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6609{
6610 slotbuf[0] = 0xd002;
6611}
6612
6613static void
6614Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
6615{
6616 slotbuf[0] = 0x800000;
6617}
6618
6619static void
6620Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
6621{
6622 slotbuf[0] = 0xc00000;
6623}
6624
6625static void
6626Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6627{
6628 slotbuf[0] = 0x900000;
6629}
6630
6631static void
6632Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6633{
6634 slotbuf[0] = 0xa00000;
6635}
6636
6637static void
6638Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
6639{
6640 slotbuf[0] = 0xb00000;
6641}
6642
6643static void
6644Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6645{
6646 slotbuf[0] = 0xd00000;
6647}
6648
6649static void
6650Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6651{
6652 slotbuf[0] = 0xe00000;
6653}
6654
6655static void
6656Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
6657{
6658 slotbuf[0] = 0xf00000;
6659}
6660
6661static void
6662Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
6663{
6664 slotbuf[0] = 0x100000;
6665}
6666
6667static void
6668Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
6669{
6670 slotbuf[0] = 0x200000;
6671}
6672
6673static void
6674Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
6675{
6676 slotbuf[0] = 0x300000;
6677}
6678
6679static void
6680Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6681{
6682 slotbuf[0] = 0x26;
6683}
6684
6685static void
6686Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
6687{
6688 slotbuf[0] = 0x66;
6689}
6690
6691static void
6692Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
6693{
6694 slotbuf[0] = 0xe6;
6695}
6696
6697static void
6698Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
6699{
6700 slotbuf[0] = 0xa6;
6701}
6702
6703static void
6704Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
6705{
6706 slotbuf[0] = 0x6007;
6707}
6708
6709static void
6710Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6711{
6712 slotbuf[0] = 0xe007;
6713}
6714
6715static void
6716Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6717{
6718 slotbuf[0] = 0xf6;
6719}
6720
6721static void
6722Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6723{
6724 slotbuf[0] = 0xb6;
6725}
6726
6727static void
6728Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
6729{
6730 slotbuf[0] = 0x1007;
6731}
6732
6733static void
6734Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
6735{
6736 slotbuf[0] = 0x9007;
6737}
6738
6739static void
6740Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
6741{
6742 slotbuf[0] = 0xa007;
6743}
6744
6745static void
6746Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
6747{
6748 slotbuf[0] = 0x2007;
6749}
6750
6751static void
6752Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
6753{
6754 slotbuf[0] = 0xb007;
6755}
6756
6757static void
6758Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
6759{
6760 slotbuf[0] = 0x3007;
6761}
6762
6763static void
6764Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
6765{
6766 slotbuf[0] = 0x8007;
6767}
6768
6769static void
6770Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
6771{
6772 slotbuf[0] = 0x7;
6773}
6774
6775static void
6776Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
6777{
6778 slotbuf[0] = 0x4007;
6779}
6780
6781static void
6782Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
6783{
6784 slotbuf[0] = 0xc007;
6785}
6786
6787static void
6788Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
6789{
6790 slotbuf[0] = 0x5007;
6791}
6792
6793static void
6794Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
6795{
6796 slotbuf[0] = 0xd007;
6797}
6798
6799static void
6800Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6801{
6802 slotbuf[0] = 0x16;
6803}
6804
6805static void
6806Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6807{
6808 slotbuf[0] = 0x56;
6809}
6810
6811static void
6812Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6813{
6814 slotbuf[0] = 0xd6;
6815}
6816
6817static void
6818Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6819{
6820 slotbuf[0] = 0x96;
6821}
6822
6823static void
6824Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6825{
6826 slotbuf[0] = 0x5;
6827}
6828
6829static void
6830Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6831{
6832 slotbuf[0] = 0xc0;
6833}
6834
6835static void
6836Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6837{
6838 slotbuf[0] = 0x40000;
6839}
6840
6841static void
6842Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
6843{
6844 slotbuf[0] = 0;
6845}
6846
6847static void
6848Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
6849{
6850 slotbuf[0] = 0x6;
6851}
6852
6853static void
6854Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
6855{
6856 slotbuf[0] = 0xa0;
6857}
6858
6859static void
6860Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6861{
6862 slotbuf[0] = 0x1002;
6863}
6864
6865static void
6866Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
6867{
6868 slotbuf[0] = 0x9002;
6869}
6870
6871static void
6872Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
6873{
6874 slotbuf[0] = 0x2002;
6875}
6876
6877static void
6878Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
6879{
6880 slotbuf[0] = 0x1;
6881}
6882
6883static void
6884Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6885{
6886 slotbuf[0] = 0x2;
6887}
6888
6889static void
6890Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
6891{
6892 slotbuf[0] = 0x8076;
6893}
6894
6895static void
6896Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6897{
6898 slotbuf[0] = 0x9076;
6899}
6900
6901static void
6902Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6903{
6904 slotbuf[0] = 0xa076;
6905}
6906
6907static void
6908Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6909{
6910 slotbuf[0] = 0xa002;
6911}
6912
6913static void
6914Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6915{
6916 slotbuf[0] = 0x830000;
6917}
6918
6919static void
6920Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6921{
6922 slotbuf[0] = 0x930000;
6923}
6924
6925static void
6926Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6927{
6928 slotbuf[0] = 0xa30000;
6929}
6930
6931static void
6932Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6933{
6934 slotbuf[0] = 0xb30000;
6935}
6936
6937static void
6938Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
6939{
6940 slotbuf[0] = 0x600000;
6941}
6942
6943static void
6944Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
6945{
6946 slotbuf[0] = 0x600100;
6947}
6948
6949static void
6950Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
6951{
6952 slotbuf[0] = 0x20f0;
6953}
6954
6955static void
6956Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
6957{
6958 slotbuf[0] = 0x80;
6959}
6960
6961static void
6962Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
6963{
6964 slotbuf[0] = 0x5100;
6965}
6966
6967static void
6968Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
6969{
6970 slotbuf[0] = 0x5002;
6971}
6972
6973static void
6974Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
6975{
6976 slotbuf[0] = 0x6002;
6977}
6978
6979static void
6980Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf)
6981{
6982 slotbuf[0] = 0x590000;
6983}
6984
6985static void
6986Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
6987{
6988 slotbuf[0] = 0x4002;
6989}
6990
6991static void
6992Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
6993{
6994 slotbuf[0] = 0x400000;
6995}
6996
6997static void
6998Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
6999{
7000 slotbuf[0] = 0x401000;
7001}
7002
7003static void
7004Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
7005{
7006 slotbuf[0] = 0x402000;
7007}
7008
7009static void
7010Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
7011{
7012 slotbuf[0] = 0x403000;
7013}
7014
7015static void
7016Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
7017{
7018 slotbuf[0] = 0x404000;
7019}
7020
7021static void
7022Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7023{
7024 slotbuf[0] = 0xa10000;
7025}
7026
7027static void
7028Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
7029{
7030 slotbuf[0] = 0x810000;
7031}
7032
7033static void
7034Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7035{
7036 slotbuf[0] = 0x910000;
7037}
7038
7039static void
7040Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
7041{
7042 slotbuf[0] = 0xb10000;
7043}
7044
7045static void
7046Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
7047{
7048 slotbuf[0] = 0x10000;
7049}
7050
7051static void
7052Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
7053{
7054 slotbuf[0] = 0x210000;
7055}
7056
7057static void
7058Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
7059{
7060 slotbuf[0] = 0x410000;
7061}
7062
7063static void
7064Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
7065{
7066 slotbuf[0] = 0x20c0;
7067}
7068
7069static void
7070Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
7071{
7072 slotbuf[0] = 0x20d0;
7073}
7074
7075static void
7076Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
7077{
7078 slotbuf[0] = 0x2000;
7079}
7080
7081static void
7082Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
7083{
7084 slotbuf[0] = 0x2010;
7085}
7086
7087static void
7088Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
7089{
7090 slotbuf[0] = 0x2020;
7091}
7092
7093static void
7094Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
7095{
7096 slotbuf[0] = 0x2030;
7097}
7098
7099static void
7100Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
7101{
7102 slotbuf[0] = 0x6000;
7103}
7104
7105static void
7106Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
7107{
7108 slotbuf[0] = 0x30100;
7109}
7110
7111static void
7112Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
7113{
7114 slotbuf[0] = 0x130100;
7115}
7116
7117static void
7118Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
7119{
7120 slotbuf[0] = 0x610100;
7121}
7122
7123static void
7124Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
7125{
7126 slotbuf[0] = 0x30200;
7127}
7128
7129static void
7130Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
7131{
7132 slotbuf[0] = 0x130200;
7133}
7134
7135static void
7136Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
7137{
7138 slotbuf[0] = 0x610200;
7139}
7140
7141static void
7142Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
7143{
7144 slotbuf[0] = 0x30000;
7145}
7146
7147static void
7148Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
7149{
7150 slotbuf[0] = 0x130000;
7151}
7152
7153static void
7154Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
7155{
7156 slotbuf[0] = 0x610000;
7157}
7158
7159static void
7160Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
7161{
7162 slotbuf[0] = 0x30300;
7163}
7164
7165static void
7166Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
7167{
7168 slotbuf[0] = 0x130300;
7169}
7170
7171static void
7172Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
7173{
7174 slotbuf[0] = 0x610300;
7175}
7176
7177static void
7178Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7179{
7180 slotbuf[0] = 0x36100;
7181}
7182
7183static void
7184Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7185{
7186 slotbuf[0] = 0x136100;
7187}
7188
7189static void
7190Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7191{
7192 slotbuf[0] = 0x616100;
7193}
7194
7195static void
7196Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
7197{
7198 slotbuf[0] = 0x30500;
7199}
7200
7201static void
7202Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
7203{
7204 slotbuf[0] = 0x130500;
7205}
7206
7207static void
7208Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
7209{
7210 slotbuf[0] = 0x610500;
7211}
7212
7213static void
7214Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7215{
7216 slotbuf[0] = 0x3b000;
7217}
7218
7219static void
7220Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7221{
7222 slotbuf[0] = 0x13b000;
7223}
7224
7225static void
7226Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7227{
7228 slotbuf[0] = 0x3d000;
7229}
7230
7231static void
7232Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
7233{
7234 slotbuf[0] = 0x3e600;
7235}
7236
7237static void
7238Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
7239{
7240 slotbuf[0] = 0x13e600;
7241}
7242
7243static void
7244Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
7245{
7246 slotbuf[0] = 0x61e600;
7247}
7248
7249static void
7250Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7251{
7252 slotbuf[0] = 0x3b100;
7253}
7254
7255static void
7256Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7257{
7258 slotbuf[0] = 0x13b100;
7259}
7260
7261static void
7262Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7263{
7264 slotbuf[0] = 0x61b100;
7265}
7266
7267static void
7268Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7269{
7270 slotbuf[0] = 0x3d100;
7271}
7272
7273static void
7274Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7275{
7276 slotbuf[0] = 0x13d100;
7277}
7278
7279static void
7280Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7281{
7282 slotbuf[0] = 0x61d100;
7283}
7284
7285static void
7286Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7287{
7288 slotbuf[0] = 0x3b200;
7289}
7290
7291static void
7292Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7293{
7294 slotbuf[0] = 0x13b200;
7295}
7296
7297static void
7298Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7299{
7300 slotbuf[0] = 0x61b200;
7301}
7302
7303static void
7304Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7305{
7306 slotbuf[0] = 0x3d200;
7307}
7308
7309static void
7310Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7311{
7312 slotbuf[0] = 0x13d200;
7313}
7314
7315static void
7316Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7317{
7318 slotbuf[0] = 0x61d200;
7319}
7320
7321static void
7322Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7323{
7324 slotbuf[0] = 0x3b300;
7325}
7326
7327static void
7328Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7329{
7330 slotbuf[0] = 0x13b300;
7331}
7332
7333static void
7334Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7335{
7336 slotbuf[0] = 0x61b300;
7337}
7338
7339static void
7340Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7341{
7342 slotbuf[0] = 0x3d300;
7343}
7344
7345static void
7346Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7347{
7348 slotbuf[0] = 0x13d300;
7349}
7350
7351static void
7352Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7353{
7354 slotbuf[0] = 0x61d300;
7355}
7356
7357static void
7358Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7359{
7360 slotbuf[0] = 0x3b400;
7361}
7362
7363static void
7364Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7365{
7366 slotbuf[0] = 0x13b400;
7367}
7368
7369static void
7370Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7371{
7372 slotbuf[0] = 0x61b400;
7373}
7374
7375static void
7376Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7377{
7378 slotbuf[0] = 0x3d400;
7379}
7380
7381static void
7382Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7383{
7384 slotbuf[0] = 0x13d400;
7385}
7386
7387static void
7388Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7389{
7390 slotbuf[0] = 0x61d400;
7391}
7392
7393static void
7394Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7395{
7396 slotbuf[0] = 0x3b500;
7397}
7398
7399static void
7400Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7401{
7402 slotbuf[0] = 0x13b500;
7403}
7404
7405static void
7406Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7407{
7408 slotbuf[0] = 0x61b500;
7409}
7410
7411static void
7412Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7413{
7414 slotbuf[0] = 0x3d500;
7415}
7416
7417static void
7418Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7419{
7420 slotbuf[0] = 0x13d500;
7421}
7422
7423static void
7424Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7425{
7426 slotbuf[0] = 0x61d500;
7427}
7428
7429static void
7430Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7431{
7432 slotbuf[0] = 0x3b600;
7433}
7434
7435static void
7436Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7437{
7438 slotbuf[0] = 0x13b600;
7439}
7440
7441static void
7442Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7443{
7444 slotbuf[0] = 0x61b600;
7445}
7446
7447static void
7448Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7449{
7450 slotbuf[0] = 0x3d600;
7451}
7452
7453static void
7454Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7455{
7456 slotbuf[0] = 0x13d600;
7457}
7458
7459static void
7460Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7461{
7462 slotbuf[0] = 0x61d600;
7463}
7464
7465static void
7466Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7467{
7468 slotbuf[0] = 0x3b700;
7469}
7470
7471static void
7472Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7473{
7474 slotbuf[0] = 0x13b700;
7475}
7476
7477static void
7478Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7479{
7480 slotbuf[0] = 0x61b700;
7481}
7482
7483static void
7484Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7485{
7486 slotbuf[0] = 0x3d700;
7487}
7488
7489static void
7490Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7491{
7492 slotbuf[0] = 0x13d700;
7493}
7494
7495static void
7496Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7497{
7498 slotbuf[0] = 0x61d700;
7499}
7500
7501static void
7502Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7503{
7504 slotbuf[0] = 0x3c200;
7505}
7506
7507static void
7508Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7509{
7510 slotbuf[0] = 0x13c200;
7511}
7512
7513static void
7514Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7515{
7516 slotbuf[0] = 0x61c200;
7517}
7518
7519static void
7520Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7521{
7522 slotbuf[0] = 0x3c300;
7523}
7524
7525static void
7526Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7527{
7528 slotbuf[0] = 0x13c300;
7529}
7530
7531static void
7532Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7533{
7534 slotbuf[0] = 0x61c300;
7535}
7536
7537static void
7538Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7539{
7540 slotbuf[0] = 0x3c400;
7541}
7542
7543static void
7544Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7545{
7546 slotbuf[0] = 0x13c400;
7547}
7548
7549static void
7550Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7551{
7552 slotbuf[0] = 0x61c400;
7553}
7554
7555static void
7556Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7557{
7558 slotbuf[0] = 0x3c500;
7559}
7560
7561static void
7562Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7563{
7564 slotbuf[0] = 0x13c500;
7565}
7566
7567static void
7568Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7569{
7570 slotbuf[0] = 0x61c500;
7571}
7572
7573static void
7574Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7575{
7576 slotbuf[0] = 0x3c600;
7577}
7578
7579static void
7580Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7581{
7582 slotbuf[0] = 0x13c600;
7583}
7584
7585static void
7586Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7587{
7588 slotbuf[0] = 0x61c600;
7589}
7590
7591static void
7592Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7593{
7594 slotbuf[0] = 0x3c700;
7595}
7596
7597static void
7598Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7599{
7600 slotbuf[0] = 0x13c700;
7601}
7602
7603static void
7604Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7605{
7606 slotbuf[0] = 0x61c700;
7607}
7608
7609static void
7610Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
7611{
7612 slotbuf[0] = 0x3ee00;
7613}
7614
7615static void
7616Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
7617{
7618 slotbuf[0] = 0x13ee00;
7619}
7620
7621static void
7622Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
7623{
7624 slotbuf[0] = 0x61ee00;
7625}
7626
7627static void
7628Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
7629{
7630 slotbuf[0] = 0x3c000;
7631}
7632
7633static void
7634Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
7635{
7636 slotbuf[0] = 0x13c000;
7637}
7638
7639static void
7640Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
7641{
7642 slotbuf[0] = 0x61c000;
7643}
7644
7645static void
7646Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
7647{
7648 slotbuf[0] = 0x3e800;
7649}
7650
7651static void
7652Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
7653{
7654 slotbuf[0] = 0x13e800;
7655}
7656
7657static void
7658Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
7659{
7660 slotbuf[0] = 0x61e800;
7661}
7662
7663static void
7664Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7665{
7666 slotbuf[0] = 0x3f400;
7667}
7668
7669static void
7670Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7671{
7672 slotbuf[0] = 0x13f400;
7673}
7674
7675static void
7676Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7677{
7678 slotbuf[0] = 0x61f400;
7679}
7680
7681static void
7682Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7683{
7684 slotbuf[0] = 0x3f500;
7685}
7686
7687static void
7688Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7689{
7690 slotbuf[0] = 0x13f500;
7691}
7692
7693static void
7694Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7695{
7696 slotbuf[0] = 0x61f500;
7697}
7698
7699static void
7700Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
7701{
7702 slotbuf[0] = 0x3eb00;
7703}
7704
7705static void
7706Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
7707{
7708 slotbuf[0] = 0x3e700;
7709}
7710
7711static void
7712Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
7713{
7714 slotbuf[0] = 0x13e700;
7715}
7716
7717static void
7718Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
7719{
7720 slotbuf[0] = 0x61e700;
7721}
7722
7723static void
7724Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
7725{
7726 slotbuf[0] = 0xc10000;
7727}
7728
7729static void
7730Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
7731{
7732 slotbuf[0] = 0xd10000;
7733}
7734
7735static void
7736Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
7737{
7738 slotbuf[0] = 0x820000;
7739}
7740
7741static void
7742Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7743{
7744 slotbuf[0] = 0x740004;
7745}
7746
7747static void
7748Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7749{
7750 slotbuf[0] = 0x750004;
7751}
7752
7753static void
7754Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7755{
7756 slotbuf[0] = 0x760004;
7757}
7758
7759static void
7760Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7761{
7762 slotbuf[0] = 0x770004;
7763}
7764
7765static void
7766Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7767{
7768 slotbuf[0] = 0x700004;
7769}
7770
7771static void
7772Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7773{
7774 slotbuf[0] = 0x710004;
7775}
7776
7777static void
7778Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7779{
7780 slotbuf[0] = 0x720004;
7781}
7782
7783static void
7784Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7785{
7786 slotbuf[0] = 0x730004;
7787}
7788
7789static void
7790Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7791{
7792 slotbuf[0] = 0x340004;
7793}
7794
7795static void
7796Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7797{
7798 slotbuf[0] = 0x350004;
7799}
7800
7801static void
7802Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7803{
7804 slotbuf[0] = 0x360004;
7805}
7806
7807static void
7808Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7809{
7810 slotbuf[0] = 0x370004;
7811}
7812
7813static void
7814Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7815{
7816 slotbuf[0] = 0x640004;
7817}
7818
7819static void
7820Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7821{
7822 slotbuf[0] = 0x650004;
7823}
7824
7825static void
7826Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7827{
7828 slotbuf[0] = 0x660004;
7829}
7830
7831static void
7832Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7833{
7834 slotbuf[0] = 0x670004;
7835}
7836
7837static void
7838Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7839{
7840 slotbuf[0] = 0x240004;
7841}
7842
7843static void
7844Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7845{
7846 slotbuf[0] = 0x250004;
7847}
7848
7849static void
7850Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7851{
7852 slotbuf[0] = 0x260004;
7853}
7854
7855static void
7856Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7857{
7858 slotbuf[0] = 0x270004;
7859}
7860
7861static void
7862Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7863{
7864 slotbuf[0] = 0x780004;
7865}
7866
7867static void
7868Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7869{
7870 slotbuf[0] = 0x790004;
7871}
7872
7873static void
7874Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7875{
7876 slotbuf[0] = 0x7a0004;
7877}
7878
7879static void
7880Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7881{
7882 slotbuf[0] = 0x7b0004;
7883}
7884
7885static void
7886Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7887{
7888 slotbuf[0] = 0x7c0004;
7889}
7890
7891static void
7892Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7893{
7894 slotbuf[0] = 0x7d0004;
7895}
7896
7897static void
7898Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7899{
7900 slotbuf[0] = 0x7e0004;
7901}
7902
7903static void
7904Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7905{
7906 slotbuf[0] = 0x7f0004;
7907}
7908
7909static void
7910Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7911{
7912 slotbuf[0] = 0x380004;
7913}
7914
7915static void
7916Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7917{
7918 slotbuf[0] = 0x390004;
7919}
7920
7921static void
7922Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7923{
7924 slotbuf[0] = 0x3a0004;
7925}
7926
7927static void
7928Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7929{
7930 slotbuf[0] = 0x3b0004;
7931}
7932
7933static void
7934Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7935{
7936 slotbuf[0] = 0x3c0004;
7937}
7938
7939static void
7940Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7941{
7942 slotbuf[0] = 0x3d0004;
7943}
7944
7945static void
7946Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7947{
7948 slotbuf[0] = 0x3e0004;
7949}
7950
7951static void
7952Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7953{
7954 slotbuf[0] = 0x3f0004;
7955}
7956
7957static void
7958Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7959{
7960 slotbuf[0] = 0x680004;
7961}
7962
7963static void
7964Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7965{
7966 slotbuf[0] = 0x690004;
7967}
7968
7969static void
7970Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7971{
7972 slotbuf[0] = 0x6a0004;
7973}
7974
7975static void
7976Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7977{
7978 slotbuf[0] = 0x6b0004;
7979}
7980
7981static void
7982Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7983{
7984 slotbuf[0] = 0x6c0004;
7985}
7986
7987static void
7988Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7989{
7990 slotbuf[0] = 0x6d0004;
7991}
7992
7993static void
7994Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7995{
7996 slotbuf[0] = 0x6e0004;
7997}
7998
7999static void
8000Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
8001{
8002 slotbuf[0] = 0x6f0004;
8003}
8004
8005static void
8006Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
8007{
8008 slotbuf[0] = 0x280004;
8009}
8010
8011static void
8012Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
8013{
8014 slotbuf[0] = 0x290004;
8015}
8016
8017static void
8018Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
8019{
8020 slotbuf[0] = 0x2a0004;
8021}
8022
8023static void
8024Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
8025{
8026 slotbuf[0] = 0x2b0004;
8027}
8028
8029static void
8030Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
8031{
8032 slotbuf[0] = 0x2c0004;
8033}
8034
8035static void
8036Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
8037{
8038 slotbuf[0] = 0x2d0004;
8039}
8040
8041static void
8042Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
8043{
8044 slotbuf[0] = 0x2e0004;
8045}
8046
8047static void
8048Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
8049{
8050 slotbuf[0] = 0x2f0004;
8051}
8052
8053static void
8054Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
8055{
8056 slotbuf[0] = 0x580004;
8057}
8058
8059static void
8060Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
8061{
8062 slotbuf[0] = 0x480004;
8063}
8064
8065static void
8066Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
8067{
8068 slotbuf[0] = 0x590004;
8069}
8070
8071static void
8072Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
8073{
8074 slotbuf[0] = 0x490004;
8075}
8076
8077static void
8078Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
8079{
8080 slotbuf[0] = 0x5a0004;
8081}
8082
8083static void
8084Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
8085{
8086 slotbuf[0] = 0x4a0004;
8087}
8088
8089static void
8090Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
8091{
8092 slotbuf[0] = 0x5b0004;
8093}
8094
8095static void
8096Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
8097{
8098 slotbuf[0] = 0x4b0004;
8099}
8100
8101static void
8102Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
8103{
8104 slotbuf[0] = 0x180004;
8105}
8106
8107static void
8108Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
8109{
8110 slotbuf[0] = 0x80004;
8111}
8112
8113static void
8114Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
8115{
8116 slotbuf[0] = 0x190004;
8117}
8118
8119static void
8120Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
8121{
8122 slotbuf[0] = 0x90004;
8123}
8124
8125static void
8126Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
8127{
8128 slotbuf[0] = 0x1a0004;
8129}
8130
8131static void
8132Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
8133{
8134 slotbuf[0] = 0xa0004;
8135}
8136
8137static void
8138Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
8139{
8140 slotbuf[0] = 0x1b0004;
8141}
8142
8143static void
8144Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
8145{
8146 slotbuf[0] = 0xb0004;
8147}
8148
8149static void
8150Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
8151{
8152 slotbuf[0] = 0x900004;
8153}
8154
8155static void
8156Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
8157{
8158 slotbuf[0] = 0x800004;
8159}
8160
8161static void
8162Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8163{
8164 slotbuf[0] = 0x32000;
8165}
8166
8167static void
8168Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8169{
8170 slotbuf[0] = 0x132000;
8171}
8172
8173static void
8174Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8175{
8176 slotbuf[0] = 0x612000;
8177}
8178
8179static void
8180Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8181{
8182 slotbuf[0] = 0x32100;
8183}
8184
8185static void
8186Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8187{
8188 slotbuf[0] = 0x132100;
8189}
8190
8191static void
8192Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8193{
8194 slotbuf[0] = 0x612100;
8195}
8196
8197static void
8198Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
8199{
8200 slotbuf[0] = 0x32200;
8201}
8202
8203static void
8204Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
8205{
8206 slotbuf[0] = 0x132200;
8207}
8208
8209static void
8210Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
8211{
8212 slotbuf[0] = 0x612200;
8213}
8214
8215static void
8216Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
8217{
8218 slotbuf[0] = 0x32300;
8219}
8220
8221static void
8222Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
8223{
8224 slotbuf[0] = 0x132300;
8225}
8226
8227static void
8228Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
8229{
8230 slotbuf[0] = 0x612300;
8231}
8232
8233static void
8234Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
8235{
8236 slotbuf[0] = 0x31000;
8237}
8238
8239static void
8240Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
8241{
8242 slotbuf[0] = 0x131000;
8243}
8244
8245static void
8246Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
8247{
8248 slotbuf[0] = 0x611000;
8249}
8250
8251static void
8252Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8253{
8254 slotbuf[0] = 0x31100;
8255}
8256
8257static void
8258Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8259{
8260 slotbuf[0] = 0x131100;
8261}
8262
8263static void
8264Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8265{
8266 slotbuf[0] = 0x611100;
8267}
8268
8269static void
8270Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8271{
8272 slotbuf[0] = 0x3010;
8273}
8274
8275static void
8276Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
8277{
8278 slotbuf[0] = 0x7000;
8279}
8280
8281static void
8282Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
8283{
8284 slotbuf[0] = 0x3e200;
8285}
8286
8287static void
8288Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
8289{
8290 slotbuf[0] = 0x13e200;
8291}
8292
8293static void
8294Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
8295{
8296 slotbuf[0] = 0x13e300;
8297}
8298
8299static void
8300Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
8301{
8302 slotbuf[0] = 0x3e400;
8303}
8304
8305static void
8306Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
8307{
8308 slotbuf[0] = 0x13e400;
8309}
8310
8311static void
8312Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
8313{
8314 slotbuf[0] = 0x61e400;
8315}
8316
8317static void
8318Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
8319{
8320 slotbuf[0] = 0x4000;
8321}
8322
8323static void
8324Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
8325{
8326 slotbuf[0] = 0xf02d;
8327}
8328
8329static void
8330Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8331{
8332 slotbuf[0] = 0x39000;
8333}
8334
8335static void
8336Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8337{
8338 slotbuf[0] = 0x139000;
8339}
8340
8341static void
8342Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8343{
8344 slotbuf[0] = 0x619000;
8345}
8346
8347static void
8348Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8349{
8350 slotbuf[0] = 0x3a000;
8351}
8352
8353static void
8354Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8355{
8356 slotbuf[0] = 0x13a000;
8357}
8358
8359static void
8360Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8361{
8362 slotbuf[0] = 0x61a000;
8363}
8364
8365static void
8366Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8367{
8368 slotbuf[0] = 0x39100;
8369}
8370
8371static void
8372Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8373{
8374 slotbuf[0] = 0x139100;
8375}
8376
8377static void
8378Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8379{
8380 slotbuf[0] = 0x619100;
8381}
8382
8383static void
8384Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8385{
8386 slotbuf[0] = 0x3a100;
8387}
8388
8389static void
8390Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8391{
8392 slotbuf[0] = 0x13a100;
8393}
8394
8395static void
8396Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8397{
8398 slotbuf[0] = 0x61a100;
8399}
8400
8401static void
8402Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8403{
8404 slotbuf[0] = 0x38000;
8405}
8406
8407static void
8408Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8409{
8410 slotbuf[0] = 0x138000;
8411}
8412
8413static void
8414Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8415{
8416 slotbuf[0] = 0x618000;
8417}
8418
8419static void
8420Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8421{
8422 slotbuf[0] = 0x38100;
8423}
8424
8425static void
8426Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8427{
8428 slotbuf[0] = 0x138100;
8429}
8430
8431static void
8432Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8433{
8434 slotbuf[0] = 0x618100;
8435}
8436
8437static void
8438Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
8439{
8440 slotbuf[0] = 0x36000;
8441}
8442
8443static void
8444Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
8445{
8446 slotbuf[0] = 0x136000;
8447}
8448
8449static void
8450Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
8451{
8452 slotbuf[0] = 0x616000;
8453}
8454
8455static void
8456Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
8457{
8458 slotbuf[0] = 0x3e900;
8459}
8460
8461static void
8462Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
8463{
8464 slotbuf[0] = 0x13e900;
8465}
8466
8467static void
8468Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
8469{
8470 slotbuf[0] = 0x61e900;
8471}
8472
8473static void
8474Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
8475{
8476 slotbuf[0] = 0x3ec00;
8477}
8478
8479static void
8480Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
8481{
8482 slotbuf[0] = 0x13ec00;
8483}
8484
8485static void
8486Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
8487{
8488 slotbuf[0] = 0x61ec00;
8489}
8490
8491static void
8492Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
8493{
8494 slotbuf[0] = 0x3ed00;
8495}
8496
8497static void
8498Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
8499{
8500 slotbuf[0] = 0x13ed00;
8501}
8502
8503static void
8504Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
8505{
8506 slotbuf[0] = 0x61ed00;
8507}
8508
8509static void
8510Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
8511{
8512 slotbuf[0] = 0x36800;
8513}
8514
8515static void
8516Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
8517{
8518 slotbuf[0] = 0x136800;
8519}
8520
8521static void
8522Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
8523{
8524 slotbuf[0] = 0x616800;
8525}
8526
8527static void
8528Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
8529{
8530 slotbuf[0] = 0x70e0;
8531}
8532
8533static void
8534Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
8535{
8536 slotbuf[0] = 0x70f0;
8537}
8538
8539static void
8540Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
8541{
8542 slotbuf[0] = 0xf1e000;
8543}
8544
8545static void
8546Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
8547{
8548 slotbuf[0] = 0xf1e010;
8549}
8550
8551static void
8552Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
8553{
8554 slotbuf[0] = 0x135900;
8555}
8556
8557static void
8558Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
8559{
8560 slotbuf[0] = 0x3ea00;
8561}
8562
8563static void
8564Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
8565{
8566 slotbuf[0] = 0x13ea00;
8567}
8568
8569static void
8570Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
8571{
8572 slotbuf[0] = 0x61ea00;
8573}
8574
8575static void
8576Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8577{
8578 slotbuf[0] = 0x3f000;
8579}
8580
8581static void
8582Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8583{
8584 slotbuf[0] = 0x13f000;
8585}
8586
8587static void
8588Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8589{
8590 slotbuf[0] = 0x61f000;
8591}
8592
8593static void
8594Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8595{
8596 slotbuf[0] = 0x3f100;
8597}
8598
8599static void
8600Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8601{
8602 slotbuf[0] = 0x13f100;
8603}
8604
8605static void
8606Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8607{
8608 slotbuf[0] = 0x61f100;
8609}
8610
8611static void
8612Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
8613{
8614 slotbuf[0] = 0x3f200;
8615}
8616
8617static void
8618Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
8619{
8620 slotbuf[0] = 0x13f200;
8621}
8622
8623static void
8624Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
8625{
8626 slotbuf[0] = 0x61f200;
8627}
8628
8629static void
8630Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
8631{
8632 slotbuf[0] = 0x70c2;
8633}
8634
8635static void
8636Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8637{
8638 slotbuf[0] = 0x70e2;
8639}
8640
8641static void
8642Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
8643{
8644 slotbuf[0] = 0x70d2;
8645}
8646
8647static void
8648Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8649{
8650 slotbuf[0] = 0x270d2;
8651}
8652
8653static void
8654Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8655{
8656 slotbuf[0] = 0x370d2;
8657}
8658
8659static void
8660Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
8661{
8662 slotbuf[0] = 0x70f2;
8663}
8664
8665static void
8666Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
8667{
8668 slotbuf[0] = 0xf10000;
8669}
8670
8671static void
8672Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
8673{
8674 slotbuf[0] = 0xf12000;
8675}
8676
8677static void
8678Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
8679{
8680 slotbuf[0] = 0xf11000;
8681}
8682
8683static void
8684Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
8685{
8686 slotbuf[0] = 0xf13000;
8687}
8688
8689static void
8690Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8691{
8692 slotbuf[0] = 0x7042;
8693}
8694
8695static void
8696Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8697{
8698 slotbuf[0] = 0x7052;
8699}
8700
8701static void
8702Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
8703{
8704 slotbuf[0] = 0xf7082;
8705}
8706
8707static void
8708Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8709{
8710 slotbuf[0] = 0x47082;
8711}
8712
8713static void
8714Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8715{
8716 slotbuf[0] = 0x57082;
8717}
8718
8719static void
8720Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8721{
8722 slotbuf[0] = 0x7062;
8723}
8724
8725static void
8726Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
8727{
8728 slotbuf[0] = 0x7072;
8729}
8730
8731static void
8732Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
8733{
8734 slotbuf[0] = 0x7002;
8735}
8736
8737static void
8738Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
8739{
8740 slotbuf[0] = 0x7012;
8741}
8742
8743static void
8744Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
8745{
8746 slotbuf[0] = 0x7022;
8747}
8748
8749static void
8750Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
8751{
8752 slotbuf[0] = 0x7032;
8753}
8754
8755static void
8756Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
8757{
8758 slotbuf[0] = 0x7082;
8759}
8760
8761static void
8762Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8763{
8764 slotbuf[0] = 0x27082;
8765}
8766
8767static void
8768Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8769{
8770 slotbuf[0] = 0x37082;
8771}
8772
8773static void
8774Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
8775{
8776 slotbuf[0] = 0xf19000;
8777}
8778
8779static void
8780Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
8781{
8782 slotbuf[0] = 0xf18000;
8783}
8784
8785static void
8786Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8787{
8788 slotbuf[0] = 0x50c000;
8789}
8790
8791static void
8792Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8793{
8794 slotbuf[0] = 0x50d000;
8795}
8796
8797static void
8798Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8799{
8800 slotbuf[0] = 0x50b000;
8801}
8802
8803static void
8804Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8805{
8806 slotbuf[0] = 0x50f000;
8807}
8808
8809static void
8810Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8811{
8812 slotbuf[0] = 0x50e000;
8813}
8814
8815static void
8816Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8817{
8818 slotbuf[0] = 0x504000;
8819}
8820
8821static void
8822Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8823{
8824 slotbuf[0] = 0x505000;
8825}
8826
8827static void
8828Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8829{
8830 slotbuf[0] = 0x503000;
8831}
8832
8833static void
8834Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8835{
8836 slotbuf[0] = 0x507000;
8837}
8838
8839static void
8840Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8841{
8842 slotbuf[0] = 0x506000;
8843}
8844
8845static void
8846Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
8847{
8848 slotbuf[0] = 0x330000;
8849}
8850
8851static void
8852Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
8853{
8854 slotbuf[0] = 0x430000;
8855}
8856
8857static void
8858Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
8859{
8860 slotbuf[0] = 0x530000;
8861}
8862
8863static void
8864Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8865{
8866 slotbuf[0] = 0x630000;
8867}
8868
8869static void
8870Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8871{
8872 slotbuf[0] = 0x730000;
8873}
8874
8875static void
8876Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
8877{
8878 slotbuf[0] = 0x40e000;
8879}
8880
8881static void
8882Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
8883{
8884 slotbuf[0] = 0x40f000;
8885}
8886
8887static void
8888Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
8889{
8890 slotbuf[0] = 0x230000;
8891}
8892
8893static void
8894Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
8895{
8896 slotbuf[0] = 0xb002;
8897}
8898
8899static void
8900Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
8901{
8902 slotbuf[0] = 0xf002;
8903}
8904
8905static void
8906Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
8907{
8908 slotbuf[0] = 0xe002;
8909}
8910
8911static void
8912Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8913{
8914 slotbuf[0] = 0x30c00;
8915}
8916
8917static void
8918Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8919{
8920 slotbuf[0] = 0x130c00;
8921}
8922
8923static void
8924Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8925{
8926 slotbuf[0] = 0x610c00;
8927}
8928
8929static void
8930Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
8931{
8932 slotbuf[0] = 0x36300;
8933}
8934
8935static void
8936Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
8937{
8938 slotbuf[0] = 0x136300;
8939}
8940
8941static void
8942Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
8943{
8944 slotbuf[0] = 0x616300;
8945}
8946
8947static void
8948Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
8949{
8950 slotbuf[0] = 0xc20000;
8951}
8952
8953static void
8954Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
8955{
8956 slotbuf[0] = 0xd20000;
8957}
8958
8959static void
8960Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8961{
8962 slotbuf[0] = 0xe20000;
8963}
8964
8965static void
8966Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
8967{
8968 slotbuf[0] = 0xf20000;
8969}
8970
8971static void
8972Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
8973{
8974 slotbuf[0] = 0x406000;
8975}
8976
8977static void
8978Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
8979{
8980 slotbuf[0] = 0x407000;
8981}
8982
8983static void
8984Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
8985{
8986 slotbuf[0] = 0xe30e60;
8987}
8988
8989static void
8990Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
8991{
8992 slotbuf[0] = 0xf3e600;
8993}
8994
8995static void
8996Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf)
8997{
8998 slotbuf[0] = 0xe0000;
8999}
9000
9001static void
9002Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
9003{
9004 slotbuf[0] = 0xe1000;
9005}
9006
9007static void
9008Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
9009{
9010 slotbuf[0] = 0xe1200;
9011}
9012
9013static void
9014Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
9015{
9016 slotbuf[0] = 0xe2000;
9017}
9018
9019static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
9020 Opcode_excw_Slot_inst_encode, 0, 0
9021};
9022
9023static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
9024 Opcode_rfe_Slot_inst_encode, 0, 0
9025};
9026
9027static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
9028 Opcode_rfde_Slot_inst_encode, 0, 0
9029};
9030
9031static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
9032 Opcode_syscall_Slot_inst_encode, 0, 0
9033};
9034
9035static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
9036 Opcode_call12_Slot_inst_encode, 0, 0
9037};
9038
9039static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
9040 Opcode_call8_Slot_inst_encode, 0, 0
9041};
9042
9043static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
9044 Opcode_call4_Slot_inst_encode, 0, 0
9045};
9046
9047static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
9048 Opcode_callx12_Slot_inst_encode, 0, 0
9049};
9050
9051static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
9052 Opcode_callx8_Slot_inst_encode, 0, 0
9053};
9054
9055static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
9056 Opcode_callx4_Slot_inst_encode, 0, 0
9057};
9058
9059static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
9060 Opcode_entry_Slot_inst_encode, 0, 0
9061};
9062
9063static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
9064 Opcode_movsp_Slot_inst_encode, 0, 0
9065};
9066
9067static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
9068 Opcode_rotw_Slot_inst_encode, 0, 0
9069};
9070
9071static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
9072 Opcode_retw_Slot_inst_encode, 0, 0
9073};
9074
9075static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
9076 0, 0, Opcode_retw_n_Slot_inst16b_encode
9077};
9078
9079static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
9080 Opcode_rfwo_Slot_inst_encode, 0, 0
9081};
9082
9083static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
9084 Opcode_rfwu_Slot_inst_encode, 0, 0
9085};
9086
9087static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
9088 Opcode_l32e_Slot_inst_encode, 0, 0
9089};
9090
9091static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
9092 Opcode_s32e_Slot_inst_encode, 0, 0
9093};
9094
9095static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
9096 Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
9097};
9098
9099static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
9100 Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
9101};
9102
9103static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
9104 Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
9105};
9106
9107static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
9108 Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
9109};
9110
9111static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
9112 Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
9113};
9114
9115static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
9116 Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
9117};
9118
9119static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
9120 0, Opcode_add_n_Slot_inst16a_encode, 0
9121};
9122
9123static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
9124 0, Opcode_addi_n_Slot_inst16a_encode, 0
9125};
9126
9127static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
9128 0, 0, Opcode_beqz_n_Slot_inst16b_encode
9129};
9130
9131static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
9132 0, 0, Opcode_bnez_n_Slot_inst16b_encode
9133};
9134
9135static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
9136 0, 0, Opcode_ill_n_Slot_inst16b_encode
9137};
9138
9139static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
9140 0, Opcode_l32i_n_Slot_inst16a_encode, 0
9141};
9142
9143static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
9144 0, 0, Opcode_mov_n_Slot_inst16b_encode
9145};
9146
9147static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
9148 0, 0, Opcode_movi_n_Slot_inst16b_encode
9149};
9150
9151static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
9152 0, 0, Opcode_nop_n_Slot_inst16b_encode
9153};
9154
9155static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
9156 0, 0, Opcode_ret_n_Slot_inst16b_encode
9157};
9158
9159static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
9160 0, Opcode_s32i_n_Slot_inst16a_encode, 0
9161};
9162
9163static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
9164 Opcode_addi_Slot_inst_encode, 0, 0
9165};
9166
9167static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
9168 Opcode_addmi_Slot_inst_encode, 0, 0
9169};
9170
9171static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
9172 Opcode_add_Slot_inst_encode, 0, 0
9173};
9174
9175static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
9176 Opcode_sub_Slot_inst_encode, 0, 0
9177};
9178
9179static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
9180 Opcode_addx2_Slot_inst_encode, 0, 0
9181};
9182
9183static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
9184 Opcode_addx4_Slot_inst_encode, 0, 0
9185};
9186
9187static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
9188 Opcode_addx8_Slot_inst_encode, 0, 0
9189};
9190
9191static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
9192 Opcode_subx2_Slot_inst_encode, 0, 0
9193};
9194
9195static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
9196 Opcode_subx4_Slot_inst_encode, 0, 0
9197};
9198
9199static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
9200 Opcode_subx8_Slot_inst_encode, 0, 0
9201};
9202
9203static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
9204 Opcode_and_Slot_inst_encode, 0, 0
9205};
9206
9207static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
9208 Opcode_or_Slot_inst_encode, 0, 0
9209};
9210
9211static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
9212 Opcode_xor_Slot_inst_encode, 0, 0
9213};
9214
9215static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
9216 Opcode_beqi_Slot_inst_encode, 0, 0
9217};
9218
9219static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
9220 Opcode_bnei_Slot_inst_encode, 0, 0
9221};
9222
9223static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
9224 Opcode_bgei_Slot_inst_encode, 0, 0
9225};
9226
9227static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
9228 Opcode_blti_Slot_inst_encode, 0, 0
9229};
9230
9231static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
9232 Opcode_bbci_Slot_inst_encode, 0, 0
9233};
9234
9235static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
9236 Opcode_bbsi_Slot_inst_encode, 0, 0
9237};
9238
9239static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
9240 Opcode_bgeui_Slot_inst_encode, 0, 0
9241};
9242
9243static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
9244 Opcode_bltui_Slot_inst_encode, 0, 0
9245};
9246
9247static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
9248 Opcode_beq_Slot_inst_encode, 0, 0
9249};
9250
9251static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
9252 Opcode_bne_Slot_inst_encode, 0, 0
9253};
9254
9255static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
9256 Opcode_bge_Slot_inst_encode, 0, 0
9257};
9258
9259static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
9260 Opcode_blt_Slot_inst_encode, 0, 0
9261};
9262
9263static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
9264 Opcode_bgeu_Slot_inst_encode, 0, 0
9265};
9266
9267static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
9268 Opcode_bltu_Slot_inst_encode, 0, 0
9269};
9270
9271static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
9272 Opcode_bany_Slot_inst_encode, 0, 0
9273};
9274
9275static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
9276 Opcode_bnone_Slot_inst_encode, 0, 0
9277};
9278
9279static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
9280 Opcode_ball_Slot_inst_encode, 0, 0
9281};
9282
9283static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
9284 Opcode_bnall_Slot_inst_encode, 0, 0
9285};
9286
9287static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
9288 Opcode_bbc_Slot_inst_encode, 0, 0
9289};
9290
9291static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
9292 Opcode_bbs_Slot_inst_encode, 0, 0
9293};
9294
9295static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
9296 Opcode_beqz_Slot_inst_encode, 0, 0
9297};
9298
9299static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
9300 Opcode_bnez_Slot_inst_encode, 0, 0
9301};
9302
9303static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
9304 Opcode_bgez_Slot_inst_encode, 0, 0
9305};
9306
9307static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
9308 Opcode_bltz_Slot_inst_encode, 0, 0
9309};
9310
9311static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
9312 Opcode_call0_Slot_inst_encode, 0, 0
9313};
9314
9315static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
9316 Opcode_callx0_Slot_inst_encode, 0, 0
9317};
9318
9319static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
9320 Opcode_extui_Slot_inst_encode, 0, 0
9321};
9322
9323static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
9324 Opcode_ill_Slot_inst_encode, 0, 0
9325};
9326
9327static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
9328 Opcode_j_Slot_inst_encode, 0, 0
9329};
9330
9331static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
9332 Opcode_jx_Slot_inst_encode, 0, 0
9333};
9334
9335static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
9336 Opcode_l16ui_Slot_inst_encode, 0, 0
9337};
9338
9339static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
9340 Opcode_l16si_Slot_inst_encode, 0, 0
9341};
9342
9343static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
9344 Opcode_l32i_Slot_inst_encode, 0, 0
9345};
9346
9347static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
9348 Opcode_l32r_Slot_inst_encode, 0, 0
9349};
9350
9351static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
9352 Opcode_l8ui_Slot_inst_encode, 0, 0
9353};
9354
9355static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
9356 Opcode_loop_Slot_inst_encode, 0, 0
9357};
9358
9359static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
9360 Opcode_loopnez_Slot_inst_encode, 0, 0
9361};
9362
9363static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
9364 Opcode_loopgtz_Slot_inst_encode, 0, 0
9365};
9366
9367static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
9368 Opcode_movi_Slot_inst_encode, 0, 0
9369};
9370
9371static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
9372 Opcode_moveqz_Slot_inst_encode, 0, 0
9373};
9374
9375static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
9376 Opcode_movnez_Slot_inst_encode, 0, 0
9377};
9378
9379static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
9380 Opcode_movltz_Slot_inst_encode, 0, 0
9381};
9382
9383static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
9384 Opcode_movgez_Slot_inst_encode, 0, 0
9385};
9386
9387static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
9388 Opcode_neg_Slot_inst_encode, 0, 0
9389};
9390
9391static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
9392 Opcode_abs_Slot_inst_encode, 0, 0
9393};
9394
9395static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
9396 Opcode_nop_Slot_inst_encode, 0, 0
9397};
9398
9399static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
9400 Opcode_ret_Slot_inst_encode, 0, 0
9401};
9402
9403static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
9404 Opcode_simcall_Slot_inst_encode, 0, 0
9405};
9406
9407static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
9408 Opcode_s16i_Slot_inst_encode, 0, 0
9409};
9410
9411static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
9412 Opcode_s32i_Slot_inst_encode, 0, 0
9413};
9414
9415static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = {
9416 Opcode_s32nb_Slot_inst_encode, 0, 0
9417};
9418
9419static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
9420 Opcode_s8i_Slot_inst_encode, 0, 0
9421};
9422
9423static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
9424 Opcode_ssr_Slot_inst_encode, 0, 0
9425};
9426
9427static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
9428 Opcode_ssl_Slot_inst_encode, 0, 0
9429};
9430
9431static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
9432 Opcode_ssa8l_Slot_inst_encode, 0, 0
9433};
9434
9435static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
9436 Opcode_ssa8b_Slot_inst_encode, 0, 0
9437};
9438
9439static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
9440 Opcode_ssai_Slot_inst_encode, 0, 0
9441};
9442
9443static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
9444 Opcode_sll_Slot_inst_encode, 0, 0
9445};
9446
9447static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
9448 Opcode_src_Slot_inst_encode, 0, 0
9449};
9450
9451static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
9452 Opcode_srl_Slot_inst_encode, 0, 0
9453};
9454
9455static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
9456 Opcode_sra_Slot_inst_encode, 0, 0
9457};
9458
9459static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
9460 Opcode_slli_Slot_inst_encode, 0, 0
9461};
9462
9463static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
9464 Opcode_srai_Slot_inst_encode, 0, 0
9465};
9466
9467static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
9468 Opcode_srli_Slot_inst_encode, 0, 0
9469};
9470
9471static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
9472 Opcode_memw_Slot_inst_encode, 0, 0
9473};
9474
9475static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
9476 Opcode_extw_Slot_inst_encode, 0, 0
9477};
9478
9479static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
9480 Opcode_isync_Slot_inst_encode, 0, 0
9481};
9482
9483static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
9484 Opcode_rsync_Slot_inst_encode, 0, 0
9485};
9486
9487static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
9488 Opcode_esync_Slot_inst_encode, 0, 0
9489};
9490
9491static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
9492 Opcode_dsync_Slot_inst_encode, 0, 0
9493};
9494
9495static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
9496 Opcode_rsil_Slot_inst_encode, 0, 0
9497};
9498
9499static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
9500 Opcode_rsr_lend_Slot_inst_encode, 0, 0
9501};
9502
9503static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
9504 Opcode_wsr_lend_Slot_inst_encode, 0, 0
9505};
9506
9507static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
9508 Opcode_xsr_lend_Slot_inst_encode, 0, 0
9509};
9510
9511static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
9512 Opcode_rsr_lcount_Slot_inst_encode, 0, 0
9513};
9514
9515static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
9516 Opcode_wsr_lcount_Slot_inst_encode, 0, 0
9517};
9518
9519static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
9520 Opcode_xsr_lcount_Slot_inst_encode, 0, 0
9521};
9522
9523static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
9524 Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
9525};
9526
9527static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
9528 Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
9529};
9530
9531static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
9532 Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
9533};
9534
9535static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
9536 Opcode_rsr_sar_Slot_inst_encode, 0, 0
9537};
9538
9539static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
9540 Opcode_wsr_sar_Slot_inst_encode, 0, 0
9541};
9542
9543static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
9544 Opcode_xsr_sar_Slot_inst_encode, 0, 0
9545};
9546
9547static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = {
9548 Opcode_rsr_memctl_Slot_inst_encode, 0, 0
9549};
9550
9551static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = {
9552 Opcode_wsr_memctl_Slot_inst_encode, 0, 0
9553};
9554
9555static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = {
9556 Opcode_xsr_memctl_Slot_inst_encode, 0, 0
9557};
9558
9559static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
9560 Opcode_rsr_litbase_Slot_inst_encode, 0, 0
9561};
9562
9563static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
9564 Opcode_wsr_litbase_Slot_inst_encode, 0, 0
9565};
9566
9567static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
9568 Opcode_xsr_litbase_Slot_inst_encode, 0, 0
9569};
9570
9571static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = {
9572 Opcode_rsr_configid0_Slot_inst_encode, 0, 0
9573};
9574
9575static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = {
9576 Opcode_wsr_configid0_Slot_inst_encode, 0, 0
9577};
9578
9579static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = {
9580 Opcode_rsr_configid1_Slot_inst_encode, 0, 0
9581};
9582
9583static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
9584 Opcode_rsr_ps_Slot_inst_encode, 0, 0
9585};
9586
9587static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
9588 Opcode_wsr_ps_Slot_inst_encode, 0, 0
9589};
9590
9591static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
9592 Opcode_xsr_ps_Slot_inst_encode, 0, 0
9593};
9594
9595static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
9596 Opcode_rsr_epc1_Slot_inst_encode, 0, 0
9597};
9598
9599static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
9600 Opcode_wsr_epc1_Slot_inst_encode, 0, 0
9601};
9602
9603static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
9604 Opcode_xsr_epc1_Slot_inst_encode, 0, 0
9605};
9606
9607static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
9608 Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
9609};
9610
9611static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
9612 Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
9613};
9614
9615static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
9616 Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
9617};
9618
9619static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
9620 Opcode_rsr_epc2_Slot_inst_encode, 0, 0
9621};
9622
9623static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
9624 Opcode_wsr_epc2_Slot_inst_encode, 0, 0
9625};
9626
9627static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
9628 Opcode_xsr_epc2_Slot_inst_encode, 0, 0
9629};
9630
9631static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
9632 Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
9633};
9634
9635static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
9636 Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
9637};
9638
9639static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
9640 Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
9641};
9642
9643static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
9644 Opcode_rsr_epc3_Slot_inst_encode, 0, 0
9645};
9646
9647static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
9648 Opcode_wsr_epc3_Slot_inst_encode, 0, 0
9649};
9650
9651static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
9652 Opcode_xsr_epc3_Slot_inst_encode, 0, 0
9653};
9654
9655static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
9656 Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
9657};
9658
9659static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
9660 Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
9661};
9662
9663static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
9664 Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
9665};
9666
9667static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
9668 Opcode_rsr_epc4_Slot_inst_encode, 0, 0
9669};
9670
9671static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
9672 Opcode_wsr_epc4_Slot_inst_encode, 0, 0
9673};
9674
9675static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
9676 Opcode_xsr_epc4_Slot_inst_encode, 0, 0
9677};
9678
9679static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
9680 Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
9681};
9682
9683static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
9684 Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
9685};
9686
9687static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
9688 Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
9689};
9690
9691static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
9692 Opcode_rsr_epc5_Slot_inst_encode, 0, 0
9693};
9694
9695static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
9696 Opcode_wsr_epc5_Slot_inst_encode, 0, 0
9697};
9698
9699static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
9700 Opcode_xsr_epc5_Slot_inst_encode, 0, 0
9701};
9702
9703static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
9704 Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
9705};
9706
9707static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
9708 Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
9709};
9710
9711static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
9712 Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
9713};
9714
9715static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
9716 Opcode_rsr_epc6_Slot_inst_encode, 0, 0
9717};
9718
9719static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
9720 Opcode_wsr_epc6_Slot_inst_encode, 0, 0
9721};
9722
9723static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
9724 Opcode_xsr_epc6_Slot_inst_encode, 0, 0
9725};
9726
9727static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
9728 Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
9729};
9730
9731static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
9732 Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
9733};
9734
9735static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
9736 Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
9737};
9738
9739static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
9740 Opcode_rsr_epc7_Slot_inst_encode, 0, 0
9741};
9742
9743static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
9744 Opcode_wsr_epc7_Slot_inst_encode, 0, 0
9745};
9746
9747static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
9748 Opcode_xsr_epc7_Slot_inst_encode, 0, 0
9749};
9750
9751static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
9752 Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
9753};
9754
9755static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
9756 Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
9757};
9758
9759static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
9760 Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
9761};
9762
9763static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
9764 Opcode_rsr_eps2_Slot_inst_encode, 0, 0
9765};
9766
9767static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
9768 Opcode_wsr_eps2_Slot_inst_encode, 0, 0
9769};
9770
9771static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
9772 Opcode_xsr_eps2_Slot_inst_encode, 0, 0
9773};
9774
9775static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
9776 Opcode_rsr_eps3_Slot_inst_encode, 0, 0
9777};
9778
9779static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
9780 Opcode_wsr_eps3_Slot_inst_encode, 0, 0
9781};
9782
9783static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
9784 Opcode_xsr_eps3_Slot_inst_encode, 0, 0
9785};
9786
9787static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
9788 Opcode_rsr_eps4_Slot_inst_encode, 0, 0
9789};
9790
9791static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
9792 Opcode_wsr_eps4_Slot_inst_encode, 0, 0
9793};
9794
9795static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
9796 Opcode_xsr_eps4_Slot_inst_encode, 0, 0
9797};
9798
9799static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
9800 Opcode_rsr_eps5_Slot_inst_encode, 0, 0
9801};
9802
9803static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
9804 Opcode_wsr_eps5_Slot_inst_encode, 0, 0
9805};
9806
9807static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
9808 Opcode_xsr_eps5_Slot_inst_encode, 0, 0
9809};
9810
9811static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
9812 Opcode_rsr_eps6_Slot_inst_encode, 0, 0
9813};
9814
9815static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
9816 Opcode_wsr_eps6_Slot_inst_encode, 0, 0
9817};
9818
9819static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
9820 Opcode_xsr_eps6_Slot_inst_encode, 0, 0
9821};
9822
9823static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
9824 Opcode_rsr_eps7_Slot_inst_encode, 0, 0
9825};
9826
9827static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
9828 Opcode_wsr_eps7_Slot_inst_encode, 0, 0
9829};
9830
9831static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
9832 Opcode_xsr_eps7_Slot_inst_encode, 0, 0
9833};
9834
9835static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
9836 Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
9837};
9838
9839static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
9840 Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
9841};
9842
9843static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
9844 Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
9845};
9846
9847static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
9848 Opcode_rsr_depc_Slot_inst_encode, 0, 0
9849};
9850
9851static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
9852 Opcode_wsr_depc_Slot_inst_encode, 0, 0
9853};
9854
9855static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
9856 Opcode_xsr_depc_Slot_inst_encode, 0, 0
9857};
9858
9859static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
9860 Opcode_rsr_exccause_Slot_inst_encode, 0, 0
9861};
9862
9863static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
9864 Opcode_wsr_exccause_Slot_inst_encode, 0, 0
9865};
9866
9867static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
9868 Opcode_xsr_exccause_Slot_inst_encode, 0, 0
9869};
9870
9871static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
9872 Opcode_rsr_misc0_Slot_inst_encode, 0, 0
9873};
9874
9875static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
9876 Opcode_wsr_misc0_Slot_inst_encode, 0, 0
9877};
9878
9879static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
9880 Opcode_xsr_misc0_Slot_inst_encode, 0, 0
9881};
9882
9883static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
9884 Opcode_rsr_misc1_Slot_inst_encode, 0, 0
9885};
9886
9887static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
9888 Opcode_wsr_misc1_Slot_inst_encode, 0, 0
9889};
9890
9891static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
9892 Opcode_xsr_misc1_Slot_inst_encode, 0, 0
9893};
9894
9895static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
9896 Opcode_rsr_prid_Slot_inst_encode, 0, 0
9897};
9898
9899static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
9900 Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
9901};
9902
9903static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
9904 Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
9905};
9906
9907static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
9908 Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
9909};
9910
9911static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
9912 Opcode_mul16u_Slot_inst_encode, 0, 0
9913};
9914
9915static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
9916 Opcode_mul16s_Slot_inst_encode, 0, 0
9917};
9918
9919static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
9920 Opcode_mull_Slot_inst_encode, 0, 0
9921};
9922
9923static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
9924 Opcode_mul_aa_ll_Slot_inst_encode, 0, 0
9925};
9926
9927static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
9928 Opcode_mul_aa_hl_Slot_inst_encode, 0, 0
9929};
9930
9931static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
9932 Opcode_mul_aa_lh_Slot_inst_encode, 0, 0
9933};
9934
9935static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
9936 Opcode_mul_aa_hh_Slot_inst_encode, 0, 0
9937};
9938
9939static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
9940 Opcode_umul_aa_ll_Slot_inst_encode, 0, 0
9941};
9942
9943static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
9944 Opcode_umul_aa_hl_Slot_inst_encode, 0, 0
9945};
9946
9947static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
9948 Opcode_umul_aa_lh_Slot_inst_encode, 0, 0
9949};
9950
9951static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
9952 Opcode_umul_aa_hh_Slot_inst_encode, 0, 0
9953};
9954
9955static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
9956 Opcode_mul_ad_ll_Slot_inst_encode, 0, 0
9957};
9958
9959static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
9960 Opcode_mul_ad_hl_Slot_inst_encode, 0, 0
9961};
9962
9963static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
9964 Opcode_mul_ad_lh_Slot_inst_encode, 0, 0
9965};
9966
9967static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
9968 Opcode_mul_ad_hh_Slot_inst_encode, 0, 0
9969};
9970
9971static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
9972 Opcode_mul_da_ll_Slot_inst_encode, 0, 0
9973};
9974
9975static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
9976 Opcode_mul_da_hl_Slot_inst_encode, 0, 0
9977};
9978
9979static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
9980 Opcode_mul_da_lh_Slot_inst_encode, 0, 0
9981};
9982
9983static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
9984 Opcode_mul_da_hh_Slot_inst_encode, 0, 0
9985};
9986
9987static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
9988 Opcode_mul_dd_ll_Slot_inst_encode, 0, 0
9989};
9990
9991static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
9992 Opcode_mul_dd_hl_Slot_inst_encode, 0, 0
9993};
9994
9995static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
9996 Opcode_mul_dd_lh_Slot_inst_encode, 0, 0
9997};
9998
9999static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
10000 Opcode_mul_dd_hh_Slot_inst_encode, 0, 0
10001};
10002
10003static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
10004 Opcode_mula_aa_ll_Slot_inst_encode, 0, 0
10005};
10006
10007static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
10008 Opcode_mula_aa_hl_Slot_inst_encode, 0, 0
10009};
10010
10011static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
10012 Opcode_mula_aa_lh_Slot_inst_encode, 0, 0
10013};
10014
10015static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
10016 Opcode_mula_aa_hh_Slot_inst_encode, 0, 0
10017};
10018
10019static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
10020 Opcode_muls_aa_ll_Slot_inst_encode, 0, 0
10021};
10022
10023static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
10024 Opcode_muls_aa_hl_Slot_inst_encode, 0, 0
10025};
10026
10027static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
10028 Opcode_muls_aa_lh_Slot_inst_encode, 0, 0
10029};
10030
10031static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
10032 Opcode_muls_aa_hh_Slot_inst_encode, 0, 0
10033};
10034
10035static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
10036 Opcode_mula_ad_ll_Slot_inst_encode, 0, 0
10037};
10038
10039static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
10040 Opcode_mula_ad_hl_Slot_inst_encode, 0, 0
10041};
10042
10043static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
10044 Opcode_mula_ad_lh_Slot_inst_encode, 0, 0
10045};
10046
10047static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
10048 Opcode_mula_ad_hh_Slot_inst_encode, 0, 0
10049};
10050
10051static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
10052 Opcode_muls_ad_ll_Slot_inst_encode, 0, 0
10053};
10054
10055static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
10056 Opcode_muls_ad_hl_Slot_inst_encode, 0, 0
10057};
10058
10059static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
10060 Opcode_muls_ad_lh_Slot_inst_encode, 0, 0
10061};
10062
10063static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
10064 Opcode_muls_ad_hh_Slot_inst_encode, 0, 0
10065};
10066
10067static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
10068 Opcode_mula_da_ll_Slot_inst_encode, 0, 0
10069};
10070
10071static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
10072 Opcode_mula_da_hl_Slot_inst_encode, 0, 0
10073};
10074
10075static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
10076 Opcode_mula_da_lh_Slot_inst_encode, 0, 0
10077};
10078
10079static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
10080 Opcode_mula_da_hh_Slot_inst_encode, 0, 0
10081};
10082
10083static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
10084 Opcode_muls_da_ll_Slot_inst_encode, 0, 0
10085};
10086
10087static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
10088 Opcode_muls_da_hl_Slot_inst_encode, 0, 0
10089};
10090
10091static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
10092 Opcode_muls_da_lh_Slot_inst_encode, 0, 0
10093};
10094
10095static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
10096 Opcode_muls_da_hh_Slot_inst_encode, 0, 0
10097};
10098
10099static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
10100 Opcode_mula_dd_ll_Slot_inst_encode, 0, 0
10101};
10102
10103static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
10104 Opcode_mula_dd_hl_Slot_inst_encode, 0, 0
10105};
10106
10107static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
10108 Opcode_mula_dd_lh_Slot_inst_encode, 0, 0
10109};
10110
10111static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
10112 Opcode_mula_dd_hh_Slot_inst_encode, 0, 0
10113};
10114
10115static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
10116 Opcode_muls_dd_ll_Slot_inst_encode, 0, 0
10117};
10118
10119static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
10120 Opcode_muls_dd_hl_Slot_inst_encode, 0, 0
10121};
10122
10123static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
10124 Opcode_muls_dd_lh_Slot_inst_encode, 0, 0
10125};
10126
10127static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
10128 Opcode_muls_dd_hh_Slot_inst_encode, 0, 0
10129};
10130
10131static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
10132 Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0
10133};
10134
10135static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
10136 Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0
10137};
10138
10139static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
10140 Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0
10141};
10142
10143static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
10144 Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0
10145};
10146
10147static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
10148 Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0
10149};
10150
10151static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
10152 Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0
10153};
10154
10155static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
10156 Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0
10157};
10158
10159static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
10160 Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0
10161};
10162
10163static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
10164 Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0
10165};
10166
10167static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
10168 Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0
10169};
10170
10171static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
10172 Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0
10173};
10174
10175static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
10176 Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0
10177};
10178
10179static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
10180 Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0
10181};
10182
10183static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
10184 Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0
10185};
10186
10187static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
10188 Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0
10189};
10190
10191static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
10192 Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0
10193};
10194
10195static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
10196 Opcode_lddec_Slot_inst_encode, 0, 0
10197};
10198
10199static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
10200 Opcode_ldinc_Slot_inst_encode, 0, 0
10201};
10202
10203static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
10204 Opcode_rsr_m0_Slot_inst_encode, 0, 0
10205};
10206
10207static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
10208 Opcode_wsr_m0_Slot_inst_encode, 0, 0
10209};
10210
10211static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
10212 Opcode_xsr_m0_Slot_inst_encode, 0, 0
10213};
10214
10215static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
10216 Opcode_rsr_m1_Slot_inst_encode, 0, 0
10217};
10218
10219static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
10220 Opcode_wsr_m1_Slot_inst_encode, 0, 0
10221};
10222
10223static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
10224 Opcode_xsr_m1_Slot_inst_encode, 0, 0
10225};
10226
10227static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
10228 Opcode_rsr_m2_Slot_inst_encode, 0, 0
10229};
10230
10231static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
10232 Opcode_wsr_m2_Slot_inst_encode, 0, 0
10233};
10234
10235static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
10236 Opcode_xsr_m2_Slot_inst_encode, 0, 0
10237};
10238
10239static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
10240 Opcode_rsr_m3_Slot_inst_encode, 0, 0
10241};
10242
10243static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
10244 Opcode_wsr_m3_Slot_inst_encode, 0, 0
10245};
10246
10247static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
10248 Opcode_xsr_m3_Slot_inst_encode, 0, 0
10249};
10250
10251static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
10252 Opcode_rsr_acclo_Slot_inst_encode, 0, 0
10253};
10254
10255static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
10256 Opcode_wsr_acclo_Slot_inst_encode, 0, 0
10257};
10258
10259static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
10260 Opcode_xsr_acclo_Slot_inst_encode, 0, 0
10261};
10262
10263static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
10264 Opcode_rsr_acchi_Slot_inst_encode, 0, 0
10265};
10266
10267static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
10268 Opcode_wsr_acchi_Slot_inst_encode, 0, 0
10269};
10270
10271static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
10272 Opcode_xsr_acchi_Slot_inst_encode, 0, 0
10273};
10274
10275static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
10276 Opcode_rfi_Slot_inst_encode, 0, 0
10277};
10278
10279static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
10280 Opcode_waiti_Slot_inst_encode, 0, 0
10281};
10282
10283static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
10284 Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
10285};
10286
10287static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
10288 Opcode_wsr_intset_Slot_inst_encode, 0, 0
10289};
10290
10291static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
10292 Opcode_wsr_intclear_Slot_inst_encode, 0, 0
10293};
10294
10295static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
10296 Opcode_rsr_intenable_Slot_inst_encode, 0, 0
10297};
10298
10299static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
10300 Opcode_wsr_intenable_Slot_inst_encode, 0, 0
10301};
10302
10303static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
10304 Opcode_xsr_intenable_Slot_inst_encode, 0, 0
10305};
10306
10307static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
10308 Opcode_break_Slot_inst_encode, 0, 0
10309};
10310
10311static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
10312 0, 0, Opcode_break_n_Slot_inst16b_encode
10313};
10314
10315static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
10316 Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
10317};
10318
10319static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
10320 Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
10321};
10322
10323static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
10324 Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
10325};
10326
10327static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
10328 Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
10329};
10330
10331static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
10332 Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
10333};
10334
10335static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
10336 Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
10337};
10338
10339static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
10340 Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
10341};
10342
10343static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
10344 Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
10345};
10346
10347static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
10348 Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
10349};
10350
10351static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
10352 Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
10353};
10354
10355static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
10356 Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
10357};
10358
10359static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
10360 Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
10361};
10362
10363static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
10364 Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
10365};
10366
10367static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
10368 Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
10369};
10370
10371static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
10372 Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
10373};
10374
10375static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
10376 Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
10377};
10378
10379static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
10380 Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
10381};
10382
10383static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
10384 Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
10385};
10386
10387static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
10388 Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
10389};
10390
10391static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
10392 Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
10393};
10394
10395static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
10396 Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
10397};
10398
10399static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
10400 Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
10401};
10402
10403static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
10404 Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
10405};
10406
10407static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
10408 Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
10409};
10410
10411static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
10412 Opcode_rsr_icount_Slot_inst_encode, 0, 0
10413};
10414
10415static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
10416 Opcode_wsr_icount_Slot_inst_encode, 0, 0
10417};
10418
10419static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
10420 Opcode_xsr_icount_Slot_inst_encode, 0, 0
10421};
10422
10423static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
10424 Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
10425};
10426
10427static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
10428 Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
10429};
10430
10431static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
10432 Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
10433};
10434
10435static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
10436 Opcode_rsr_ddr_Slot_inst_encode, 0, 0
10437};
10438
10439static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
10440 Opcode_wsr_ddr_Slot_inst_encode, 0, 0
10441};
10442
10443static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
10444 Opcode_xsr_ddr_Slot_inst_encode, 0, 0
10445};
10446
10447static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = {
10448 Opcode_lddr32_p_Slot_inst_encode, 0, 0
10449};
10450
10451static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = {
10452 Opcode_sddr32_p_Slot_inst_encode, 0, 0
10453};
10454
10455static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
10456 Opcode_rfdo_Slot_inst_encode, 0, 0
10457};
10458
10459static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
10460 Opcode_rfdd_Slot_inst_encode, 0, 0
10461};
10462
10463static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
10464 Opcode_wsr_mmid_Slot_inst_encode, 0, 0
10465};
10466
10467static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
10468 Opcode_rsr_ccount_Slot_inst_encode, 0, 0
10469};
10470
10471static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
10472 Opcode_wsr_ccount_Slot_inst_encode, 0, 0
10473};
10474
10475static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
10476 Opcode_xsr_ccount_Slot_inst_encode, 0, 0
10477};
10478
10479static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
10480 Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
10481};
10482
10483static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
10484 Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
10485};
10486
10487static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
10488 Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
10489};
10490
10491static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
10492 Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
10493};
10494
10495static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
10496 Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
10497};
10498
10499static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
10500 Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
10501};
10502
10503static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
10504 Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
10505};
10506
10507static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
10508 Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
10509};
10510
10511static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
10512 Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
10513};
10514
10515static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
10516 Opcode_ipf_Slot_inst_encode, 0, 0
10517};
10518
10519static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
10520 Opcode_ihi_Slot_inst_encode, 0, 0
10521};
10522
10523static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
10524 Opcode_ipfl_Slot_inst_encode, 0, 0
10525};
10526
10527static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
10528 Opcode_ihu_Slot_inst_encode, 0, 0
10529};
10530
10531static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
10532 Opcode_iiu_Slot_inst_encode, 0, 0
10533};
10534
10535static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
10536 Opcode_iii_Slot_inst_encode, 0, 0
10537};
10538
10539static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
10540 Opcode_lict_Slot_inst_encode, 0, 0
10541};
10542
10543static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
10544 Opcode_licw_Slot_inst_encode, 0, 0
10545};
10546
10547static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
10548 Opcode_sict_Slot_inst_encode, 0, 0
10549};
10550
10551static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
10552 Opcode_sicw_Slot_inst_encode, 0, 0
10553};
10554
10555static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
10556 Opcode_dhwb_Slot_inst_encode, 0, 0
10557};
10558
10559static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
10560 Opcode_dhwbi_Slot_inst_encode, 0, 0
10561};
10562
10563static xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = {
10564 Opcode_diwbui_p_Slot_inst_encode, 0, 0
10565};
10566
10567static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
10568 Opcode_diwb_Slot_inst_encode, 0, 0
10569};
10570
10571static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
10572 Opcode_diwbi_Slot_inst_encode, 0, 0
10573};
10574
10575static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
10576 Opcode_dhi_Slot_inst_encode, 0, 0
10577};
10578
10579static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
10580 Opcode_dii_Slot_inst_encode, 0, 0
10581};
10582
10583static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
10584 Opcode_dpfr_Slot_inst_encode, 0, 0
10585};
10586
10587static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
10588 Opcode_dpfw_Slot_inst_encode, 0, 0
10589};
10590
10591static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
10592 Opcode_dpfro_Slot_inst_encode, 0, 0
10593};
10594
10595static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
10596 Opcode_dpfwo_Slot_inst_encode, 0, 0
10597};
10598
10599static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
10600 Opcode_dpfl_Slot_inst_encode, 0, 0
10601};
10602
10603static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
10604 Opcode_dhu_Slot_inst_encode, 0, 0
10605};
10606
10607static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
10608 Opcode_diu_Slot_inst_encode, 0, 0
10609};
10610
10611static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
10612 Opcode_sdct_Slot_inst_encode, 0, 0
10613};
10614
10615static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
10616 Opcode_ldct_Slot_inst_encode, 0, 0
10617};
10618
10619static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
10620 Opcode_idtlb_Slot_inst_encode, 0, 0
10621};
10622
10623static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
10624 Opcode_pdtlb_Slot_inst_encode, 0, 0
10625};
10626
10627static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
10628 Opcode_rdtlb0_Slot_inst_encode, 0, 0
10629};
10630
10631static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
10632 Opcode_rdtlb1_Slot_inst_encode, 0, 0
10633};
10634
10635static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
10636 Opcode_wdtlb_Slot_inst_encode, 0, 0
10637};
10638
10639static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
10640 Opcode_iitlb_Slot_inst_encode, 0, 0
10641};
10642
10643static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
10644 Opcode_pitlb_Slot_inst_encode, 0, 0
10645};
10646
10647static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
10648 Opcode_ritlb0_Slot_inst_encode, 0, 0
10649};
10650
10651static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
10652 Opcode_ritlb1_Slot_inst_encode, 0, 0
10653};
10654
10655static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
10656 Opcode_witlb_Slot_inst_encode, 0, 0
10657};
10658
10659static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
10660 Opcode_clamps_Slot_inst_encode, 0, 0
10661};
10662
10663static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
10664 Opcode_min_Slot_inst_encode, 0, 0
10665};
10666
10667static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
10668 Opcode_max_Slot_inst_encode, 0, 0
10669};
10670
10671static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
10672 Opcode_minu_Slot_inst_encode, 0, 0
10673};
10674
10675static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
10676 Opcode_maxu_Slot_inst_encode, 0, 0
10677};
10678
10679static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
10680 Opcode_nsa_Slot_inst_encode, 0, 0
10681};
10682
10683static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
10684 Opcode_nsau_Slot_inst_encode, 0, 0
10685};
10686
10687static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
10688 Opcode_sext_Slot_inst_encode, 0, 0
10689};
10690
10691static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
10692 Opcode_l32ai_Slot_inst_encode, 0, 0
10693};
10694
10695static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
10696 Opcode_s32ri_Slot_inst_encode, 0, 0
10697};
10698
10699static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
10700 Opcode_s32c1i_Slot_inst_encode, 0, 0
10701};
10702
10703static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
10704 Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
10705};
10706
10707static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
10708 Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
10709};
10710
10711static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
10712 Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
10713};
10714
10715static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
10716 Opcode_rsr_atomctl_Slot_inst_encode, 0, 0
10717};
10718
10719static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
10720 Opcode_wsr_atomctl_Slot_inst_encode, 0, 0
10721};
10722
10723static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
10724 Opcode_xsr_atomctl_Slot_inst_encode, 0, 0
10725};
10726
10727static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
10728 Opcode_quou_Slot_inst_encode, 0, 0
10729};
10730
10731static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
10732 Opcode_quos_Slot_inst_encode, 0, 0
10733};
10734
10735static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
10736 Opcode_remu_Slot_inst_encode, 0, 0
10737};
10738
10739static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
10740 Opcode_rems_Slot_inst_encode, 0, 0
10741};
10742
10743static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
10744 Opcode_rer_Slot_inst_encode, 0, 0
10745};
10746
10747static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
10748 Opcode_wer_Slot_inst_encode, 0, 0
10749};
10750
10751static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = {
10752 Opcode_rur_expstate_Slot_inst_encode, 0, 0
10753};
10754
10755static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = {
10756 Opcode_wur_expstate_Slot_inst_encode, 0, 0
10757};
10758
10759static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = {
10760 Opcode_read_impwire_Slot_inst_encode, 0, 0
10761};
10762
10763static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = {
10764 Opcode_setb_expstate_Slot_inst_encode, 0, 0
10765};
10766
10767static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = {
10768 Opcode_clrb_expstate_Slot_inst_encode, 0, 0
10769};
10770
10771static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = {
10772 Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
10773};
10774
10775
10776
10777
10778\f
10779/* Opcode table. */
10780
10781static xtensa_opcode_internal opcodes[] = {
10782 { "excw", ICLASS_xt_iclass_excw,
10783 0,
10784 Opcode_excw_encode_fns, 0, 0 },
10785 { "rfe", ICLASS_xt_iclass_rfe,
10786 XTENSA_OPCODE_IS_JUMP,
10787 Opcode_rfe_encode_fns, 0, 0 },
10788 { "rfde", ICLASS_xt_iclass_rfde,
10789 XTENSA_OPCODE_IS_JUMP,
10790 Opcode_rfde_encode_fns, 0, 0 },
10791 { "syscall", ICLASS_xt_iclass_syscall,
10792 0,
10793 Opcode_syscall_encode_fns, 0, 0 },
10794 { "call12", ICLASS_xt_iclass_call12,
10795 XTENSA_OPCODE_IS_CALL,
10796 Opcode_call12_encode_fns, 0, 0 },
10797 { "call8", ICLASS_xt_iclass_call8,
10798 XTENSA_OPCODE_IS_CALL,
10799 Opcode_call8_encode_fns, 0, 0 },
10800 { "call4", ICLASS_xt_iclass_call4,
10801 XTENSA_OPCODE_IS_CALL,
10802 Opcode_call4_encode_fns, 0, 0 },
10803 { "callx12", ICLASS_xt_iclass_callx12,
10804 XTENSA_OPCODE_IS_CALL,
10805 Opcode_callx12_encode_fns, 0, 0 },
10806 { "callx8", ICLASS_xt_iclass_callx8,
10807 XTENSA_OPCODE_IS_CALL,
10808 Opcode_callx8_encode_fns, 0, 0 },
10809 { "callx4", ICLASS_xt_iclass_callx4,
10810 XTENSA_OPCODE_IS_CALL,
10811 Opcode_callx4_encode_fns, 0, 0 },
10812 { "entry", ICLASS_xt_iclass_entry,
10813 0,
10814 Opcode_entry_encode_fns, 0, 0 },
10815 { "movsp", ICLASS_xt_iclass_movsp,
10816 0,
10817 Opcode_movsp_encode_fns, 0, 0 },
10818 { "rotw", ICLASS_xt_iclass_rotw,
10819 0,
10820 Opcode_rotw_encode_fns, 0, 0 },
10821 { "retw", ICLASS_xt_iclass_retw,
10822 XTENSA_OPCODE_IS_JUMP,
10823 Opcode_retw_encode_fns, 0, 0 },
10824 { "retw.n", ICLASS_xt_iclass_retw,
10825 XTENSA_OPCODE_IS_JUMP,
10826 Opcode_retw_n_encode_fns, 0, 0 },
10827 { "rfwo", ICLASS_xt_iclass_rfwou,
10828 XTENSA_OPCODE_IS_JUMP,
10829 Opcode_rfwo_encode_fns, 0, 0 },
10830 { "rfwu", ICLASS_xt_iclass_rfwou,
10831 XTENSA_OPCODE_IS_JUMP,
10832 Opcode_rfwu_encode_fns, 0, 0 },
10833 { "l32e", ICLASS_xt_iclass_l32e,
10834 0,
10835 Opcode_l32e_encode_fns, 0, 0 },
10836 { "s32e", ICLASS_xt_iclass_s32e,
10837 0,
10838 Opcode_s32e_encode_fns, 0, 0 },
10839 { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
10840 0,
10841 Opcode_rsr_windowbase_encode_fns, 0, 0 },
10842 { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
10843 0,
10844 Opcode_wsr_windowbase_encode_fns, 0, 0 },
10845 { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
10846 0,
10847 Opcode_xsr_windowbase_encode_fns, 0, 0 },
10848 { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
10849 0,
10850 Opcode_rsr_windowstart_encode_fns, 0, 0 },
10851 { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
10852 0,
10853 Opcode_wsr_windowstart_encode_fns, 0, 0 },
10854 { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
10855 0,
10856 Opcode_xsr_windowstart_encode_fns, 0, 0 },
10857 { "add.n", ICLASS_xt_iclass_add_n,
10858 0,
10859 Opcode_add_n_encode_fns, 0, 0 },
10860 { "addi.n", ICLASS_xt_iclass_addi_n,
10861 0,
10862 Opcode_addi_n_encode_fns, 0, 0 },
10863 { "beqz.n", ICLASS_xt_iclass_bz6,
10864 XTENSA_OPCODE_IS_BRANCH,
10865 Opcode_beqz_n_encode_fns, 0, 0 },
10866 { "bnez.n", ICLASS_xt_iclass_bz6,
10867 XTENSA_OPCODE_IS_BRANCH,
10868 Opcode_bnez_n_encode_fns, 0, 0 },
10869 { "ill.n", ICLASS_xt_iclass_ill_n,
10870 0,
10871 Opcode_ill_n_encode_fns, 0, 0 },
10872 { "l32i.n", ICLASS_xt_iclass_loadi4,
10873 0,
10874 Opcode_l32i_n_encode_fns, 0, 0 },
10875 { "mov.n", ICLASS_xt_iclass_mov_n,
10876 0,
10877 Opcode_mov_n_encode_fns, 0, 0 },
10878 { "movi.n", ICLASS_xt_iclass_movi_n,
10879 0,
10880 Opcode_movi_n_encode_fns, 0, 0 },
10881 { "nop.n", ICLASS_xt_iclass_nopn,
10882 0,
10883 Opcode_nop_n_encode_fns, 0, 0 },
10884 { "ret.n", ICLASS_xt_iclass_retn,
10885 XTENSA_OPCODE_IS_JUMP,
10886 Opcode_ret_n_encode_fns, 0, 0 },
10887 { "s32i.n", ICLASS_xt_iclass_storei4,
10888 0,
10889 Opcode_s32i_n_encode_fns, 0, 0 },
10890 { "addi", ICLASS_xt_iclass_addi,
10891 0,
10892 Opcode_addi_encode_fns, 0, 0 },
10893 { "addmi", ICLASS_xt_iclass_addmi,
10894 0,
10895 Opcode_addmi_encode_fns, 0, 0 },
10896 { "add", ICLASS_xt_iclass_addsub,
10897 0,
10898 Opcode_add_encode_fns, 0, 0 },
10899 { "sub", ICLASS_xt_iclass_addsub,
10900 0,
10901 Opcode_sub_encode_fns, 0, 0 },
10902 { "addx2", ICLASS_xt_iclass_addsub,
10903 0,
10904 Opcode_addx2_encode_fns, 0, 0 },
10905 { "addx4", ICLASS_xt_iclass_addsub,
10906 0,
10907 Opcode_addx4_encode_fns, 0, 0 },
10908 { "addx8", ICLASS_xt_iclass_addsub,
10909 0,
10910 Opcode_addx8_encode_fns, 0, 0 },
10911 { "subx2", ICLASS_xt_iclass_addsub,
10912 0,
10913 Opcode_subx2_encode_fns, 0, 0 },
10914 { "subx4", ICLASS_xt_iclass_addsub,
10915 0,
10916 Opcode_subx4_encode_fns, 0, 0 },
10917 { "subx8", ICLASS_xt_iclass_addsub,
10918 0,
10919 Opcode_subx8_encode_fns, 0, 0 },
10920 { "and", ICLASS_xt_iclass_bit,
10921 0,
10922 Opcode_and_encode_fns, 0, 0 },
10923 { "or", ICLASS_xt_iclass_bit,
10924 0,
10925 Opcode_or_encode_fns, 0, 0 },
10926 { "xor", ICLASS_xt_iclass_bit,
10927 0,
10928 Opcode_xor_encode_fns, 0, 0 },
10929 { "beqi", ICLASS_xt_iclass_bsi8,
10930 XTENSA_OPCODE_IS_BRANCH,
10931 Opcode_beqi_encode_fns, 0, 0 },
10932 { "bnei", ICLASS_xt_iclass_bsi8,
10933 XTENSA_OPCODE_IS_BRANCH,
10934 Opcode_bnei_encode_fns, 0, 0 },
10935 { "bgei", ICLASS_xt_iclass_bsi8,
10936 XTENSA_OPCODE_IS_BRANCH,
10937 Opcode_bgei_encode_fns, 0, 0 },
10938 { "blti", ICLASS_xt_iclass_bsi8,
10939 XTENSA_OPCODE_IS_BRANCH,
10940 Opcode_blti_encode_fns, 0, 0 },
10941 { "bbci", ICLASS_xt_iclass_bsi8b,
10942 XTENSA_OPCODE_IS_BRANCH,
10943 Opcode_bbci_encode_fns, 0, 0 },
10944 { "bbsi", ICLASS_xt_iclass_bsi8b,
10945 XTENSA_OPCODE_IS_BRANCH,
10946 Opcode_bbsi_encode_fns, 0, 0 },
10947 { "bgeui", ICLASS_xt_iclass_bsi8u,
10948 XTENSA_OPCODE_IS_BRANCH,
10949 Opcode_bgeui_encode_fns, 0, 0 },
10950 { "bltui", ICLASS_xt_iclass_bsi8u,
10951 XTENSA_OPCODE_IS_BRANCH,
10952 Opcode_bltui_encode_fns, 0, 0 },
10953 { "beq", ICLASS_xt_iclass_bst8,
10954 XTENSA_OPCODE_IS_BRANCH,
10955 Opcode_beq_encode_fns, 0, 0 },
10956 { "bne", ICLASS_xt_iclass_bst8,
10957 XTENSA_OPCODE_IS_BRANCH,
10958 Opcode_bne_encode_fns, 0, 0 },
10959 { "bge", ICLASS_xt_iclass_bst8,
10960 XTENSA_OPCODE_IS_BRANCH,
10961 Opcode_bge_encode_fns, 0, 0 },
10962 { "blt", ICLASS_xt_iclass_bst8,
10963 XTENSA_OPCODE_IS_BRANCH,
10964 Opcode_blt_encode_fns, 0, 0 },
10965 { "bgeu", ICLASS_xt_iclass_bst8,
10966 XTENSA_OPCODE_IS_BRANCH,
10967 Opcode_bgeu_encode_fns, 0, 0 },
10968 { "bltu", ICLASS_xt_iclass_bst8,
10969 XTENSA_OPCODE_IS_BRANCH,
10970 Opcode_bltu_encode_fns, 0, 0 },
10971 { "bany", ICLASS_xt_iclass_bst8,
10972 XTENSA_OPCODE_IS_BRANCH,
10973 Opcode_bany_encode_fns, 0, 0 },
10974 { "bnone", ICLASS_xt_iclass_bst8,
10975 XTENSA_OPCODE_IS_BRANCH,
10976 Opcode_bnone_encode_fns, 0, 0 },
10977 { "ball", ICLASS_xt_iclass_bst8,
10978 XTENSA_OPCODE_IS_BRANCH,
10979 Opcode_ball_encode_fns, 0, 0 },
10980 { "bnall", ICLASS_xt_iclass_bst8,
10981 XTENSA_OPCODE_IS_BRANCH,
10982 Opcode_bnall_encode_fns, 0, 0 },
10983 { "bbc", ICLASS_xt_iclass_bst8,
10984 XTENSA_OPCODE_IS_BRANCH,
10985 Opcode_bbc_encode_fns, 0, 0 },
10986 { "bbs", ICLASS_xt_iclass_bst8,
10987 XTENSA_OPCODE_IS_BRANCH,
10988 Opcode_bbs_encode_fns, 0, 0 },
10989 { "beqz", ICLASS_xt_iclass_bsz12,
10990 XTENSA_OPCODE_IS_BRANCH,
10991 Opcode_beqz_encode_fns, 0, 0 },
10992 { "bnez", ICLASS_xt_iclass_bsz12,
10993 XTENSA_OPCODE_IS_BRANCH,
10994 Opcode_bnez_encode_fns, 0, 0 },
10995 { "bgez", ICLASS_xt_iclass_bsz12,
10996 XTENSA_OPCODE_IS_BRANCH,
10997 Opcode_bgez_encode_fns, 0, 0 },
10998 { "bltz", ICLASS_xt_iclass_bsz12,
10999 XTENSA_OPCODE_IS_BRANCH,
11000 Opcode_bltz_encode_fns, 0, 0 },
11001 { "call0", ICLASS_xt_iclass_call0,
11002 XTENSA_OPCODE_IS_CALL,
11003 Opcode_call0_encode_fns, 0, 0 },
11004 { "callx0", ICLASS_xt_iclass_callx0,
11005 XTENSA_OPCODE_IS_CALL,
11006 Opcode_callx0_encode_fns, 0, 0 },
11007 { "extui", ICLASS_xt_iclass_exti,
11008 0,
11009 Opcode_extui_encode_fns, 0, 0 },
11010 { "ill", ICLASS_xt_iclass_ill,
11011 0,
11012 Opcode_ill_encode_fns, 0, 0 },
11013 { "j", ICLASS_xt_iclass_jump,
11014 XTENSA_OPCODE_IS_JUMP,
11015 Opcode_j_encode_fns, 0, 0 },
11016 { "jx", ICLASS_xt_iclass_jumpx,
11017 XTENSA_OPCODE_IS_JUMP,
11018 Opcode_jx_encode_fns, 0, 0 },
11019 { "l16ui", ICLASS_xt_iclass_l16ui,
11020 0,
11021 Opcode_l16ui_encode_fns, 0, 0 },
11022 { "l16si", ICLASS_xt_iclass_l16si,
11023 0,
11024 Opcode_l16si_encode_fns, 0, 0 },
11025 { "l32i", ICLASS_xt_iclass_l32i,
11026 0,
11027 Opcode_l32i_encode_fns, 0, 0 },
11028 { "l32r", ICLASS_xt_iclass_l32r,
11029 0,
11030 Opcode_l32r_encode_fns, 0, 0 },
11031 { "l8ui", ICLASS_xt_iclass_l8i,
11032 0,
11033 Opcode_l8ui_encode_fns, 0, 0 },
11034 { "loop", ICLASS_xt_iclass_loop,
11035 XTENSA_OPCODE_IS_LOOP,
11036 Opcode_loop_encode_fns, 0, 0 },
11037 { "loopnez", ICLASS_xt_iclass_loopz,
11038 XTENSA_OPCODE_IS_LOOP,
11039 Opcode_loopnez_encode_fns, 0, 0 },
11040 { "loopgtz", ICLASS_xt_iclass_loopz,
11041 XTENSA_OPCODE_IS_LOOP,
11042 Opcode_loopgtz_encode_fns, 0, 0 },
11043 { "movi", ICLASS_xt_iclass_movi,
11044 0,
11045 Opcode_movi_encode_fns, 0, 0 },
11046 { "moveqz", ICLASS_xt_iclass_movz,
11047 0,
11048 Opcode_moveqz_encode_fns, 0, 0 },
11049 { "movnez", ICLASS_xt_iclass_movz,
11050 0,
11051 Opcode_movnez_encode_fns, 0, 0 },
11052 { "movltz", ICLASS_xt_iclass_movz,
11053 0,
11054 Opcode_movltz_encode_fns, 0, 0 },
11055 { "movgez", ICLASS_xt_iclass_movz,
11056 0,
11057 Opcode_movgez_encode_fns, 0, 0 },
11058 { "neg", ICLASS_xt_iclass_neg,
11059 0,
11060 Opcode_neg_encode_fns, 0, 0 },
11061 { "abs", ICLASS_xt_iclass_neg,
11062 0,
11063 Opcode_abs_encode_fns, 0, 0 },
11064 { "nop", ICLASS_xt_iclass_nop,
11065 0,
11066 Opcode_nop_encode_fns, 0, 0 },
11067 { "ret", ICLASS_xt_iclass_return,
11068 XTENSA_OPCODE_IS_JUMP,
11069 Opcode_ret_encode_fns, 0, 0 },
11070 { "simcall", ICLASS_xt_iclass_simcall,
11071 0,
11072 Opcode_simcall_encode_fns, 0, 0 },
11073 { "s16i", ICLASS_xt_iclass_s16i,
11074 0,
11075 Opcode_s16i_encode_fns, 0, 0 },
11076 { "s32i", ICLASS_xt_iclass_s32i,
11077 0,
11078 Opcode_s32i_encode_fns, 0, 0 },
11079 { "s32nb", ICLASS_xt_iclass_s32nb,
11080 0,
11081 Opcode_s32nb_encode_fns, 0, 0 },
11082 { "s8i", ICLASS_xt_iclass_s8i,
11083 0,
11084 Opcode_s8i_encode_fns, 0, 0 },
11085 { "ssr", ICLASS_xt_iclass_sar,
11086 0,
11087 Opcode_ssr_encode_fns, 0, 0 },
11088 { "ssl", ICLASS_xt_iclass_sar,
11089 0,
11090 Opcode_ssl_encode_fns, 0, 0 },
11091 { "ssa8l", ICLASS_xt_iclass_sar,
11092 0,
11093 Opcode_ssa8l_encode_fns, 0, 0 },
11094 { "ssa8b", ICLASS_xt_iclass_sar,
11095 0,
11096 Opcode_ssa8b_encode_fns, 0, 0 },
11097 { "ssai", ICLASS_xt_iclass_sari,
11098 0,
11099 Opcode_ssai_encode_fns, 0, 0 },
11100 { "sll", ICLASS_xt_iclass_shifts,
11101 0,
11102 Opcode_sll_encode_fns, 0, 0 },
11103 { "src", ICLASS_xt_iclass_shiftst,
11104 0,
11105 Opcode_src_encode_fns, 0, 0 },
11106 { "srl", ICLASS_xt_iclass_shiftt,
11107 0,
11108 Opcode_srl_encode_fns, 0, 0 },
11109 { "sra", ICLASS_xt_iclass_shiftt,
11110 0,
11111 Opcode_sra_encode_fns, 0, 0 },
11112 { "slli", ICLASS_xt_iclass_slli,
11113 0,
11114 Opcode_slli_encode_fns, 0, 0 },
11115 { "srai", ICLASS_xt_iclass_srai,
11116 0,
11117 Opcode_srai_encode_fns, 0, 0 },
11118 { "srli", ICLASS_xt_iclass_srli,
11119 0,
11120 Opcode_srli_encode_fns, 0, 0 },
11121 { "memw", ICLASS_xt_iclass_memw,
11122 0,
11123 Opcode_memw_encode_fns, 0, 0 },
11124 { "extw", ICLASS_xt_iclass_extw,
11125 0,
11126 Opcode_extw_encode_fns, 0, 0 },
11127 { "isync", ICLASS_xt_iclass_isync,
11128 0,
11129 Opcode_isync_encode_fns, 0, 0 },
11130 { "rsync", ICLASS_xt_iclass_sync,
11131 0,
11132 Opcode_rsync_encode_fns, 0, 0 },
11133 { "esync", ICLASS_xt_iclass_sync,
11134 0,
11135 Opcode_esync_encode_fns, 0, 0 },
11136 { "dsync", ICLASS_xt_iclass_sync,
11137 0,
11138 Opcode_dsync_encode_fns, 0, 0 },
11139 { "rsil", ICLASS_xt_iclass_rsil,
11140 0,
11141 Opcode_rsil_encode_fns, 0, 0 },
11142 { "rsr.lend", ICLASS_xt_iclass_rsr_lend,
11143 0,
11144 Opcode_rsr_lend_encode_fns, 0, 0 },
11145 { "wsr.lend", ICLASS_xt_iclass_wsr_lend,
11146 0,
11147 Opcode_wsr_lend_encode_fns, 0, 0 },
11148 { "xsr.lend", ICLASS_xt_iclass_xsr_lend,
11149 0,
11150 Opcode_xsr_lend_encode_fns, 0, 0 },
11151 { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount,
11152 0,
11153 Opcode_rsr_lcount_encode_fns, 0, 0 },
11154 { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount,
11155 0,
11156 Opcode_wsr_lcount_encode_fns, 0, 0 },
11157 { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount,
11158 0,
11159 Opcode_xsr_lcount_encode_fns, 0, 0 },
11160 { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg,
11161 0,
11162 Opcode_rsr_lbeg_encode_fns, 0, 0 },
11163 { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg,
11164 0,
11165 Opcode_wsr_lbeg_encode_fns, 0, 0 },
11166 { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg,
11167 0,
11168 Opcode_xsr_lbeg_encode_fns, 0, 0 },
11169 { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
11170 0,
11171 Opcode_rsr_sar_encode_fns, 0, 0 },
11172 { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
11173 0,
11174 Opcode_wsr_sar_encode_fns, 0, 0 },
11175 { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
11176 0,
11177 Opcode_xsr_sar_encode_fns, 0, 0 },
11178 { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl,
11179 0,
11180 Opcode_rsr_memctl_encode_fns, 0, 0 },
11181 { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl,
11182 0,
11183 Opcode_wsr_memctl_encode_fns, 0, 0 },
11184 { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl,
11185 0,
11186 Opcode_xsr_memctl_encode_fns, 0, 0 },
11187 { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
11188 0,
11189 Opcode_rsr_litbase_encode_fns, 0, 0 },
11190 { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
11191 0,
11192 Opcode_wsr_litbase_encode_fns, 0, 0 },
11193 { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
11194 0,
11195 Opcode_xsr_litbase_encode_fns, 0, 0 },
11196 { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0,
11197 0,
11198 Opcode_rsr_configid0_encode_fns, 0, 0 },
11199 { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0,
11200 0,
11201 Opcode_wsr_configid0_encode_fns, 0, 0 },
11202 { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1,
11203 0,
11204 Opcode_rsr_configid1_encode_fns, 0, 0 },
11205 { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
11206 0,
11207 Opcode_rsr_ps_encode_fns, 0, 0 },
11208 { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
11209 0,
11210 Opcode_wsr_ps_encode_fns, 0, 0 },
11211 { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
11212 0,
11213 Opcode_xsr_ps_encode_fns, 0, 0 },
11214 { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
11215 0,
11216 Opcode_rsr_epc1_encode_fns, 0, 0 },
11217 { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
11218 0,
11219 Opcode_wsr_epc1_encode_fns, 0, 0 },
11220 { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
11221 0,
11222 Opcode_xsr_epc1_encode_fns, 0, 0 },
11223 { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
11224 0,
11225 Opcode_rsr_excsave1_encode_fns, 0, 0 },
11226 { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
11227 0,
11228 Opcode_wsr_excsave1_encode_fns, 0, 0 },
11229 { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
11230 0,
11231 Opcode_xsr_excsave1_encode_fns, 0, 0 },
11232 { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
11233 0,
11234 Opcode_rsr_epc2_encode_fns, 0, 0 },
11235 { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
11236 0,
11237 Opcode_wsr_epc2_encode_fns, 0, 0 },
11238 { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
11239 0,
11240 Opcode_xsr_epc2_encode_fns, 0, 0 },
11241 { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
11242 0,
11243 Opcode_rsr_excsave2_encode_fns, 0, 0 },
11244 { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
11245 0,
11246 Opcode_wsr_excsave2_encode_fns, 0, 0 },
11247 { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
11248 0,
11249 Opcode_xsr_excsave2_encode_fns, 0, 0 },
11250 { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3,
11251 0,
11252 Opcode_rsr_epc3_encode_fns, 0, 0 },
11253 { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3,
11254 0,
11255 Opcode_wsr_epc3_encode_fns, 0, 0 },
11256 { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3,
11257 0,
11258 Opcode_xsr_epc3_encode_fns, 0, 0 },
11259 { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3,
11260 0,
11261 Opcode_rsr_excsave3_encode_fns, 0, 0 },
11262 { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3,
11263 0,
11264 Opcode_wsr_excsave3_encode_fns, 0, 0 },
11265 { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3,
11266 0,
11267 Opcode_xsr_excsave3_encode_fns, 0, 0 },
11268 { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4,
11269 0,
11270 Opcode_rsr_epc4_encode_fns, 0, 0 },
11271 { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4,
11272 0,
11273 Opcode_wsr_epc4_encode_fns, 0, 0 },
11274 { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4,
11275 0,
11276 Opcode_xsr_epc4_encode_fns, 0, 0 },
11277 { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4,
11278 0,
11279 Opcode_rsr_excsave4_encode_fns, 0, 0 },
11280 { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4,
11281 0,
11282 Opcode_wsr_excsave4_encode_fns, 0, 0 },
11283 { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4,
11284 0,
11285 Opcode_xsr_excsave4_encode_fns, 0, 0 },
11286 { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
11287 0,
11288 Opcode_rsr_epc5_encode_fns, 0, 0 },
11289 { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
11290 0,
11291 Opcode_wsr_epc5_encode_fns, 0, 0 },
11292 { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
11293 0,
11294 Opcode_xsr_epc5_encode_fns, 0, 0 },
11295 { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5,
11296 0,
11297 Opcode_rsr_excsave5_encode_fns, 0, 0 },
11298 { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5,
11299 0,
11300 Opcode_wsr_excsave5_encode_fns, 0, 0 },
11301 { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5,
11302 0,
11303 Opcode_xsr_excsave5_encode_fns, 0, 0 },
11304 { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6,
11305 0,
11306 Opcode_rsr_epc6_encode_fns, 0, 0 },
11307 { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6,
11308 0,
11309 Opcode_wsr_epc6_encode_fns, 0, 0 },
11310 { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6,
11311 0,
11312 Opcode_xsr_epc6_encode_fns, 0, 0 },
11313 { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6,
11314 0,
11315 Opcode_rsr_excsave6_encode_fns, 0, 0 },
11316 { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6,
11317 0,
11318 Opcode_wsr_excsave6_encode_fns, 0, 0 },
11319 { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6,
11320 0,
11321 Opcode_xsr_excsave6_encode_fns, 0, 0 },
11322 { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7,
11323 0,
11324 Opcode_rsr_epc7_encode_fns, 0, 0 },
11325 { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7,
11326 0,
11327 Opcode_wsr_epc7_encode_fns, 0, 0 },
11328 { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7,
11329 0,
11330 Opcode_xsr_epc7_encode_fns, 0, 0 },
11331 { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7,
11332 0,
11333 Opcode_rsr_excsave7_encode_fns, 0, 0 },
11334 { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7,
11335 0,
11336 Opcode_wsr_excsave7_encode_fns, 0, 0 },
11337 { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7,
11338 0,
11339 Opcode_xsr_excsave7_encode_fns, 0, 0 },
11340 { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
11341 0,
11342 Opcode_rsr_eps2_encode_fns, 0, 0 },
11343 { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
11344 0,
11345 Opcode_wsr_eps2_encode_fns, 0, 0 },
11346 { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
11347 0,
11348 Opcode_xsr_eps2_encode_fns, 0, 0 },
11349 { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3,
11350 0,
11351 Opcode_rsr_eps3_encode_fns, 0, 0 },
11352 { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3,
11353 0,
11354 Opcode_wsr_eps3_encode_fns, 0, 0 },
11355 { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3,
11356 0,
11357 Opcode_xsr_eps3_encode_fns, 0, 0 },
11358 { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4,
11359 0,
11360 Opcode_rsr_eps4_encode_fns, 0, 0 },
11361 { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4,
11362 0,
11363 Opcode_wsr_eps4_encode_fns, 0, 0 },
11364 { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4,
11365 0,
11366 Opcode_xsr_eps4_encode_fns, 0, 0 },
11367 { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5,
11368 0,
11369 Opcode_rsr_eps5_encode_fns, 0, 0 },
11370 { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5,
11371 0,
11372 Opcode_wsr_eps5_encode_fns, 0, 0 },
11373 { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5,
11374 0,
11375 Opcode_xsr_eps5_encode_fns, 0, 0 },
11376 { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6,
11377 0,
11378 Opcode_rsr_eps6_encode_fns, 0, 0 },
11379 { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6,
11380 0,
11381 Opcode_wsr_eps6_encode_fns, 0, 0 },
11382 { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6,
11383 0,
11384 Opcode_xsr_eps6_encode_fns, 0, 0 },
11385 { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7,
11386 0,
11387 Opcode_rsr_eps7_encode_fns, 0, 0 },
11388 { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7,
11389 0,
11390 Opcode_wsr_eps7_encode_fns, 0, 0 },
11391 { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7,
11392 0,
11393 Opcode_xsr_eps7_encode_fns, 0, 0 },
11394 { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
11395 0,
11396 Opcode_rsr_excvaddr_encode_fns, 0, 0 },
11397 { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
11398 0,
11399 Opcode_wsr_excvaddr_encode_fns, 0, 0 },
11400 { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
11401 0,
11402 Opcode_xsr_excvaddr_encode_fns, 0, 0 },
11403 { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
11404 0,
11405 Opcode_rsr_depc_encode_fns, 0, 0 },
11406 { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
11407 0,
11408 Opcode_wsr_depc_encode_fns, 0, 0 },
11409 { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
11410 0,
11411 Opcode_xsr_depc_encode_fns, 0, 0 },
11412 { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
11413 0,
11414 Opcode_rsr_exccause_encode_fns, 0, 0 },
11415 { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
11416 0,
11417 Opcode_wsr_exccause_encode_fns, 0, 0 },
11418 { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
11419 0,
11420 Opcode_xsr_exccause_encode_fns, 0, 0 },
11421 { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
11422 0,
11423 Opcode_rsr_misc0_encode_fns, 0, 0 },
11424 { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
11425 0,
11426 Opcode_wsr_misc0_encode_fns, 0, 0 },
11427 { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
11428 0,
11429 Opcode_xsr_misc0_encode_fns, 0, 0 },
11430 { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
11431 0,
11432 Opcode_rsr_misc1_encode_fns, 0, 0 },
11433 { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
11434 0,
11435 Opcode_wsr_misc1_encode_fns, 0, 0 },
11436 { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
11437 0,
11438 Opcode_xsr_misc1_encode_fns, 0, 0 },
11439 { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
11440 0,
11441 Opcode_rsr_prid_encode_fns, 0, 0 },
11442 { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
11443 0,
11444 Opcode_rsr_vecbase_encode_fns, 0, 0 },
11445 { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
11446 0,
11447 Opcode_wsr_vecbase_encode_fns, 0, 0 },
11448 { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
11449 0,
11450 Opcode_xsr_vecbase_encode_fns, 0, 0 },
11451 { "mul16u", ICLASS_xt_mul16,
11452 0,
11453 Opcode_mul16u_encode_fns, 0, 0 },
11454 { "mul16s", ICLASS_xt_mul16,
11455 0,
11456 Opcode_mul16s_encode_fns, 0, 0 },
11457 { "mull", ICLASS_xt_mul32,
11458 0,
11459 Opcode_mull_encode_fns, 0, 0 },
11460 { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa,
11461 0,
11462 Opcode_mul_aa_ll_encode_fns, 0, 0 },
11463 { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa,
11464 0,
11465 Opcode_mul_aa_hl_encode_fns, 0, 0 },
11466 { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa,
11467 0,
11468 Opcode_mul_aa_lh_encode_fns, 0, 0 },
11469 { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa,
11470 0,
11471 Opcode_mul_aa_hh_encode_fns, 0, 0 },
11472 { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa,
11473 0,
11474 Opcode_umul_aa_ll_encode_fns, 0, 0 },
11475 { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa,
11476 0,
11477 Opcode_umul_aa_hl_encode_fns, 0, 0 },
11478 { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa,
11479 0,
11480 Opcode_umul_aa_lh_encode_fns, 0, 0 },
11481 { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa,
11482 0,
11483 Opcode_umul_aa_hh_encode_fns, 0, 0 },
11484 { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad,
11485 0,
11486 Opcode_mul_ad_ll_encode_fns, 0, 0 },
11487 { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad,
11488 0,
11489 Opcode_mul_ad_hl_encode_fns, 0, 0 },
11490 { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad,
11491 0,
11492 Opcode_mul_ad_lh_encode_fns, 0, 0 },
11493 { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad,
11494 0,
11495 Opcode_mul_ad_hh_encode_fns, 0, 0 },
11496 { "mul.da.ll", ICLASS_xt_iclass_mac16_da,
11497 0,
11498 Opcode_mul_da_ll_encode_fns, 0, 0 },
11499 { "mul.da.hl", ICLASS_xt_iclass_mac16_da,
11500 0,
11501 Opcode_mul_da_hl_encode_fns, 0, 0 },
11502 { "mul.da.lh", ICLASS_xt_iclass_mac16_da,
11503 0,
11504 Opcode_mul_da_lh_encode_fns, 0, 0 },
11505 { "mul.da.hh", ICLASS_xt_iclass_mac16_da,
11506 0,
11507 Opcode_mul_da_hh_encode_fns, 0, 0 },
11508 { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd,
11509 0,
11510 Opcode_mul_dd_ll_encode_fns, 0, 0 },
11511 { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd,
11512 0,
11513 Opcode_mul_dd_hl_encode_fns, 0, 0 },
11514 { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd,
11515 0,
11516 Opcode_mul_dd_lh_encode_fns, 0, 0 },
11517 { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd,
11518 0,
11519 Opcode_mul_dd_hh_encode_fns, 0, 0 },
11520 { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa,
11521 0,
11522 Opcode_mula_aa_ll_encode_fns, 0, 0 },
11523 { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa,
11524 0,
11525 Opcode_mula_aa_hl_encode_fns, 0, 0 },
11526 { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa,
11527 0,
11528 Opcode_mula_aa_lh_encode_fns, 0, 0 },
11529 { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa,
11530 0,
11531 Opcode_mula_aa_hh_encode_fns, 0, 0 },
11532 { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa,
11533 0,
11534 Opcode_muls_aa_ll_encode_fns, 0, 0 },
11535 { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa,
11536 0,
11537 Opcode_muls_aa_hl_encode_fns, 0, 0 },
11538 { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa,
11539 0,
11540 Opcode_muls_aa_lh_encode_fns, 0, 0 },
11541 { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa,
11542 0,
11543 Opcode_muls_aa_hh_encode_fns, 0, 0 },
11544 { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad,
11545 0,
11546 Opcode_mula_ad_ll_encode_fns, 0, 0 },
11547 { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad,
11548 0,
11549 Opcode_mula_ad_hl_encode_fns, 0, 0 },
11550 { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad,
11551 0,
11552 Opcode_mula_ad_lh_encode_fns, 0, 0 },
11553 { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad,
11554 0,
11555 Opcode_mula_ad_hh_encode_fns, 0, 0 },
11556 { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad,
11557 0,
11558 Opcode_muls_ad_ll_encode_fns, 0, 0 },
11559 { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad,
11560 0,
11561 Opcode_muls_ad_hl_encode_fns, 0, 0 },
11562 { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad,
11563 0,
11564 Opcode_muls_ad_lh_encode_fns, 0, 0 },
11565 { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad,
11566 0,
11567 Opcode_muls_ad_hh_encode_fns, 0, 0 },
11568 { "mula.da.ll", ICLASS_xt_iclass_mac16a_da,
11569 0,
11570 Opcode_mula_da_ll_encode_fns, 0, 0 },
11571 { "mula.da.hl", ICLASS_xt_iclass_mac16a_da,
11572 0,
11573 Opcode_mula_da_hl_encode_fns, 0, 0 },
11574 { "mula.da.lh", ICLASS_xt_iclass_mac16a_da,
11575 0,
11576 Opcode_mula_da_lh_encode_fns, 0, 0 },
11577 { "mula.da.hh", ICLASS_xt_iclass_mac16a_da,
11578 0,
11579 Opcode_mula_da_hh_encode_fns, 0, 0 },
11580 { "muls.da.ll", ICLASS_xt_iclass_mac16a_da,
11581 0,
11582 Opcode_muls_da_ll_encode_fns, 0, 0 },
11583 { "muls.da.hl", ICLASS_xt_iclass_mac16a_da,
11584 0,
11585 Opcode_muls_da_hl_encode_fns, 0, 0 },
11586 { "muls.da.lh", ICLASS_xt_iclass_mac16a_da,
11587 0,
11588 Opcode_muls_da_lh_encode_fns, 0, 0 },
11589 { "muls.da.hh", ICLASS_xt_iclass_mac16a_da,
11590 0,
11591 Opcode_muls_da_hh_encode_fns, 0, 0 },
11592 { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd,
11593 0,
11594 Opcode_mula_dd_ll_encode_fns, 0, 0 },
11595 { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd,
11596 0,
11597 Opcode_mula_dd_hl_encode_fns, 0, 0 },
11598 { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd,
11599 0,
11600 Opcode_mula_dd_lh_encode_fns, 0, 0 },
11601 { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd,
11602 0,
11603 Opcode_mula_dd_hh_encode_fns, 0, 0 },
11604 { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd,
11605 0,
11606 Opcode_muls_dd_ll_encode_fns, 0, 0 },
11607 { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd,
11608 0,
11609 Opcode_muls_dd_hl_encode_fns, 0, 0 },
11610 { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd,
11611 0,
11612 Opcode_muls_dd_lh_encode_fns, 0, 0 },
11613 { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd,
11614 0,
11615 Opcode_muls_dd_hh_encode_fns, 0, 0 },
11616 { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da,
11617 0,
11618 Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
11619 { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da,
11620 0,
11621 Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
11622 { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da,
11623 0,
11624 Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
11625 { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da,
11626 0,
11627 Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
11628 { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da,
11629 0,
11630 Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
11631 { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da,
11632 0,
11633 Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
11634 { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da,
11635 0,
11636 Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
11637 { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da,
11638 0,
11639 Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
11640 { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd,
11641 0,
11642 Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
11643 { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd,
11644 0,
11645 Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
11646 { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd,
11647 0,
11648 Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
11649 { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd,
11650 0,
11651 Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
11652 { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd,
11653 0,
11654 Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
11655 { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd,
11656 0,
11657 Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
11658 { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd,
11659 0,
11660 Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
11661 { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd,
11662 0,
11663 Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
11664 { "lddec", ICLASS_xt_iclass_mac16_l,
11665 0,
11666 Opcode_lddec_encode_fns, 0, 0 },
11667 { "ldinc", ICLASS_xt_iclass_mac16_l,
11668 0,
11669 Opcode_ldinc_encode_fns, 0, 0 },
11670 { "rsr.m0", ICLASS_xt_iclass_rsr_m0,
11671 0,
11672 Opcode_rsr_m0_encode_fns, 0, 0 },
11673 { "wsr.m0", ICLASS_xt_iclass_wsr_m0,
11674 0,
11675 Opcode_wsr_m0_encode_fns, 0, 0 },
11676 { "xsr.m0", ICLASS_xt_iclass_xsr_m0,
11677 0,
11678 Opcode_xsr_m0_encode_fns, 0, 0 },
11679 { "rsr.m1", ICLASS_xt_iclass_rsr_m1,
11680 0,
11681 Opcode_rsr_m1_encode_fns, 0, 0 },
11682 { "wsr.m1", ICLASS_xt_iclass_wsr_m1,
11683 0,
11684 Opcode_wsr_m1_encode_fns, 0, 0 },
11685 { "xsr.m1", ICLASS_xt_iclass_xsr_m1,
11686 0,
11687 Opcode_xsr_m1_encode_fns, 0, 0 },
11688 { "rsr.m2", ICLASS_xt_iclass_rsr_m2,
11689 0,
11690 Opcode_rsr_m2_encode_fns, 0, 0 },
11691 { "wsr.m2", ICLASS_xt_iclass_wsr_m2,
11692 0,
11693 Opcode_wsr_m2_encode_fns, 0, 0 },
11694 { "xsr.m2", ICLASS_xt_iclass_xsr_m2,
11695 0,
11696 Opcode_xsr_m2_encode_fns, 0, 0 },
11697 { "rsr.m3", ICLASS_xt_iclass_rsr_m3,
11698 0,
11699 Opcode_rsr_m3_encode_fns, 0, 0 },
11700 { "wsr.m3", ICLASS_xt_iclass_wsr_m3,
11701 0,
11702 Opcode_wsr_m3_encode_fns, 0, 0 },
11703 { "xsr.m3", ICLASS_xt_iclass_xsr_m3,
11704 0,
11705 Opcode_xsr_m3_encode_fns, 0, 0 },
11706 { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo,
11707 0,
11708 Opcode_rsr_acclo_encode_fns, 0, 0 },
11709 { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo,
11710 0,
11711 Opcode_wsr_acclo_encode_fns, 0, 0 },
11712 { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo,
11713 0,
11714 Opcode_xsr_acclo_encode_fns, 0, 0 },
11715 { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi,
11716 0,
11717 Opcode_rsr_acchi_encode_fns, 0, 0 },
11718 { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi,
11719 0,
11720 Opcode_wsr_acchi_encode_fns, 0, 0 },
11721 { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi,
11722 0,
11723 Opcode_xsr_acchi_encode_fns, 0, 0 },
11724 { "rfi", ICLASS_xt_iclass_rfi,
11725 XTENSA_OPCODE_IS_JUMP,
11726 Opcode_rfi_encode_fns, 0, 0 },
11727 { "waiti", ICLASS_xt_iclass_wait,
11728 0,
11729 Opcode_waiti_encode_fns, 0, 0 },
11730 { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
11731 0,
11732 Opcode_rsr_interrupt_encode_fns, 0, 0 },
11733 { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
11734 0,
11735 Opcode_wsr_intset_encode_fns, 0, 0 },
11736 { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
11737 0,
11738 Opcode_wsr_intclear_encode_fns, 0, 0 },
11739 { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
11740 0,
11741 Opcode_rsr_intenable_encode_fns, 0, 0 },
11742 { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
11743 0,
11744 Opcode_wsr_intenable_encode_fns, 0, 0 },
11745 { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
11746 0,
11747 Opcode_xsr_intenable_encode_fns, 0, 0 },
11748 { "break", ICLASS_xt_iclass_break,
11749 0,
11750 Opcode_break_encode_fns, 0, 0 },
11751 { "break.n", ICLASS_xt_iclass_break_n,
11752 0,
11753 Opcode_break_n_encode_fns, 0, 0 },
11754 { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0,
11755 0,
11756 Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
11757 { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0,
11758 0,
11759 Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
11760 { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0,
11761 0,
11762 Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
11763 { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0,
11764 0,
11765 Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
11766 { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0,
11767 0,
11768 Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
11769 { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0,
11770 0,
11771 Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
11772 { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1,
11773 0,
11774 Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
11775 { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1,
11776 0,
11777 Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
11778 { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1,
11779 0,
11780 Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
11781 { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1,
11782 0,
11783 Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
11784 { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1,
11785 0,
11786 Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
11787 { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1,
11788 0,
11789 Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
11790 { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0,
11791 0,
11792 Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
11793 { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0,
11794 0,
11795 Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
11796 { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0,
11797 0,
11798 Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
11799 { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1,
11800 0,
11801 Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
11802 { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1,
11803 0,
11804 Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
11805 { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1,
11806 0,
11807 Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
11808 { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable,
11809 0,
11810 Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
11811 { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable,
11812 0,
11813 Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
11814 { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable,
11815 0,
11816 Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
11817 { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
11818 0,
11819 Opcode_rsr_debugcause_encode_fns, 0, 0 },
11820 { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
11821 0,
11822 Opcode_wsr_debugcause_encode_fns, 0, 0 },
11823 { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
11824 0,
11825 Opcode_xsr_debugcause_encode_fns, 0, 0 },
11826 { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
11827 0,
11828 Opcode_rsr_icount_encode_fns, 0, 0 },
11829 { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
11830 0,
11831 Opcode_wsr_icount_encode_fns, 0, 0 },
11832 { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
11833 0,
11834 Opcode_xsr_icount_encode_fns, 0, 0 },
11835 { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
11836 0,
11837 Opcode_rsr_icountlevel_encode_fns, 0, 0 },
11838 { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
11839 0,
11840 Opcode_wsr_icountlevel_encode_fns, 0, 0 },
11841 { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
11842 0,
11843 Opcode_xsr_icountlevel_encode_fns, 0, 0 },
11844 { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
11845 0,
11846 Opcode_rsr_ddr_encode_fns, 0, 0 },
11847 { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
11848 0,
11849 Opcode_wsr_ddr_encode_fns, 0, 0 },
11850 { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
11851 0,
11852 Opcode_xsr_ddr_encode_fns, 0, 0 },
11853 { "lddr32.p", ICLASS_xt_iclass_lddr32_p,
11854 0,
11855 Opcode_lddr32_p_encode_fns, 0, 0 },
11856 { "sddr32.p", ICLASS_xt_iclass_sddr32_p,
11857 0,
11858 Opcode_sddr32_p_encode_fns, 0, 0 },
11859 { "rfdo", ICLASS_xt_iclass_rfdo,
11860 XTENSA_OPCODE_IS_JUMP,
11861 Opcode_rfdo_encode_fns, 0, 0 },
11862 { "rfdd", ICLASS_xt_iclass_rfdd,
11863 XTENSA_OPCODE_IS_JUMP,
11864 Opcode_rfdd_encode_fns, 0, 0 },
11865 { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid,
11866 0,
11867 Opcode_wsr_mmid_encode_fns, 0, 0 },
11868 { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
11869 0,
11870 Opcode_rsr_ccount_encode_fns, 0, 0 },
11871 { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
11872 0,
11873 Opcode_wsr_ccount_encode_fns, 0, 0 },
11874 { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
11875 0,
11876 Opcode_xsr_ccount_encode_fns, 0, 0 },
11877 { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
11878 0,
11879 Opcode_rsr_ccompare0_encode_fns, 0, 0 },
11880 { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
11881 0,
11882 Opcode_wsr_ccompare0_encode_fns, 0, 0 },
11883 { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
11884 0,
11885 Opcode_xsr_ccompare0_encode_fns, 0, 0 },
11886 { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
11887 0,
11888 Opcode_rsr_ccompare1_encode_fns, 0, 0 },
11889 { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
11890 0,
11891 Opcode_wsr_ccompare1_encode_fns, 0, 0 },
11892 { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
11893 0,
11894 Opcode_xsr_ccompare1_encode_fns, 0, 0 },
11895 { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2,
11896 0,
11897 Opcode_rsr_ccompare2_encode_fns, 0, 0 },
11898 { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2,
11899 0,
11900 Opcode_wsr_ccompare2_encode_fns, 0, 0 },
11901 { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2,
11902 0,
11903 Opcode_xsr_ccompare2_encode_fns, 0, 0 },
11904 { "ipf", ICLASS_xt_iclass_icache,
11905 0,
11906 Opcode_ipf_encode_fns, 0, 0 },
11907 { "ihi", ICLASS_xt_iclass_icache,
11908 0,
11909 Opcode_ihi_encode_fns, 0, 0 },
11910 { "ipfl", ICLASS_xt_iclass_icache_lock,
11911 0,
11912 Opcode_ipfl_encode_fns, 0, 0 },
11913 { "ihu", ICLASS_xt_iclass_icache_lock,
11914 0,
11915 Opcode_ihu_encode_fns, 0, 0 },
11916 { "iiu", ICLASS_xt_iclass_icache_lock,
11917 0,
11918 Opcode_iiu_encode_fns, 0, 0 },
11919 { "iii", ICLASS_xt_iclass_icache_inv,
11920 0,
11921 Opcode_iii_encode_fns, 0, 0 },
11922 { "lict", ICLASS_xt_iclass_licx,
11923 0,
11924 Opcode_lict_encode_fns, 0, 0 },
11925 { "licw", ICLASS_xt_iclass_licx,
11926 0,
11927 Opcode_licw_encode_fns, 0, 0 },
11928 { "sict", ICLASS_xt_iclass_sicx,
11929 0,
11930 Opcode_sict_encode_fns, 0, 0 },
11931 { "sicw", ICLASS_xt_iclass_sicx,
11932 0,
11933 Opcode_sicw_encode_fns, 0, 0 },
11934 { "dhwb", ICLASS_xt_iclass_dcache,
11935 0,
11936 Opcode_dhwb_encode_fns, 0, 0 },
11937 { "dhwbi", ICLASS_xt_iclass_dcache,
11938 0,
11939 Opcode_dhwbi_encode_fns, 0, 0 },
11940 { "diwbui.p", ICLASS_xt_iclass_dcache_dyn,
11941 0,
11942 Opcode_diwbui_p_encode_fns, 0, 0 },
11943 { "diwb", ICLASS_xt_iclass_dcache_ind,
11944 0,
11945 Opcode_diwb_encode_fns, 0, 0 },
11946 { "diwbi", ICLASS_xt_iclass_dcache_ind,
11947 0,
11948 Opcode_diwbi_encode_fns, 0, 0 },
11949 { "dhi", ICLASS_xt_iclass_dcache_inv,
11950 0,
11951 Opcode_dhi_encode_fns, 0, 0 },
11952 { "dii", ICLASS_xt_iclass_dcache_inv,
11953 0,
11954 Opcode_dii_encode_fns, 0, 0 },
11955 { "dpfr", ICLASS_xt_iclass_dpf,
11956 0,
11957 Opcode_dpfr_encode_fns, 0, 0 },
11958 { "dpfw", ICLASS_xt_iclass_dpf,
11959 0,
11960 Opcode_dpfw_encode_fns, 0, 0 },
11961 { "dpfro", ICLASS_xt_iclass_dpf,
11962 0,
11963 Opcode_dpfro_encode_fns, 0, 0 },
11964 { "dpfwo", ICLASS_xt_iclass_dpf,
11965 0,
11966 Opcode_dpfwo_encode_fns, 0, 0 },
11967 { "dpfl", ICLASS_xt_iclass_dcache_lock,
11968 0,
11969 Opcode_dpfl_encode_fns, 0, 0 },
11970 { "dhu", ICLASS_xt_iclass_dcache_lock,
11971 0,
11972 Opcode_dhu_encode_fns, 0, 0 },
11973 { "diu", ICLASS_xt_iclass_dcache_lock,
11974 0,
11975 Opcode_diu_encode_fns, 0, 0 },
11976 { "sdct", ICLASS_xt_iclass_sdct,
11977 0,
11978 Opcode_sdct_encode_fns, 0, 0 },
11979 { "ldct", ICLASS_xt_iclass_ldct,
11980 0,
11981 Opcode_ldct_encode_fns, 0, 0 },
11982 { "idtlb", ICLASS_xt_iclass_idtlb,
11983 0,
11984 Opcode_idtlb_encode_fns, 0, 0 },
11985 { "pdtlb", ICLASS_xt_iclass_rdtlb,
11986 0,
11987 Opcode_pdtlb_encode_fns, 0, 0 },
11988 { "rdtlb0", ICLASS_xt_iclass_rdtlb,
11989 0,
11990 Opcode_rdtlb0_encode_fns, 0, 0 },
11991 { "rdtlb1", ICLASS_xt_iclass_rdtlb,
11992 0,
11993 Opcode_rdtlb1_encode_fns, 0, 0 },
11994 { "wdtlb", ICLASS_xt_iclass_wdtlb,
11995 0,
11996 Opcode_wdtlb_encode_fns, 0, 0 },
11997 { "iitlb", ICLASS_xt_iclass_iitlb,
11998 0,
11999 Opcode_iitlb_encode_fns, 0, 0 },
12000 { "pitlb", ICLASS_xt_iclass_ritlb,
12001 0,
12002 Opcode_pitlb_encode_fns, 0, 0 },
12003 { "ritlb0", ICLASS_xt_iclass_ritlb,
12004 0,
12005 Opcode_ritlb0_encode_fns, 0, 0 },
12006 { "ritlb1", ICLASS_xt_iclass_ritlb,
12007 0,
12008 Opcode_ritlb1_encode_fns, 0, 0 },
12009 { "witlb", ICLASS_xt_iclass_witlb,
12010 0,
12011 Opcode_witlb_encode_fns, 0, 0 },
12012 { "clamps", ICLASS_xt_iclass_clamp,
12013 0,
12014 Opcode_clamps_encode_fns, 0, 0 },
12015 { "min", ICLASS_xt_iclass_minmax,
12016 0,
12017 Opcode_min_encode_fns, 0, 0 },
12018 { "max", ICLASS_xt_iclass_minmax,
12019 0,
12020 Opcode_max_encode_fns, 0, 0 },
12021 { "minu", ICLASS_xt_iclass_minmax,
12022 0,
12023 Opcode_minu_encode_fns, 0, 0 },
12024 { "maxu", ICLASS_xt_iclass_minmax,
12025 0,
12026 Opcode_maxu_encode_fns, 0, 0 },
12027 { "nsa", ICLASS_xt_iclass_nsa,
12028 0,
12029 Opcode_nsa_encode_fns, 0, 0 },
12030 { "nsau", ICLASS_xt_iclass_nsa,
12031 0,
12032 Opcode_nsau_encode_fns, 0, 0 },
12033 { "sext", ICLASS_xt_iclass_sx,
12034 0,
12035 Opcode_sext_encode_fns, 0, 0 },
12036 { "l32ai", ICLASS_xt_iclass_l32ai,
12037 0,
12038 Opcode_l32ai_encode_fns, 0, 0 },
12039 { "s32ri", ICLASS_xt_iclass_s32ri,
12040 0,
12041 Opcode_s32ri_encode_fns, 0, 0 },
12042 { "s32c1i", ICLASS_xt_iclass_s32c1i,
12043 0,
12044 Opcode_s32c1i_encode_fns, 0, 0 },
12045 { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
12046 0,
12047 Opcode_rsr_scompare1_encode_fns, 0, 0 },
12048 { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
12049 0,
12050 Opcode_wsr_scompare1_encode_fns, 0, 0 },
12051 { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
12052 0,
12053 Opcode_xsr_scompare1_encode_fns, 0, 0 },
12054 { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl,
12055 0,
12056 Opcode_rsr_atomctl_encode_fns, 0, 0 },
12057 { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl,
12058 0,
12059 Opcode_wsr_atomctl_encode_fns, 0, 0 },
12060 { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl,
12061 0,
12062 Opcode_xsr_atomctl_encode_fns, 0, 0 },
12063 { "quou", ICLASS_xt_iclass_div,
12064 0,
12065 Opcode_quou_encode_fns, 0, 0 },
12066 { "quos", ICLASS_xt_iclass_div,
12067 0,
12068 Opcode_quos_encode_fns, 0, 0 },
12069 { "remu", ICLASS_xt_iclass_div,
12070 0,
12071 Opcode_remu_encode_fns, 0, 0 },
12072 { "rems", ICLASS_xt_iclass_div,
12073 0,
12074 Opcode_rems_encode_fns, 0, 0 },
12075 { "rer", ICLASS_xt_iclass_rer,
12076 0,
12077 Opcode_rer_encode_fns, 0, 0 },
12078 { "wer", ICLASS_xt_iclass_wer,
12079 0,
12080 Opcode_wer_encode_fns, 0, 0 },
12081 { "rur.expstate", ICLASS_rur_expstate,
12082 0,
12083 Opcode_rur_expstate_encode_fns, 0, 0 },
12084 { "wur.expstate", ICLASS_wur_expstate,
12085 0,
12086 Opcode_wur_expstate_encode_fns, 0, 0 },
12087 { "read_impwire", ICLASS_iclass_READ_IMPWIRE,
12088 0,
12089 Opcode_read_impwire_encode_fns, 0, 0 },
12090 { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE,
12091 0,
12092 Opcode_setb_expstate_encode_fns, 0, 0 },
12093 { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE,
12094 0,
12095 Opcode_clrb_expstate_encode_fns, 0, 0 },
12096 { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE,
12097 0,
12098 Opcode_wrmsk_expstate_encode_fns, 0, 0 }
12099};
12100
12101enum xtensa_opcode_id {
12102 OPCODE_EXCW,
12103 OPCODE_RFE,
12104 OPCODE_RFDE,
12105 OPCODE_SYSCALL,
12106 OPCODE_CALL12,
12107 OPCODE_CALL8,
12108 OPCODE_CALL4,
12109 OPCODE_CALLX12,
12110 OPCODE_CALLX8,
12111 OPCODE_CALLX4,
12112 OPCODE_ENTRY,
12113 OPCODE_MOVSP,
12114 OPCODE_ROTW,
12115 OPCODE_RETW,
12116 OPCODE_RETW_N,
12117 OPCODE_RFWO,
12118 OPCODE_RFWU,
12119 OPCODE_L32E,
12120 OPCODE_S32E,
12121 OPCODE_RSR_WINDOWBASE,
12122 OPCODE_WSR_WINDOWBASE,
12123 OPCODE_XSR_WINDOWBASE,
12124 OPCODE_RSR_WINDOWSTART,
12125 OPCODE_WSR_WINDOWSTART,
12126 OPCODE_XSR_WINDOWSTART,
12127 OPCODE_ADD_N,
12128 OPCODE_ADDI_N,
12129 OPCODE_BEQZ_N,
12130 OPCODE_BNEZ_N,
12131 OPCODE_ILL_N,
12132 OPCODE_L32I_N,
12133 OPCODE_MOV_N,
12134 OPCODE_MOVI_N,
12135 OPCODE_NOP_N,
12136 OPCODE_RET_N,
12137 OPCODE_S32I_N,
12138 OPCODE_ADDI,
12139 OPCODE_ADDMI,
12140 OPCODE_ADD,
12141 OPCODE_SUB,
12142 OPCODE_ADDX2,
12143 OPCODE_ADDX4,
12144 OPCODE_ADDX8,
12145 OPCODE_SUBX2,
12146 OPCODE_SUBX4,
12147 OPCODE_SUBX8,
12148 OPCODE_AND,
12149 OPCODE_OR,
12150 OPCODE_XOR,
12151 OPCODE_BEQI,
12152 OPCODE_BNEI,
12153 OPCODE_BGEI,
12154 OPCODE_BLTI,
12155 OPCODE_BBCI,
12156 OPCODE_BBSI,
12157 OPCODE_BGEUI,
12158 OPCODE_BLTUI,
12159 OPCODE_BEQ,
12160 OPCODE_BNE,
12161 OPCODE_BGE,
12162 OPCODE_BLT,
12163 OPCODE_BGEU,
12164 OPCODE_BLTU,
12165 OPCODE_BANY,
12166 OPCODE_BNONE,
12167 OPCODE_BALL,
12168 OPCODE_BNALL,
12169 OPCODE_BBC,
12170 OPCODE_BBS,
12171 OPCODE_BEQZ,
12172 OPCODE_BNEZ,
12173 OPCODE_BGEZ,
12174 OPCODE_BLTZ,
12175 OPCODE_CALL0,
12176 OPCODE_CALLX0,
12177 OPCODE_EXTUI,
12178 OPCODE_ILL,
12179 OPCODE_J,
12180 OPCODE_JX,
12181 OPCODE_L16UI,
12182 OPCODE_L16SI,
12183 OPCODE_L32I,
12184 OPCODE_L32R,
12185 OPCODE_L8UI,
12186 OPCODE_LOOP,
12187 OPCODE_LOOPNEZ,
12188 OPCODE_LOOPGTZ,
12189 OPCODE_MOVI,
12190 OPCODE_MOVEQZ,
12191 OPCODE_MOVNEZ,
12192 OPCODE_MOVLTZ,
12193 OPCODE_MOVGEZ,
12194 OPCODE_NEG,
12195 OPCODE_ABS,
12196 OPCODE_NOP,
12197 OPCODE_RET,
12198 OPCODE_SIMCALL,
12199 OPCODE_S16I,
12200 OPCODE_S32I,
12201 OPCODE_S32NB,
12202 OPCODE_S8I,
12203 OPCODE_SSR,
12204 OPCODE_SSL,
12205 OPCODE_SSA8L,
12206 OPCODE_SSA8B,
12207 OPCODE_SSAI,
12208 OPCODE_SLL,
12209 OPCODE_SRC,
12210 OPCODE_SRL,
12211 OPCODE_SRA,
12212 OPCODE_SLLI,
12213 OPCODE_SRAI,
12214 OPCODE_SRLI,
12215 OPCODE_MEMW,
12216 OPCODE_EXTW,
12217 OPCODE_ISYNC,
12218 OPCODE_RSYNC,
12219 OPCODE_ESYNC,
12220 OPCODE_DSYNC,
12221 OPCODE_RSIL,
12222 OPCODE_RSR_LEND,
12223 OPCODE_WSR_LEND,
12224 OPCODE_XSR_LEND,
12225 OPCODE_RSR_LCOUNT,
12226 OPCODE_WSR_LCOUNT,
12227 OPCODE_XSR_LCOUNT,
12228 OPCODE_RSR_LBEG,
12229 OPCODE_WSR_LBEG,
12230 OPCODE_XSR_LBEG,
12231 OPCODE_RSR_SAR,
12232 OPCODE_WSR_SAR,
12233 OPCODE_XSR_SAR,
12234 OPCODE_RSR_MEMCTL,
12235 OPCODE_WSR_MEMCTL,
12236 OPCODE_XSR_MEMCTL,
12237 OPCODE_RSR_LITBASE,
12238 OPCODE_WSR_LITBASE,
12239 OPCODE_XSR_LITBASE,
12240 OPCODE_RSR_CONFIGID0,
12241 OPCODE_WSR_CONFIGID0,
12242 OPCODE_RSR_CONFIGID1,
12243 OPCODE_RSR_PS,
12244 OPCODE_WSR_PS,
12245 OPCODE_XSR_PS,
12246 OPCODE_RSR_EPC1,
12247 OPCODE_WSR_EPC1,
12248 OPCODE_XSR_EPC1,
12249 OPCODE_RSR_EXCSAVE1,
12250 OPCODE_WSR_EXCSAVE1,
12251 OPCODE_XSR_EXCSAVE1,
12252 OPCODE_RSR_EPC2,
12253 OPCODE_WSR_EPC2,
12254 OPCODE_XSR_EPC2,
12255 OPCODE_RSR_EXCSAVE2,
12256 OPCODE_WSR_EXCSAVE2,
12257 OPCODE_XSR_EXCSAVE2,
12258 OPCODE_RSR_EPC3,
12259 OPCODE_WSR_EPC3,
12260 OPCODE_XSR_EPC3,
12261 OPCODE_RSR_EXCSAVE3,
12262 OPCODE_WSR_EXCSAVE3,
12263 OPCODE_XSR_EXCSAVE3,
12264 OPCODE_RSR_EPC4,
12265 OPCODE_WSR_EPC4,
12266 OPCODE_XSR_EPC4,
12267 OPCODE_RSR_EXCSAVE4,
12268 OPCODE_WSR_EXCSAVE4,
12269 OPCODE_XSR_EXCSAVE4,
12270 OPCODE_RSR_EPC5,
12271 OPCODE_WSR_EPC5,
12272 OPCODE_XSR_EPC5,
12273 OPCODE_RSR_EXCSAVE5,
12274 OPCODE_WSR_EXCSAVE5,
12275 OPCODE_XSR_EXCSAVE5,
12276 OPCODE_RSR_EPC6,
12277 OPCODE_WSR_EPC6,
12278 OPCODE_XSR_EPC6,
12279 OPCODE_RSR_EXCSAVE6,
12280 OPCODE_WSR_EXCSAVE6,
12281 OPCODE_XSR_EXCSAVE6,
12282 OPCODE_RSR_EPC7,
12283 OPCODE_WSR_EPC7,
12284 OPCODE_XSR_EPC7,
12285 OPCODE_RSR_EXCSAVE7,
12286 OPCODE_WSR_EXCSAVE7,
12287 OPCODE_XSR_EXCSAVE7,
12288 OPCODE_RSR_EPS2,
12289 OPCODE_WSR_EPS2,
12290 OPCODE_XSR_EPS2,
12291 OPCODE_RSR_EPS3,
12292 OPCODE_WSR_EPS3,
12293 OPCODE_XSR_EPS3,
12294 OPCODE_RSR_EPS4,
12295 OPCODE_WSR_EPS4,
12296 OPCODE_XSR_EPS4,
12297 OPCODE_RSR_EPS5,
12298 OPCODE_WSR_EPS5,
12299 OPCODE_XSR_EPS5,
12300 OPCODE_RSR_EPS6,
12301 OPCODE_WSR_EPS6,
12302 OPCODE_XSR_EPS6,
12303 OPCODE_RSR_EPS7,
12304 OPCODE_WSR_EPS7,
12305 OPCODE_XSR_EPS7,
12306 OPCODE_RSR_EXCVADDR,
12307 OPCODE_WSR_EXCVADDR,
12308 OPCODE_XSR_EXCVADDR,
12309 OPCODE_RSR_DEPC,
12310 OPCODE_WSR_DEPC,
12311 OPCODE_XSR_DEPC,
12312 OPCODE_RSR_EXCCAUSE,
12313 OPCODE_WSR_EXCCAUSE,
12314 OPCODE_XSR_EXCCAUSE,
12315 OPCODE_RSR_MISC0,
12316 OPCODE_WSR_MISC0,
12317 OPCODE_XSR_MISC0,
12318 OPCODE_RSR_MISC1,
12319 OPCODE_WSR_MISC1,
12320 OPCODE_XSR_MISC1,
12321 OPCODE_RSR_PRID,
12322 OPCODE_RSR_VECBASE,
12323 OPCODE_WSR_VECBASE,
12324 OPCODE_XSR_VECBASE,
12325 OPCODE_MUL16U,
12326 OPCODE_MUL16S,
12327 OPCODE_MULL,
12328 OPCODE_MUL_AA_LL,
12329 OPCODE_MUL_AA_HL,
12330 OPCODE_MUL_AA_LH,
12331 OPCODE_MUL_AA_HH,
12332 OPCODE_UMUL_AA_LL,
12333 OPCODE_UMUL_AA_HL,
12334 OPCODE_UMUL_AA_LH,
12335 OPCODE_UMUL_AA_HH,
12336 OPCODE_MUL_AD_LL,
12337 OPCODE_MUL_AD_HL,
12338 OPCODE_MUL_AD_LH,
12339 OPCODE_MUL_AD_HH,
12340 OPCODE_MUL_DA_LL,
12341 OPCODE_MUL_DA_HL,
12342 OPCODE_MUL_DA_LH,
12343 OPCODE_MUL_DA_HH,
12344 OPCODE_MUL_DD_LL,
12345 OPCODE_MUL_DD_HL,
12346 OPCODE_MUL_DD_LH,
12347 OPCODE_MUL_DD_HH,
12348 OPCODE_MULA_AA_LL,
12349 OPCODE_MULA_AA_HL,
12350 OPCODE_MULA_AA_LH,
12351 OPCODE_MULA_AA_HH,
12352 OPCODE_MULS_AA_LL,
12353 OPCODE_MULS_AA_HL,
12354 OPCODE_MULS_AA_LH,
12355 OPCODE_MULS_AA_HH,
12356 OPCODE_MULA_AD_LL,
12357 OPCODE_MULA_AD_HL,
12358 OPCODE_MULA_AD_LH,
12359 OPCODE_MULA_AD_HH,
12360 OPCODE_MULS_AD_LL,
12361 OPCODE_MULS_AD_HL,
12362 OPCODE_MULS_AD_LH,
12363 OPCODE_MULS_AD_HH,
12364 OPCODE_MULA_DA_LL,
12365 OPCODE_MULA_DA_HL,
12366 OPCODE_MULA_DA_LH,
12367 OPCODE_MULA_DA_HH,
12368 OPCODE_MULS_DA_LL,
12369 OPCODE_MULS_DA_HL,
12370 OPCODE_MULS_DA_LH,
12371 OPCODE_MULS_DA_HH,
12372 OPCODE_MULA_DD_LL,
12373 OPCODE_MULA_DD_HL,
12374 OPCODE_MULA_DD_LH,
12375 OPCODE_MULA_DD_HH,
12376 OPCODE_MULS_DD_LL,
12377 OPCODE_MULS_DD_HL,
12378 OPCODE_MULS_DD_LH,
12379 OPCODE_MULS_DD_HH,
12380 OPCODE_MULA_DA_LL_LDDEC,
12381 OPCODE_MULA_DA_LL_LDINC,
12382 OPCODE_MULA_DA_HL_LDDEC,
12383 OPCODE_MULA_DA_HL_LDINC,
12384 OPCODE_MULA_DA_LH_LDDEC,
12385 OPCODE_MULA_DA_LH_LDINC,
12386 OPCODE_MULA_DA_HH_LDDEC,
12387 OPCODE_MULA_DA_HH_LDINC,
12388 OPCODE_MULA_DD_LL_LDDEC,
12389 OPCODE_MULA_DD_LL_LDINC,
12390 OPCODE_MULA_DD_HL_LDDEC,
12391 OPCODE_MULA_DD_HL_LDINC,
12392 OPCODE_MULA_DD_LH_LDDEC,
12393 OPCODE_MULA_DD_LH_LDINC,
12394 OPCODE_MULA_DD_HH_LDDEC,
12395 OPCODE_MULA_DD_HH_LDINC,
12396 OPCODE_LDDEC,
12397 OPCODE_LDINC,
12398 OPCODE_RSR_M0,
12399 OPCODE_WSR_M0,
12400 OPCODE_XSR_M0,
12401 OPCODE_RSR_M1,
12402 OPCODE_WSR_M1,
12403 OPCODE_XSR_M1,
12404 OPCODE_RSR_M2,
12405 OPCODE_WSR_M2,
12406 OPCODE_XSR_M2,
12407 OPCODE_RSR_M3,
12408 OPCODE_WSR_M3,
12409 OPCODE_XSR_M3,
12410 OPCODE_RSR_ACCLO,
12411 OPCODE_WSR_ACCLO,
12412 OPCODE_XSR_ACCLO,
12413 OPCODE_RSR_ACCHI,
12414 OPCODE_WSR_ACCHI,
12415 OPCODE_XSR_ACCHI,
12416 OPCODE_RFI,
12417 OPCODE_WAITI,
12418 OPCODE_RSR_INTERRUPT,
12419 OPCODE_WSR_INTSET,
12420 OPCODE_WSR_INTCLEAR,
12421 OPCODE_RSR_INTENABLE,
12422 OPCODE_WSR_INTENABLE,
12423 OPCODE_XSR_INTENABLE,
12424 OPCODE_BREAK,
12425 OPCODE_BREAK_N,
12426 OPCODE_RSR_DBREAKA0,
12427 OPCODE_WSR_DBREAKA0,
12428 OPCODE_XSR_DBREAKA0,
12429 OPCODE_RSR_DBREAKC0,
12430 OPCODE_WSR_DBREAKC0,
12431 OPCODE_XSR_DBREAKC0,
12432 OPCODE_RSR_DBREAKA1,
12433 OPCODE_WSR_DBREAKA1,
12434 OPCODE_XSR_DBREAKA1,
12435 OPCODE_RSR_DBREAKC1,
12436 OPCODE_WSR_DBREAKC1,
12437 OPCODE_XSR_DBREAKC1,
12438 OPCODE_RSR_IBREAKA0,
12439 OPCODE_WSR_IBREAKA0,
12440 OPCODE_XSR_IBREAKA0,
12441 OPCODE_RSR_IBREAKA1,
12442 OPCODE_WSR_IBREAKA1,
12443 OPCODE_XSR_IBREAKA1,
12444 OPCODE_RSR_IBREAKENABLE,
12445 OPCODE_WSR_IBREAKENABLE,
12446 OPCODE_XSR_IBREAKENABLE,
12447 OPCODE_RSR_DEBUGCAUSE,
12448 OPCODE_WSR_DEBUGCAUSE,
12449 OPCODE_XSR_DEBUGCAUSE,
12450 OPCODE_RSR_ICOUNT,
12451 OPCODE_WSR_ICOUNT,
12452 OPCODE_XSR_ICOUNT,
12453 OPCODE_RSR_ICOUNTLEVEL,
12454 OPCODE_WSR_ICOUNTLEVEL,
12455 OPCODE_XSR_ICOUNTLEVEL,
12456 OPCODE_RSR_DDR,
12457 OPCODE_WSR_DDR,
12458 OPCODE_XSR_DDR,
12459 OPCODE_LDDR32_P,
12460 OPCODE_SDDR32_P,
12461 OPCODE_RFDO,
12462 OPCODE_RFDD,
12463 OPCODE_WSR_MMID,
12464 OPCODE_RSR_CCOUNT,
12465 OPCODE_WSR_CCOUNT,
12466 OPCODE_XSR_CCOUNT,
12467 OPCODE_RSR_CCOMPARE0,
12468 OPCODE_WSR_CCOMPARE0,
12469 OPCODE_XSR_CCOMPARE0,
12470 OPCODE_RSR_CCOMPARE1,
12471 OPCODE_WSR_CCOMPARE1,
12472 OPCODE_XSR_CCOMPARE1,
12473 OPCODE_RSR_CCOMPARE2,
12474 OPCODE_WSR_CCOMPARE2,
12475 OPCODE_XSR_CCOMPARE2,
12476 OPCODE_IPF,
12477 OPCODE_IHI,
12478 OPCODE_IPFL,
12479 OPCODE_IHU,
12480 OPCODE_IIU,
12481 OPCODE_III,
12482 OPCODE_LICT,
12483 OPCODE_LICW,
12484 OPCODE_SICT,
12485 OPCODE_SICW,
12486 OPCODE_DHWB,
12487 OPCODE_DHWBI,
12488 OPCODE_DIWBUI_P,
12489 OPCODE_DIWB,
12490 OPCODE_DIWBI,
12491 OPCODE_DHI,
12492 OPCODE_DII,
12493 OPCODE_DPFR,
12494 OPCODE_DPFW,
12495 OPCODE_DPFRO,
12496 OPCODE_DPFWO,
12497 OPCODE_DPFL,
12498 OPCODE_DHU,
12499 OPCODE_DIU,
12500 OPCODE_SDCT,
12501 OPCODE_LDCT,
12502 OPCODE_IDTLB,
12503 OPCODE_PDTLB,
12504 OPCODE_RDTLB0,
12505 OPCODE_RDTLB1,
12506 OPCODE_WDTLB,
12507 OPCODE_IITLB,
12508 OPCODE_PITLB,
12509 OPCODE_RITLB0,
12510 OPCODE_RITLB1,
12511 OPCODE_WITLB,
12512 OPCODE_CLAMPS,
12513 OPCODE_MIN,
12514 OPCODE_MAX,
12515 OPCODE_MINU,
12516 OPCODE_MAXU,
12517 OPCODE_NSA,
12518 OPCODE_NSAU,
12519 OPCODE_SEXT,
12520 OPCODE_L32AI,
12521 OPCODE_S32RI,
12522 OPCODE_S32C1I,
12523 OPCODE_RSR_SCOMPARE1,
12524 OPCODE_WSR_SCOMPARE1,
12525 OPCODE_XSR_SCOMPARE1,
12526 OPCODE_RSR_ATOMCTL,
12527 OPCODE_WSR_ATOMCTL,
12528 OPCODE_XSR_ATOMCTL,
12529 OPCODE_QUOU,
12530 OPCODE_QUOS,
12531 OPCODE_REMU,
12532 OPCODE_REMS,
12533 OPCODE_RER,
12534 OPCODE_WER,
12535 OPCODE_RUR_EXPSTATE,
12536 OPCODE_WUR_EXPSTATE,
12537 OPCODE_READ_IMPWIRE,
12538 OPCODE_SETB_EXPSTATE,
12539 OPCODE_CLRB_EXPSTATE,
12540 OPCODE_WRMSK_EXPSTATE
12541};
12542
12543\f
12544/* Slot-specific opcode decode functions. */
12545
12546static int
12547Slot_inst_decode (const xtensa_insnbuf insn)
12548{
12549 if (Field_op0_Slot_inst_get (insn) == 0)
12550 {
12551 if (Field_op1_Slot_inst_get (insn) == 0)
12552 {
12553 if (Field_op2_Slot_inst_get (insn) == 0)
12554 {
12555 if (Field_r_Slot_inst_get (insn) == 0)
12556 {
12557 if (Field_m_Slot_inst_get (insn) == 0 &&
12558 Field_s_Slot_inst_get (insn) == 0 &&
12559 Field_n_Slot_inst_get (insn) == 0)
12560 return OPCODE_ILL;
12561 if (Field_m_Slot_inst_get (insn) == 2)
12562 {
12563 if (Field_n_Slot_inst_get (insn) == 0)
12564 return OPCODE_RET;
12565 if (Field_n_Slot_inst_get (insn) == 1)
12566 return OPCODE_RETW;
12567 if (Field_n_Slot_inst_get (insn) == 2)
12568 return OPCODE_JX;
12569 }
12570 if (Field_m_Slot_inst_get (insn) == 3)
12571 {
12572 if (Field_n_Slot_inst_get (insn) == 0)
12573 return OPCODE_CALLX0;
12574 if (Field_n_Slot_inst_get (insn) == 1)
12575 return OPCODE_CALLX4;
12576 if (Field_n_Slot_inst_get (insn) == 2)
12577 return OPCODE_CALLX8;
12578 if (Field_n_Slot_inst_get (insn) == 3)
12579 return OPCODE_CALLX12;
12580 }
12581 }
12582 if (Field_r_Slot_inst_get (insn) == 1)
12583 return OPCODE_MOVSP;
12584 if (Field_r_Slot_inst_get (insn) == 2)
12585 {
12586 if (Field_s_Slot_inst_get (insn) == 0)
12587 {
12588 if (Field_t_Slot_inst_get (insn) == 0)
12589 return OPCODE_ISYNC;
12590 if (Field_t_Slot_inst_get (insn) == 1)
12591 return OPCODE_RSYNC;
12592 if (Field_t_Slot_inst_get (insn) == 2)
12593 return OPCODE_ESYNC;
12594 if (Field_t_Slot_inst_get (insn) == 3)
12595 return OPCODE_DSYNC;
12596 if (Field_t_Slot_inst_get (insn) == 8)
12597 return OPCODE_EXCW;
12598 if (Field_t_Slot_inst_get (insn) == 12)
12599 return OPCODE_MEMW;
12600 if (Field_t_Slot_inst_get (insn) == 13)
12601 return OPCODE_EXTW;
12602 if (Field_t_Slot_inst_get (insn) == 15)
12603 return OPCODE_NOP;
12604 }
12605 }
12606 if (Field_r_Slot_inst_get (insn) == 3)
12607 {
12608 if (Field_t_Slot_inst_get (insn) == 0)
12609 {
12610 if (Field_s_Slot_inst_get (insn) == 0)
12611 return OPCODE_RFE;
12612 if (Field_s_Slot_inst_get (insn) == 2)
12613 return OPCODE_RFDE;
12614 if (Field_s_Slot_inst_get (insn) == 4)
12615 return OPCODE_RFWO;
12616 if (Field_s_Slot_inst_get (insn) == 5)
12617 return OPCODE_RFWU;
12618 }
12619 if (Field_t_Slot_inst_get (insn) == 1)
12620 return OPCODE_RFI;
12621 }
12622 if (Field_r_Slot_inst_get (insn) == 4)
12623 return OPCODE_BREAK;
12624 if (Field_r_Slot_inst_get (insn) == 5)
12625 {
12626 if (Field_s_Slot_inst_get (insn) == 0 &&
12627 Field_t_Slot_inst_get (insn) == 0)
12628 return OPCODE_SYSCALL;
12629 if (Field_s_Slot_inst_get (insn) == 1 &&
12630 Field_t_Slot_inst_get (insn) == 0)
12631 return OPCODE_SIMCALL;
12632 }
12633 if (Field_r_Slot_inst_get (insn) == 6)
12634 return OPCODE_RSIL;
12635 if (Field_r_Slot_inst_get (insn) == 7 &&
12636 Field_t_Slot_inst_get (insn) == 0)
12637 return OPCODE_WAITI;
12638 if (Field_r_Slot_inst_get (insn) == 7)
12639 {
12640 if (Field_t_Slot_inst_get (insn) == 14)
12641 return OPCODE_LDDR32_P;
12642 if (Field_t_Slot_inst_get (insn) == 15)
12643 return OPCODE_SDDR32_P;
12644 }
12645 }
12646 if (Field_op2_Slot_inst_get (insn) == 1)
12647 return OPCODE_AND;
12648 if (Field_op2_Slot_inst_get (insn) == 2)
12649 return OPCODE_OR;
12650 if (Field_op2_Slot_inst_get (insn) == 3)
12651 return OPCODE_XOR;
12652 if (Field_op2_Slot_inst_get (insn) == 4)
12653 {
12654 if (Field_r_Slot_inst_get (insn) == 0 &&
12655 Field_t_Slot_inst_get (insn) == 0)
12656 return OPCODE_SSR;
12657 if (Field_r_Slot_inst_get (insn) == 1 &&
12658 Field_t_Slot_inst_get (insn) == 0)
12659 return OPCODE_SSL;
12660 if (Field_r_Slot_inst_get (insn) == 2 &&
12661 Field_t_Slot_inst_get (insn) == 0)
12662 return OPCODE_SSA8L;
12663 if (Field_r_Slot_inst_get (insn) == 3 &&
12664 Field_t_Slot_inst_get (insn) == 0)
12665 return OPCODE_SSA8B;
12666 if (Field_r_Slot_inst_get (insn) == 4 &&
12667 Field_thi3_Slot_inst_get (insn) == 0)
12668 return OPCODE_SSAI;
12669 if (Field_r_Slot_inst_get (insn) == 6)
12670 return OPCODE_RER;
12671 if (Field_r_Slot_inst_get (insn) == 7)
12672 return OPCODE_WER;
12673 if (Field_r_Slot_inst_get (insn) == 8 &&
12674 Field_s_Slot_inst_get (insn) == 0)
12675 return OPCODE_ROTW;
12676 if (Field_r_Slot_inst_get (insn) == 14)
12677 return OPCODE_NSA;
12678 if (Field_r_Slot_inst_get (insn) == 15)
12679 return OPCODE_NSAU;
12680 }
12681 if (Field_op2_Slot_inst_get (insn) == 5)
12682 {
12683 if (Field_r_Slot_inst_get (insn) == 3)
12684 return OPCODE_RITLB0;
12685 if (Field_r_Slot_inst_get (insn) == 4 &&
12686 Field_t_Slot_inst_get (insn) == 0)
12687 return OPCODE_IITLB;
12688 if (Field_r_Slot_inst_get (insn) == 5)
12689 return OPCODE_PITLB;
12690 if (Field_r_Slot_inst_get (insn) == 6)
12691 return OPCODE_WITLB;
12692 if (Field_r_Slot_inst_get (insn) == 7)
12693 return OPCODE_RITLB1;
12694 if (Field_r_Slot_inst_get (insn) == 11)
12695 return OPCODE_RDTLB0;
12696 if (Field_r_Slot_inst_get (insn) == 12 &&
12697 Field_t_Slot_inst_get (insn) == 0)
12698 return OPCODE_IDTLB;
12699 if (Field_r_Slot_inst_get (insn) == 13)
12700 return OPCODE_PDTLB;
12701 if (Field_r_Slot_inst_get (insn) == 14)
12702 return OPCODE_WDTLB;
12703 if (Field_r_Slot_inst_get (insn) == 15)
12704 return OPCODE_RDTLB1;
12705 }
12706 if (Field_op2_Slot_inst_get (insn) == 6)
12707 {
12708 if (Field_s_Slot_inst_get (insn) == 0)
12709 return OPCODE_NEG;
12710 if (Field_s_Slot_inst_get (insn) == 1)
12711 return OPCODE_ABS;
12712 }
12713 if (Field_op2_Slot_inst_get (insn) == 8)
12714 return OPCODE_ADD;
12715 if (Field_op2_Slot_inst_get (insn) == 9)
12716 return OPCODE_ADDX2;
12717 if (Field_op2_Slot_inst_get (insn) == 10)
12718 return OPCODE_ADDX4;
12719 if (Field_op2_Slot_inst_get (insn) == 11)
12720 return OPCODE_ADDX8;
12721 if (Field_op2_Slot_inst_get (insn) == 12)
12722 return OPCODE_SUB;
12723 if (Field_op2_Slot_inst_get (insn) == 13)
12724 return OPCODE_SUBX2;
12725 if (Field_op2_Slot_inst_get (insn) == 14)
12726 return OPCODE_SUBX4;
12727 if (Field_op2_Slot_inst_get (insn) == 15)
12728 return OPCODE_SUBX8;
12729 }
12730 if (Field_op1_Slot_inst_get (insn) == 1)
12731 {
12732 if ((Field_op2_Slot_inst_get (insn) == 0 ||
12733 Field_op2_Slot_inst_get (insn) == 1))
12734 return OPCODE_SLLI;
12735 if ((Field_op2_Slot_inst_get (insn) == 2 ||
12736 Field_op2_Slot_inst_get (insn) == 3))
12737 return OPCODE_SRAI;
12738 if (Field_op2_Slot_inst_get (insn) == 4)
12739 return OPCODE_SRLI;
12740 if (Field_op2_Slot_inst_get (insn) == 6)
12741 {
12742 if (Field_sr_Slot_inst_get (insn) == 0)
12743 return OPCODE_XSR_LBEG;
12744 if (Field_sr_Slot_inst_get (insn) == 1)
12745 return OPCODE_XSR_LEND;
12746 if (Field_sr_Slot_inst_get (insn) == 2)
12747 return OPCODE_XSR_LCOUNT;
12748 if (Field_sr_Slot_inst_get (insn) == 3)
12749 return OPCODE_XSR_SAR;
12750 if (Field_sr_Slot_inst_get (insn) == 5)
12751 return OPCODE_XSR_LITBASE;
12752 if (Field_sr_Slot_inst_get (insn) == 12)
12753 return OPCODE_XSR_SCOMPARE1;
12754 if (Field_sr_Slot_inst_get (insn) == 16)
12755 return OPCODE_XSR_ACCLO;
12756 if (Field_sr_Slot_inst_get (insn) == 17)
12757 return OPCODE_XSR_ACCHI;
12758 if (Field_sr_Slot_inst_get (insn) == 32)
12759 return OPCODE_XSR_M0;
12760 if (Field_sr_Slot_inst_get (insn) == 33)
12761 return OPCODE_XSR_M1;
12762 if (Field_sr_Slot_inst_get (insn) == 34)
12763 return OPCODE_XSR_M2;
12764 if (Field_sr_Slot_inst_get (insn) == 35)
12765 return OPCODE_XSR_M3;
12766 if (Field_sr_Slot_inst_get (insn) == 72)
12767 return OPCODE_XSR_WINDOWBASE;
12768 if (Field_sr_Slot_inst_get (insn) == 73)
12769 return OPCODE_XSR_WINDOWSTART;
12770 if (Field_sr_Slot_inst_get (insn) == 96)
12771 return OPCODE_XSR_IBREAKENABLE;
12772 if (Field_sr_Slot_inst_get (insn) == 97)
12773 return OPCODE_XSR_MEMCTL;
12774 if (Field_sr_Slot_inst_get (insn) == 99)
12775 return OPCODE_XSR_ATOMCTL;
12776 if (Field_sr_Slot_inst_get (insn) == 104)
12777 return OPCODE_XSR_DDR;
12778 if (Field_sr_Slot_inst_get (insn) == 128)
12779 return OPCODE_XSR_IBREAKA0;
12780 if (Field_sr_Slot_inst_get (insn) == 129)
12781 return OPCODE_XSR_IBREAKA1;
12782 if (Field_sr_Slot_inst_get (insn) == 144)
12783 return OPCODE_XSR_DBREAKA0;
12784 if (Field_sr_Slot_inst_get (insn) == 145)
12785 return OPCODE_XSR_DBREAKA1;
12786 if (Field_sr_Slot_inst_get (insn) == 160)
12787 return OPCODE_XSR_DBREAKC0;
12788 if (Field_sr_Slot_inst_get (insn) == 161)
12789 return OPCODE_XSR_DBREAKC1;
12790 if (Field_sr_Slot_inst_get (insn) == 177)
12791 return OPCODE_XSR_EPC1;
12792 if (Field_sr_Slot_inst_get (insn) == 178)
12793 return OPCODE_XSR_EPC2;
12794 if (Field_sr_Slot_inst_get (insn) == 179)
12795 return OPCODE_XSR_EPC3;
12796 if (Field_sr_Slot_inst_get (insn) == 180)
12797 return OPCODE_XSR_EPC4;
12798 if (Field_sr_Slot_inst_get (insn) == 181)
12799 return OPCODE_XSR_EPC5;
12800 if (Field_sr_Slot_inst_get (insn) == 182)
12801 return OPCODE_XSR_EPC6;
12802 if (Field_sr_Slot_inst_get (insn) == 183)
12803 return OPCODE_XSR_EPC7;
12804 if (Field_sr_Slot_inst_get (insn) == 192)
12805 return OPCODE_XSR_DEPC;
12806 if (Field_sr_Slot_inst_get (insn) == 194)
12807 return OPCODE_XSR_EPS2;
12808 if (Field_sr_Slot_inst_get (insn) == 195)
12809 return OPCODE_XSR_EPS3;
12810 if (Field_sr_Slot_inst_get (insn) == 196)
12811 return OPCODE_XSR_EPS4;
12812 if (Field_sr_Slot_inst_get (insn) == 197)
12813 return OPCODE_XSR_EPS5;
12814 if (Field_sr_Slot_inst_get (insn) == 198)
12815 return OPCODE_XSR_EPS6;
12816 if (Field_sr_Slot_inst_get (insn) == 199)
12817 return OPCODE_XSR_EPS7;
12818 if (Field_sr_Slot_inst_get (insn) == 209)
12819 return OPCODE_XSR_EXCSAVE1;
12820 if (Field_sr_Slot_inst_get (insn) == 210)
12821 return OPCODE_XSR_EXCSAVE2;
12822 if (Field_sr_Slot_inst_get (insn) == 211)
12823 return OPCODE_XSR_EXCSAVE3;
12824 if (Field_sr_Slot_inst_get (insn) == 212)
12825 return OPCODE_XSR_EXCSAVE4;
12826 if (Field_sr_Slot_inst_get (insn) == 213)
12827 return OPCODE_XSR_EXCSAVE5;
12828 if (Field_sr_Slot_inst_get (insn) == 214)
12829 return OPCODE_XSR_EXCSAVE6;
12830 if (Field_sr_Slot_inst_get (insn) == 215)
12831 return OPCODE_XSR_EXCSAVE7;
12832 if (Field_sr_Slot_inst_get (insn) == 228)
12833 return OPCODE_XSR_INTENABLE;
12834 if (Field_sr_Slot_inst_get (insn) == 230)
12835 return OPCODE_XSR_PS;
12836 if (Field_sr_Slot_inst_get (insn) == 231)
12837 return OPCODE_XSR_VECBASE;
12838 if (Field_sr_Slot_inst_get (insn) == 232)
12839 return OPCODE_XSR_EXCCAUSE;
12840 if (Field_sr_Slot_inst_get (insn) == 233)
12841 return OPCODE_XSR_DEBUGCAUSE;
12842 if (Field_sr_Slot_inst_get (insn) == 234)
12843 return OPCODE_XSR_CCOUNT;
12844 if (Field_sr_Slot_inst_get (insn) == 236)
12845 return OPCODE_XSR_ICOUNT;
12846 if (Field_sr_Slot_inst_get (insn) == 237)
12847 return OPCODE_XSR_ICOUNTLEVEL;
12848 if (Field_sr_Slot_inst_get (insn) == 238)
12849 return OPCODE_XSR_EXCVADDR;
12850 if (Field_sr_Slot_inst_get (insn) == 240)
12851 return OPCODE_XSR_CCOMPARE0;
12852 if (Field_sr_Slot_inst_get (insn) == 241)
12853 return OPCODE_XSR_CCOMPARE1;
12854 if (Field_sr_Slot_inst_get (insn) == 242)
12855 return OPCODE_XSR_CCOMPARE2;
12856 if (Field_sr_Slot_inst_get (insn) == 244)
12857 return OPCODE_XSR_MISC0;
12858 if (Field_sr_Slot_inst_get (insn) == 245)
12859 return OPCODE_XSR_MISC1;
12860 }
12861 if (Field_op2_Slot_inst_get (insn) == 8)
12862 return OPCODE_SRC;
12863 if (Field_op2_Slot_inst_get (insn) == 9 &&
12864 Field_s_Slot_inst_get (insn) == 0)
12865 return OPCODE_SRL;
12866 if (Field_op2_Slot_inst_get (insn) == 10 &&
12867 Field_t_Slot_inst_get (insn) == 0)
12868 return OPCODE_SLL;
12869 if (Field_op2_Slot_inst_get (insn) == 11 &&
12870 Field_s_Slot_inst_get (insn) == 0)
12871 return OPCODE_SRA;
12872 if (Field_op2_Slot_inst_get (insn) == 12)
12873 return OPCODE_MUL16U;
12874 if (Field_op2_Slot_inst_get (insn) == 13)
12875 return OPCODE_MUL16S;
12876 if (Field_op2_Slot_inst_get (insn) == 15)
12877 {
12878 if (Field_r_Slot_inst_get (insn) == 0)
12879 return OPCODE_LICT;
12880 if (Field_r_Slot_inst_get (insn) == 1)
12881 return OPCODE_SICT;
12882 if (Field_r_Slot_inst_get (insn) == 2)
12883 return OPCODE_LICW;
12884 if (Field_r_Slot_inst_get (insn) == 3)
12885 return OPCODE_SICW;
12886 if (Field_r_Slot_inst_get (insn) == 8)
12887 return OPCODE_LDCT;
12888 if (Field_r_Slot_inst_get (insn) == 9)
12889 return OPCODE_SDCT;
12890 if (Field_r_Slot_inst_get (insn) == 14 &&
12891 Field_t_Slot_inst_get (insn) == 0)
12892 return OPCODE_RFDO;
12893 if (Field_r_Slot_inst_get (insn) == 14 &&
12894 Field_t_Slot_inst_get (insn) == 1)
12895 return OPCODE_RFDD;
12896 }
12897 }
12898 if (Field_op1_Slot_inst_get (insn) == 2)
12899 {
12900 if (Field_op2_Slot_inst_get (insn) == 8)
12901 return OPCODE_MULL;
12902 if (Field_op2_Slot_inst_get (insn) == 12)
12903 return OPCODE_QUOU;
12904 if (Field_op2_Slot_inst_get (insn) == 13)
12905 return OPCODE_QUOS;
12906 if (Field_op2_Slot_inst_get (insn) == 14)
12907 return OPCODE_REMU;
12908 if (Field_op2_Slot_inst_get (insn) == 15)
12909 return OPCODE_REMS;
12910 }
12911 if (Field_op1_Slot_inst_get (insn) == 3)
12912 {
12913 if (Field_op2_Slot_inst_get (insn) == 0)
12914 {
12915 if (Field_sr_Slot_inst_get (insn) == 0)
12916 return OPCODE_RSR_LBEG;
12917 if (Field_sr_Slot_inst_get (insn) == 1)
12918 return OPCODE_RSR_LEND;
12919 if (Field_sr_Slot_inst_get (insn) == 2)
12920 return OPCODE_RSR_LCOUNT;
12921 if (Field_sr_Slot_inst_get (insn) == 3)
12922 return OPCODE_RSR_SAR;
12923 if (Field_sr_Slot_inst_get (insn) == 5)
12924 return OPCODE_RSR_LITBASE;
12925 if (Field_sr_Slot_inst_get (insn) == 12)
12926 return OPCODE_RSR_SCOMPARE1;
12927 if (Field_sr_Slot_inst_get (insn) == 16)
12928 return OPCODE_RSR_ACCLO;
12929 if (Field_sr_Slot_inst_get (insn) == 17)
12930 return OPCODE_RSR_ACCHI;
12931 if (Field_sr_Slot_inst_get (insn) == 32)
12932 return OPCODE_RSR_M0;
12933 if (Field_sr_Slot_inst_get (insn) == 33)
12934 return OPCODE_RSR_M1;
12935 if (Field_sr_Slot_inst_get (insn) == 34)
12936 return OPCODE_RSR_M2;
12937 if (Field_sr_Slot_inst_get (insn) == 35)
12938 return OPCODE_RSR_M3;
12939 if (Field_sr_Slot_inst_get (insn) == 72)
12940 return OPCODE_RSR_WINDOWBASE;
12941 if (Field_sr_Slot_inst_get (insn) == 73)
12942 return OPCODE_RSR_WINDOWSTART;
12943 if (Field_sr_Slot_inst_get (insn) == 96)
12944 return OPCODE_RSR_IBREAKENABLE;
12945 if (Field_sr_Slot_inst_get (insn) == 97)
12946 return OPCODE_RSR_MEMCTL;
12947 if (Field_sr_Slot_inst_get (insn) == 99)
12948 return OPCODE_RSR_ATOMCTL;
12949 if (Field_sr_Slot_inst_get (insn) == 104)
12950 return OPCODE_RSR_DDR;
12951 if (Field_sr_Slot_inst_get (insn) == 128)
12952 return OPCODE_RSR_IBREAKA0;
12953 if (Field_sr_Slot_inst_get (insn) == 129)
12954 return OPCODE_RSR_IBREAKA1;
12955 if (Field_sr_Slot_inst_get (insn) == 144)
12956 return OPCODE_RSR_DBREAKA0;
12957 if (Field_sr_Slot_inst_get (insn) == 145)
12958 return OPCODE_RSR_DBREAKA1;
12959 if (Field_sr_Slot_inst_get (insn) == 160)
12960 return OPCODE_RSR_DBREAKC0;
12961 if (Field_sr_Slot_inst_get (insn) == 161)
12962 return OPCODE_RSR_DBREAKC1;
12963 if (Field_sr_Slot_inst_get (insn) == 176)
12964 return OPCODE_RSR_CONFIGID0;
12965 if (Field_sr_Slot_inst_get (insn) == 177)
12966 return OPCODE_RSR_EPC1;
12967 if (Field_sr_Slot_inst_get (insn) == 178)
12968 return OPCODE_RSR_EPC2;
12969 if (Field_sr_Slot_inst_get (insn) == 179)
12970 return OPCODE_RSR_EPC3;
12971 if (Field_sr_Slot_inst_get (insn) == 180)
12972 return OPCODE_RSR_EPC4;
12973 if (Field_sr_Slot_inst_get (insn) == 181)
12974 return OPCODE_RSR_EPC5;
12975 if (Field_sr_Slot_inst_get (insn) == 182)
12976 return OPCODE_RSR_EPC6;
12977 if (Field_sr_Slot_inst_get (insn) == 183)
12978 return OPCODE_RSR_EPC7;
12979 if (Field_sr_Slot_inst_get (insn) == 192)
12980 return OPCODE_RSR_DEPC;
12981 if (Field_sr_Slot_inst_get (insn) == 194)
12982 return OPCODE_RSR_EPS2;
12983 if (Field_sr_Slot_inst_get (insn) == 195)
12984 return OPCODE_RSR_EPS3;
12985 if (Field_sr_Slot_inst_get (insn) == 196)
12986 return OPCODE_RSR_EPS4;
12987 if (Field_sr_Slot_inst_get (insn) == 197)
12988 return OPCODE_RSR_EPS5;
12989 if (Field_sr_Slot_inst_get (insn) == 198)
12990 return OPCODE_RSR_EPS6;
12991 if (Field_sr_Slot_inst_get (insn) == 199)
12992 return OPCODE_RSR_EPS7;
12993 if (Field_sr_Slot_inst_get (insn) == 208)
12994 return OPCODE_RSR_CONFIGID1;
12995 if (Field_sr_Slot_inst_get (insn) == 209)
12996 return OPCODE_RSR_EXCSAVE1;
12997 if (Field_sr_Slot_inst_get (insn) == 210)
12998 return OPCODE_RSR_EXCSAVE2;
12999 if (Field_sr_Slot_inst_get (insn) == 211)
13000 return OPCODE_RSR_EXCSAVE3;
13001 if (Field_sr_Slot_inst_get (insn) == 212)
13002 return OPCODE_RSR_EXCSAVE4;
13003 if (Field_sr_Slot_inst_get (insn) == 213)
13004 return OPCODE_RSR_EXCSAVE5;
13005 if (Field_sr_Slot_inst_get (insn) == 214)
13006 return OPCODE_RSR_EXCSAVE6;
13007 if (Field_sr_Slot_inst_get (insn) == 215)
13008 return OPCODE_RSR_EXCSAVE7;
13009 if (Field_sr_Slot_inst_get (insn) == 226)
13010 return OPCODE_RSR_INTERRUPT;
13011 if (Field_sr_Slot_inst_get (insn) == 228)
13012 return OPCODE_RSR_INTENABLE;
13013 if (Field_sr_Slot_inst_get (insn) == 230)
13014 return OPCODE_RSR_PS;
13015 if (Field_sr_Slot_inst_get (insn) == 231)
13016 return OPCODE_RSR_VECBASE;
13017 if (Field_sr_Slot_inst_get (insn) == 232)
13018 return OPCODE_RSR_EXCCAUSE;
13019 if (Field_sr_Slot_inst_get (insn) == 233)
13020 return OPCODE_RSR_DEBUGCAUSE;
13021 if (Field_sr_Slot_inst_get (insn) == 234)
13022 return OPCODE_RSR_CCOUNT;
13023 if (Field_sr_Slot_inst_get (insn) == 235)
13024 return OPCODE_RSR_PRID;
13025 if (Field_sr_Slot_inst_get (insn) == 236)
13026 return OPCODE_RSR_ICOUNT;
13027 if (Field_sr_Slot_inst_get (insn) == 237)
13028 return OPCODE_RSR_ICOUNTLEVEL;
13029 if (Field_sr_Slot_inst_get (insn) == 238)
13030 return OPCODE_RSR_EXCVADDR;
13031 if (Field_sr_Slot_inst_get (insn) == 240)
13032 return OPCODE_RSR_CCOMPARE0;
13033 if (Field_sr_Slot_inst_get (insn) == 241)
13034 return OPCODE_RSR_CCOMPARE1;
13035 if (Field_sr_Slot_inst_get (insn) == 242)
13036 return OPCODE_RSR_CCOMPARE2;
13037 if (Field_sr_Slot_inst_get (insn) == 244)
13038 return OPCODE_RSR_MISC0;
13039 if (Field_sr_Slot_inst_get (insn) == 245)
13040 return OPCODE_RSR_MISC1;
13041 }
13042 if (Field_op2_Slot_inst_get (insn) == 1)
13043 {
13044 if (Field_sr_Slot_inst_get (insn) == 0)
13045 return OPCODE_WSR_LBEG;
13046 if (Field_sr_Slot_inst_get (insn) == 1)
13047 return OPCODE_WSR_LEND;
13048 if (Field_sr_Slot_inst_get (insn) == 2)
13049 return OPCODE_WSR_LCOUNT;
13050 if (Field_sr_Slot_inst_get (insn) == 3)
13051 return OPCODE_WSR_SAR;
13052 if (Field_sr_Slot_inst_get (insn) == 5)
13053 return OPCODE_WSR_LITBASE;
13054 if (Field_sr_Slot_inst_get (insn) == 12)
13055 return OPCODE_WSR_SCOMPARE1;
13056 if (Field_sr_Slot_inst_get (insn) == 16)
13057 return OPCODE_WSR_ACCLO;
13058 if (Field_sr_Slot_inst_get (insn) == 17)
13059 return OPCODE_WSR_ACCHI;
13060 if (Field_sr_Slot_inst_get (insn) == 32)
13061 return OPCODE_WSR_M0;
13062 if (Field_sr_Slot_inst_get (insn) == 33)
13063 return OPCODE_WSR_M1;
13064 if (Field_sr_Slot_inst_get (insn) == 34)
13065 return OPCODE_WSR_M2;
13066 if (Field_sr_Slot_inst_get (insn) == 35)
13067 return OPCODE_WSR_M3;
13068 if (Field_sr_Slot_inst_get (insn) == 72)
13069 return OPCODE_WSR_WINDOWBASE;
13070 if (Field_sr_Slot_inst_get (insn) == 73)
13071 return OPCODE_WSR_WINDOWSTART;
13072 if (Field_sr_Slot_inst_get (insn) == 89)
13073 return OPCODE_WSR_MMID;
13074 if (Field_sr_Slot_inst_get (insn) == 96)
13075 return OPCODE_WSR_IBREAKENABLE;
13076 if (Field_sr_Slot_inst_get (insn) == 97)
13077 return OPCODE_WSR_MEMCTL;
13078 if (Field_sr_Slot_inst_get (insn) == 99)
13079 return OPCODE_WSR_ATOMCTL;
13080 if (Field_sr_Slot_inst_get (insn) == 104)
13081 return OPCODE_WSR_DDR;
13082 if (Field_sr_Slot_inst_get (insn) == 128)
13083 return OPCODE_WSR_IBREAKA0;
13084 if (Field_sr_Slot_inst_get (insn) == 129)
13085 return OPCODE_WSR_IBREAKA1;
13086 if (Field_sr_Slot_inst_get (insn) == 144)
13087 return OPCODE_WSR_DBREAKA0;
13088 if (Field_sr_Slot_inst_get (insn) == 145)
13089 return OPCODE_WSR_DBREAKA1;
13090 if (Field_sr_Slot_inst_get (insn) == 160)
13091 return OPCODE_WSR_DBREAKC0;
13092 if (Field_sr_Slot_inst_get (insn) == 161)
13093 return OPCODE_WSR_DBREAKC1;
13094 if (Field_sr_Slot_inst_get (insn) == 176)
13095 return OPCODE_WSR_CONFIGID0;
13096 if (Field_sr_Slot_inst_get (insn) == 177)
13097 return OPCODE_WSR_EPC1;
13098 if (Field_sr_Slot_inst_get (insn) == 178)
13099 return OPCODE_WSR_EPC2;
13100 if (Field_sr_Slot_inst_get (insn) == 179)
13101 return OPCODE_WSR_EPC3;
13102 if (Field_sr_Slot_inst_get (insn) == 180)
13103 return OPCODE_WSR_EPC4;
13104 if (Field_sr_Slot_inst_get (insn) == 181)
13105 return OPCODE_WSR_EPC5;
13106 if (Field_sr_Slot_inst_get (insn) == 182)
13107 return OPCODE_WSR_EPC6;
13108 if (Field_sr_Slot_inst_get (insn) == 183)
13109 return OPCODE_WSR_EPC7;
13110 if (Field_sr_Slot_inst_get (insn) == 192)
13111 return OPCODE_WSR_DEPC;
13112 if (Field_sr_Slot_inst_get (insn) == 194)
13113 return OPCODE_WSR_EPS2;
13114 if (Field_sr_Slot_inst_get (insn) == 195)
13115 return OPCODE_WSR_EPS3;
13116 if (Field_sr_Slot_inst_get (insn) == 196)
13117 return OPCODE_WSR_EPS4;
13118 if (Field_sr_Slot_inst_get (insn) == 197)
13119 return OPCODE_WSR_EPS5;
13120 if (Field_sr_Slot_inst_get (insn) == 198)
13121 return OPCODE_WSR_EPS6;
13122 if (Field_sr_Slot_inst_get (insn) == 199)
13123 return OPCODE_WSR_EPS7;
13124 if (Field_sr_Slot_inst_get (insn) == 209)
13125 return OPCODE_WSR_EXCSAVE1;
13126 if (Field_sr_Slot_inst_get (insn) == 210)
13127 return OPCODE_WSR_EXCSAVE2;
13128 if (Field_sr_Slot_inst_get (insn) == 211)
13129 return OPCODE_WSR_EXCSAVE3;
13130 if (Field_sr_Slot_inst_get (insn) == 212)
13131 return OPCODE_WSR_EXCSAVE4;
13132 if (Field_sr_Slot_inst_get (insn) == 213)
13133 return OPCODE_WSR_EXCSAVE5;
13134 if (Field_sr_Slot_inst_get (insn) == 214)
13135 return OPCODE_WSR_EXCSAVE6;
13136 if (Field_sr_Slot_inst_get (insn) == 215)
13137 return OPCODE_WSR_EXCSAVE7;
13138 if (Field_sr_Slot_inst_get (insn) == 226)
13139 return OPCODE_WSR_INTSET;
13140 if (Field_sr_Slot_inst_get (insn) == 227)
13141 return OPCODE_WSR_INTCLEAR;
13142 if (Field_sr_Slot_inst_get (insn) == 228)
13143 return OPCODE_WSR_INTENABLE;
13144 if (Field_sr_Slot_inst_get (insn) == 230)
13145 return OPCODE_WSR_PS;
13146 if (Field_sr_Slot_inst_get (insn) == 231)
13147 return OPCODE_WSR_VECBASE;
13148 if (Field_sr_Slot_inst_get (insn) == 232)
13149 return OPCODE_WSR_EXCCAUSE;
13150 if (Field_sr_Slot_inst_get (insn) == 233)
13151 return OPCODE_WSR_DEBUGCAUSE;
13152 if (Field_sr_Slot_inst_get (insn) == 234)
13153 return OPCODE_WSR_CCOUNT;
13154 if (Field_sr_Slot_inst_get (insn) == 236)
13155 return OPCODE_WSR_ICOUNT;
13156 if (Field_sr_Slot_inst_get (insn) == 237)
13157 return OPCODE_WSR_ICOUNTLEVEL;
13158 if (Field_sr_Slot_inst_get (insn) == 238)
13159 return OPCODE_WSR_EXCVADDR;
13160 if (Field_sr_Slot_inst_get (insn) == 240)
13161 return OPCODE_WSR_CCOMPARE0;
13162 if (Field_sr_Slot_inst_get (insn) == 241)
13163 return OPCODE_WSR_CCOMPARE1;
13164 if (Field_sr_Slot_inst_get (insn) == 242)
13165 return OPCODE_WSR_CCOMPARE2;
13166 if (Field_sr_Slot_inst_get (insn) == 244)
13167 return OPCODE_WSR_MISC0;
13168 if (Field_sr_Slot_inst_get (insn) == 245)
13169 return OPCODE_WSR_MISC1;
13170 }
13171 if (Field_op2_Slot_inst_get (insn) == 2)
13172 return OPCODE_SEXT;
13173 if (Field_op2_Slot_inst_get (insn) == 3)
13174 return OPCODE_CLAMPS;
13175 if (Field_op2_Slot_inst_get (insn) == 4)
13176 return OPCODE_MIN;
13177 if (Field_op2_Slot_inst_get (insn) == 5)
13178 return OPCODE_MAX;
13179 if (Field_op2_Slot_inst_get (insn) == 6)
13180 return OPCODE_MINU;
13181 if (Field_op2_Slot_inst_get (insn) == 7)
13182 return OPCODE_MAXU;
13183 if (Field_op2_Slot_inst_get (insn) == 8)
13184 return OPCODE_MOVEQZ;
13185 if (Field_op2_Slot_inst_get (insn) == 9)
13186 return OPCODE_MOVNEZ;
13187 if (Field_op2_Slot_inst_get (insn) == 10)
13188 return OPCODE_MOVLTZ;
13189 if (Field_op2_Slot_inst_get (insn) == 11)
13190 return OPCODE_MOVGEZ;
13191 if (Field_op2_Slot_inst_get (insn) == 14)
13192 {
13193 if (Field_st_Slot_inst_get (insn) == 230)
13194 return OPCODE_RUR_EXPSTATE;
13195 }
13196 if (Field_op2_Slot_inst_get (insn) == 15)
13197 {
13198 if (Field_sr_Slot_inst_get (insn) == 230)
13199 return OPCODE_WUR_EXPSTATE;
13200 }
13201 }
13202 if ((Field_op1_Slot_inst_get (insn) == 4 ||
13203 Field_op1_Slot_inst_get (insn) == 5))
13204 return OPCODE_EXTUI;
13205 if (Field_op1_Slot_inst_get (insn) == 9)
13206 {
13207 if (Field_op2_Slot_inst_get (insn) == 0)
13208 return OPCODE_L32E;
13209 if (Field_op2_Slot_inst_get (insn) == 4)
13210 return OPCODE_S32E;
13211 if (Field_op2_Slot_inst_get (insn) == 5)
13212 return OPCODE_S32NB;
13213 }
13214 if (Field_r_Slot_inst_get (insn) == 0 &&
13215 Field_s_Slot_inst_get (insn) == 0 &&
13216 Field_op2_Slot_inst_get (insn) == 0 &&
13217 Field_op1_Slot_inst_get (insn) == 14)
13218 return OPCODE_READ_IMPWIRE;
13219 if (Field_r_Slot_inst_get (insn) == 1 &&
13220 Field_s3to1_Slot_inst_get (insn) == 0 &&
13221 Field_op2_Slot_inst_get (insn) == 0 &&
13222 Field_op1_Slot_inst_get (insn) == 14)
13223 return OPCODE_SETB_EXPSTATE;
13224 if (Field_r_Slot_inst_get (insn) == 1 &&
13225 Field_s3to1_Slot_inst_get (insn) == 1 &&
13226 Field_op2_Slot_inst_get (insn) == 0 &&
13227 Field_op1_Slot_inst_get (insn) == 14)
13228 return OPCODE_CLRB_EXPSTATE;
13229 if (Field_r_Slot_inst_get (insn) == 2 &&
13230 Field_op2_Slot_inst_get (insn) == 0 &&
13231 Field_op1_Slot_inst_get (insn) == 14)
13232 return OPCODE_WRMSK_EXPSTATE;
13233 }
13234 if (Field_op0_Slot_inst_get (insn) == 1)
13235 return OPCODE_L32R;
13236 if (Field_op0_Slot_inst_get (insn) == 2)
13237 {
13238 if (Field_r_Slot_inst_get (insn) == 0)
13239 return OPCODE_L8UI;
13240 if (Field_r_Slot_inst_get (insn) == 1)
13241 return OPCODE_L16UI;
13242 if (Field_r_Slot_inst_get (insn) == 2)
13243 return OPCODE_L32I;
13244 if (Field_r_Slot_inst_get (insn) == 4)
13245 return OPCODE_S8I;
13246 if (Field_r_Slot_inst_get (insn) == 5)
13247 return OPCODE_S16I;
13248 if (Field_r_Slot_inst_get (insn) == 6)
13249 return OPCODE_S32I;
13250 if (Field_r_Slot_inst_get (insn) == 7)
13251 {
13252 if (Field_t_Slot_inst_get (insn) == 0)
13253 return OPCODE_DPFR;
13254 if (Field_t_Slot_inst_get (insn) == 1)
13255 return OPCODE_DPFW;
13256 if (Field_t_Slot_inst_get (insn) == 2)
13257 return OPCODE_DPFRO;
13258 if (Field_t_Slot_inst_get (insn) == 3)
13259 return OPCODE_DPFWO;
13260 if (Field_t_Slot_inst_get (insn) == 4)
13261 return OPCODE_DHWB;
13262 if (Field_t_Slot_inst_get (insn) == 5)
13263 return OPCODE_DHWBI;
13264 if (Field_t_Slot_inst_get (insn) == 6)
13265 return OPCODE_DHI;
13266 if (Field_t_Slot_inst_get (insn) == 7)
13267 return OPCODE_DII;
13268 if (Field_t_Slot_inst_get (insn) == 8)
13269 {
13270 if (Field_op1_Slot_inst_get (insn) == 0)
13271 return OPCODE_DPFL;
13272 if (Field_op1_Slot_inst_get (insn) == 2)
13273 return OPCODE_DHU;
13274 if (Field_op1_Slot_inst_get (insn) == 3)
13275 return OPCODE_DIU;
13276 if (Field_op1_Slot_inst_get (insn) == 4)
13277 return OPCODE_DIWB;
13278 if (Field_op1_Slot_inst_get (insn) == 5)
13279 return OPCODE_DIWBI;
13280 if (Field_op1_Slot_inst_get (insn) == 15 &&
13281 Field_op2_Slot_inst_get (insn) == 0)
13282 return OPCODE_DIWBUI_P;
13283 }
13284 if (Field_t_Slot_inst_get (insn) == 12)
13285 return OPCODE_IPF;
13286 if (Field_t_Slot_inst_get (insn) == 13)
13287 {
13288 if (Field_op1_Slot_inst_get (insn) == 0)
13289 return OPCODE_IPFL;
13290 if (Field_op1_Slot_inst_get (insn) == 2)
13291 return OPCODE_IHU;
13292 if (Field_op1_Slot_inst_get (insn) == 3)
13293 return OPCODE_IIU;
13294 }
13295 if (Field_t_Slot_inst_get (insn) == 14)
13296 return OPCODE_IHI;
13297 if (Field_t_Slot_inst_get (insn) == 15)
13298 return OPCODE_III;
13299 }
13300 if (Field_r_Slot_inst_get (insn) == 9)
13301 return OPCODE_L16SI;
13302 if (Field_r_Slot_inst_get (insn) == 10)
13303 return OPCODE_MOVI;
13304 if (Field_r_Slot_inst_get (insn) == 11)
13305 return OPCODE_L32AI;
13306 if (Field_r_Slot_inst_get (insn) == 12)
13307 return OPCODE_ADDI;
13308 if (Field_r_Slot_inst_get (insn) == 13)
13309 return OPCODE_ADDMI;
13310 if (Field_r_Slot_inst_get (insn) == 14)
13311 return OPCODE_S32C1I;
13312 if (Field_r_Slot_inst_get (insn) == 15)
13313 return OPCODE_S32RI;
13314 }
13315 if (Field_op0_Slot_inst_get (insn) == 4)
13316 {
13317 if (Field_op2_Slot_inst_get (insn) == 0)
13318 {
13319 if (Field_op1_Slot_inst_get (insn) == 8 &&
13320 Field_t3_Slot_inst_get (insn) == 0 &&
13321 Field_tlo_Slot_inst_get (insn) == 0 &&
13322 Field_r3_Slot_inst_get (insn) == 0)
13323 return OPCODE_MULA_DD_LL_LDINC;
13324 if (Field_op1_Slot_inst_get (insn) == 9 &&
13325 Field_t3_Slot_inst_get (insn) == 0 &&
13326 Field_tlo_Slot_inst_get (insn) == 0 &&
13327 Field_r3_Slot_inst_get (insn) == 0)
13328 return OPCODE_MULA_DD_HL_LDINC;
13329 if (Field_op1_Slot_inst_get (insn) == 10 &&
13330 Field_t3_Slot_inst_get (insn) == 0 &&
13331 Field_tlo_Slot_inst_get (insn) == 0 &&
13332 Field_r3_Slot_inst_get (insn) == 0)
13333 return OPCODE_MULA_DD_LH_LDINC;
13334 if (Field_op1_Slot_inst_get (insn) == 11 &&
13335 Field_t3_Slot_inst_get (insn) == 0 &&
13336 Field_tlo_Slot_inst_get (insn) == 0 &&
13337 Field_r3_Slot_inst_get (insn) == 0)
13338 return OPCODE_MULA_DD_HH_LDINC;
13339 }
13340 if (Field_op2_Slot_inst_get (insn) == 1)
13341 {
13342 if (Field_op1_Slot_inst_get (insn) == 8 &&
13343 Field_t3_Slot_inst_get (insn) == 0 &&
13344 Field_tlo_Slot_inst_get (insn) == 0 &&
13345 Field_r3_Slot_inst_get (insn) == 0)
13346 return OPCODE_MULA_DD_LL_LDDEC;
13347 if (Field_op1_Slot_inst_get (insn) == 9 &&
13348 Field_t3_Slot_inst_get (insn) == 0 &&
13349 Field_tlo_Slot_inst_get (insn) == 0 &&
13350 Field_r3_Slot_inst_get (insn) == 0)
13351 return OPCODE_MULA_DD_HL_LDDEC;
13352 if (Field_op1_Slot_inst_get (insn) == 10 &&
13353 Field_t3_Slot_inst_get (insn) == 0 &&
13354 Field_tlo_Slot_inst_get (insn) == 0 &&
13355 Field_r3_Slot_inst_get (insn) == 0)
13356 return OPCODE_MULA_DD_LH_LDDEC;
13357 if (Field_op1_Slot_inst_get (insn) == 11 &&
13358 Field_t3_Slot_inst_get (insn) == 0 &&
13359 Field_tlo_Slot_inst_get (insn) == 0 &&
13360 Field_r3_Slot_inst_get (insn) == 0)
13361 return OPCODE_MULA_DD_HH_LDDEC;
13362 }
13363 if (Field_op2_Slot_inst_get (insn) == 2)
13364 {
13365 if (Field_op1_Slot_inst_get (insn) == 4 &&
13366 Field_s_Slot_inst_get (insn) == 0 &&
13367 Field_w_Slot_inst_get (insn) == 0 &&
13368 Field_r3_Slot_inst_get (insn) == 0 &&
13369 Field_t3_Slot_inst_get (insn) == 0 &&
13370 Field_tlo_Slot_inst_get (insn) == 0)
13371 return OPCODE_MUL_DD_LL;
13372 if (Field_op1_Slot_inst_get (insn) == 5 &&
13373 Field_s_Slot_inst_get (insn) == 0 &&
13374 Field_w_Slot_inst_get (insn) == 0 &&
13375 Field_r3_Slot_inst_get (insn) == 0 &&
13376 Field_t3_Slot_inst_get (insn) == 0 &&
13377 Field_tlo_Slot_inst_get (insn) == 0)
13378 return OPCODE_MUL_DD_HL;
13379 if (Field_op1_Slot_inst_get (insn) == 6 &&
13380 Field_s_Slot_inst_get (insn) == 0 &&
13381 Field_w_Slot_inst_get (insn) == 0 &&
13382 Field_r3_Slot_inst_get (insn) == 0 &&
13383 Field_t3_Slot_inst_get (insn) == 0 &&
13384 Field_tlo_Slot_inst_get (insn) == 0)
13385 return OPCODE_MUL_DD_LH;
13386 if (Field_op1_Slot_inst_get (insn) == 7 &&
13387 Field_s_Slot_inst_get (insn) == 0 &&
13388 Field_w_Slot_inst_get (insn) == 0 &&
13389 Field_r3_Slot_inst_get (insn) == 0 &&
13390 Field_t3_Slot_inst_get (insn) == 0 &&
13391 Field_tlo_Slot_inst_get (insn) == 0)
13392 return OPCODE_MUL_DD_HH;
13393 if (Field_op1_Slot_inst_get (insn) == 8 &&
13394 Field_s_Slot_inst_get (insn) == 0 &&
13395 Field_w_Slot_inst_get (insn) == 0 &&
13396 Field_r3_Slot_inst_get (insn) == 0 &&
13397 Field_t3_Slot_inst_get (insn) == 0 &&
13398 Field_tlo_Slot_inst_get (insn) == 0)
13399 return OPCODE_MULA_DD_LL;
13400 if (Field_op1_Slot_inst_get (insn) == 9 &&
13401 Field_s_Slot_inst_get (insn) == 0 &&
13402 Field_w_Slot_inst_get (insn) == 0 &&
13403 Field_r3_Slot_inst_get (insn) == 0 &&
13404 Field_t3_Slot_inst_get (insn) == 0 &&
13405 Field_tlo_Slot_inst_get (insn) == 0)
13406 return OPCODE_MULA_DD_HL;
13407 if (Field_op1_Slot_inst_get (insn) == 10 &&
13408 Field_s_Slot_inst_get (insn) == 0 &&
13409 Field_w_Slot_inst_get (insn) == 0 &&
13410 Field_r3_Slot_inst_get (insn) == 0 &&
13411 Field_t3_Slot_inst_get (insn) == 0 &&
13412 Field_tlo_Slot_inst_get (insn) == 0)
13413 return OPCODE_MULA_DD_LH;
13414 if (Field_op1_Slot_inst_get (insn) == 11 &&
13415 Field_s_Slot_inst_get (insn) == 0 &&
13416 Field_w_Slot_inst_get (insn) == 0 &&
13417 Field_r3_Slot_inst_get (insn) == 0 &&
13418 Field_t3_Slot_inst_get (insn) == 0 &&
13419 Field_tlo_Slot_inst_get (insn) == 0)
13420 return OPCODE_MULA_DD_HH;
13421 if (Field_op1_Slot_inst_get (insn) == 12 &&
13422 Field_s_Slot_inst_get (insn) == 0 &&
13423 Field_w_Slot_inst_get (insn) == 0 &&
13424 Field_r3_Slot_inst_get (insn) == 0 &&
13425 Field_t3_Slot_inst_get (insn) == 0 &&
13426 Field_tlo_Slot_inst_get (insn) == 0)
13427 return OPCODE_MULS_DD_LL;
13428 if (Field_op1_Slot_inst_get (insn) == 13 &&
13429 Field_s_Slot_inst_get (insn) == 0 &&
13430 Field_w_Slot_inst_get (insn) == 0 &&
13431 Field_r3_Slot_inst_get (insn) == 0 &&
13432 Field_t3_Slot_inst_get (insn) == 0 &&
13433 Field_tlo_Slot_inst_get (insn) == 0)
13434 return OPCODE_MULS_DD_HL;
13435 if (Field_op1_Slot_inst_get (insn) == 14 &&
13436 Field_s_Slot_inst_get (insn) == 0 &&
13437 Field_w_Slot_inst_get (insn) == 0 &&
13438 Field_r3_Slot_inst_get (insn) == 0 &&
13439 Field_t3_Slot_inst_get (insn) == 0 &&
13440 Field_tlo_Slot_inst_get (insn) == 0)
13441 return OPCODE_MULS_DD_LH;
13442 if (Field_op1_Slot_inst_get (insn) == 15 &&
13443 Field_s_Slot_inst_get (insn) == 0 &&
13444 Field_w_Slot_inst_get (insn) == 0 &&
13445 Field_r3_Slot_inst_get (insn) == 0 &&
13446 Field_t3_Slot_inst_get (insn) == 0 &&
13447 Field_tlo_Slot_inst_get (insn) == 0)
13448 return OPCODE_MULS_DD_HH;
13449 }
13450 if (Field_op2_Slot_inst_get (insn) == 3)
13451 {
13452 if (Field_op1_Slot_inst_get (insn) == 4 &&
13453 Field_r_Slot_inst_get (insn) == 0 &&
13454 Field_t3_Slot_inst_get (insn) == 0 &&
13455 Field_tlo_Slot_inst_get (insn) == 0)
13456 return OPCODE_MUL_AD_LL;
13457 if (Field_op1_Slot_inst_get (insn) == 5 &&
13458 Field_r_Slot_inst_get (insn) == 0 &&
13459 Field_t3_Slot_inst_get (insn) == 0 &&
13460 Field_tlo_Slot_inst_get (insn) == 0)
13461 return OPCODE_MUL_AD_HL;
13462 if (Field_op1_Slot_inst_get (insn) == 6 &&
13463 Field_r_Slot_inst_get (insn) == 0 &&
13464 Field_t3_Slot_inst_get (insn) == 0 &&
13465 Field_tlo_Slot_inst_get (insn) == 0)
13466 return OPCODE_MUL_AD_LH;
13467 if (Field_op1_Slot_inst_get (insn) == 7 &&
13468 Field_r_Slot_inst_get (insn) == 0 &&
13469 Field_t3_Slot_inst_get (insn) == 0 &&
13470 Field_tlo_Slot_inst_get (insn) == 0)
13471 return OPCODE_MUL_AD_HH;
13472 if (Field_op1_Slot_inst_get (insn) == 8 &&
13473 Field_r_Slot_inst_get (insn) == 0 &&
13474 Field_t3_Slot_inst_get (insn) == 0 &&
13475 Field_tlo_Slot_inst_get (insn) == 0)
13476 return OPCODE_MULA_AD_LL;
13477 if (Field_op1_Slot_inst_get (insn) == 9 &&
13478 Field_r_Slot_inst_get (insn) == 0 &&
13479 Field_t3_Slot_inst_get (insn) == 0 &&
13480 Field_tlo_Slot_inst_get (insn) == 0)
13481 return OPCODE_MULA_AD_HL;
13482 if (Field_op1_Slot_inst_get (insn) == 10 &&
13483 Field_r_Slot_inst_get (insn) == 0 &&
13484 Field_t3_Slot_inst_get (insn) == 0 &&
13485 Field_tlo_Slot_inst_get (insn) == 0)
13486 return OPCODE_MULA_AD_LH;
13487 if (Field_op1_Slot_inst_get (insn) == 11 &&
13488 Field_r_Slot_inst_get (insn) == 0 &&
13489 Field_t3_Slot_inst_get (insn) == 0 &&
13490 Field_tlo_Slot_inst_get (insn) == 0)
13491 return OPCODE_MULA_AD_HH;
13492 if (Field_op1_Slot_inst_get (insn) == 12 &&
13493 Field_r_Slot_inst_get (insn) == 0 &&
13494 Field_t3_Slot_inst_get (insn) == 0 &&
13495 Field_tlo_Slot_inst_get (insn) == 0)
13496 return OPCODE_MULS_AD_LL;
13497 if (Field_op1_Slot_inst_get (insn) == 13 &&
13498 Field_r_Slot_inst_get (insn) == 0 &&
13499 Field_t3_Slot_inst_get (insn) == 0 &&
13500 Field_tlo_Slot_inst_get (insn) == 0)
13501 return OPCODE_MULS_AD_HL;
13502 if (Field_op1_Slot_inst_get (insn) == 14 &&
13503 Field_r_Slot_inst_get (insn) == 0 &&
13504 Field_t3_Slot_inst_get (insn) == 0 &&
13505 Field_tlo_Slot_inst_get (insn) == 0)
13506 return OPCODE_MULS_AD_LH;
13507 if (Field_op1_Slot_inst_get (insn) == 15 &&
13508 Field_r_Slot_inst_get (insn) == 0 &&
13509 Field_t3_Slot_inst_get (insn) == 0 &&
13510 Field_tlo_Slot_inst_get (insn) == 0)
13511 return OPCODE_MULS_AD_HH;
13512 }
13513 if (Field_op2_Slot_inst_get (insn) == 4)
13514 {
13515 if (Field_op1_Slot_inst_get (insn) == 8 &&
13516 Field_r3_Slot_inst_get (insn) == 0)
13517 return OPCODE_MULA_DA_LL_LDINC;
13518 if (Field_op1_Slot_inst_get (insn) == 9 &&
13519 Field_r3_Slot_inst_get (insn) == 0)
13520 return OPCODE_MULA_DA_HL_LDINC;
13521 if (Field_op1_Slot_inst_get (insn) == 10 &&
13522 Field_r3_Slot_inst_get (insn) == 0)
13523 return OPCODE_MULA_DA_LH_LDINC;
13524 if (Field_op1_Slot_inst_get (insn) == 11 &&
13525 Field_r3_Slot_inst_get (insn) == 0)
13526 return OPCODE_MULA_DA_HH_LDINC;
13527 }
13528 if (Field_op2_Slot_inst_get (insn) == 5)
13529 {
13530 if (Field_op1_Slot_inst_get (insn) == 8 &&
13531 Field_r3_Slot_inst_get (insn) == 0)
13532 return OPCODE_MULA_DA_LL_LDDEC;
13533 if (Field_op1_Slot_inst_get (insn) == 9 &&
13534 Field_r3_Slot_inst_get (insn) == 0)
13535 return OPCODE_MULA_DA_HL_LDDEC;
13536 if (Field_op1_Slot_inst_get (insn) == 10 &&
13537 Field_r3_Slot_inst_get (insn) == 0)
13538 return OPCODE_MULA_DA_LH_LDDEC;
13539 if (Field_op1_Slot_inst_get (insn) == 11 &&
13540 Field_r3_Slot_inst_get (insn) == 0)
13541 return OPCODE_MULA_DA_HH_LDDEC;
13542 }
13543 if (Field_op2_Slot_inst_get (insn) == 6)
13544 {
13545 if (Field_op1_Slot_inst_get (insn) == 4 &&
13546 Field_s_Slot_inst_get (insn) == 0 &&
13547 Field_w_Slot_inst_get (insn) == 0 &&
13548 Field_r3_Slot_inst_get (insn) == 0)
13549 return OPCODE_MUL_DA_LL;
13550 if (Field_op1_Slot_inst_get (insn) == 5 &&
13551 Field_s_Slot_inst_get (insn) == 0 &&
13552 Field_w_Slot_inst_get (insn) == 0 &&
13553 Field_r3_Slot_inst_get (insn) == 0)
13554 return OPCODE_MUL_DA_HL;
13555 if (Field_op1_Slot_inst_get (insn) == 6 &&
13556 Field_s_Slot_inst_get (insn) == 0 &&
13557 Field_w_Slot_inst_get (insn) == 0 &&
13558 Field_r3_Slot_inst_get (insn) == 0)
13559 return OPCODE_MUL_DA_LH;
13560 if (Field_op1_Slot_inst_get (insn) == 7 &&
13561 Field_s_Slot_inst_get (insn) == 0 &&
13562 Field_w_Slot_inst_get (insn) == 0 &&
13563 Field_r3_Slot_inst_get (insn) == 0)
13564 return OPCODE_MUL_DA_HH;
13565 if (Field_op1_Slot_inst_get (insn) == 8 &&
13566 Field_s_Slot_inst_get (insn) == 0 &&
13567 Field_w_Slot_inst_get (insn) == 0 &&
13568 Field_r3_Slot_inst_get (insn) == 0)
13569 return OPCODE_MULA_DA_LL;
13570 if (Field_op1_Slot_inst_get (insn) == 9 &&
13571 Field_s_Slot_inst_get (insn) == 0 &&
13572 Field_w_Slot_inst_get (insn) == 0 &&
13573 Field_r3_Slot_inst_get (insn) == 0)
13574 return OPCODE_MULA_DA_HL;
13575 if (Field_op1_Slot_inst_get (insn) == 10 &&
13576 Field_s_Slot_inst_get (insn) == 0 &&
13577 Field_w_Slot_inst_get (insn) == 0 &&
13578 Field_r3_Slot_inst_get (insn) == 0)
13579 return OPCODE_MULA_DA_LH;
13580 if (Field_op1_Slot_inst_get (insn) == 11 &&
13581 Field_s_Slot_inst_get (insn) == 0 &&
13582 Field_w_Slot_inst_get (insn) == 0 &&
13583 Field_r3_Slot_inst_get (insn) == 0)
13584 return OPCODE_MULA_DA_HH;
13585 if (Field_op1_Slot_inst_get (insn) == 12 &&
13586 Field_s_Slot_inst_get (insn) == 0 &&
13587 Field_w_Slot_inst_get (insn) == 0 &&
13588 Field_r3_Slot_inst_get (insn) == 0)
13589 return OPCODE_MULS_DA_LL;
13590 if (Field_op1_Slot_inst_get (insn) == 13 &&
13591 Field_s_Slot_inst_get (insn) == 0 &&
13592 Field_w_Slot_inst_get (insn) == 0 &&
13593 Field_r3_Slot_inst_get (insn) == 0)
13594 return OPCODE_MULS_DA_HL;
13595 if (Field_op1_Slot_inst_get (insn) == 14 &&
13596 Field_s_Slot_inst_get (insn) == 0 &&
13597 Field_w_Slot_inst_get (insn) == 0 &&
13598 Field_r3_Slot_inst_get (insn) == 0)
13599 return OPCODE_MULS_DA_LH;
13600 if (Field_op1_Slot_inst_get (insn) == 15 &&
13601 Field_s_Slot_inst_get (insn) == 0 &&
13602 Field_w_Slot_inst_get (insn) == 0 &&
13603 Field_r3_Slot_inst_get (insn) == 0)
13604 return OPCODE_MULS_DA_HH;
13605 }
13606 if (Field_op2_Slot_inst_get (insn) == 7)
13607 {
13608 if (Field_op1_Slot_inst_get (insn) == 0 &&
13609 Field_r_Slot_inst_get (insn) == 0)
13610 return OPCODE_UMUL_AA_LL;
13611 if (Field_op1_Slot_inst_get (insn) == 1 &&
13612 Field_r_Slot_inst_get (insn) == 0)
13613 return OPCODE_UMUL_AA_HL;
13614 if (Field_op1_Slot_inst_get (insn) == 2 &&
13615 Field_r_Slot_inst_get (insn) == 0)
13616 return OPCODE_UMUL_AA_LH;
13617 if (Field_op1_Slot_inst_get (insn) == 3 &&
13618 Field_r_Slot_inst_get (insn) == 0)
13619 return OPCODE_UMUL_AA_HH;
13620 if (Field_op1_Slot_inst_get (insn) == 4 &&
13621 Field_r_Slot_inst_get (insn) == 0)
13622 return OPCODE_MUL_AA_LL;
13623 if (Field_op1_Slot_inst_get (insn) == 5 &&
13624 Field_r_Slot_inst_get (insn) == 0)
13625 return OPCODE_MUL_AA_HL;
13626 if (Field_op1_Slot_inst_get (insn) == 6 &&
13627 Field_r_Slot_inst_get (insn) == 0)
13628 return OPCODE_MUL_AA_LH;
13629 if (Field_op1_Slot_inst_get (insn) == 7 &&
13630 Field_r_Slot_inst_get (insn) == 0)
13631 return OPCODE_MUL_AA_HH;
13632 if (Field_op1_Slot_inst_get (insn) == 8 &&
13633 Field_r_Slot_inst_get (insn) == 0)
13634 return OPCODE_MULA_AA_LL;
13635 if (Field_op1_Slot_inst_get (insn) == 9 &&
13636 Field_r_Slot_inst_get (insn) == 0)
13637 return OPCODE_MULA_AA_HL;
13638 if (Field_op1_Slot_inst_get (insn) == 10 &&
13639 Field_r_Slot_inst_get (insn) == 0)
13640 return OPCODE_MULA_AA_LH;
13641 if (Field_op1_Slot_inst_get (insn) == 11 &&
13642 Field_r_Slot_inst_get (insn) == 0)
13643 return OPCODE_MULA_AA_HH;
13644 if (Field_op1_Slot_inst_get (insn) == 12 &&
13645 Field_r_Slot_inst_get (insn) == 0)
13646 return OPCODE_MULS_AA_LL;
13647 if (Field_op1_Slot_inst_get (insn) == 13 &&
13648 Field_r_Slot_inst_get (insn) == 0)
13649 return OPCODE_MULS_AA_HL;
13650 if (Field_op1_Slot_inst_get (insn) == 14 &&
13651 Field_r_Slot_inst_get (insn) == 0)
13652 return OPCODE_MULS_AA_LH;
13653 if (Field_op1_Slot_inst_get (insn) == 15 &&
13654 Field_r_Slot_inst_get (insn) == 0)
13655 return OPCODE_MULS_AA_HH;
13656 }
13657 if (Field_op2_Slot_inst_get (insn) == 8)
13658 {
13659 if (Field_op1_Slot_inst_get (insn) == 0 &&
13660 Field_t_Slot_inst_get (insn) == 0 &&
13661 Field_rhi_Slot_inst_get (insn) == 0)
13662 return OPCODE_LDINC;
13663 }
13664 if (Field_op2_Slot_inst_get (insn) == 9)
13665 {
13666 if (Field_op1_Slot_inst_get (insn) == 0 &&
13667 Field_t_Slot_inst_get (insn) == 0 &&
13668 Field_rhi_Slot_inst_get (insn) == 0)
13669 return OPCODE_LDDEC;
13670 }
13671 }
13672 if (Field_op0_Slot_inst_get (insn) == 5)
13673 {
13674 if (Field_n_Slot_inst_get (insn) == 0)
13675 return OPCODE_CALL0;
13676 if (Field_n_Slot_inst_get (insn) == 1)
13677 return OPCODE_CALL4;
13678 if (Field_n_Slot_inst_get (insn) == 2)
13679 return OPCODE_CALL8;
13680 if (Field_n_Slot_inst_get (insn) == 3)
13681 return OPCODE_CALL12;
13682 }
13683 if (Field_op0_Slot_inst_get (insn) == 6)
13684 {
13685 if (Field_n_Slot_inst_get (insn) == 0)
13686 return OPCODE_J;
13687 if (Field_n_Slot_inst_get (insn) == 1)
13688 {
13689 if (Field_m_Slot_inst_get (insn) == 0)
13690 return OPCODE_BEQZ;
13691 if (Field_m_Slot_inst_get (insn) == 1)
13692 return OPCODE_BNEZ;
13693 if (Field_m_Slot_inst_get (insn) == 2)
13694 return OPCODE_BLTZ;
13695 if (Field_m_Slot_inst_get (insn) == 3)
13696 return OPCODE_BGEZ;
13697 }
13698 if (Field_n_Slot_inst_get (insn) == 2)
13699 {
13700 if (Field_m_Slot_inst_get (insn) == 0)
13701 return OPCODE_BEQI;
13702 if (Field_m_Slot_inst_get (insn) == 1)
13703 return OPCODE_BNEI;
13704 if (Field_m_Slot_inst_get (insn) == 2)
13705 return OPCODE_BLTI;
13706 if (Field_m_Slot_inst_get (insn) == 3)
13707 return OPCODE_BGEI;
13708 }
13709 if (Field_n_Slot_inst_get (insn) == 3)
13710 {
13711 if (Field_m_Slot_inst_get (insn) == 0)
13712 return OPCODE_ENTRY;
13713 if (Field_m_Slot_inst_get (insn) == 1)
13714 {
13715 if (Field_r_Slot_inst_get (insn) == 8)
13716 return OPCODE_LOOP;
13717 if (Field_r_Slot_inst_get (insn) == 9)
13718 return OPCODE_LOOPNEZ;
13719 if (Field_r_Slot_inst_get (insn) == 10)
13720 return OPCODE_LOOPGTZ;
13721 }
13722 if (Field_m_Slot_inst_get (insn) == 2)
13723 return OPCODE_BLTUI;
13724 if (Field_m_Slot_inst_get (insn) == 3)
13725 return OPCODE_BGEUI;
13726 }
13727 }
13728 if (Field_op0_Slot_inst_get (insn) == 7)
13729 {
13730 if (Field_r_Slot_inst_get (insn) == 0)
13731 return OPCODE_BNONE;
13732 if (Field_r_Slot_inst_get (insn) == 1)
13733 return OPCODE_BEQ;
13734 if (Field_r_Slot_inst_get (insn) == 2)
13735 return OPCODE_BLT;
13736 if (Field_r_Slot_inst_get (insn) == 3)
13737 return OPCODE_BLTU;
13738 if (Field_r_Slot_inst_get (insn) == 4)
13739 return OPCODE_BALL;
13740 if (Field_r_Slot_inst_get (insn) == 5)
13741 return OPCODE_BBC;
13742 if ((Field_r_Slot_inst_get (insn) == 6 ||
13743 Field_r_Slot_inst_get (insn) == 7))
13744 return OPCODE_BBCI;
13745 if (Field_r_Slot_inst_get (insn) == 8)
13746 return OPCODE_BANY;
13747 if (Field_r_Slot_inst_get (insn) == 9)
13748 return OPCODE_BNE;
13749 if (Field_r_Slot_inst_get (insn) == 10)
13750 return OPCODE_BGE;
13751 if (Field_r_Slot_inst_get (insn) == 11)
13752 return OPCODE_BGEU;
13753 if (Field_r_Slot_inst_get (insn) == 12)
13754 return OPCODE_BNALL;
13755 if (Field_r_Slot_inst_get (insn) == 13)
13756 return OPCODE_BBS;
13757 if ((Field_r_Slot_inst_get (insn) == 14 ||
13758 Field_r_Slot_inst_get (insn) == 15))
13759 return OPCODE_BBSI;
13760 }
13761 return XTENSA_UNDEFINED;
13762}
13763
13764static int
13765Slot_inst16b_decode (const xtensa_insnbuf insn)
13766{
13767 if (Field_op0_Slot_inst16b_get (insn) == 12)
13768 {
13769 if (Field_i_Slot_inst16b_get (insn) == 0)
13770 return OPCODE_MOVI_N;
13771 if (Field_i_Slot_inst16b_get (insn) == 1)
13772 {
13773 if (Field_z_Slot_inst16b_get (insn) == 0)
13774 return OPCODE_BEQZ_N;
13775 if (Field_z_Slot_inst16b_get (insn) == 1)
13776 return OPCODE_BNEZ_N;
13777 }
13778 }
13779 if (Field_op0_Slot_inst16b_get (insn) == 13)
13780 {
13781 if (Field_r_Slot_inst16b_get (insn) == 0)
13782 return OPCODE_MOV_N;
13783 if (Field_r_Slot_inst16b_get (insn) == 15)
13784 {
13785 if (Field_t_Slot_inst16b_get (insn) == 0)
13786 return OPCODE_RET_N;
13787 if (Field_t_Slot_inst16b_get (insn) == 1)
13788 return OPCODE_RETW_N;
13789 if (Field_t_Slot_inst16b_get (insn) == 2)
13790 return OPCODE_BREAK_N;
13791 if (Field_t_Slot_inst16b_get (insn) == 3 &&
13792 Field_s_Slot_inst16b_get (insn) == 0)
13793 return OPCODE_NOP_N;
13794 if (Field_t_Slot_inst16b_get (insn) == 6 &&
13795 Field_s_Slot_inst16b_get (insn) == 0)
13796 return OPCODE_ILL_N;
13797 }
13798 }
13799 return XTENSA_UNDEFINED;
13800}
13801
13802static int
13803Slot_inst16a_decode (const xtensa_insnbuf insn)
13804{
13805 if (Field_op0_Slot_inst16a_get (insn) == 8)
13806 return OPCODE_L32I_N;
13807 if (Field_op0_Slot_inst16a_get (insn) == 9)
13808 return OPCODE_S32I_N;
13809 if (Field_op0_Slot_inst16a_get (insn) == 10)
13810 return OPCODE_ADD_N;
13811 if (Field_op0_Slot_inst16a_get (insn) == 11)
13812 return OPCODE_ADDI_N;
13813 return XTENSA_UNDEFINED;
13814}
13815
13816\f
13817/* Instruction slots. */
13818
13819static void
13820Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
13821 xtensa_insnbuf slotbuf)
13822{
13823 slotbuf[0] = (insn[0] & 0xffffff);
13824}
13825
13826static void
13827Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
13828 const xtensa_insnbuf slotbuf)
13829{
13830 insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
13831}
13832
13833static void
13834Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
13835 xtensa_insnbuf slotbuf)
13836{
13837 slotbuf[0] = (insn[0] & 0xffff);
13838}
13839
13840static void
13841Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
13842 const xtensa_insnbuf slotbuf)
13843{
13844 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
13845}
13846
13847static void
13848Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
13849 xtensa_insnbuf slotbuf)
13850{
13851 slotbuf[0] = (insn[0] & 0xffff);
13852}
13853
13854static void
13855Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
13856 const xtensa_insnbuf slotbuf)
13857{
13858 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
13859}
13860
13861static xtensa_get_field_fn
13862Slot_inst_get_field_fns[] = {
13863 Field_t_Slot_inst_get,
13864 Field_bbi4_Slot_inst_get,
13865 Field_bbi_Slot_inst_get,
13866 Field_imm12_Slot_inst_get,
13867 Field_imm8_Slot_inst_get,
13868 Field_s_Slot_inst_get,
13869 Field_imm12b_Slot_inst_get,
13870 Field_imm16_Slot_inst_get,
13871 Field_m_Slot_inst_get,
13872 Field_n_Slot_inst_get,
13873 Field_offset_Slot_inst_get,
13874 Field_op0_Slot_inst_get,
13875 Field_op1_Slot_inst_get,
13876 Field_op2_Slot_inst_get,
13877 Field_r_Slot_inst_get,
13878 Field_sa4_Slot_inst_get,
13879 Field_sae4_Slot_inst_get,
13880 Field_sae_Slot_inst_get,
13881 Field_sal_Slot_inst_get,
13882 Field_sargt_Slot_inst_get,
13883 Field_sas4_Slot_inst_get,
13884 Field_sas_Slot_inst_get,
13885 Field_sr_Slot_inst_get,
13886 Field_st_Slot_inst_get,
13887 Field_thi3_Slot_inst_get,
13888 Field_imm4_Slot_inst_get,
13889 Field_mn_Slot_inst_get,
13890 0,
13891 0,
13892 0,
13893 0,
13894 0,
13895 0,
13896 0,
13897 0,
13898 Field_r3_Slot_inst_get,
13899 Field_rbit2_Slot_inst_get,
13900 Field_rhi_Slot_inst_get,
13901 Field_t3_Slot_inst_get,
13902 Field_tbit2_Slot_inst_get,
13903 Field_tlo_Slot_inst_get,
13904 Field_w_Slot_inst_get,
13905 Field_y_Slot_inst_get,
13906 Field_x_Slot_inst_get,
13907 Field_xt_wbr15_imm_Slot_inst_get,
13908 Field_xt_wbr18_imm_Slot_inst_get,
13909 Field_bitindex_Slot_inst_get,
13910 Field_s3to1_Slot_inst_get,
13911 Implicit_Field_ar0_get,
13912 Implicit_Field_ar4_get,
13913 Implicit_Field_ar8_get,
13914 Implicit_Field_ar12_get,
13915 Implicit_Field_mr0_get,
13916 Implicit_Field_mr1_get,
13917 Implicit_Field_mr2_get,
13918 Implicit_Field_mr3_get
13919};
13920
13921static xtensa_set_field_fn
13922Slot_inst_set_field_fns[] = {
13923 Field_t_Slot_inst_set,
13924 Field_bbi4_Slot_inst_set,
13925 Field_bbi_Slot_inst_set,
13926 Field_imm12_Slot_inst_set,
13927 Field_imm8_Slot_inst_set,
13928 Field_s_Slot_inst_set,
13929 Field_imm12b_Slot_inst_set,
13930 Field_imm16_Slot_inst_set,
13931 Field_m_Slot_inst_set,
13932 Field_n_Slot_inst_set,
13933 Field_offset_Slot_inst_set,
13934 Field_op0_Slot_inst_set,
13935 Field_op1_Slot_inst_set,
13936 Field_op2_Slot_inst_set,
13937 Field_r_Slot_inst_set,
13938 Field_sa4_Slot_inst_set,
13939 Field_sae4_Slot_inst_set,
13940 Field_sae_Slot_inst_set,
13941 Field_sal_Slot_inst_set,
13942 Field_sargt_Slot_inst_set,
13943 Field_sas4_Slot_inst_set,
13944 Field_sas_Slot_inst_set,
13945 Field_sr_Slot_inst_set,
13946 Field_st_Slot_inst_set,
13947 Field_thi3_Slot_inst_set,
13948 Field_imm4_Slot_inst_set,
13949 Field_mn_Slot_inst_set,
13950 0,
13951 0,
13952 0,
13953 0,
13954 0,
13955 0,
13956 0,
13957 0,
13958 Field_r3_Slot_inst_set,
13959 Field_rbit2_Slot_inst_set,
13960 Field_rhi_Slot_inst_set,
13961 Field_t3_Slot_inst_set,
13962 Field_tbit2_Slot_inst_set,
13963 Field_tlo_Slot_inst_set,
13964 Field_w_Slot_inst_set,
13965 Field_y_Slot_inst_set,
13966 Field_x_Slot_inst_set,
13967 Field_xt_wbr15_imm_Slot_inst_set,
13968 Field_xt_wbr18_imm_Slot_inst_set,
13969 Field_bitindex_Slot_inst_set,
13970 Field_s3to1_Slot_inst_set,
13971 Implicit_Field_set,
13972 Implicit_Field_set,
13973 Implicit_Field_set,
13974 Implicit_Field_set,
13975 Implicit_Field_set,
13976 Implicit_Field_set,
13977 Implicit_Field_set,
13978 Implicit_Field_set
13979};
13980
13981static xtensa_get_field_fn
13982Slot_inst16a_get_field_fns[] = {
13983 Field_t_Slot_inst16a_get,
13984 0,
13985 0,
13986 0,
13987 0,
13988 Field_s_Slot_inst16a_get,
13989 0,
13990 0,
13991 0,
13992 0,
13993 0,
13994 Field_op0_Slot_inst16a_get,
13995 0,
13996 0,
13997 Field_r_Slot_inst16a_get,
13998 0,
13999 0,
14000 0,
14001 0,
14002 0,
14003 0,
14004 0,
14005 Field_sr_Slot_inst16a_get,
14006 Field_st_Slot_inst16a_get,
14007 0,
14008 Field_imm4_Slot_inst16a_get,
14009 0,
14010 Field_i_Slot_inst16a_get,
14011 Field_imm6lo_Slot_inst16a_get,
14012 Field_imm6hi_Slot_inst16a_get,
14013 Field_imm7lo_Slot_inst16a_get,
14014 Field_imm7hi_Slot_inst16a_get,
14015 Field_z_Slot_inst16a_get,
14016 Field_imm6_Slot_inst16a_get,
14017 Field_imm7_Slot_inst16a_get,
14018 0,
14019 0,
14020 0,
14021 0,
14022 0,
14023 0,
14024 0,
14025 0,
14026 0,
14027 0,
14028 0,
14029 Field_bitindex_Slot_inst16a_get,
14030 Field_s3to1_Slot_inst16a_get,
14031 Implicit_Field_ar0_get,
14032 Implicit_Field_ar4_get,
14033 Implicit_Field_ar8_get,
14034 Implicit_Field_ar12_get,
14035 Implicit_Field_mr0_get,
14036 Implicit_Field_mr1_get,
14037 Implicit_Field_mr2_get,
14038 Implicit_Field_mr3_get
14039};
14040
14041static xtensa_set_field_fn
14042Slot_inst16a_set_field_fns[] = {
14043 Field_t_Slot_inst16a_set,
14044 0,
14045 0,
14046 0,
14047 0,
14048 Field_s_Slot_inst16a_set,
14049 0,
14050 0,
14051 0,
14052 0,
14053 0,
14054 Field_op0_Slot_inst16a_set,
14055 0,
14056 0,
14057 Field_r_Slot_inst16a_set,
14058 0,
14059 0,
14060 0,
14061 0,
14062 0,
14063 0,
14064 0,
14065 Field_sr_Slot_inst16a_set,
14066 Field_st_Slot_inst16a_set,
14067 0,
14068 Field_imm4_Slot_inst16a_set,
14069 0,
14070 Field_i_Slot_inst16a_set,
14071 Field_imm6lo_Slot_inst16a_set,
14072 Field_imm6hi_Slot_inst16a_set,
14073 Field_imm7lo_Slot_inst16a_set,
14074 Field_imm7hi_Slot_inst16a_set,
14075 Field_z_Slot_inst16a_set,
14076 Field_imm6_Slot_inst16a_set,
14077 Field_imm7_Slot_inst16a_set,
14078 0,
14079 0,
14080 0,
14081 0,
14082 0,
14083 0,
14084 0,
14085 0,
14086 0,
14087 0,
14088 0,
14089 Field_bitindex_Slot_inst16a_set,
14090 Field_s3to1_Slot_inst16a_set,
14091 Implicit_Field_set,
14092 Implicit_Field_set,
14093 Implicit_Field_set,
14094 Implicit_Field_set,
14095 Implicit_Field_set,
14096 Implicit_Field_set,
14097 Implicit_Field_set,
14098 Implicit_Field_set
14099};
14100
14101static xtensa_get_field_fn
14102Slot_inst16b_get_field_fns[] = {
14103 Field_t_Slot_inst16b_get,
14104 0,
14105 0,
14106 0,
14107 0,
14108 Field_s_Slot_inst16b_get,
14109 0,
14110 0,
14111 0,
14112 0,
14113 0,
14114 Field_op0_Slot_inst16b_get,
14115 0,
14116 0,
14117 Field_r_Slot_inst16b_get,
14118 0,
14119 0,
14120 0,
14121 0,
14122 0,
14123 0,
14124 0,
14125 Field_sr_Slot_inst16b_get,
14126 Field_st_Slot_inst16b_get,
14127 0,
14128 Field_imm4_Slot_inst16b_get,
14129 0,
14130 Field_i_Slot_inst16b_get,
14131 Field_imm6lo_Slot_inst16b_get,
14132 Field_imm6hi_Slot_inst16b_get,
14133 Field_imm7lo_Slot_inst16b_get,
14134 Field_imm7hi_Slot_inst16b_get,
14135 Field_z_Slot_inst16b_get,
14136 Field_imm6_Slot_inst16b_get,
14137 Field_imm7_Slot_inst16b_get,
14138 0,
14139 0,
14140 0,
14141 0,
14142 0,
14143 0,
14144 0,
14145 0,
14146 0,
14147 0,
14148 0,
14149 Field_bitindex_Slot_inst16b_get,
14150 Field_s3to1_Slot_inst16b_get,
14151 Implicit_Field_ar0_get,
14152 Implicit_Field_ar4_get,
14153 Implicit_Field_ar8_get,
14154 Implicit_Field_ar12_get,
14155 Implicit_Field_mr0_get,
14156 Implicit_Field_mr1_get,
14157 Implicit_Field_mr2_get,
14158 Implicit_Field_mr3_get
14159};
14160
14161static xtensa_set_field_fn
14162Slot_inst16b_set_field_fns[] = {
14163 Field_t_Slot_inst16b_set,
14164 0,
14165 0,
14166 0,
14167 0,
14168 Field_s_Slot_inst16b_set,
14169 0,
14170 0,
14171 0,
14172 0,
14173 0,
14174 Field_op0_Slot_inst16b_set,
14175 0,
14176 0,
14177 Field_r_Slot_inst16b_set,
14178 0,
14179 0,
14180 0,
14181 0,
14182 0,
14183 0,
14184 0,
14185 Field_sr_Slot_inst16b_set,
14186 Field_st_Slot_inst16b_set,
14187 0,
14188 Field_imm4_Slot_inst16b_set,
14189 0,
14190 Field_i_Slot_inst16b_set,
14191 Field_imm6lo_Slot_inst16b_set,
14192 Field_imm6hi_Slot_inst16b_set,
14193 Field_imm7lo_Slot_inst16b_set,
14194 Field_imm7hi_Slot_inst16b_set,
14195 Field_z_Slot_inst16b_set,
14196 Field_imm6_Slot_inst16b_set,
14197 Field_imm7_Slot_inst16b_set,
14198 0,
14199 0,
14200 0,
14201 0,
14202 0,
14203 0,
14204 0,
14205 0,
14206 0,
14207 0,
14208 0,
14209 Field_bitindex_Slot_inst16b_set,
14210 Field_s3to1_Slot_inst16b_set,
14211 Implicit_Field_set,
14212 Implicit_Field_set,
14213 Implicit_Field_set,
14214 Implicit_Field_set,
14215 Implicit_Field_set,
14216 Implicit_Field_set,
14217 Implicit_Field_set,
14218 Implicit_Field_set
14219};
14220
14221static xtensa_slot_internal slots[] = {
14222 { "Inst", "x24", 0,
14223 Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
14224 Slot_inst_get_field_fns, Slot_inst_set_field_fns,
14225 Slot_inst_decode, "nop" },
14226 { "Inst16a", "x16a", 0,
14227 Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
14228 Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
14229 Slot_inst16a_decode, "" },
14230 { "Inst16b", "x16b", 0,
14231 Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
14232 Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
14233 Slot_inst16b_decode, "nop.n" }
14234};
14235
14236\f
14237/* Instruction formats. */
14238
14239static void
14240Format_x24_encode (xtensa_insnbuf insn)
14241{
14242 insn[0] = 0;
14243}
14244
14245static void
14246Format_x16a_encode (xtensa_insnbuf insn)
14247{
14248 insn[0] = 0x8;
14249}
14250
14251static void
14252Format_x16b_encode (xtensa_insnbuf insn)
14253{
14254 insn[0] = 0xc;
14255}
14256
14257static int Format_x24_slots[] = { 0 };
14258
14259static int Format_x16a_slots[] = { 1 };
14260
14261static int Format_x16b_slots[] = { 2 };
14262
14263static xtensa_format_internal formats[] = {
14264 { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
14265 { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
14266 { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
14267};
14268
14269
14270static int
14271format_decoder (const xtensa_insnbuf insn)
14272{
14273 if ((insn[0] & 0x8) == 0)
14274 return 0; /* x24 */
14275 if ((insn[0] & 0xc) == 0x8)
14276 return 1; /* x16a */
14277 if ((insn[0] & 0xe) == 0xc)
14278 return 2; /* x16b */
14279 return -1;
14280}
14281
14282static int length_table[256] = {
14283 3,
14284 3,
14285 3,
14286 3,
14287 3,
14288 3,
14289 3,
14290 3,
14291 2,
14292 2,
14293 2,
14294 2,
14295 2,
14296 2,
14297 -1,
14298 -1,
14299 3,
14300 3,
14301 3,
14302 3,
14303 3,
14304 3,
14305 3,
14306 3,
14307 2,
14308 2,
14309 2,
14310 2,
14311 2,
14312 2,
14313 -1,
14314 -1,
14315 3,
14316 3,
14317 3,
14318 3,
14319 3,
14320 3,
14321 3,
14322 3,
14323 2,
14324 2,
14325 2,
14326 2,
14327 2,
14328 2,
14329 -1,
14330 -1,
14331 3,
14332 3,
14333 3,
14334 3,
14335 3,
14336 3,
14337 3,
14338 3,
14339 2,
14340 2,
14341 2,
14342 2,
14343 2,
14344 2,
14345 -1,
14346 -1,
14347 3,
14348 3,
14349 3,
14350 3,
14351 3,
14352 3,
14353 3,
14354 3,
14355 2,
14356 2,
14357 2,
14358 2,
14359 2,
14360 2,
14361 -1,
14362 -1,
14363 3,
14364 3,
14365 3,
14366 3,
14367 3,
14368 3,
14369 3,
14370 3,
14371 2,
14372 2,
14373 2,
14374 2,
14375 2,
14376 2,
14377 -1,
14378 -1,
14379 3,
14380 3,
14381 3,
14382 3,
14383 3,
14384 3,
14385 3,
14386 3,
14387 2,
14388 2,
14389 2,
14390 2,
14391 2,
14392 2,
14393 -1,
14394 -1,
14395 3,
14396 3,
14397 3,
14398 3,
14399 3,
14400 3,
14401 3,
14402 3,
14403 2,
14404 2,
14405 2,
14406 2,
14407 2,
14408 2,
14409 -1,
14410 -1,
14411 3,
14412 3,
14413 3,
14414 3,
14415 3,
14416 3,
14417 3,
14418 3,
14419 2,
14420 2,
14421 2,
14422 2,
14423 2,
14424 2,
14425 -1,
14426 -1,
14427 3,
14428 3,
14429 3,
14430 3,
14431 3,
14432 3,
14433 3,
14434 3,
14435 2,
14436 2,
14437 2,
14438 2,
14439 2,
14440 2,
14441 -1,
14442 -1,
14443 3,
14444 3,
14445 3,
14446 3,
14447 3,
14448 3,
14449 3,
14450 3,
14451 2,
14452 2,
14453 2,
14454 2,
14455 2,
14456 2,
14457 -1,
14458 -1,
14459 3,
14460 3,
14461 3,
14462 3,
14463 3,
14464 3,
14465 3,
14466 3,
14467 2,
14468 2,
14469 2,
14470 2,
14471 2,
14472 2,
14473 -1,
14474 -1,
14475 3,
14476 3,
14477 3,
14478 3,
14479 3,
14480 3,
14481 3,
14482 3,
14483 2,
14484 2,
14485 2,
14486 2,
14487 2,
14488 2,
14489 -1,
14490 -1,
14491 3,
14492 3,
14493 3,
14494 3,
14495 3,
14496 3,
14497 3,
14498 3,
14499 2,
14500 2,
14501 2,
14502 2,
14503 2,
14504 2,
14505 -1,
14506 -1,
14507 3,
14508 3,
14509 3,
14510 3,
14511 3,
14512 3,
14513 3,
14514 3,
14515 2,
14516 2,
14517 2,
14518 2,
14519 2,
14520 2,
14521 -1,
14522 -1,
14523 3,
14524 3,
14525 3,
14526 3,
14527 3,
14528 3,
14529 3,
14530 3,
14531 2,
14532 2,
14533 2,
14534 2,
14535 2,
14536 2,
14537 -1,
14538 -1
14539};
14540
14541static int
14542length_decoder (const unsigned char *insn)
14543{
14544 int l = insn[0];
14545 return length_table[l];
14546}
14547
14548\f
14549/* Top-level ISA structure. */
14550
14551xtensa_isa_internal xtensa_modules = {
14552 0 /* little-endian */,
14553 3 /* insn_size */, 0,
14554 3, formats, format_decoder, length_decoder,
14555 3, slots,
14556 56 /* num_fields */,
14557 94, operands,
14558 313, iclasses,
14559 439, opcodes, 0,
14560 2, regfiles,
14561 NUM_STATES, states, 0,
14562 NUM_SYSREGS, sysregs, 0,
14563 { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
14564 6, interfaces, 0,
14565 0, funcUnits, 0
14566};
Empty description
This page took 1.491233 seconds and 4 git commands to generate.