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[PATCH] alpha: fix linux syscall convention
[qemu.git] / hw / spitz.c
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b00052e4
AZ		 1/*
2 * PXA270-based Clamshell PDA platforms.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <[email protected]>
6 *
7 * This code is licensed under the GNU GPL v2.
8 */
9
87ecb68b
PB		 10#include "hw.h"
11#include "pxa.h"
12#include "arm-misc.h"
13#include "sysemu.h"
14#include "pcmcia.h"
15#include "i2c.h"
16#include "flash.h"
17#include "qemu-timer.h"
18#include "devices.h"
e33d8cdb 19#include "sharpsl.h"
87ecb68b
PB		 20#include "console.h"
21#include "block.h"
22#include "audio/audio.h"
23#include "boards.h"
b00052e4 24
b00052e4 25#undef REG_FMT
444ce241
FB		 26#if TARGET_PHYS_ADDR_BITS == 32
27#define REG_FMT "0x%02x"
28#else
b00052e4 29#define REG_FMT "0x%02lx"
444ce241 30#endif
b00052e4
AZ		 31
32/* Spitz Flash */
33#define FLASH_BASE 0x0c000000
34#define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */
35#define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */
36#define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */
37#define FLASH_ECCCNTR 0x0c /* ECC byte counter */
38#define FLASH_ECCCLRR 0x10 /* Clear ECC */
39#define FLASH_FLASHIO 0x14 /* Flash I/O */
40#define FLASH_FLASHCTL 0x18 /* Flash Control */
41
42#define FLASHCTL_CE0 (1 << 0)
43#define FLASHCTL_CLE (1 << 1)
44#define FLASHCTL_ALE (1 << 2)
45#define FLASHCTL_WP (1 << 3)
46#define FLASHCTL_CE1 (1 << 4)
47#define FLASHCTL_RYBY (1 << 5)
48#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
49
50struct sl_nand_s {
51 target_phys_addr_t target_base;
52 struct nand_flash_s *nand;
53 uint8_t ctl;
54 struct ecc_state_s ecc;
55};
56
57static uint32_t sl_readb(void *opaque, target_phys_addr_t addr)
58{
59 struct sl_nand_s *s = (struct sl_nand_s *) opaque;
60 int ryby;
61 addr -= s->target_base;
62
63 switch (addr) {
64#define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
65 case FLASH_ECCLPLB:
66 return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
67 BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
68
69#define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to))
70 case FLASH_ECCLPUB:
71 return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
72 BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
73
74 case FLASH_ECCCP:
75 return s->ecc.cp;
76
77 case FLASH_ECCCNTR:
78 return s->ecc.count & 0xff;
79
80 case FLASH_FLASHCTL:
81 nand_getpins(s->nand, &ryby);
82 if (ryby)
83 return s->ctl | FLASHCTL_RYBY;
84 else
85 return s->ctl;
86
87 case FLASH_FLASHIO:
88 return ecc_digest(&s->ecc, nand_getio(s->nand));
89
90 default:
89cdb6af 91 zaurus_printf("Bad register offset " REG_FMT "\n", addr);
b00052e4
AZ		 92 }
93 return 0;
94}
95
a5236105
AZ		 96static uint32_t sl_readl(void *opaque, target_phys_addr_t addr)
97{
98 struct sl_nand_s *s = (struct sl_nand_s *) opaque;
99 addr -= s->target_base;
100
101 if (addr == FLASH_FLASHIO)
102 return ecc_digest(&s->ecc, nand_getio(s->nand)) |
103 (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16);
104
105 return sl_readb(opaque, addr);
106}
107
b00052e4
AZ		 108static void sl_writeb(void *opaque, target_phys_addr_t addr,
109 uint32_t value)
110{
111 struct sl_nand_s *s = (struct sl_nand_s *) opaque;
112 addr -= s->target_base;
113
114 switch (addr) {
115 case FLASH_ECCCLRR:
116 /* Value is ignored. */
117 ecc_reset(&s->ecc);
118 break;
119
120 case FLASH_FLASHCTL:
121 s->ctl = value & 0xff & ~FLASHCTL_RYBY;
122 nand_setpins(s->nand,
123 s->ctl & FLASHCTL_CLE,
124 s->ctl & FLASHCTL_ALE,
125 s->ctl & FLASHCTL_NCE,
126 s->ctl & FLASHCTL_WP,
127 0);
128 break;
129
130 case FLASH_FLASHIO:
131 nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff));
132 break;
133
134 default:
89cdb6af 135 zaurus_printf("Bad register offset " REG_FMT "\n", addr);
b00052e4
AZ		 136 }
137}
138
aa941b94
AZ		 139static void sl_save(QEMUFile *f, void *opaque)
140{
141 struct sl_nand_s *s = (struct sl_nand_s *) opaque;
142
143 qemu_put_8s(f, &s->ctl);
144 ecc_put(f, &s->ecc);
145}
146
147static int sl_load(QEMUFile *f, void *opaque, int version_id)
148{
149 struct sl_nand_s *s = (struct sl_nand_s *) opaque;
150
151 qemu_get_8s(f, &s->ctl);
152 ecc_get(f, &s->ecc);
153
154 return 0;
155}
156
b00052e4
AZ		 157enum {
158 FLASH_128M,
159 FLASH_1024M,
160};
161
162static void sl_flash_register(struct pxa2xx_state_s *cpu, int size)
163{
164 int iomemtype;
165 struct sl_nand_s *s;
166 CPUReadMemoryFunc *sl_readfn[] = {
167 sl_readb,
168 sl_readb,
a5236105 169 sl_readl,
b00052e4
AZ		 170 };
171 CPUWriteMemoryFunc *sl_writefn[] = {
172 sl_writeb,
173 sl_writeb,
174 sl_writeb,
175 };
176
177 s = (struct sl_nand_s *) qemu_mallocz(sizeof(struct sl_nand_s));
178 s->target_base = FLASH_BASE;
179 s->ctl = 0;
180 if (size == FLASH_128M)
181 s->nand = nand_init(NAND_MFR_SAMSUNG, 0x73);
182 else if (size == FLASH_1024M)
183 s->nand = nand_init(NAND_MFR_SAMSUNG, 0xf1);
184
185 iomemtype = cpu_register_io_memory(0, sl_readfn,
186 sl_writefn, s);
187 cpu_register_physical_memory(s->target_base, 0x40, iomemtype);
aa941b94
AZ		 188
189 register_savevm("sl_flash", 0, 0, sl_save, sl_load, s);
b00052e4
AZ		 190}
191
192/* Spitz Keyboard */
193
194#define SPITZ_KEY_STROBE_NUM 11
195#define SPITZ_KEY_SENSE_NUM 7
196
197static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
198 12, 17, 91, 34, 36, 38, 39
199};
200
201static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = {
202 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114
203};
204
205/* Eighth additional row maps the special keys */
206static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
207 { 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 },
208 { -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 },
209 { 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25, -1 , -1 , -1 },
210 { 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26, -1 , 0x36, -1 },
211 { 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34, -1 , 0x1c, 0x2a, -1 },
2b76bdc9
AZ		 212 { 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33, -1 , 0x48, -1 , -1 , 0x38 },
213 { 0x37, 0x3d, -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d, -1 , -1 },
b00052e4
AZ		 214 { 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 },
215};
216
217#define SPITZ_GPIO_AK_INT 13 /* Remote control */
218#define SPITZ_GPIO_SYNC 16 /* Sync button */
219#define SPITZ_GPIO_ON_KEY 95 /* Power button */
220#define SPITZ_GPIO_SWA 97 /* Lid */
221#define SPITZ_GPIO_SWB 96 /* Tablet mode */
222
223/* The special buttons are mapped to unused keys */
224static const int spitz_gpiomap[5] = {
225 SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY,
226 SPITZ_GPIO_SWA, SPITZ_GPIO_SWB,
227};
228static int spitz_gpio_invert[5] = { 0, 0, 0, 0, 0, };
229
230struct spitz_keyboard_s {
38641a52
AZ		 231 qemu_irq sense[SPITZ_KEY_SENSE_NUM];
232 qemu_irq *strobe;
233 qemu_irq gpiomap[5];
b00052e4
AZ		 234 int keymap[0x80];
235 uint16_t keyrow[SPITZ_KEY_SENSE_NUM];
236 uint16_t strobe_state;
237 uint16_t sense_state;
238
239 uint16_t pre_map[0x100];
240 uint16_t modifiers;
241 uint16_t imodifiers;
242 uint8_t fifo[16];
243 int fifopos, fifolen;
244 QEMUTimer *kbdtimer;
245};
246
247static void spitz_keyboard_sense_update(struct spitz_keyboard_s *s)
248{
249 int i;
250 uint16_t strobe, sense = 0;
251 for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) {
252 strobe = s->keyrow[i] & s->strobe_state;
253 if (strobe) {
254 sense |= 1 << i;
255 if (!(s->sense_state & (1 << i)))
38641a52 256 qemu_irq_raise(s->sense[i]);
b00052e4 257 } else if (s->sense_state & (1 << i))
38641a52 258 qemu_irq_lower(s->sense[i]);
b00052e4
AZ		 259 }
260
261 s->sense_state = sense;
262}
263
38641a52 264static void spitz_keyboard_strobe(void *opaque, int line, int level)
b00052e4 265{
38641a52
AZ		 266 struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
267
268 if (level)
269 s->strobe_state |= 1 << line;
270 else
271 s->strobe_state &= ~(1 << line);
272 spitz_keyboard_sense_update(s);
b00052e4
AZ		 273}
274
275static void spitz_keyboard_keydown(struct spitz_keyboard_s *s, int keycode)
276{
277 int spitz_keycode = s->keymap[keycode & 0x7f];
278 if (spitz_keycode == -1)
279 return;
280
281 /* Handle the additional keys */
282 if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) {
38641a52 283 qemu_set_irq(s->gpiomap[spitz_keycode & 0xf], (keycode < 0x80) ^
b00052e4
AZ		 284 spitz_gpio_invert[spitz_keycode & 0xf]);
285 return;
286 }
287
288 if (keycode & 0x80)
289 s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf));
290 else
291 s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf);
292
293 spitz_keyboard_sense_update(s);
294}
295
296#define SHIFT (1 << 7)
297#define CTRL (1 << 8)
298#define FN (1 << 9)
299
300#define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
301
302static void spitz_keyboard_handler(struct spitz_keyboard_s *s, int keycode)
303{
304 uint16_t code;
305 int mapcode;
306 switch (keycode) {
307 case 0x2a: /* Left Shift */
308 s->modifiers |= 1;
309 break;
310 case 0xaa:
311 s->modifiers &= ~1;
312 break;
313 case 0x36: /* Right Shift */
314 s->modifiers |= 2;
315 break;
316 case 0xb6:
317 s->modifiers &= ~2;
318 break;
319 case 0x1d: /* Control */
320 s->modifiers |= 4;
321 break;
322 case 0x9d:
323 s->modifiers &= ~4;
324 break;
325 case 0x38: /* Alt */
326 s->modifiers |= 8;
327 break;
328 case 0xb8:
329 s->modifiers &= ~8;
330 break;
331 }
332
333 code = s->pre_map[mapcode = ((s->modifiers & 3) ?
334 (keycode | SHIFT) :
335 (keycode & ~SHIFT))];
336
337 if (code != mapcode) {
338#if 0
339 if ((code & SHIFT) && !(s->modifiers & 1))
340 QUEUE_KEY(0x2a | (keycode & 0x80));
341 if ((code & CTRL ) && !(s->modifiers & 4))
342 QUEUE_KEY(0x1d | (keycode & 0x80));
343 if ((code & FN ) && !(s->modifiers & 8))
344 QUEUE_KEY(0x38 | (keycode & 0x80));
345 if ((code & FN ) && (s->modifiers & 1))
346 QUEUE_KEY(0x2a | (~keycode & 0x80));
347 if ((code & FN ) && (s->modifiers & 2))
348 QUEUE_KEY(0x36 | (~keycode & 0x80));
349#else
350 if (keycode & 0x80) {
351 if ((s->imodifiers & 1 ) && !(s->modifiers & 1))
352 QUEUE_KEY(0x2a | 0x80);
353 if ((s->imodifiers & 4 ) && !(s->modifiers & 4))
354 QUEUE_KEY(0x1d | 0x80);
355 if ((s->imodifiers & 8 ) && !(s->modifiers & 8))
356 QUEUE_KEY(0x38 | 0x80);
357 if ((s->imodifiers & 0x10) && (s->modifiers & 1))
358 QUEUE_KEY(0x2a);
359 if ((s->imodifiers & 0x20) && (s->modifiers & 2))
360 QUEUE_KEY(0x36);
361 s->imodifiers = 0;
362 } else {
363 if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) {
364 QUEUE_KEY(0x2a);
365 s->imodifiers |= 1;
366 }
367 if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) {
368 QUEUE_KEY(0x1d);
369 s->imodifiers |= 4;
370 }
371 if ((code & FN ) && !((s->modifiers | s->imodifiers) & 8)) {
372 QUEUE_KEY(0x38);
373 s->imodifiers |= 8;
374 }
375 if ((code & FN ) && (s->modifiers & 1) &&
376 !(s->imodifiers & 0x10)) {
377 QUEUE_KEY(0x2a | 0x80);
378 s->imodifiers |= 0x10;
379 }
380 if ((code & FN ) && (s->modifiers & 2) &&
381 !(s->imodifiers & 0x20)) {
382 QUEUE_KEY(0x36 | 0x80);
383 s->imodifiers |= 0x20;
384 }
385 }
386#endif
387 }
388
389 QUEUE_KEY((code & 0x7f) | (keycode & 0x80));
390}
391
392static void spitz_keyboard_tick(void *opaque)
393{
394 struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
395
396 if (s->fifolen) {
397 spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]);
398 s->fifolen --;
399 if (s->fifopos >= 16)
400 s->fifopos = 0;
401 }
402
403 qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) + ticks_per_sec / 32);
404}
405
406static void spitz_keyboard_pre_map(struct spitz_keyboard_s *s)
407{
408 int i;
409 for (i = 0; i < 0x100; i ++)
410 s->pre_map[i] = i;
411 s->pre_map[0x02 | SHIFT ] = 0x02 | SHIFT; /* exclam */
412 s->pre_map[0x28 | SHIFT ] = 0x03 | SHIFT; /* quotedbl */
413 s->pre_map[0x04 | SHIFT ] = 0x04 | SHIFT; /* numbersign */
414 s->pre_map[0x05 | SHIFT ] = 0x05 | SHIFT; /* dollar */
415 s->pre_map[0x06 | SHIFT ] = 0x06 | SHIFT; /* percent */
416 s->pre_map[0x08 | SHIFT ] = 0x07 | SHIFT; /* ampersand */
417 s->pre_map[0x28 ] = 0x08 | SHIFT; /* apostrophe */
418 s->pre_map[0x0a | SHIFT ] = 0x09 | SHIFT; /* parenleft */
419 s->pre_map[0x0b | SHIFT ] = 0x0a | SHIFT; /* parenright */
420 s->pre_map[0x29 | SHIFT ] = 0x0b | SHIFT; /* asciitilde */
421 s->pre_map[0x03 | SHIFT ] = 0x0c | SHIFT; /* at */
422 s->pre_map[0xd3 ] = 0x0e | FN; /* Delete */
423 s->pre_map[0x3a ] = 0x0f | FN; /* Caps_Lock */
424 s->pre_map[0x07 | SHIFT ] = 0x11 | FN; /* asciicircum */
425 s->pre_map[0x0d ] = 0x12 | FN; /* equal */
426 s->pre_map[0x0d | SHIFT ] = 0x13 | FN; /* plus */
427 s->pre_map[0x1a ] = 0x14 | FN; /* bracketleft */
428 s->pre_map[0x1b ] = 0x15 | FN; /* bracketright */
2b76bdc9
AZ		 429 s->pre_map[0x1a | SHIFT ] = 0x16 | FN; /* braceleft */
430 s->pre_map[0x1b | SHIFT ] = 0x17 | FN; /* braceright */
b00052e4
AZ		 431 s->pre_map[0x27 ] = 0x22 | FN; /* semicolon */
432 s->pre_map[0x27 | SHIFT ] = 0x23 | FN; /* colon */
433 s->pre_map[0x09 | SHIFT ] = 0x24 | FN; /* asterisk */
434 s->pre_map[0x2b ] = 0x25 | FN; /* backslash */
435 s->pre_map[0x2b | SHIFT ] = 0x26 | FN; /* bar */
436 s->pre_map[0x0c | SHIFT ] = 0x30 | FN; /* underscore */
2b76bdc9 437 s->pre_map[0x33 | SHIFT ] = 0x33 | FN; /* less */
b00052e4 438 s->pre_map[0x35 ] = 0x33 | SHIFT; /* slash */
2b76bdc9 439 s->pre_map[0x34 | SHIFT ] = 0x34 | FN; /* greater */
b00052e4
AZ		 440 s->pre_map[0x35 | SHIFT ] = 0x34 | SHIFT; /* question */
441 s->pre_map[0x49 ] = 0x48 | FN; /* Page_Up */
442 s->pre_map[0x51 ] = 0x50 | FN; /* Page_Down */
443
444 s->modifiers = 0;
445 s->imodifiers = 0;
446 s->fifopos = 0;
447 s->fifolen = 0;
448 s->kbdtimer = qemu_new_timer(vm_clock, spitz_keyboard_tick, s);
449 spitz_keyboard_tick(s);
450}
451
452#undef SHIFT
453#undef CTRL
454#undef FN
455
aa941b94
AZ		 456static void spitz_keyboard_save(QEMUFile *f, void *opaque)
457{
458 struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
459 int i;
460
461 qemu_put_be16s(f, &s->sense_state);
462 qemu_put_be16s(f, &s->strobe_state);
463 for (i = 0; i < 5; i ++)
464 qemu_put_byte(f, spitz_gpio_invert[i]);
465}
466
467static int spitz_keyboard_load(QEMUFile *f, void *opaque, int version_id)
468{
469 struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque;
470 int i;
471
472 qemu_get_be16s(f, &s->sense_state);
473 qemu_get_be16s(f, &s->strobe_state);
474 for (i = 0; i < 5; i ++)
475 spitz_gpio_invert[i] = qemu_get_byte(f);
476
477 /* Release all pressed keys */
478 memset(s->keyrow, 0, sizeof(s->keyrow));
479 spitz_keyboard_sense_update(s);
480 s->modifiers = 0;
481 s->imodifiers = 0;
482 s->fifopos = 0;
483 s->fifolen = 0;
484
485 return 0;
486}
487
b00052e4
AZ		 488static void spitz_keyboard_register(struct pxa2xx_state_s *cpu)
489{
490 int i, j;
491 struct spitz_keyboard_s *s;
492
493 s = (struct spitz_keyboard_s *)
494 qemu_mallocz(sizeof(struct spitz_keyboard_s));
495 memset(s, 0, sizeof(struct spitz_keyboard_s));
b00052e4
AZ		 496
497 for (i = 0; i < 0x80; i ++)
498 s->keymap[i] = -1;
499 for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++)
500 for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++)
501 if (spitz_keymap[i][j] != -1)
502 s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
503
38641a52
AZ		 504 for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++)
505 s->sense[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpio_key_sense[i]];
506
507 for (i = 0; i < 5; i ++)
508 s->gpiomap[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpiomap[i]];
509
510 s->strobe = qemu_allocate_irqs(spitz_keyboard_strobe, s,
511 SPITZ_KEY_STROBE_NUM);
b00052e4 512 for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++)
38641a52 513 pxa2xx_gpio_out_set(cpu->gpio, spitz_gpio_key_strobe[i], s->strobe[i]);
b00052e4
AZ		 514
515 spitz_keyboard_pre_map(s);
516 qemu_add_kbd_event_handler((QEMUPutKBDEvent *) spitz_keyboard_handler, s);
aa941b94
AZ		 517
518 register_savevm("spitz_keyboard", 0, 0,
519 spitz_keyboard_save, spitz_keyboard_load, s);
b00052e4
AZ		 520}
521
b00052e4
AZ		 522/* LCD backlight controller */
523
524#define LCDTG_RESCTL 0x00
525#define LCDTG_PHACTRL 0x01
526#define LCDTG_DUTYCTRL 0x02
527#define LCDTG_POWERREG0 0x03
528#define LCDTG_POWERREG1 0x04
529#define LCDTG_GPOR3 0x05
530#define LCDTG_PICTRL 0x06
531#define LCDTG_POLCTRL 0x07
532
533static int bl_intensity, bl_power;
534
535static void spitz_bl_update(struct pxa2xx_state_s *s)
536{
537 if (bl_power && bl_intensity)
89cdb6af 538 zaurus_printf("LCD Backlight now at %i/63\n", bl_intensity);
b00052e4 539 else
89cdb6af 540 zaurus_printf("LCD Backlight now off\n");
b00052e4
AZ		 541}
542
38641a52 543static inline void spitz_bl_bit5(void *opaque, int line, int level)
b00052e4
AZ		 544{
545 int prev = bl_intensity;
546
547 if (level)
548 bl_intensity &= ~0x20;
549 else
550 bl_intensity |= 0x20;
551
552 if (bl_power && prev != bl_intensity)
553 spitz_bl_update((struct pxa2xx_state_s *) opaque);
554}
555
38641a52 556static inline void spitz_bl_power(void *opaque, int line, int level)
b00052e4
AZ		 557{
558 bl_power = !!level;
559 spitz_bl_update((struct pxa2xx_state_s *) opaque);
560}
561
562static void spitz_lcdtg_dac_put(void *opaque, uint8_t cmd)
563{
564 int addr, value;
565 addr = cmd >> 5;
566 value = cmd & 0x1f;
567
568 switch (addr) {
569 case LCDTG_RESCTL:
570 if (value)
89cdb6af 571 zaurus_printf("LCD in QVGA mode\n");
b00052e4 572 else
89cdb6af 573 zaurus_printf("LCD in VGA mode\n");
b00052e4
AZ		 574 break;
575
576 case LCDTG_DUTYCTRL:
577 bl_intensity &= ~0x1f;
578 bl_intensity |= value;
579 if (bl_power)
580 spitz_bl_update((struct pxa2xx_state_s *) opaque);
581 break;
582
583 case LCDTG_POWERREG0:
584 /* Set common voltage to M62332FP */
585 break;
586 }
587}
588
589/* SSP devices */
590
591#define CORGI_SSP_PORT 2
592
593#define SPITZ_GPIO_LCDCON_CS 53
594#define SPITZ_GPIO_ADS7846_CS 14
595#define SPITZ_GPIO_MAX1111_CS 20
596#define SPITZ_GPIO_TP_INT 11
597
598static int lcd_en, ads_en, max_en;
599static struct max111x_s *max1111;
600static struct ads7846_state_s *ads7846;
601
602/* "Demux" the signal based on current chipselect */
603static uint32_t corgi_ssp_read(void *opaque)
604{
605 if (lcd_en)
606 return 0;
607 if (ads_en)
608 return ads7846_read(ads7846);
609 if (max_en)
610 return max111x_read(max1111);
611 return 0;
612}
613
614static void corgi_ssp_write(void *opaque, uint32_t value)
615{
616 if (lcd_en)
617 spitz_lcdtg_dac_put(opaque, value);
618 if (ads_en)
619 ads7846_write(ads7846, value);
620 if (max_en)
621 max111x_write(max1111, value);
622}
623
38641a52 624static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
b00052e4 625{
38641a52
AZ		 626 switch (line) {
627 case 0:
b00052e4 628 lcd_en = !level;
38641a52
AZ		 629 break;
630 case 1:
b00052e4 631 ads_en = !level;
38641a52
AZ		 632 break;
633 case 2:
b00052e4 634 max_en = !level;
38641a52
AZ		 635 break;
636 }
b00052e4
AZ		 637}
638
639#define MAX1111_BATT_VOLT 1
640#define MAX1111_BATT_TEMP 2
641#define MAX1111_ACIN_VOLT 3
642
643#define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */
644#define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */
645#define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */
646
38641a52 647static void spitz_adc_temp_on(void *opaque, int line, int level)
b00052e4
AZ		 648{
649 if (!max1111)
650 return;
651
652 if (level)
653 max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
654 else
655 max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
656}
657
aa941b94
AZ		 658static void spitz_ssp_save(QEMUFile *f, void *opaque)
659{
660 qemu_put_be32(f, lcd_en);
661 qemu_put_be32(f, ads_en);
662 qemu_put_be32(f, max_en);
663 qemu_put_be32(f, bl_intensity);
664 qemu_put_be32(f, bl_power);
665}
666
667static int spitz_ssp_load(QEMUFile *f, void *opaque, int version_id)
668{
669 lcd_en = qemu_get_be32(f);
670 ads_en = qemu_get_be32(f);
671 max_en = qemu_get_be32(f);
672 bl_intensity = qemu_get_be32(f);
673 bl_power = qemu_get_be32(f);
674
675 return 0;
676}
677
b00052e4
AZ		 678static void spitz_ssp_attach(struct pxa2xx_state_s *cpu)
679{
38641a52
AZ		 680 qemu_irq *chipselects;
681
b00052e4
AZ		 682 lcd_en = ads_en = max_en = 0;
683
38641a52 684 ads7846 = ads7846_init(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_TP_INT]);
b00052e4
AZ		 685
686 max1111 = max1111_init(0);
687 max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
688 max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
689 max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
690
691 pxa2xx_ssp_attach(cpu->ssp[CORGI_SSP_PORT - 1], corgi_ssp_read,
692 corgi_ssp_write, cpu);
693
38641a52
AZ		 694 chipselects = qemu_allocate_irqs(corgi_ssp_gpio_cs, cpu, 3);
695 pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_LCDCON_CS, chipselects[0]);
696 pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ADS7846_CS, chipselects[1]);
697 pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_MAX1111_CS, chipselects[2]);
b00052e4
AZ		 698
699 bl_intensity = 0x20;
700 bl_power = 0;
aa941b94
AZ		 701
702 register_savevm("spitz_ssp", 0, 0, spitz_ssp_save, spitz_ssp_load, cpu);
b00052e4
AZ		 703}
704
705/* CF Microdrive */
706
707static void spitz_microdrive_attach(struct pxa2xx_state_s *cpu)
708{
709 struct pcmcia_card_s *md;
e4bcb14c
TS		 710 int index;
711 BlockDriverState *bs;
b00052e4 712
e4bcb14c
TS		 713 index = drive_get_index(IF_IDE, 0, 0);
714 if (index == -1)
715 return;
716 bs = drives_table[index].bdrv;
717 if (bdrv_is_inserted(bs) && !bdrv_is_removable(bs)) {
b00052e4 718 md = dscm1xxxx_init(bs);
bf5ee248 719 pxa2xx_pcmcia_attach(cpu->pcmcia[1], md);
b00052e4
AZ		 720 }
721}
722
adb86c37
AZ		 723/* Wm8750 and Max7310 on I2C */
724
725#define AKITA_MAX_ADDR 0x18
611d7189
AZ		 726#define SPITZ_WM_ADDRL 0x1b
727#define SPITZ_WM_ADDRH 0x1a
adb86c37
AZ		 728
729#define SPITZ_GPIO_WM 5
730
731#ifdef HAS_AUDIO
38641a52 732static void spitz_wm8750_addr(void *opaque, int line, int level)
adb86c37
AZ		 733{
734 i2c_slave *wm = (i2c_slave *) opaque;
735 if (level)
736 i2c_set_slave_address(wm, SPITZ_WM_ADDRH);
737 else
738 i2c_set_slave_address(wm, SPITZ_WM_ADDRL);
739}
740#endif
741
742static void spitz_i2c_setup(struct pxa2xx_state_s *cpu)
743{
744 /* Attach the CPU on one end of our I2C bus. */
745 i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
746
747#ifdef HAS_AUDIO
748 AudioState *audio;
749 i2c_slave *wm;
750
751 audio = AUD_init();
752 if (!audio)
753 return;
754 /* Attach a WM8750 to the bus */
755 wm = wm8750_init(bus, audio);
756
38641a52
AZ		 757 spitz_wm8750_addr(wm, 0, 0);
758 pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_WM,
759 qemu_allocate_irqs(spitz_wm8750_addr, wm, 1)[0]);
adb86c37
AZ		 760 /* .. and to the sound interface. */
761 cpu->i2s->opaque = wm;
762 cpu->i2s->codec_out = wm8750_dac_dat;
763 cpu->i2s->codec_in = wm8750_adc_dat;
764 wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s);
765#endif
766}
767
768static void spitz_akita_i2c_setup(struct pxa2xx_state_s *cpu)
769{
770 /* Attach a Max7310 to Akita I2C bus. */
771 i2c_set_slave_address(max7310_init(pxa2xx_i2c_bus(cpu->i2c[0])),
772 AKITA_MAX_ADDR);
773}
774
b00052e4
AZ		 775/* Other peripherals */
776
38641a52 777static void spitz_out_switch(void *opaque, int line, int level)
b00052e4 778{
38641a52
AZ		 779 switch (line) {
780 case 0:
89cdb6af 781 zaurus_printf("Charging %s.\n", level ? "off" : "on");
38641a52
AZ		 782 break;
783 case 1:
89cdb6af 784 zaurus_printf("Discharging %s.\n", level ? "on" : "off");
38641a52
AZ		 785 break;
786 case 2:
89cdb6af 787 zaurus_printf("Green LED %s.\n", level ? "on" : "off");
38641a52
AZ		 788 break;
789 case 3:
89cdb6af 790 zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
38641a52
AZ		 791 break;
792 case 4:
793 spitz_bl_bit5(opaque, line, level);
794 break;
795 case 5:
796 spitz_bl_power(opaque, line, level);
797 break;
798 case 6:
799 spitz_adc_temp_on(opaque, line, level);
800 break;
801 }
b00052e4
AZ		 802}
803
804#define SPITZ_SCP_LED_GREEN 1
805#define SPITZ_SCP_JK_B 2
806#define SPITZ_SCP_CHRG_ON 3
807#define SPITZ_SCP_MUTE_L 4
808#define SPITZ_SCP_MUTE_R 5
809#define SPITZ_SCP_CF_POWER 6
810#define SPITZ_SCP_LED_ORANGE 7
811#define SPITZ_SCP_JK_A 8
812#define SPITZ_SCP_ADC_TEMP_ON 9
813#define SPITZ_SCP2_IR_ON 1
814#define SPITZ_SCP2_AKIN_PULLUP 2
815#define SPITZ_SCP2_BACKLIGHT_CONT 7
816#define SPITZ_SCP2_BACKLIGHT_ON 8
817#define SPITZ_SCP2_MIC_BIAS 9
818
819static void spitz_scoop_gpio_setup(struct pxa2xx_state_s *cpu,
e33d8cdb 820 struct scoop_info_s *scp0, struct scoop_info_s *scp1)
b00052e4 821{
38641a52
AZ		 822 qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
823
e33d8cdb
AZ		 824 scoop_gpio_out_set(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
825 scoop_gpio_out_set(scp0, SPITZ_SCP_JK_B, outsignals[1]);
826 scoop_gpio_out_set(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
827 scoop_gpio_out_set(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
b00052e4 828
e33d8cdb
AZ		 829 if (scp1) {
830 scoop_gpio_out_set(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
831 scoop_gpio_out_set(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
b00052e4
AZ		 832 }
833
e33d8cdb 834 scoop_gpio_out_set(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
b00052e4
AZ		 835}
836
837#define SPITZ_GPIO_HSYNC 22
838#define SPITZ_GPIO_SD_DETECT 9
839#define SPITZ_GPIO_SD_WP 81
840#define SPITZ_GPIO_ON_RESET 89
841#define SPITZ_GPIO_BAT_COVER 90
842#define SPITZ_GPIO_CF1_IRQ 105
843#define SPITZ_GPIO_CF1_CD 94
844#define SPITZ_GPIO_CF2_IRQ 106
845#define SPITZ_GPIO_CF2_CD 93
846
38641a52 847static int spitz_hsync;
b00052e4 848
38641a52 849static void spitz_lcd_hsync_handler(void *opaque, int line, int level)
b00052e4
AZ		 850{
851 struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque;
38641a52 852 qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_HSYNC], spitz_hsync);
b00052e4
AZ		 853 spitz_hsync ^= 1;
854}
855
b00052e4
AZ		 856static void spitz_gpio_setup(struct pxa2xx_state_s *cpu, int slots)
857{
38641a52 858 qemu_irq lcd_hsync;
b00052e4
AZ		 859 /*
860 * Bad hack: We toggle the LCD hsync GPIO on every GPIO status
861 * read to satisfy broken guests that poll-wait for hsync.
862 * Simulating a real hsync event would be less practical and
863 * wouldn't guarantee that a guest ever exits the loop.
864 */
865 spitz_hsync = 0;
38641a52
AZ		 866 lcd_hsync = qemu_allocate_irqs(spitz_lcd_hsync_handler, cpu, 1)[0];
867 pxa2xx_gpio_read_notifier(cpu->gpio, lcd_hsync);
868 pxa2xx_lcd_vsync_notifier(cpu->lcd, lcd_hsync);
b00052e4
AZ		 869
870 /* MMC/SD host */
02ce600c
AZ		 871 pxa2xx_mmci_handlers(cpu->mmc,
872 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_WP],
873 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_DETECT]);
b00052e4
AZ		 874
875 /* Battery lock always closed */
38641a52 876 qemu_irq_raise(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_BAT_COVER]);
b00052e4
AZ		 877
878 /* Handle reset */
38641a52 879 pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset);
b00052e4
AZ		 880
881 /* PCMCIA signals: card's IRQ and Card-Detect */
b00052e4 882 if (slots >= 1)
38641a52
AZ		 883 pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
884 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_IRQ],
885 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_CD]);
b00052e4 886 if (slots >= 2)
38641a52
AZ		 887 pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1],
888 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_IRQ],
889 pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_CD]);
b00052e4
AZ		 890
891 /* Initialise the screen rotation related signals */
892 spitz_gpio_invert[3] = 0; /* Always open */
893 if (graphic_rotate) { /* Tablet mode */
894 spitz_gpio_invert[4] = 0;
895 } else { /* Portrait mode */
896 spitz_gpio_invert[4] = 1;
897 }
38641a52
AZ		 898 qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWA],
899 spitz_gpio_invert[3]);
900 qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWB],
901 spitz_gpio_invert[4]);
b00052e4
AZ		 902}
903
b00052e4
AZ		 904/* Board init. */
905enum spitz_model_e { spitz, akita, borzoi, terrier };
906
7fb4fdcf
AZ		 907#define SPITZ_RAM 0x04000000
908#define SPITZ_ROM 0x00800000
909
f93eb9ff
AZ		 910static struct arm_boot_info spitz_binfo = {
911 .loader_start = PXA2XX_SDRAM_BASE,
912 .ram_size = 0x04000000,
913};
914
00f82b8a 915static void spitz_common_init(ram_addr_t ram_size, int vga_ram_size,
b00052e4
AZ		 916 DisplayState *ds, const char *kernel_filename,
917 const char *kernel_cmdline, const char *initrd_filename,
4207117c 918 const char *cpu_model, enum spitz_model_e model, int arm_id)
b00052e4 919{
b00052e4 920 struct pxa2xx_state_s *cpu;
e33d8cdb 921 struct scoop_info_s *scp0, *scp1 = NULL;
b00052e4 922
4207117c
AZ		 923 if (!cpu_model)
924 cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
b00052e4 925
d95b2f8d 926 /* Setup CPU & memory */
7fb4fdcf 927 if (ram_size < SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE) {
b00052e4 928 fprintf(stderr, "This platform requires %i bytes of memory\n",
7fb4fdcf 929 SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE);
b00052e4
AZ		 930 exit(1);
931 }
7fb4fdcf 932 cpu = pxa270_init(spitz_binfo.ram_size, ds, cpu_model);
b00052e4
AZ		 933
934 sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
935
7fb4fdcf
AZ		 936 cpu_register_physical_memory(0, SPITZ_ROM,
937 qemu_ram_alloc(SPITZ_ROM) | IO_MEM_ROM);
b00052e4
AZ		 938
939 /* Setup peripherals */
940 spitz_keyboard_register(cpu);
941
942 spitz_ssp_attach(cpu);
943
e33d8cdb
AZ		 944 scp0 = scoop_init(cpu, 0, 0x10800000);
945 if (model != akita) {
946 scp1 = scoop_init(cpu, 1, 0x08800040);
947 }
b00052e4 948
e33d8cdb 949 spitz_scoop_gpio_setup(cpu, scp0, scp1);
b00052e4
AZ		 950
951 spitz_gpio_setup(cpu, (model == akita) ? 1 : 2);
952
adb86c37
AZ		 953 spitz_i2c_setup(cpu);
954
955 if (model == akita)
956 spitz_akita_i2c_setup(cpu);
957
b00052e4 958 if (model == terrier)
bf5ee248 959 /* A 6.0 GB microdrive is permanently sitting in CF slot 1. */
b00052e4
AZ		 960 spitz_microdrive_attach(cpu);
961 else if (model != akita)
bf5ee248 962 /* A 4.0 GB microdrive is permanently sitting in CF slot 1. */
b00052e4
AZ		 963 spitz_microdrive_attach(cpu);
964
965 /* Setup initial (reset) machine state */
f93eb9ff 966 cpu->env->regs[15] = spitz_binfo.loader_start;
b00052e4 967
f93eb9ff
AZ		 968 spitz_binfo.kernel_filename = kernel_filename;
969 spitz_binfo.kernel_cmdline = kernel_cmdline;
970 spitz_binfo.initrd_filename = initrd_filename;
971 spitz_binfo.board_id = arm_id;
972 arm_load_kernel(cpu->env, &spitz_binfo);
d95b2f8d 973 sl_bootparam_write(SL_PXA_PARAM_BASE - PXA2XX_SDRAM_BASE);
b00052e4
AZ		 974}
975
00f82b8a 976static void spitz_init(ram_addr_t ram_size, int vga_ram_size,
6ac0e82d 977 const char *boot_device, DisplayState *ds,
b00052e4
AZ		 978 const char *kernel_filename, const char *kernel_cmdline,
979 const char *initrd_filename, const char *cpu_model)
980{
981 spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
4207117c 982 kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
b00052e4
AZ		 983}
984
00f82b8a 985static void borzoi_init(ram_addr_t ram_size, int vga_ram_size,
6ac0e82d 986 const char *boot_device, DisplayState *ds,
b00052e4
AZ		 987 const char *kernel_filename, const char *kernel_cmdline,
988 const char *initrd_filename, const char *cpu_model)
989{
990 spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
4207117c 991 kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
b00052e4
AZ		 992}
993
00f82b8a 994static void akita_init(ram_addr_t ram_size, int vga_ram_size,
6ac0e82d 995 const char *boot_device, DisplayState *ds,
b00052e4
AZ		 996 const char *kernel_filename, const char *kernel_cmdline,
997 const char *initrd_filename, const char *cpu_model)
998{
999 spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
4207117c 1000 kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
b00052e4
AZ		 1001}
1002
00f82b8a 1003static void terrier_init(ram_addr_t ram_size, int vga_ram_size,
6ac0e82d 1004 const char *boot_device, DisplayState *ds,
b00052e4
AZ		 1005 const char *kernel_filename, const char *kernel_cmdline,
1006 const char *initrd_filename, const char *cpu_model)
1007{
1008 spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
4207117c 1009 kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f);
b00052e4
AZ		 1010}
1011
1012QEMUMachine akitapda_machine = {
1013 "akita",
1014 "Akita PDA (PXA270)",
1015 akita_init,
7fb4fdcf 1016 SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE + RAMSIZE_FIXED,
b00052e4
AZ		 1017};
1018
1019QEMUMachine spitzpda_machine = {
1020 "spitz",
1021 "Spitz PDA (PXA270)",
1022 spitz_init,
7fb4fdcf 1023 SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE + RAMSIZE_FIXED,
b00052e4
AZ		 1024};
1025
1026QEMUMachine borzoipda_machine = {
1027 "borzoi",
1028 "Borzoi PDA (PXA270)",
1029 borzoi_init,
7fb4fdcf 1030 SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE + RAMSIZE_FIXED,
b00052e4
AZ		 1031};
1032
1033QEMUMachine terrierpda_machine = {
1034 "terrier",
1035 "Terrier PDA (PXA270)",
1036 terrier_init,
7fb4fdcf 1037 SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE + RAMSIZE_FIXED,
b00052e4 1038};
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