[qemu.git] / hw / intc / xics_kvm.c

/*
 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
 *
 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics, in-kernel emulation
 *
 * Copyright (c) 2013 David Gibson, IBM Corporation.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 *
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/hw.h"
#include "trace.h"
#include "sysemu/kvm.h"
#include "hw/ppc/spapr.h"
#include "hw/ppc/xics.h"
#include "kvm_ppc.h"
#include "qemu/config-file.h"
#include "qemu/error-report.h"

#include <sys/ioctl.h>

typedef struct KVMXICSState {
    XICSState parent_obj;

    int kernel_xics_fd;
} KVMXICSState;

/*
 * ICP-KVM
 */
static void icp_get_kvm_state(ICPState *ss)
{
    uint64_t state;
    struct kvm_one_reg reg = {
        .id = KVM_REG_PPC_ICP_STATE,
        .addr = (uintptr_t)&state,
    };
    int ret;

    /* ICP for this CPU thread is not in use, exiting */
    if (!ss->cs) {
        return;
    }

    ret = kvm_vcpu_ioctl(ss->cs, KVM_GET_ONE_REG, &reg);
    if (ret != 0) {
        error_report("Unable to retrieve KVM interrupt controller state"
                " for CPU %ld: %s", kvm_arch_vcpu_id(ss->cs), strerror(errno));
        exit(1);
    }

    ss->xirr = state >> KVM_REG_PPC_ICP_XISR_SHIFT;
    ss->mfrr = (state >> KVM_REG_PPC_ICP_MFRR_SHIFT)
        & KVM_REG_PPC_ICP_MFRR_MASK;
    ss->pending_priority = (state >> KVM_REG_PPC_ICP_PPRI_SHIFT)
        & KVM_REG_PPC_ICP_PPRI_MASK;
}

static int icp_set_kvm_state(ICPState *ss, int version_id)
{
    uint64_t state;
    struct kvm_one_reg reg = {
        .id = KVM_REG_PPC_ICP_STATE,
        .addr = (uintptr_t)&state,
    };
    int ret;

    /* ICP for this CPU thread is not in use, exiting */
    if (!ss->cs) {
        return 0;
    }

    state = ((uint64_t)ss->xirr << KVM_REG_PPC_ICP_XISR_SHIFT)
        | ((uint64_t)ss->mfrr << KVM_REG_PPC_ICP_MFRR_SHIFT)
        | ((uint64_t)ss->pending_priority << KVM_REG_PPC_ICP_PPRI_SHIFT);

    ret = kvm_vcpu_ioctl(ss->cs, KVM_SET_ONE_REG, &reg);
    if (ret != 0) {
        error_report("Unable to restore KVM interrupt controller state (0x%"
                PRIx64 ") for CPU %ld: %s", state, kvm_arch_vcpu_id(ss->cs),
                strerror(errno));
        return ret;
    }

    return 0;
}

static void icp_kvm_reset(DeviceState *dev)
{
    ICPState *icp = ICP(dev);

    icp->xirr = 0;
    icp->pending_priority = 0xff;
    icp->mfrr = 0xff;

    /* Make all outputs as deasserted only if the CPU thread is in use */
    if (icp->output) {
        qemu_set_irq(icp->output, 0);
    }

    icp_set_kvm_state(icp, 1);
}

static void icp_kvm_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    ICPStateClass *icpc = ICP_CLASS(klass);

    dc->reset = icp_kvm_reset;
    icpc->pre_save = icp_get_kvm_state;
    icpc->post_load = icp_set_kvm_state;
}

static const TypeInfo icp_kvm_info = {
    .name = TYPE_KVM_ICP,
    .parent = TYPE_ICP,
    .instance_size = sizeof(ICPState),
    .class_init = icp_kvm_class_init,
    .class_size = sizeof(ICPStateClass),
};

/*
 * ICS-KVM
 */
static void ics_get_kvm_state(ICSState *ics)
{
    KVMXICSState *xicskvm = XICS_SPAPR_KVM(ics->xics);
    uint64_t state;
    struct kvm_device_attr attr = {
        .flags = 0,
        .group = KVM_DEV_XICS_GRP_SOURCES,
        .addr = (uint64_t)(uintptr_t)&state,
    };
    int i;

    for (i = 0; i < ics->nr_irqs; i++) {
        ICSIRQState *irq = &ics->irqs[i];
        int ret;

        attr.attr = i + ics->offset;

        ret = ioctl(xicskvm->kernel_xics_fd, KVM_GET_DEVICE_ATTR, &attr);
        if (ret != 0) {
            error_report("Unable to retrieve KVM interrupt controller state"
                    " for IRQ %d: %s", i + ics->offset, strerror(errno));
            exit(1);
        }

        irq->server = state & KVM_XICS_DESTINATION_MASK;
        irq->saved_priority = (state >> KVM_XICS_PRIORITY_SHIFT)
            & KVM_XICS_PRIORITY_MASK;
        /*
         * To be consistent with the software emulation in xics.c, we
         * split out the masked state + priority that we get from the
         * kernel into 'current priority' (0xff if masked) and
         * 'saved priority' (if masked, this is the priority the
         * interrupt had before it was masked).  Masking and unmasking
         * are done with the ibm,int-off and ibm,int-on RTAS calls.
         */
        if (state & KVM_XICS_MASKED) {
            irq->priority = 0xff;
        } else {
            irq->priority = irq->saved_priority;
        }

        if (state & KVM_XICS_PENDING) {
            if (state & KVM_XICS_LEVEL_SENSITIVE) {
                irq->status |= XICS_STATUS_ASSERTED;
            } else {
                /*
                 * A pending edge-triggered interrupt (or MSI)
                 * must have been rejected previously when we
                 * first detected it and tried to deliver it,
                 * so mark it as pending and previously rejected
                 * for consistency with how xics.c works.
                 */
                irq->status |= XICS_STATUS_MASKED_PENDING
                    | XICS_STATUS_REJECTED;
            }
        }
    }
}

static int ics_set_kvm_state(ICSState *ics, int version_id)
{
    KVMXICSState *xicskvm = XICS_SPAPR_KVM(ics->xics);
    uint64_t state;
    struct kvm_device_attr attr = {
        .flags = 0,
        .group = KVM_DEV_XICS_GRP_SOURCES,
        .addr = (uint64_t)(uintptr_t)&state,
    };
    int i;

    for (i = 0; i < ics->nr_irqs; i++) {
        ICSIRQState *irq = &ics->irqs[i];
        int ret;

        attr.attr = i + ics->offset;

        state = irq->server;
        state |= (uint64_t)(irq->saved_priority & KVM_XICS_PRIORITY_MASK)
            << KVM_XICS_PRIORITY_SHIFT;
        if (irq->priority != irq->saved_priority) {
            assert(irq->priority == 0xff);
            state |= KVM_XICS_MASKED;
        }

        if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
            state |= KVM_XICS_LEVEL_SENSITIVE;
            if (irq->status & XICS_STATUS_ASSERTED) {
                state |= KVM_XICS_PENDING;
            }
        } else {
            if (irq->status & XICS_STATUS_MASKED_PENDING) {
                state |= KVM_XICS_PENDING;
            }
        }

        ret = ioctl(xicskvm->kernel_xics_fd, KVM_SET_DEVICE_ATTR, &attr);
        if (ret != 0) {
            error_report("Unable to restore KVM interrupt controller state"
                    " for IRQs %d: %s", i + ics->offset, strerror(errno));
            return ret;
        }
    }

    return 0;
}

static void ics_kvm_set_irq(void *opaque, int srcno, int val)
{
    ICSState *ics = opaque;
    struct kvm_irq_level args;
    int rc;

    args.irq = srcno + ics->offset;
    if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MSI) {
        if (!val) {
            return;
        }
        args.level = KVM_INTERRUPT_SET;
    } else {
        args.level = val ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
    }
    rc = kvm_vm_ioctl(kvm_state, KVM_IRQ_LINE, &args);
    if (rc < 0) {
        perror("kvm_irq_line");
    }
}

static void ics_kvm_reset(DeviceState *dev)
{
    ICSState *ics = ICS_SIMPLE(dev);
    int i;
    uint8_t flags[ics->nr_irqs];

    for (i = 0; i < ics->nr_irqs; i++) {
        flags[i] = ics->irqs[i].flags;
    }

    memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);

    for (i = 0; i < ics->nr_irqs; i++) {
        ics->irqs[i].priority = 0xff;
        ics->irqs[i].saved_priority = 0xff;
        ics->irqs[i].flags = flags[i];
    }

    ics_set_kvm_state(ics, 1);
}

static void ics_kvm_realize(DeviceState *dev, Error **errp)
{
    ICSState *ics = ICS_SIMPLE(dev);

    if (!ics->nr_irqs) {
        error_setg(errp, "Number of interrupts needs to be greater 0");
        return;
    }
    ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
    ics->qirqs = qemu_allocate_irqs(ics_kvm_set_irq, ics, ics->nr_irqs);
}

static void ics_kvm_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    ICSStateClass *icsc = ICS_BASE_CLASS(klass);

    dc->realize = ics_kvm_realize;
    dc->reset = ics_kvm_reset;
    icsc->pre_save = ics_get_kvm_state;
    icsc->post_load = ics_set_kvm_state;
}

static const TypeInfo ics_kvm_info = {
    .name = TYPE_ICS_KVM,
    .parent = TYPE_ICS_SIMPLE,
    .instance_size = sizeof(ICSState),
    .class_init = ics_kvm_class_init,
};

/*
 * XICS-KVM
 */
static void xics_kvm_cpu_setup(XICSState *xics, PowerPCCPU *cpu)
{
    CPUState *cs;
    ICPState *ss;
    KVMXICSState *xicskvm = XICS_SPAPR_KVM(xics);
    int ret;

    cs = CPU(cpu);
    ss = &xics->ss[cs->cpu_index];

    assert(cs->cpu_index < xics->nr_servers);
    if (xicskvm->kernel_xics_fd == -1) {
        abort();
    }

    /*
     * If we are reusing a parked vCPU fd corresponding to the CPU
     * which was hot-removed earlier we don't have to renable
     * KVM_CAP_IRQ_XICS capability again.
     */
    if (ss->cap_irq_xics_enabled) {
        return;
    }

    ret = kvm_vcpu_enable_cap(cs, KVM_CAP_IRQ_XICS, 0, xicskvm->kernel_xics_fd,
                              kvm_arch_vcpu_id(cs));
    if (ret < 0) {
        error_report("Unable to connect CPU%ld to kernel XICS: %s",
                     kvm_arch_vcpu_id(cs), strerror(errno));
        exit(1);
    }
    ss->cap_irq_xics_enabled = true;
}

static void xics_kvm_set_nr_irqs(XICSState *xics, uint32_t nr_irqs,
                                 Error **errp)
{
    ICSState *ics = QLIST_FIRST(&xics->ics);

    /* This needs to be deprecated ... */
    xics->nr_irqs = nr_irqs;
    if (ics) {
        ics->nr_irqs = nr_irqs;
    }
}

static void xics_kvm_set_nr_servers(XICSState *xics, uint32_t nr_servers,
                                    Error **errp)
{
    xics_set_nr_servers(xics, nr_servers, TYPE_KVM_ICP, errp);
}

static void rtas_dummy(PowerPCCPU *cpu, sPAPRMachineState *spapr,
                       uint32_t token,
                       uint32_t nargs, target_ulong args,
                       uint32_t nret, target_ulong rets)
{
    error_report("pseries: %s must never be called for in-kernel XICS",
                 __func__);
}

static void xics_kvm_realize(DeviceState *dev, Error **errp)
{
    KVMXICSState *xicskvm = XICS_SPAPR_KVM(dev);
    XICSState *xics = XICS_COMMON(dev);
    ICSState *ics;
    int i, rc;
    Error *error = NULL;
    struct kvm_create_device xics_create_device = {
        .type = KVM_DEV_TYPE_XICS,
        .flags = 0,
    };

    if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_IRQ_XICS)) {
        error_setg(errp,
                   "KVM and IRQ_XICS capability must be present for in-kernel XICS");
        goto fail;
    }

    spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_dummy);
    spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_dummy);
    spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_dummy);
    spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_dummy);

    rc = kvmppc_define_rtas_kernel_token(RTAS_IBM_SET_XIVE, "ibm,set-xive");
    if (rc < 0) {
        error_setg(errp, "kvmppc_define_rtas_kernel_token: ibm,set-xive");
        goto fail;
    }

    rc = kvmppc_define_rtas_kernel_token(RTAS_IBM_GET_XIVE, "ibm,get-xive");
    if (rc < 0) {
        error_setg(errp, "kvmppc_define_rtas_kernel_token: ibm,get-xive");
        goto fail;
    }

    rc = kvmppc_define_rtas_kernel_token(RTAS_IBM_INT_ON, "ibm,int-on");
    if (rc < 0) {
        error_setg(errp, "kvmppc_define_rtas_kernel_token: ibm,int-on");
        goto fail;
    }

    rc = kvmppc_define_rtas_kernel_token(RTAS_IBM_INT_OFF, "ibm,int-off");
    if (rc < 0) {
        error_setg(errp, "kvmppc_define_rtas_kernel_token: ibm,int-off");
        goto fail;
    }

    /* Create the kernel ICP */
    rc = kvm_vm_ioctl(kvm_state, KVM_CREATE_DEVICE, &xics_create_device);
    if (rc < 0) {
        error_setg_errno(errp, -rc, "Error on KVM_CREATE_DEVICE for XICS");
        goto fail;
    }

    xicskvm->kernel_xics_fd = xics_create_device.fd;

    QLIST_FOREACH(ics, &xics->ics, list) {
        object_property_set_bool(OBJECT(ics), true, "realized", &error);
        if (error) {
            error_propagate(errp, error);
            goto fail;
        }
    }

    assert(xics->nr_servers);
    for (i = 0; i < xics->nr_servers; i++) {
        object_property_set_bool(OBJECT(&xics->ss[i]), true, "realized",
                                 &error);
        if (error) {
            error_propagate(errp, error);
            goto fail;
        }
    }

    kvm_kernel_irqchip = true;
    kvm_msi_via_irqfd_allowed = true;
    kvm_gsi_direct_mapping = true;

    return;

fail:
    kvmppc_define_rtas_kernel_token(0, "ibm,set-xive");
    kvmppc_define_rtas_kernel_token(0, "ibm,get-xive");
    kvmppc_define_rtas_kernel_token(0, "ibm,int-on");
    kvmppc_define_rtas_kernel_token(0, "ibm,int-off");
}

static void xics_kvm_initfn(Object *obj)
{
    XICSState *xics = XICS_COMMON(obj);
    ICSState *ics;

    ics = ICS_SIMPLE(object_new(TYPE_ICS_KVM));
    object_property_add_child(obj, "ics", OBJECT(ics), NULL);
    ics->xics = xics;
    QLIST_INSERT_HEAD(&xics->ics, ics, list);
}

static void xics_kvm_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);
    XICSStateClass *xsc = XICS_COMMON_CLASS(oc);

    dc->realize = xics_kvm_realize;
    xsc->cpu_setup = xics_kvm_cpu_setup;
    xsc->set_nr_irqs = xics_kvm_set_nr_irqs;
    xsc->set_nr_servers = xics_kvm_set_nr_servers;
}

static const TypeInfo xics_spapr_kvm_info = {
    .name          = TYPE_XICS_SPAPR_KVM,
    .parent        = TYPE_XICS_COMMON,
    .instance_size = sizeof(KVMXICSState),
    .class_init    = xics_kvm_class_init,
    .instance_init = xics_kvm_initfn,
};

static void xics_kvm_register_types(void)
{
    type_register_static(&xics_spapr_kvm_info);
    type_register_static(&ics_kvm_info);
    type_register_static(&icp_kvm_info);
}

type_init(xics_kvm_register_types)
Commit	Line	Data
11ad93f6 DG	1	/*
	2	* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
	3	*
	4	* PAPR Virtualized Interrupt System, aka ICS/ICP aka xics, in-kernel emulation
	5	*
	6	* Copyright (c) 2013 David Gibson, IBM Corporation.
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*
	26	*/
	27
0d75590d	28	#include "qemu/osdep.h"
da34e65c	29	#include "qapi/error.h"
4771d756 PB	30	#include "qemu-common.h"
4771d756 PB	31	#include "cpu.h"
11ad93f6 DG	32	#include "hw/hw.h"
11ad93f6 DG	33	#include "trace.h"
77ac58dd	34	#include "sysemu/kvm.h"
11ad93f6 DG	35	#include "hw/ppc/spapr.h"
	36	#include "hw/ppc/xics.h"
	37	#include "kvm_ppc.h"
	38	#include "qemu/config-file.h"
	39	#include "qemu/error-report.h"
	40
	41	#include <sys/ioctl.h>
	42
	43	typedef struct KVMXICSState {
	44	XICSState parent_obj;
	45
11ad93f6 DG	46	int kernel_xics_fd;
	47	} KVMXICSState;
	48
	49	/*
	50	* ICP-KVM
	51	*/
	52	static void icp_get_kvm_state(ICPState *ss)
	53	{
	54	uint64_t state;
	55	struct kvm_one_reg reg = {
	56	.id = KVM_REG_PPC_ICP_STATE,
	57	.addr = (uintptr_t)&state,
	58	};
	59	int ret;
	60
	61	/* ICP for this CPU thread is not in use, exiting */
	62	if (!ss->cs) {
	63	return;
	64	}
	65
	66	ret = kvm_vcpu_ioctl(ss->cs, KVM_GET_ONE_REG, &reg);
	67	if (ret != 0) {
	68	error_report("Unable to retrieve KVM interrupt controller state"
0f20ba62	69	" for CPU %ld: %s", kvm_arch_vcpu_id(ss->cs), strerror(errno));
11ad93f6 DG	70	exit(1);
	71	}
	72
	73	ss->xirr = state >> KVM_REG_PPC_ICP_XISR_SHIFT;
	74	ss->mfrr = (state >> KVM_REG_PPC_ICP_MFRR_SHIFT)
	75	& KVM_REG_PPC_ICP_MFRR_MASK;
	76	ss->pending_priority = (state >> KVM_REG_PPC_ICP_PPRI_SHIFT)
	77	& KVM_REG_PPC_ICP_PPRI_MASK;
	78	}
	79
	80	static int icp_set_kvm_state(ICPState *ss, int version_id)
	81	{
	82	uint64_t state;
	83	struct kvm_one_reg reg = {
	84	.id = KVM_REG_PPC_ICP_STATE,
	85	.addr = (uintptr_t)&state,
	86	};
	87	int ret;
	88
	89	/* ICP for this CPU thread is not in use, exiting */
	90	if (!ss->cs) {
	91	return 0;
	92	}
	93
	94	state = ((uint64_t)ss->xirr << KVM_REG_PPC_ICP_XISR_SHIFT)
	95	\| ((uint64_t)ss->mfrr << KVM_REG_PPC_ICP_MFRR_SHIFT)
	96	\| ((uint64_t)ss->pending_priority << KVM_REG_PPC_ICP_PPRI_SHIFT);
	97
	98	ret = kvm_vcpu_ioctl(ss->cs, KVM_SET_ONE_REG, &reg);
	99	if (ret != 0) {
	100	error_report("Unable to restore KVM interrupt controller state (0x%"
0f20ba62	101	PRIx64 ") for CPU %ld: %s", state, kvm_arch_vcpu_id(ss->cs),
11ad93f6 DG	102	strerror(errno));
	103	return ret;
	104	}
	105
	106	return 0;
	107	}
	108
	109	static void icp_kvm_reset(DeviceState *dev)
	110	{
	111	ICPState *icp = ICP(dev);
	112
	113	icp->xirr = 0;
	114	icp->pending_priority = 0xff;
	115	icp->mfrr = 0xff;
	116
4a4b344c BR	117	/* Make all outputs as deasserted only if the CPU thread is in use */
	118	if (icp->output) {
	119	qemu_set_irq(icp->output, 0);
	120	}
11ad93f6 DG	121
	122	icp_set_kvm_state(icp, 1);
	123	}
	124
	125	static void icp_kvm_class_init(ObjectClass klass, void data)
	126	{
	127	DeviceClass *dc = DEVICE_CLASS(klass);
	128	ICPStateClass *icpc = ICP_CLASS(klass);
	129
	130	dc->reset = icp_kvm_reset;
	131	icpc->pre_save = icp_get_kvm_state;
	132	icpc->post_load = icp_set_kvm_state;
	133	}
	134
	135	static const TypeInfo icp_kvm_info = {
	136	.name = TYPE_KVM_ICP,
	137	.parent = TYPE_ICP,
	138	.instance_size = sizeof(ICPState),
	139	.class_init = icp_kvm_class_init,
	140	.class_size = sizeof(ICPStateClass),
	141	};
	142
	143	/*
	144	* ICS-KVM
	145	*/
	146	static void ics_get_kvm_state(ICSState *ics)
	147	{
27f24582	148	KVMXICSState *xicskvm = XICS_SPAPR_KVM(ics->xics);
11ad93f6 DG	149	uint64_t state;
	150	struct kvm_device_attr attr = {
	151	.flags = 0,
	152	.group = KVM_DEV_XICS_GRP_SOURCES,
	153	.addr = (uint64_t)(uintptr_t)&state,
	154	};
	155	int i;
	156
	157	for (i = 0; i < ics->nr_irqs; i++) {
	158	ICSIRQState *irq = &ics->irqs[i];
	159	int ret;
	160
	161	attr.attr = i + ics->offset;
	162
27f24582	163	ret = ioctl(xicskvm->kernel_xics_fd, KVM_GET_DEVICE_ATTR, &attr);
11ad93f6 DG	164	if (ret != 0) {
	165	error_report("Unable to retrieve KVM interrupt controller state"
	166	" for IRQ %d: %s", i + ics->offset, strerror(errno));
	167	exit(1);
	168	}
	169
	170	irq->server = state & KVM_XICS_DESTINATION_MASK;
	171	irq->saved_priority = (state >> KVM_XICS_PRIORITY_SHIFT)
	172	& KVM_XICS_PRIORITY_MASK;
	173	/*
	174	* To be consistent with the software emulation in xics.c, we
	175	* split out the masked state + priority that we get from the
	176	* kernel into 'current priority' (0xff if masked) and
	177	* 'saved priority' (if masked, this is the priority the
	178	* interrupt had before it was masked). Masking and unmasking
	179	* are done with the ibm,int-off and ibm,int-on RTAS calls.
	180	*/
	181	if (state & KVM_XICS_MASKED) {
	182	irq->priority = 0xff;
	183	} else {
	184	irq->priority = irq->saved_priority;
	185	}
	186
	187	if (state & KVM_XICS_PENDING) {
	188	if (state & KVM_XICS_LEVEL_SENSITIVE) {
	189	irq->status \|= XICS_STATUS_ASSERTED;
	190	} else {
	191	/*
	192	* A pending edge-triggered interrupt (or MSI)
	193	* must have been rejected previously when we
	194	* first detected it and tried to deliver it,
	195	* so mark it as pending and previously rejected
	196	* for consistency with how xics.c works.
	197	*/
	198	irq->status \|= XICS_STATUS_MASKED_PENDING
	199	\| XICS_STATUS_REJECTED;
	200	}
	201	}
	202	}
	203	}
	204
	205	static int ics_set_kvm_state(ICSState *ics, int version_id)
	206	{
27f24582	207	KVMXICSState *xicskvm = XICS_SPAPR_KVM(ics->xics);
11ad93f6 DG	208	uint64_t state;
	209	struct kvm_device_attr attr = {
	210	.flags = 0,
	211	.group = KVM_DEV_XICS_GRP_SOURCES,
	212	.addr = (uint64_t)(uintptr_t)&state,
	213	};
	214	int i;
	215
	216	for (i = 0; i < ics->nr_irqs; i++) {
	217	ICSIRQState *irq = &ics->irqs[i];
	218	int ret;
	219
	220	attr.attr = i + ics->offset;
	221
	222	state = irq->server;
	223	state \|= (uint64_t)(irq->saved_priority & KVM_XICS_PRIORITY_MASK)
	224	<< KVM_XICS_PRIORITY_SHIFT;
	225	if (irq->priority != irq->saved_priority) {
	226	assert(irq->priority == 0xff);
	227	state \|= KVM_XICS_MASKED;
	228	}
	229
4af88944	230	if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
11ad93f6 DG	231	state \|= KVM_XICS_LEVEL_SENSITIVE;
	232	if (irq->status & XICS_STATUS_ASSERTED) {
	233	state \|= KVM_XICS_PENDING;
	234	}
	235	} else {
	236	if (irq->status & XICS_STATUS_MASKED_PENDING) {
	237	state \|= KVM_XICS_PENDING;
	238	}
	239	}
	240
27f24582	241	ret = ioctl(xicskvm->kernel_xics_fd, KVM_SET_DEVICE_ATTR, &attr);
11ad93f6 DG	242	if (ret != 0) {
	243	error_report("Unable to restore KVM interrupt controller state"
	244	" for IRQs %d: %s", i + ics->offset, strerror(errno));
	245	return ret;
	246	}
	247	}
	248
	249	return 0;
	250	}
	251
	252	static void ics_kvm_set_irq(void *opaque, int srcno, int val)
	253	{
	254	ICSState *ics = opaque;
	255	struct kvm_irq_level args;
	256	int rc;
	257
	258	args.irq = srcno + ics->offset;
4af88944	259	if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MSI) {
11ad93f6 DG	260	if (!val) {
	261	return;
	262	}
	263	args.level = KVM_INTERRUPT_SET;
	264	} else {
	265	args.level = val ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
	266	}
	267	rc = kvm_vm_ioctl(kvm_state, KVM_IRQ_LINE, &args);
	268	if (rc < 0) {
	269	perror("kvm_irq_line");
	270	}
	271	}
	272
	273	static void ics_kvm_reset(DeviceState *dev)
	274	{
d4d7a59a	275	ICSState *ics = ICS_SIMPLE(dev);
fb0e843a	276	int i;
a7e519a8 AK	277	uint8_t flags[ics->nr_irqs];
	278
	279	for (i = 0; i < ics->nr_irqs; i++) {
	280	flags[i] = ics->irqs[i].flags;
	281	}
fb0e843a AK	282
fb0e843a AK	283	memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
a7e519a8	284
fb0e843a AK	285	for (i = 0; i < ics->nr_irqs; i++) {
	286	ics->irqs[i].priority = 0xff;
	287	ics->irqs[i].saved_priority = 0xff;
a7e519a8	288	ics->irqs[i].flags = flags[i];
fb0e843a AK	289	}
	290
	291	ics_set_kvm_state(ics, 1);
11ad93f6 DG	292	}
	293
	294	static void ics_kvm_realize(DeviceState dev, Error *errp)
	295	{
d4d7a59a	296	ICSState *ics = ICS_SIMPLE(dev);
11ad93f6 DG	297
	298	if (!ics->nr_irqs) {
	299	error_setg(errp, "Number of interrupts needs to be greater 0");
	300	return;
	301	}
	302	ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
11ad93f6 DG	303	ics->qirqs = qemu_allocate_irqs(ics_kvm_set_irq, ics, ics->nr_irqs);
	304	}
	305
	306	static void ics_kvm_class_init(ObjectClass klass, void data)
	307	{
	308	DeviceClass *dc = DEVICE_CLASS(klass);
d4d7a59a	309	ICSStateClass *icsc = ICS_BASE_CLASS(klass);
11ad93f6 DG	310
	311	dc->realize = ics_kvm_realize;
	312	dc->reset = ics_kvm_reset;
	313	icsc->pre_save = ics_get_kvm_state;
	314	icsc->post_load = ics_set_kvm_state;
	315	}
	316
	317	static const TypeInfo ics_kvm_info = {
d4d7a59a BH	318	.name = TYPE_ICS_KVM,
d4d7a59a BH	319	.parent = TYPE_ICS_SIMPLE,
11ad93f6 DG	320	.instance_size = sizeof(ICSState),
	321	.class_init = ics_kvm_class_init,
	322	};
	323
	324	/*
	325	* XICS-KVM
	326	*/
27f24582	327	static void xics_kvm_cpu_setup(XICSState xics, PowerPCCPU cpu)
11ad93f6 DG	328	{
	329	CPUState *cs;
	330	ICPState *ss;
27f24582	331	KVMXICSState *xicskvm = XICS_SPAPR_KVM(xics);
1b1746a4	332	int ret;
11ad93f6 DG	333
11ad93f6 DG	334	cs = CPU(cpu);
27f24582	335	ss = &xics->ss[cs->cpu_index];
11ad93f6	336
27f24582 BH	337	assert(cs->cpu_index < xics->nr_servers);
27f24582 BH	338	if (xicskvm->kernel_xics_fd == -1) {
11ad93f6 DG	339	abort();
	340	}
	341
a45863bd BR	342	/*
	343	* If we are reusing a parked vCPU fd corresponding to the CPU
	344	* which was hot-removed earlier we don't have to renable
	345	* KVM_CAP_IRQ_XICS capability again.
	346	*/
	347	if (ss->cap_irq_xics_enabled) {
	348	return;
	349	}
	350
1b1746a4 GK	351	ret = kvm_vcpu_enable_cap(cs, KVM_CAP_IRQ_XICS, 0, xicskvm->kernel_xics_fd,
	352	kvm_arch_vcpu_id(cs));
	353	if (ret < 0) {
	354	error_report("Unable to connect CPU%ld to kernel XICS: %s",
	355	kvm_arch_vcpu_id(cs), strerror(errno));
	356	exit(1);
11ad93f6	357	}
1b1746a4	358	ss->cap_irq_xics_enabled = true;
11ad93f6 DG	359	}
11ad93f6 DG	360
27f24582 BH	361	static void xics_kvm_set_nr_irqs(XICSState *xics, uint32_t nr_irqs,
27f24582 BH	362	Error **errp)
11ad93f6	363	{
cc706a53 BH	364	ICSState *ics = QLIST_FIRST(&xics->ics);
	365
	366	/* This needs to be deprecated ... */
	367	xics->nr_irqs = nr_irqs;
	368	if (ics) {
	369	ics->nr_irqs = nr_irqs;
	370	}
11ad93f6 DG	371	}
11ad93f6 DG	372
27f24582	373	static void xics_kvm_set_nr_servers(XICSState *xics, uint32_t nr_servers,
11ad93f6 DG	374	Error **errp)
11ad93f6 DG	375	{
2bb0d10a	376	xics_set_nr_servers(xics, nr_servers, TYPE_KVM_ICP, errp);
11ad93f6 DG	377	}
11ad93f6 DG	378
28e02042	379	static void rtas_dummy(PowerPCCPU cpu, sPAPRMachineState spapr,
11ad93f6 DG	380	uint32_t token,
	381	uint32_t nargs, target_ulong args,
	382	uint32_t nret, target_ulong rets)
	383	{
	384	error_report("pseries: %s must never be called for in-kernel XICS",
	385	__func__);
	386	}
	387
	388	static void xics_kvm_realize(DeviceState dev, Error *errp)
	389	{
27f24582 BH	390	KVMXICSState *xicskvm = XICS_SPAPR_KVM(dev);
27f24582 BH	391	XICSState *xics = XICS_COMMON(dev);
cc706a53	392	ICSState *ics;
11ad93f6 DG	393	int i, rc;
	394	Error *error = NULL;
	395	struct kvm_create_device xics_create_device = {
	396	.type = KVM_DEV_TYPE_XICS,
	397	.flags = 0,
	398	};
	399
	400	if (!kvm_enabled() \|\| !kvm_check_extension(kvm_state, KVM_CAP_IRQ_XICS)) {
	401	error_setg(errp,
	402	"KVM and IRQ_XICS capability must be present for in-kernel XICS");
	403	goto fail;
	404	}
	405
3a3b8502 AK	406	spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_dummy);
	407	spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_dummy);
	408	spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_dummy);
	409	spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_dummy);
11ad93f6	410
3a3b8502	411	rc = kvmppc_define_rtas_kernel_token(RTAS_IBM_SET_XIVE, "ibm,set-xive");
11ad93f6 DG	412	if (rc < 0) {
	413	error_setg(errp, "kvmppc_define_rtas_kernel_token: ibm,set-xive");
	414	goto fail;
	415	}
	416
3a3b8502	417	rc = kvmppc_define_rtas_kernel_token(RTAS_IBM_GET_XIVE, "ibm,get-xive");
11ad93f6 DG	418	if (rc < 0) {
	419	error_setg(errp, "kvmppc_define_rtas_kernel_token: ibm,get-xive");
	420	goto fail;
	421	}
	422
3a3b8502	423	rc = kvmppc_define_rtas_kernel_token(RTAS_IBM_INT_ON, "ibm,int-on");
11ad93f6 DG	424	if (rc < 0) {
	425	error_setg(errp, "kvmppc_define_rtas_kernel_token: ibm,int-on");
	426	goto fail;
	427	}
	428
3a3b8502	429	rc = kvmppc_define_rtas_kernel_token(RTAS_IBM_INT_OFF, "ibm,int-off");
11ad93f6 DG	430	if (rc < 0) {
	431	error_setg(errp, "kvmppc_define_rtas_kernel_token: ibm,int-off");
	432	goto fail;
	433	}
	434
	435	/* Create the kernel ICP */
	436	rc = kvm_vm_ioctl(kvm_state, KVM_CREATE_DEVICE, &xics_create_device);
	437	if (rc < 0) {
	438	error_setg_errno(errp, -rc, "Error on KVM_CREATE_DEVICE for XICS");
	439	goto fail;
	440	}
	441
27f24582	442	xicskvm->kernel_xics_fd = xics_create_device.fd;
11ad93f6	443
cc706a53 BH	444	QLIST_FOREACH(ics, &xics->ics, list) {
	445	object_property_set_bool(OBJECT(ics), true, "realized", &error);
	446	if (error) {
	447	error_propagate(errp, error);
	448	goto fail;
	449	}
11ad93f6 DG	450	}
11ad93f6 DG	451
27f24582 BH	452	assert(xics->nr_servers);
	453	for (i = 0; i < xics->nr_servers; i++) {
	454	object_property_set_bool(OBJECT(&xics->ss[i]), true, "realized",
	455	&error);
11ad93f6 DG	456	if (error) {
	457	error_propagate(errp, error);
	458	goto fail;
	459	}
	460	}
9554233c AK	461
9554233c AK	462	kvm_kernel_irqchip = true;
9554233c AK	463	kvm_msi_via_irqfd_allowed = true;
	464	kvm_gsi_direct_mapping = true;
	465
11ad93f6 DG	466	return;
	467
	468	fail:
	469	kvmppc_define_rtas_kernel_token(0, "ibm,set-xive");
	470	kvmppc_define_rtas_kernel_token(0, "ibm,get-xive");
	471	kvmppc_define_rtas_kernel_token(0, "ibm,int-on");
	472	kvmppc_define_rtas_kernel_token(0, "ibm,int-off");
	473	}
	474
	475	static void xics_kvm_initfn(Object *obj)
	476	{
	477	XICSState *xics = XICS_COMMON(obj);
cc706a53	478	ICSState *ics;
11ad93f6	479
d4d7a59a	480	ics = ICS_SIMPLE(object_new(TYPE_ICS_KVM));
cc706a53 BH	481	object_property_add_child(obj, "ics", OBJECT(ics), NULL);
	482	ics->xics = xics;
	483	QLIST_INSERT_HEAD(&xics->ics, ics, list);
11ad93f6 DG	484	}
	485
	486	static void xics_kvm_class_init(ObjectClass oc, void data)
	487	{
	488	DeviceClass *dc = DEVICE_CLASS(oc);
	489	XICSStateClass *xsc = XICS_COMMON_CLASS(oc);
	490
	491	dc->realize = xics_kvm_realize;
	492	xsc->cpu_setup = xics_kvm_cpu_setup;
	493	xsc->set_nr_irqs = xics_kvm_set_nr_irqs;
	494	xsc->set_nr_servers = xics_kvm_set_nr_servers;
	495	}
	496
161deaf2 BH	497	static const TypeInfo xics_spapr_kvm_info = {
161deaf2 BH	498	.name = TYPE_XICS_SPAPR_KVM,
11ad93f6 DG	499	.parent = TYPE_XICS_COMMON,
	500	.instance_size = sizeof(KVMXICSState),
	501	.class_init = xics_kvm_class_init,
	502	.instance_init = xics_kvm_initfn,
	503	};
	504
	505	static void xics_kvm_register_types(void)
	506	{
161deaf2	507	type_register_static(&xics_spapr_kvm_info);
11ad93f6 DG	508	type_register_static(&ics_kvm_info);
	509	type_register_static(&icp_kvm_info);
	510	}
	511
	512	type_init(xics_kvm_register_types)