[qemu.git] / hw / timer / i8254_common.c

/*
 * QEMU 8253/8254 - common bits of emulated and KVM kernel model
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 * Copyright (c) 2012      Jan Kiszka, Siemens AG
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/isa/isa.h"
#include "qemu/module.h"
#include "qemu/timer.h"
#include "hw/timer/i8254.h"
#include "hw/timer/i8254_internal.h"
#include "migration/qemu-file-types.h"
#include "migration/vmstate.h"

/* val must be 0 or 1 */
void pit_set_gate(ISADevice *dev, int channel, int val)
{
    PITCommonState *pit = PIT_COMMON(dev);
    PITChannelState *s = &pit->channels[channel];
    PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);

    c->set_channel_gate(pit, s, val);
}

/* get pit output bit */
int pit_get_out(PITChannelState *s, int64_t current_time)
{
    uint64_t d;
    int out;

    d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
                 NANOSECONDS_PER_SECOND);
    switch (s->mode) {
    default:
    case 0:
        out = (d >= s->count);
        break;
    case 1:
        out = (d < s->count);
        break;
    case 2:
        if ((d % s->count) == 0 && d != 0) {
            out = 1;
        } else {
            out = 0;
        }
        break;
    case 3:
        out = (d % s->count) < ((s->count + 1) >> 1);
        break;
    case 4:
    case 5:
        out = (d == s->count);
        break;
    }
    return out;
}

/* return -1 if no transition will occur.  */
int64_t pit_get_next_transition_time(PITChannelState *s, int64_t current_time)
{
    uint64_t d, next_time, base;
    int period2;

    d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
                 NANOSECONDS_PER_SECOND);
    switch (s->mode) {
    default:
    case 0:
    case 1:
        if (d < s->count) {
            next_time = s->count;
        } else {
            return -1;
        }
        break;
    case 2:
        base = QEMU_ALIGN_DOWN(d, s->count);
        if ((d - base) == 0 && d != 0) {
            next_time = base + s->count;
        } else {
            next_time = base + s->count + 1;
        }
        break;
    case 3:
        base = QEMU_ALIGN_DOWN(d, s->count);
        period2 = ((s->count + 1) >> 1);
        if ((d - base) < period2) {
            next_time = base + period2;
        } else {
            next_time = base + s->count;
        }
        break;
    case 4:
    case 5:
        if (d < s->count) {
            next_time = s->count;
        } else if (d == s->count) {
            next_time = s->count + 1;
        } else {
            return -1;
        }
        break;
    }
    /* convert to timer units */
    next_time = s->count_load_time + muldiv64(next_time, NANOSECONDS_PER_SECOND,
                                              PIT_FREQ);
    /* fix potential rounding problems */
    /* XXX: better solution: use a clock at PIT_FREQ Hz */
    if (next_time <= current_time) {
        next_time = current_time + 1;
    }
    return next_time;
}

void pit_get_channel_info_common(PITCommonState *s, PITChannelState *sc,
                                 PITChannelInfo *info)
{
    info->gate = sc->gate;
    info->mode = sc->mode;
    info->initial_count = sc->count;
    info->out = pit_get_out(sc, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
}

void pit_get_channel_info(ISADevice *dev, int channel, PITChannelInfo *info)
{
    PITCommonState *pit = PIT_COMMON(dev);
    PITChannelState *s = &pit->channels[channel];
    PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);

    c->get_channel_info(pit, s, info);
}

void pit_reset_common(PITCommonState *pit)
{
    PITChannelState *s;
    int i;

    for (i = 0; i < 3; i++) {
        s = &pit->channels[i];
        s->mode = 3;
        s->gate = (i != 2);
        s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
        s->count = 0x10000;
        if (i == 0 && !s->irq_disabled) {
            s->next_transition_time =
                pit_get_next_transition_time(s, s->count_load_time);
        }
    }
}

static void pit_common_realize(DeviceState *dev, Error **errp)
{
    ISADevice *isadev = ISA_DEVICE(dev);
    PITCommonState *pit = PIT_COMMON(dev);

    isa_register_ioport(isadev, &pit->ioports, pit->iobase);

    qdev_set_legacy_instance_id(dev, pit->iobase, 2);
}

static const VMStateDescription vmstate_pit_channel = {
    .name = "pit channel",
    .version_id = 2,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_INT32(count, PITChannelState),
        VMSTATE_UINT16(latched_count, PITChannelState),
        VMSTATE_UINT8(count_latched, PITChannelState),
        VMSTATE_UINT8(status_latched, PITChannelState),
        VMSTATE_UINT8(status, PITChannelState),
        VMSTATE_UINT8(read_state, PITChannelState),
        VMSTATE_UINT8(write_state, PITChannelState),
        VMSTATE_UINT8(write_latch, PITChannelState),
        VMSTATE_UINT8(rw_mode, PITChannelState),
        VMSTATE_UINT8(mode, PITChannelState),
        VMSTATE_UINT8(bcd, PITChannelState),
        VMSTATE_UINT8(gate, PITChannelState),
        VMSTATE_INT64(count_load_time, PITChannelState),
        VMSTATE_INT64(next_transition_time, PITChannelState),
        VMSTATE_END_OF_LIST()
    }
};

static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
{
    PITCommonState *pit = opaque;
    PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
    PITChannelState *s;
    int i;

    if (version_id != 1) {
        return -EINVAL;
    }

    for (i = 0; i < 3; i++) {
        s = &pit->channels[i];
        s->count = qemu_get_be32(f);
        qemu_get_be16s(f, &s->latched_count);
        qemu_get_8s(f, &s->count_latched);
        qemu_get_8s(f, &s->status_latched);
        qemu_get_8s(f, &s->status);
        qemu_get_8s(f, &s->read_state);
        qemu_get_8s(f, &s->write_state);
        qemu_get_8s(f, &s->write_latch);
        qemu_get_8s(f, &s->rw_mode);
        qemu_get_8s(f, &s->mode);
        qemu_get_8s(f, &s->bcd);
        qemu_get_8s(f, &s->gate);
        s->count_load_time = qemu_get_be64(f);
        s->irq_disabled = 0;
        if (i == 0) {
            s->next_transition_time = qemu_get_be64(f);
        }
    }
    if (c->post_load) {
        c->post_load(pit);
    }
    return 0;
}

static int pit_dispatch_pre_save(void *opaque)
{
    PITCommonState *s = opaque;
    PITCommonClass *c = PIT_COMMON_GET_CLASS(s);

    if (c->pre_save) {
        c->pre_save(s);
    }

    return 0;
}

static int pit_dispatch_post_load(void *opaque, int version_id)
{
    PITCommonState *s = opaque;
    PITCommonClass *c = PIT_COMMON_GET_CLASS(s);

    if (c->post_load) {
        c->post_load(s);
    }
    return 0;
}

static const VMStateDescription vmstate_pit_common = {
    .name = "i8254",
    .version_id = 3,
    .minimum_version_id = 2,
    .minimum_version_id_old = 1,
    .load_state_old = pit_load_old,
    .pre_save = pit_dispatch_pre_save,
    .post_load = pit_dispatch_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_V(channels[0].irq_disabled, PITCommonState, 3),
        VMSTATE_STRUCT_ARRAY(channels, PITCommonState, 3, 2,
                             vmstate_pit_channel, PITChannelState),
        VMSTATE_INT64(channels[0].next_transition_time,
                      PITCommonState), /* formerly irq_timer */
        VMSTATE_END_OF_LIST()
    }
};

static void pit_common_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = pit_common_realize;
    dc->vmsd = &vmstate_pit_common;
    /*
     * Reason: unlike ordinary ISA devices, the PIT may need to be
     * wired to the HPET, and because of that, some wiring is always
     * done by board code.
     */
    dc->user_creatable = false;
}

static const TypeInfo pit_common_type = {
    .name          = TYPE_PIT_COMMON,
    .parent        = TYPE_ISA_DEVICE,
    .instance_size = sizeof(PITCommonState),
    .class_size    = sizeof(PITCommonClass),
    .class_init    = pit_common_class_init,
    .abstract      = true,
};

static void register_devices(void)
{
    type_register_static(&pit_common_type);
}

type_init(register_devices);
Commit	Line	Data
d11e859e JK	1	/*
	2	* QEMU 8253/8254 - common bits of emulated and KVM kernel model
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	* Copyright (c) 2012 Jan Kiszka, Siemens AG
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
0b8fa32f	25
b6a0aa05	26	#include "qemu/osdep.h"
83c9f4ca	27	#include "hw/hw.h"
0d09e41a	28	#include "hw/isa/isa.h"
0b8fa32f	29	#include "qemu/module.h"
1de7afc9	30	#include "qemu/timer.h"
0d09e41a PB	31	#include "hw/timer/i8254.h"
0d09e41a PB	32	#include "hw/timer/i8254_internal.h"
ca77ee28	33	#include "migration/qemu-file-types.h"
d6454270	34	#include "migration/vmstate.h"
d11e859e JK	35
	36	/* val must be 0 or 1 */
	37	void pit_set_gate(ISADevice *dev, int channel, int val)
	38	{
	39	PITCommonState *pit = PIT_COMMON(dev);
	40	PITChannelState *s = &pit->channels[channel];
	41	PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
	42
	43	c->set_channel_gate(pit, s, val);
	44	}
	45
	46	/* get pit output bit */
	47	int pit_get_out(PITChannelState *s, int64_t current_time)
	48	{
	49	uint64_t d;
	50	int out;
	51
	52	d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
73bcb24d	53	NANOSECONDS_PER_SECOND);
d11e859e JK	54	switch (s->mode) {
	55	default:
	56	case 0:
	57	out = (d >= s->count);
	58	break;
	59	case 1:
	60	out = (d < s->count);
	61	break;
	62	case 2:
	63	if ((d % s->count) == 0 && d != 0) {
	64	out = 1;
	65	} else {
	66	out = 0;
	67	}
	68	break;
	69	case 3:
	70	out = (d % s->count) < ((s->count + 1) >> 1);
	71	break;
	72	case 4:
	73	case 5:
	74	out = (d == s->count);
	75	break;
	76	}
	77	return out;
	78	}
	79
	80	/* return -1 if no transition will occur. */
	81	int64_t pit_get_next_transition_time(PITChannelState *s, int64_t current_time)
	82	{
	83	uint64_t d, next_time, base;
	84	int period2;
	85
	86	d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
73bcb24d	87	NANOSECONDS_PER_SECOND);
d11e859e JK	88	switch (s->mode) {
	89	default:
	90	case 0:
	91	case 1:
	92	if (d < s->count) {
	93	next_time = s->count;
	94	} else {
	95	return -1;
	96	}
	97	break;
	98	case 2:
ec347485	99	base = QEMU_ALIGN_DOWN(d, s->count);
d11e859e JK	100	if ((d - base) == 0 && d != 0) {
	101	next_time = base + s->count;
	102	} else {
	103	next_time = base + s->count + 1;
	104	}
	105	break;
	106	case 3:
ec347485	107	base = QEMU_ALIGN_DOWN(d, s->count);
d11e859e JK	108	period2 = ((s->count + 1) >> 1);
	109	if ((d - base) < period2) {
	110	next_time = base + period2;
	111	} else {
	112	next_time = base + s->count;
	113	}
	114	break;
	115	case 4:
	116	case 5:
	117	if (d < s->count) {
	118	next_time = s->count;
	119	} else if (d == s->count) {
	120	next_time = s->count + 1;
	121	} else {
	122	return -1;
	123	}
	124	break;
	125	}
	126	/* convert to timer units */
73bcb24d	127	next_time = s->count_load_time + muldiv64(next_time, NANOSECONDS_PER_SECOND,
d11e859e JK	128	PIT_FREQ);
	129	/* fix potential rounding problems */
	130	/* XXX: better solution: use a clock at PIT_FREQ Hz */
	131	if (next_time <= current_time) {
	132	next_time = current_time + 1;
	133	}
	134	return next_time;
	135	}
	136
	137	void pit_get_channel_info_common(PITCommonState s, PITChannelState sc,
	138	PITChannelInfo *info)
	139	{
	140	info->gate = sc->gate;
	141	info->mode = sc->mode;
	142	info->initial_count = sc->count;
bc72ad67	143	info->out = pit_get_out(sc, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
d11e859e JK	144	}
	145
	146	void pit_get_channel_info(ISADevice dev, int channel, PITChannelInfo info)
	147	{
	148	PITCommonState *pit = PIT_COMMON(dev);
	149	PITChannelState *s = &pit->channels[channel];
	150	PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
	151
	152	c->get_channel_info(pit, s, info);
	153	}
	154
	155	void pit_reset_common(PITCommonState *pit)
	156	{
	157	PITChannelState *s;
	158	int i;
	159
	160	for (i = 0; i < 3; i++) {
	161	s = &pit->channels[i];
	162	s->mode = 3;
	163	s->gate = (i != 2);
bc72ad67	164	s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
d11e859e JK	165	s->count = 0x10000;
	166	if (i == 0 && !s->irq_disabled) {
	167	s->next_transition_time =
	168	pit_get_next_transition_time(s, s->count_load_time);
	169	}
	170	}
	171	}
	172
db895a1e	173	static void pit_common_realize(DeviceState dev, Error *errp)
d11e859e	174	{
db895a1e	175	ISADevice *isadev = ISA_DEVICE(dev);
d11e859e	176	PITCommonState *pit = PIT_COMMON(dev);
d11e859e	177
db895a1e	178	isa_register_ioport(isadev, &pit->ioports, pit->iobase);
d11e859e	179
db895a1e	180	qdev_set_legacy_instance_id(dev, pit->iobase, 2);
d11e859e JK	181	}
	182
	183	static const VMStateDescription vmstate_pit_channel = {
	184	.name = "pit channel",
	185	.version_id = 2,
	186	.minimum_version_id = 2,
d11e859e JK	187	.fields = (VMStateField[]) {
	188	VMSTATE_INT32(count, PITChannelState),
	189	VMSTATE_UINT16(latched_count, PITChannelState),
	190	VMSTATE_UINT8(count_latched, PITChannelState),
	191	VMSTATE_UINT8(status_latched, PITChannelState),
	192	VMSTATE_UINT8(status, PITChannelState),
	193	VMSTATE_UINT8(read_state, PITChannelState),
	194	VMSTATE_UINT8(write_state, PITChannelState),
	195	VMSTATE_UINT8(write_latch, PITChannelState),
	196	VMSTATE_UINT8(rw_mode, PITChannelState),
	197	VMSTATE_UINT8(mode, PITChannelState),
	198	VMSTATE_UINT8(bcd, PITChannelState),
	199	VMSTATE_UINT8(gate, PITChannelState),
	200	VMSTATE_INT64(count_load_time, PITChannelState),
	201	VMSTATE_INT64(next_transition_time, PITChannelState),
	202	VMSTATE_END_OF_LIST()
	203	}
	204	};
	205
	206	static int pit_load_old(QEMUFile f, void opaque, int version_id)
	207	{
	208	PITCommonState *pit = opaque;
3fbc1c0c	209	PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
d11e859e JK	210	PITChannelState *s;
	211	int i;
	212
	213	if (version_id != 1) {
	214	return -EINVAL;
	215	}
	216
	217	for (i = 0; i < 3; i++) {
	218	s = &pit->channels[i];
	219	s->count = qemu_get_be32(f);
	220	qemu_get_be16s(f, &s->latched_count);
	221	qemu_get_8s(f, &s->count_latched);
	222	qemu_get_8s(f, &s->status_latched);
	223	qemu_get_8s(f, &s->status);
	224	qemu_get_8s(f, &s->read_state);
	225	qemu_get_8s(f, &s->write_state);
	226	qemu_get_8s(f, &s->write_latch);
	227	qemu_get_8s(f, &s->rw_mode);
	228	qemu_get_8s(f, &s->mode);
	229	qemu_get_8s(f, &s->bcd);
	230	qemu_get_8s(f, &s->gate);
	231	s->count_load_time = qemu_get_be64(f);
	232	s->irq_disabled = 0;
3fbc1c0c	233	if (i == 0) {
d11e859e	234	s->next_transition_time = qemu_get_be64(f);
d11e859e JK	235	}
d11e859e JK	236	}
3fbc1c0c JK	237	if (c->post_load) {
	238	c->post_load(pit);
	239	}
d11e859e JK	240	return 0;
	241	}
	242
44b1ff31	243	static int pit_dispatch_pre_save(void *opaque)
d11e859e JK	244	{
	245	PITCommonState *s = opaque;
	246	PITCommonClass *c = PIT_COMMON_GET_CLASS(s);
	247
	248	if (c->pre_save) {
	249	c->pre_save(s);
	250	}
44b1ff31 DDAG	251
44b1ff31 DDAG	252	return 0;
d11e859e JK	253	}
	254
	255	static int pit_dispatch_post_load(void *opaque, int version_id)
	256	{
	257	PITCommonState *s = opaque;
	258	PITCommonClass *c = PIT_COMMON_GET_CLASS(s);
	259
	260	if (c->post_load) {
	261	c->post_load(s);
	262	}
	263	return 0;
	264	}
	265
	266	static const VMStateDescription vmstate_pit_common = {
	267	.name = "i8254",
	268	.version_id = 3,
	269	.minimum_version_id = 2,
	270	.minimum_version_id_old = 1,
	271	.load_state_old = pit_load_old,
	272	.pre_save = pit_dispatch_pre_save,
	273	.post_load = pit_dispatch_post_load,
	274	.fields = (VMStateField[]) {
	275	VMSTATE_UINT32_V(channels[0].irq_disabled, PITCommonState, 3),
	276	VMSTATE_STRUCT_ARRAY(channels, PITCommonState, 3, 2,
	277	vmstate_pit_channel, PITChannelState),
3fbc1c0c JK	278	VMSTATE_INT64(channels[0].next_transition_time,
3fbc1c0c JK	279	PITCommonState), /* formerly irq_timer */
d11e859e JK	280	VMSTATE_END_OF_LIST()
	281	}
	282	};
	283
	284	static void pit_common_class_init(ObjectClass klass, void data)
	285	{
d11e859e JK	286	DeviceClass *dc = DEVICE_CLASS(klass);
d11e859e JK	287
db895a1e	288	dc->realize = pit_common_realize;
d11e859e	289	dc->vmsd = &vmstate_pit_common;
f3b17640 MA	290	/*
	291	* Reason: unlike ordinary ISA devices, the PIT may need to be
	292	* wired to the HPET, and because of that, some wiring is always
	293	* done by board code.
	294	*/
e90f2a8c	295	dc->user_creatable = false;
d11e859e JK	296	}
d11e859e JK	297
8c43a6f0	298	static const TypeInfo pit_common_type = {
d11e859e JK	299	.name = TYPE_PIT_COMMON,
	300	.parent = TYPE_ISA_DEVICE,
	301	.instance_size = sizeof(PITCommonState),
	302	.class_size = sizeof(PITCommonClass),
	303	.class_init = pit_common_class_init,
	304	.abstract = true,
	305	};
	306
	307	static void register_devices(void)
	308	{
	309	type_register_static(&pit_common_type);
	310	}
	311
	312	type_init(register_devices);