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a04ff940 AF |
1 | /* |
2 | * QEMU Intel i82378 emulation (PCI to ISA bridge) | |
3 | * | |
4 | * Copyright (c) 2010-2011 Hervé Poussineau | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
0430891c | 20 | #include "qemu/osdep.h" |
83c9f4ca | 21 | #include "hw/pci/pci.h" |
0d09e41a | 22 | #include "hw/i386/pc.h" |
64552b6b | 23 | #include "hw/irq.h" |
0d09e41a | 24 | #include "hw/timer/i8254.h" |
d6454270 | 25 | #include "migration/vmstate.h" |
0d09e41a | 26 | #include "hw/audio/pcspk.h" |
a04ff940 | 27 | |
5c973678 HP |
28 | #define TYPE_I82378 "i82378" |
29 | #define I82378(obj) \ | |
30 | OBJECT_CHECK(I82378State, (obj), TYPE_I82378) | |
a04ff940 AF |
31 | |
32 | typedef struct I82378State { | |
5c973678 HP |
33 | PCIDevice parent_obj; |
34 | ||
a04ff940 AF |
35 | qemu_irq out[2]; |
36 | qemu_irq *i8259; | |
37 | MemoryRegion io; | |
a04ff940 AF |
38 | } I82378State; |
39 | ||
5c973678 | 40 | static const VMStateDescription vmstate_i82378 = { |
a04ff940 AF |
41 | .name = "pci-i82378", |
42 | .version_id = 0, | |
43 | .minimum_version_id = 0, | |
44 | .fields = (VMStateField[]) { | |
5c973678 | 45 | VMSTATE_PCI_DEVICE(parent_obj, I82378State), |
a04ff940 AF |
46 | VMSTATE_END_OF_LIST() |
47 | }, | |
48 | }; | |
49 | ||
a04ff940 AF |
50 | static void i82378_request_out0_irq(void *opaque, int irq, int level) |
51 | { | |
52 | I82378State *s = opaque; | |
53 | qemu_set_irq(s->out[0], level); | |
54 | } | |
55 | ||
56 | static void i82378_request_pic_irq(void *opaque, int irq, int level) | |
57 | { | |
58 | DeviceState *dev = opaque; | |
5c973678 | 59 | I82378State *s = I82378(dev); |
a04ff940 | 60 | |
5c973678 | 61 | qemu_set_irq(s->i8259[irq], level); |
a04ff940 AF |
62 | } |
63 | ||
9af21dbe | 64 | static void i82378_realize(PCIDevice *pci, Error **errp) |
a04ff940 | 65 | { |
5c973678 HP |
66 | DeviceState *dev = DEVICE(pci); |
67 | I82378State *s = I82378(dev); | |
68 | uint8_t *pci_conf; | |
69 | ISABus *isabus; | |
049a9f7b | 70 | ISADevice *isa; |
a04ff940 | 71 | |
5c973678 HP |
72 | pci_conf = pci->config; |
73 | pci_set_word(pci_conf + PCI_COMMAND, | |
74 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
75 | pci_set_word(pci_conf + PCI_STATUS, | |
76 | PCI_STATUS_DEVSEL_MEDIUM); | |
77 | ||
78 | pci_config_set_interrupt_pin(pci_conf, 1); /* interrupt pin 0 */ | |
79 | ||
bb2ed009 | 80 | isabus = isa_bus_new(dev, get_system_memory(), |
d10e5432 MA |
81 | pci_address_space_io(pci), errp); |
82 | if (!isabus) { | |
83 | return; | |
84 | } | |
5c973678 | 85 | |
a04ff940 AF |
86 | /* This device has: |
87 | 2 82C59 (irq) | |
88 | 1 82C54 (pit) | |
89 | 2 82C37 (dma) | |
90 | NMI | |
91 | Utility Bus Support Registers | |
92 | ||
93 | All devices accept byte access only, except timer | |
94 | */ | |
95 | ||
a04ff940 | 96 | /* 2 82C59 (irq) */ |
5105505e SZ |
97 | s->i8259 = i8259_init(isabus, |
98 | qemu_allocate_irq(i82378_request_out0_irq, s, 0)); | |
a04ff940 AF |
99 | isa_bus_irqs(isabus, s->i8259); |
100 | ||
101 | /* 1 82C54 (pit) */ | |
acf695ec | 102 | isa = i8254_pit_init(isabus, 0x40, 0, NULL); |
a04ff940 AF |
103 | |
104 | /* speaker */ | |
5c973678 | 105 | pcspk_init(isabus, isa); |
a04ff940 AF |
106 | |
107 | /* 2 82C37 (dma) */ | |
049a9f7b | 108 | isa = isa_create_simple(isabus, "i82374"); |
a04ff940 AF |
109 | } |
110 | ||
5c973678 | 111 | static void i82378_init(Object *obj) |
a04ff940 | 112 | { |
5c973678 HP |
113 | DeviceState *dev = DEVICE(obj); |
114 | I82378State *s = I82378(obj); | |
a04ff940 | 115 | |
5039d6e2 | 116 | qdev_init_gpio_out(dev, s->out, 1); |
5c973678 | 117 | qdev_init_gpio_in(dev, i82378_request_pic_irq, 16); |
a04ff940 AF |
118 | } |
119 | ||
5c973678 | 120 | static void i82378_class_init(ObjectClass *klass, void *data) |
40021f08 AL |
121 | { |
122 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
39bffca2 | 123 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 124 | |
9af21dbe | 125 | k->realize = i82378_realize; |
40021f08 AL |
126 | k->vendor_id = PCI_VENDOR_ID_INTEL; |
127 | k->device_id = PCI_DEVICE_ID_INTEL_82378; | |
128 | k->revision = 0x03; | |
129 | k->class_id = PCI_CLASS_BRIDGE_ISA; | |
5c973678 | 130 | dc->vmsd = &vmstate_i82378; |
125ee0ed | 131 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
40021f08 AL |
132 | } |
133 | ||
5c973678 HP |
134 | static const TypeInfo i82378_type_info = { |
135 | .name = TYPE_I82378, | |
39bffca2 | 136 | .parent = TYPE_PCI_DEVICE, |
5c973678 HP |
137 | .instance_size = sizeof(I82378State), |
138 | .instance_init = i82378_init, | |
139 | .class_init = i82378_class_init, | |
fd3b02c8 EH |
140 | .interfaces = (InterfaceInfo[]) { |
141 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
142 | { }, | |
143 | }, | |
a04ff940 AF |
144 | }; |
145 | ||
83f7d43a | 146 | static void i82378_register_types(void) |
a04ff940 | 147 | { |
5c973678 | 148 | type_register_static(&i82378_type_info); |
a04ff940 AF |
149 | } |
150 | ||
83f7d43a | 151 | type_init(i82378_register_types) |