]> Git Repo - qemu.git/blame - hw/usb/hcd-xhci.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
pci: removed the is_express field since a uniform interface was inserted
[qemu.git] / hw / usb / hcd-xhci.c
CommitLineData
62c6ae04
HM		 1/*
2 * USB xHCI controller emulation
3 *
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <[email protected]>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
e532b2e0 21#include "qemu/osdep.h"
f1ae32a1 22#include "hw/hw.h"
1de7afc9 23#include "qemu/timer.h"
94b037f2 24#include "qemu/queue.h"
f1ae32a1 25#include "hw/usb.h"
a2cb15b0
MT		 26#include "hw/pci/pci.h"
27#include "hw/pci/msi.h"
28#include "hw/pci/msix.h"
2d754a10 29#include "trace.h"
1108b2f8 30#include "qapi/error.h"
62c6ae04 31
0bbb2f3d
GH		 32#include "hcd-xhci.h"
33
62c6ae04
HM		 34//#define DEBUG_XHCI
35//#define DEBUG_DATA
36
37#ifdef DEBUG_XHCI
38#define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
39#else
40#define DPRINTF(...) do {} while (0)
41#endif
024426ac
GH		 42#define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \
43 __func__, __LINE__, _msg); abort(); } while (0)
62c6ae04 44
99f9aeba 45#define TRB_LINK_LIMIT 32
f89b60f6
GH		 46#define COMMAND_LIMIT 256
47#define TRANSFER_LIMIT 256
05f43d44 48
62c6ae04 49#define LEN_CAP 0x40
62c6ae04 50#define LEN_OPER (0x400 + 0x10 * MAXPORTS)
106b214c 51#define LEN_RUNTIME ((MAXINTRS + 1) * 0x20)
62c6ae04
HM		 52#define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
53
106b214c
GH		 54#define OFF_OPER LEN_CAP
55#define OFF_RUNTIME 0x1000
56#define OFF_DOORBELL 0x2000
4c47f800
GH		 57#define OFF_MSIX_TABLE 0x3000
58#define OFF_MSIX_PBA 0x3800
62c6ae04 59/* must be power of 2 */
106b214c 60#define LEN_REGS 0x4000
62c6ae04 61
106b214c
GH		 62#if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
63#error Increase OFF_RUNTIME
64#endif
65#if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
66#error Increase OFF_DOORBELL
67#endif
62c6ae04
HM		 68#if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
69# error Increase LEN_REGS
70#endif
71
62c6ae04
HM		 72/* bit definitions */
73#define USBCMD_RS (1<<0)
74#define USBCMD_HCRST (1<<1)
75#define USBCMD_INTE (1<<2)
76#define USBCMD_HSEE (1<<3)
77#define USBCMD_LHCRST (1<<7)
78#define USBCMD_CSS (1<<8)
79#define USBCMD_CRS (1<<9)
80#define USBCMD_EWE (1<<10)
81#define USBCMD_EU3S (1<<11)
82
83#define USBSTS_HCH (1<<0)
84#define USBSTS_HSE (1<<2)
85#define USBSTS_EINT (1<<3)
86#define USBSTS_PCD (1<<4)
87#define USBSTS_SSS (1<<8)
88#define USBSTS_RSS (1<<9)
89#define USBSTS_SRE (1<<10)
90#define USBSTS_CNR (1<<11)
91#define USBSTS_HCE (1<<12)
92
93
94#define PORTSC_CCS (1<<0)
95#define PORTSC_PED (1<<1)
96#define PORTSC_OCA (1<<3)
97#define PORTSC_PR (1<<4)
98#define PORTSC_PLS_SHIFT 5
99#define PORTSC_PLS_MASK 0xf
100#define PORTSC_PP (1<<9)
101#define PORTSC_SPEED_SHIFT 10
102#define PORTSC_SPEED_MASK 0xf
103#define PORTSC_SPEED_FULL (1<<10)
104#define PORTSC_SPEED_LOW (2<<10)
105#define PORTSC_SPEED_HIGH (3<<10)
106#define PORTSC_SPEED_SUPER (4<<10)
107#define PORTSC_PIC_SHIFT 14
108#define PORTSC_PIC_MASK 0x3
109#define PORTSC_LWS (1<<16)
110#define PORTSC_CSC (1<<17)
111#define PORTSC_PEC (1<<18)
112#define PORTSC_WRC (1<<19)
113#define PORTSC_OCC (1<<20)
114#define PORTSC_PRC (1<<21)
115#define PORTSC_PLC (1<<22)
116#define PORTSC_CEC (1<<23)
117#define PORTSC_CAS (1<<24)
118#define PORTSC_WCE (1<<25)
119#define PORTSC_WDE (1<<26)
120#define PORTSC_WOE (1<<27)
121#define PORTSC_DR (1<<30)
122#define PORTSC_WPR (1<<31)
123
124#define CRCR_RCS (1<<0)
125#define CRCR_CS (1<<1)
126#define CRCR_CA (1<<2)
127#define CRCR_CRR (1<<3)
128
129#define IMAN_IP (1<<0)
130#define IMAN_IE (1<<1)
131
132#define ERDP_EHB (1<<3)
133
134#define TRB_SIZE 16
135typedef struct XHCITRB {
136 uint64_t parameter;
137 uint32_t status;
138 uint32_t control;
59a70ccd 139 dma_addr_t addr;
62c6ae04
HM		 140 bool ccs;
141} XHCITRB;
142
85e05d82
GH		 143enum {
144 PLS_U0 = 0,
145 PLS_U1 = 1,
146 PLS_U2 = 2,
147 PLS_U3 = 3,
148 PLS_DISABLED = 4,
149 PLS_RX_DETECT = 5,
150 PLS_INACTIVE = 6,
151 PLS_POLLING = 7,
152 PLS_RECOVERY = 8,
153 PLS_HOT_RESET = 9,
154 PLS_COMPILANCE_MODE = 10,
155 PLS_TEST_MODE = 11,
156 PLS_RESUME = 15,
157};
62c6ae04 158
62c6ae04
HM		 159#define CR_LINK TR_LINK
160
62c6ae04
HM		 161#define TRB_C (1<<0)
162#define TRB_TYPE_SHIFT 10
163#define TRB_TYPE_MASK 0x3f
164#define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
165
166#define TRB_EV_ED (1<<2)
167
168#define TRB_TR_ENT (1<<1)
169#define TRB_TR_ISP (1<<2)
170#define TRB_TR_NS (1<<3)
171#define TRB_TR_CH (1<<4)
172#define TRB_TR_IOC (1<<5)
173#define TRB_TR_IDT (1<<6)
174#define TRB_TR_TBC_SHIFT 7
175#define TRB_TR_TBC_MASK 0x3
176#define TRB_TR_BEI (1<<9)
177#define TRB_TR_TLBPC_SHIFT 16
178#define TRB_TR_TLBPC_MASK 0xf
179#define TRB_TR_FRAMEID_SHIFT 20
180#define TRB_TR_FRAMEID_MASK 0x7ff
181#define TRB_TR_SIA (1<<31)
182
183#define TRB_TR_DIR (1<<16)
184
185#define TRB_CR_SLOTID_SHIFT 24
186#define TRB_CR_SLOTID_MASK 0xff
187#define TRB_CR_EPID_SHIFT 16
188#define TRB_CR_EPID_MASK 0x1f
189
190#define TRB_CR_BSR (1<<9)
191#define TRB_CR_DC (1<<9)
192
193#define TRB_LK_TC (1<<1)
194
2d1de850
GH		 195#define TRB_INTR_SHIFT 22
196#define TRB_INTR_MASK 0x3ff
197#define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
198
62c6ae04
HM		 199#define EP_TYPE_MASK 0x7
200#define EP_TYPE_SHIFT 3
201
202#define EP_STATE_MASK 0x7
203#define EP_DISABLED (0<<0)
204#define EP_RUNNING (1<<0)
205#define EP_HALTED (2<<0)
206#define EP_STOPPED (3<<0)
207#define EP_ERROR (4<<0)
208
209#define SLOT_STATE_MASK 0x1f
210#define SLOT_STATE_SHIFT 27
211#define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
212#define SLOT_ENABLED 0
213#define SLOT_DEFAULT 1
214#define SLOT_ADDRESSED 2
215#define SLOT_CONFIGURED 3
216
217#define SLOT_CONTEXT_ENTRIES_MASK 0x1f
218#define SLOT_CONTEXT_ENTRIES_SHIFT 27
219
85e05d82
GH		 220#define get_field(data, field) \
221 (((data) >> field##_SHIFT) & field##_MASK)
222
223#define set_field(data, newval, field) do { \
224 uint32_t val = *data; \
225 val &= ~(field##_MASK << field##_SHIFT); \
226 val |= ((newval) & field##_MASK) << field##_SHIFT; \
227 *data = val; \
228 } while (0)
229
62c6ae04
HM		 230typedef enum EPType {
231 ET_INVALID = 0,
232 ET_ISO_OUT,
233 ET_BULK_OUT,
234 ET_INTR_OUT,
235 ET_CONTROL,
236 ET_ISO_IN,
237 ET_BULK_IN,
238 ET_INTR_IN,
239} EPType;
240
62c6ae04 241typedef struct XHCITransfer {
94b037f2 242 XHCIEPContext *epctx;
62c6ae04 243 USBPacket packet;
d5a15814 244 QEMUSGList sgl;
7c605a23
GH		 245 bool running_async;
246 bool running_retry;
62c6ae04 247 bool complete;
a6fb2ddb 248 bool int_req;
62c6ae04 249 unsigned int iso_pkts;
024426ac 250 unsigned int streamid;
62c6ae04
HM		 251 bool in_xfer;
252 bool iso_xfer;
4d7a81c0 253 bool timed_xfer;
62c6ae04
HM		 254
255 unsigned int trb_count;
62c6ae04
HM		 256 XHCITRB *trbs;
257
62c6ae04
HM		 258 TRBCCode status;
259
260 unsigned int pkts;
261 unsigned int pktsize;
262 unsigned int cur_pkt;
3d139684
GH		 263
264 uint64_t mfindex_kick;
94b037f2
GH		 265
266 QTAILQ_ENTRY(XHCITransfer) next;
62c6ae04
HM		 267} XHCITransfer;
268
024426ac
GH		 269struct XHCIStreamContext {
270 dma_addr_t pctx;
271 unsigned int sct;
272 XHCIRing ring;
024426ac
GH		 273};
274
275struct XHCIEPContext {
3d139684
GH		 276 XHCIState *xhci;
277 unsigned int slotid;
278 unsigned int epid;
279
62c6ae04 280 XHCIRing ring;
94b037f2
GH		 281 uint32_t xfer_count;
282 QTAILQ_HEAD(, XHCITransfer) transfers;
7c605a23 283 XHCITransfer *retry;
62c6ae04 284 EPType type;
59a70ccd 285 dma_addr_t pctx;
62c6ae04 286 unsigned int max_psize;
62c6ae04 287 uint32_t state;
96d87bdd 288 uint32_t kick_active;
3d139684 289
024426ac
GH		 290 /* streams */
291 unsigned int max_pstreams;
292 bool lsa;
293 unsigned int nr_pstreams;
294 XHCIStreamContext *pstreams;
295
3d139684
GH		 296 /* iso xfer scheduling */
297 unsigned int interval;
298 int64_t mfindex_last;
299 QEMUTimer *kick_timer;
024426ac 300};
62c6ae04 301
62c6ae04
HM		 302typedef struct XHCIEvRingSeg {
303 uint32_t addr_low;
304 uint32_t addr_high;
305 uint32_t size;
306 uint32_t rsvd;
307} XHCIEvRingSeg;
308
01546fa6 309static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
024426ac 310 unsigned int epid, unsigned int streamid);
3a533ee8 311static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid);
0bc85da6
GH		 312static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
313 unsigned int epid);
582d6f4a 314static void xhci_xfer_report(XHCITransfer *xfer);
962d11e1
GH		 315static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v);
316static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v);
070eeef9 317static USBEndpoint *xhci_epid_to_usbep(XHCIEPContext *epctx);
01546fa6 318
f10de44e
GH		 319static const char *TRBType_names[] = {
320 [TRB_RESERVED] = "TRB_RESERVED",
321 [TR_NORMAL] = "TR_NORMAL",
322 [TR_SETUP] = "TR_SETUP",
323 [TR_DATA] = "TR_DATA",
324 [TR_STATUS] = "TR_STATUS",
325 [TR_ISOCH] = "TR_ISOCH",
326 [TR_LINK] = "TR_LINK",
327 [TR_EVDATA] = "TR_EVDATA",
328 [TR_NOOP] = "TR_NOOP",
329 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
330 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
331 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
332 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
333 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
334 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
335 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
336 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
337 [CR_RESET_DEVICE] = "CR_RESET_DEVICE",
338 [CR_FORCE_EVENT] = "CR_FORCE_EVENT",
339 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
340 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
341 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
342 [CR_FORCE_HEADER] = "CR_FORCE_HEADER",
343 [CR_NOOP] = "CR_NOOP",
344 [ER_TRANSFER] = "ER_TRANSFER",
345 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
346 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
347 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
348 [ER_DOORBELL] = "ER_DOORBELL",
349 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
350 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
351 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
f10de44e
GH		 352 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
353 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
354};
355
873123fe
GH		 356static const char *TRBCCode_names[] = {
357 [CC_INVALID] = "CC_INVALID",
358 [CC_SUCCESS] = "CC_SUCCESS",
359 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR",
360 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED",
361 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR",
362 [CC_TRB_ERROR] = "CC_TRB_ERROR",
363 [CC_STALL_ERROR] = "CC_STALL_ERROR",
364 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR",
365 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR",
366 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR",
367 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR",
368 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR",
369 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR",
370 [CC_SHORT_PACKET] = "CC_SHORT_PACKET",
371 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN",
372 [CC_RING_OVERRUN] = "CC_RING_OVERRUN",
373 [CC_VF_ER_FULL] = "CC_VF_ER_FULL",
374 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR",
375 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN",
376 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR",
377 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR",
378 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR",
379 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR",
380 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR",
381 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED",
382 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED",
383 [CC_STOPPED] = "CC_STOPPED",
384 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID",
385 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR]
386 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
387 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN",
388 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR",
389 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR",
390 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR",
391 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR",
392 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR",
393};
394
1c82392a
GH		 395static const char *ep_state_names[] = {
396 [EP_DISABLED] = "disabled",
397 [EP_RUNNING] = "running",
398 [EP_HALTED] = "halted",
399 [EP_STOPPED] = "stopped",
400 [EP_ERROR] = "error",
401};
402
f10de44e
GH		 403static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
404{
405 if (index >= llen || list[index] == NULL) {
406 return "???";
407 }
408 return list[index];
409}
410
411static const char *trb_name(XHCITRB *trb)
412{
413 return lookup_name(TRB_TYPE(*trb), TRBType_names,
414 ARRAY_SIZE(TRBType_names));
415}
f10de44e 416
873123fe
GH		 417static const char *event_name(XHCIEvent *event)
418{
419 return lookup_name(event->ccode, TRBCCode_names,
420 ARRAY_SIZE(TRBCCode_names));
421}
422
1c82392a
GH		 423static const char *ep_state_name(uint32_t state)
424{
425 return lookup_name(state, ep_state_names,
426 ARRAY_SIZE(ep_state_names));
427}
428
f9955235
GH		 429static bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit)
430{
431 return xhci->flags & (1 << bit);
432}
433
4f72b8d2
GH		 434static void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit)
435{
436 xhci->flags |= (1 << bit);
437}
438
01546fa6
GH		 439static uint64_t xhci_mfindex_get(XHCIState *xhci)
440{
bc72ad67 441 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
01546fa6
GH		 442 return (now - xhci->mfindex_start) / 125000;
443}
444
445static void xhci_mfwrap_update(XHCIState *xhci)
446{
447 const uint32_t bits = USBCMD_RS | USBCMD_EWE;
448 uint32_t mfindex, left;
449 int64_t now;
450
451 if ((xhci->usbcmd & bits) == bits) {
bc72ad67 452 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
01546fa6
GH		 453 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff;
454 left = 0x4000 - mfindex;
bc72ad67 455 timer_mod(xhci->mfwrap_timer, now + left * 125000);
01546fa6 456 } else {
bc72ad67 457 timer_del(xhci->mfwrap_timer);
01546fa6
GH		 458 }
459}
460
461static void xhci_mfwrap_timer(void *opaque)
462{
463 XHCIState *xhci = opaque;
464 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS };
465
962d11e1 466 xhci_event(xhci, &wrap, 0);
01546fa6
GH		 467 xhci_mfwrap_update(xhci);
468}
62c6ae04 469
59a70ccd 470static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high)
62c6ae04 471{
59a70ccd
DG		 472 if (sizeof(dma_addr_t) == 4) {
473 return low;
474 } else {
475 return low | (((dma_addr_t)high << 16) << 16);
476 }
62c6ae04
HM		 477}
478
59a70ccd 479static inline dma_addr_t xhci_mask64(uint64_t addr)
62c6ae04 480{
59a70ccd
DG		 481 if (sizeof(dma_addr_t) == 4) {
482 return addr & 0xffffffff;
483 } else {
484 return addr;
485 }
62c6ae04
HM		 486}
487
616b5d53
DG		 488static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr,
489 uint32_t *buf, size_t len)
490{
491 int i;
492
493 assert((len % sizeof(uint32_t)) == 0);
494
9b7d3334 495 pci_dma_read(PCI_DEVICE(xhci), addr, buf, len);
616b5d53
DG		 496
497 for (i = 0; i < (len / sizeof(uint32_t)); i++) {
498 buf[i] = le32_to_cpu(buf[i]);
499 }
500}
501
502static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr,
503 uint32_t *buf, size_t len)
504{
505 int i;
182b391e
PX		 506 uint32_t tmp[5];
507 uint32_t n = len / sizeof(uint32_t);
616b5d53
DG		 508
509 assert((len % sizeof(uint32_t)) == 0);
182b391e 510 assert(n <= ARRAY_SIZE(tmp));
616b5d53 511
182b391e 512 for (i = 0; i < n; i++) {
616b5d53
DG		 513 tmp[i] = cpu_to_le32(buf[i]);
514 }
9b7d3334 515 pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len);
616b5d53
DG		 516}
517
0846e635
GH		 518static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
519{
520 int index;
521
522 if (!uport->dev) {
523 return NULL;
524 }
525 switch (uport->dev->speed) {
526 case USB_SPEED_LOW:
527 case USB_SPEED_FULL:
528 case USB_SPEED_HIGH:
7bafd888
GH		 529 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
530 index = uport->index + xhci->numports_3;
531 } else {
532 index = uport->index;
533 }
0846e635
GH		 534 break;
535 case USB_SPEED_SUPER:
7bafd888
GH		 536 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
537 index = uport->index;
538 } else {
539 index = uport->index + xhci->numports_2;
540 }
0846e635
GH		 541 break;
542 default:
543 return NULL;
544 }
545 return &xhci->ports[index];
546}
547
4c4abe7c 548static void xhci_intx_update(XHCIState *xhci)
62c6ae04 549{
9b7d3334 550 PCIDevice *pci_dev = PCI_DEVICE(xhci);
62c6ae04
HM		 551 int level = 0;
552
9b7d3334
AF		 553 if (msix_enabled(pci_dev) ||
554 msi_enabled(pci_dev)) {
4c4abe7c
GH		 555 return;
556 }
557
962d11e1
GH		 558 if (xhci->intr[0].iman & IMAN_IP &&
559 xhci->intr[0].iman & IMAN_IE &&
215bff17 560 xhci->usbcmd & USBCMD_INTE) {
62c6ae04
HM		 561 level = 1;
562 }
563
4c4abe7c 564 trace_usb_xhci_irq_intx(level);
9e64f8a3 565 pci_set_irq(pci_dev, level);
4c4abe7c
GH		 566}
567
962d11e1 568static void xhci_msix_update(XHCIState *xhci, int v)
4c47f800 569{
9b7d3334 570 PCIDevice *pci_dev = PCI_DEVICE(xhci);
4c47f800
GH		 571 bool enabled;
572
9b7d3334 573 if (!msix_enabled(pci_dev)) {
4c47f800
GH		 574 return;
575 }
576
962d11e1
GH		 577 enabled = xhci->intr[v].iman & IMAN_IE;
578 if (enabled == xhci->intr[v].msix_used) {
4c47f800
GH		 579 return;
580 }
581
582 if (enabled) {
962d11e1 583 trace_usb_xhci_irq_msix_use(v);
9b7d3334 584 msix_vector_use(pci_dev, v);
962d11e1 585 xhci->intr[v].msix_used = true;
4c47f800 586 } else {
962d11e1 587 trace_usb_xhci_irq_msix_unuse(v);
9b7d3334 588 msix_vector_unuse(pci_dev, v);
962d11e1 589 xhci->intr[v].msix_used = false;
4c47f800
GH		 590 }
591}
592
962d11e1 593static void xhci_intr_raise(XHCIState *xhci, int v)
4c4abe7c 594{
9b7d3334 595 PCIDevice *pci_dev = PCI_DEVICE(xhci);
7da76e12 596 bool pending = (xhci->intr[v].erdp_low & ERDP_EHB);
9b7d3334 597
962d11e1
GH		 598 xhci->intr[v].erdp_low |= ERDP_EHB;
599 xhci->intr[v].iman |= IMAN_IP;
2cae4119
GH		 600 xhci->usbsts |= USBSTS_EINT;
601
7da76e12
GH		 602 if (pending) {
603 return;
604 }
962d11e1 605 if (!(xhci->intr[v].iman & IMAN_IE)) {
4c4abe7c
GH		 606 return;
607 }
608
609 if (!(xhci->usbcmd & USBCMD_INTE)) {
610 return;
611 }
612
9b7d3334 613 if (msix_enabled(pci_dev)) {
962d11e1 614 trace_usb_xhci_irq_msix(v);
9b7d3334 615 msix_notify(pci_dev, v);
4c47f800
GH		 616 return;
617 }
618
9b7d3334 619 if (msi_enabled(pci_dev)) {
962d11e1 620 trace_usb_xhci_irq_msi(v);
9b7d3334 621 msi_notify(pci_dev, v);
4c4abe7c 622 return;
62c6ae04 623 }
4c4abe7c 624
962d11e1
GH		 625 if (v == 0) {
626 trace_usb_xhci_irq_intx(1);
9e64f8a3 627 pci_irq_assert(pci_dev);
962d11e1 628 }
62c6ae04
HM		 629}
630
631static inline int xhci_running(XHCIState *xhci)
632{
898248a3 633 return !(xhci->usbsts & USBSTS_HCH);
62c6ae04
HM		 634}
635
636static void xhci_die(XHCIState *xhci)
637{
638 xhci->usbsts |= USBSTS_HCE;
d6bb65fc 639 DPRINTF("xhci: asserted controller error\n");
62c6ae04
HM		 640}
641
962d11e1 642static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
62c6ae04 643{
9b7d3334 644 PCIDevice *pci_dev = PCI_DEVICE(xhci);
962d11e1 645 XHCIInterrupter *intr = &xhci->intr[v];
62c6ae04 646 XHCITRB ev_trb;
59a70ccd 647 dma_addr_t addr;
62c6ae04
HM		 648
649 ev_trb.parameter = cpu_to_le64(event->ptr);
650 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
651 ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
652 event->flags | (event->type << TRB_TYPE_SHIFT);
962d11e1 653 if (intr->er_pcs) {
62c6ae04
HM		 654 ev_trb.control |= TRB_C;
655 }
656 ev_trb.control = cpu_to_le32(ev_trb.control);
657
962d11e1 658 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb),
873123fe
GH		 659 event_name(event), ev_trb.parameter,
660 ev_trb.status, ev_trb.control);
62c6ae04 661
962d11e1 662 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx;
9b7d3334 663 pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE);
62c6ae04 664
962d11e1
GH		 665 intr->er_ep_idx++;
666 if (intr->er_ep_idx >= intr->er_size) {
667 intr->er_ep_idx = 0;
668 intr->er_pcs = !intr->er_pcs;
62c6ae04
HM		 669 }
670}
671
962d11e1 672static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v)
62c6ae04 673{
2d1de850 674 XHCIInterrupter *intr;
59a70ccd 675 dma_addr_t erdp;
62c6ae04
HM		 676 unsigned int dp_idx;
677
91062ae0
GH		 678 if (v >= xhci->numintrs) {
679 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs);
2d1de850
GH		 680 return;
681 }
682 intr = &xhci->intr[v];
683
962d11e1
GH		 684 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
685 if (erdp < intr->er_start ||
686 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
d6bb65fc
GH		 687 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
688 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
962d11e1 689 v, intr->er_start, intr->er_size);
62c6ae04
HM		 690 xhci_die(xhci);
691 return;
692 }
693
962d11e1
GH		 694 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
695 assert(dp_idx < intr->er_size);
62c6ae04 696
898248a3
GH		 697 if ((intr->er_ep_idx + 2) % intr->er_size == dp_idx) {
698 DPRINTF("xhci: ER %d full, send ring full error\n", v);
62c6ae04 699 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
898248a3
GH		 700 xhci_write_event(xhci, &full, v);
701 } else if ((intr->er_ep_idx + 1) % intr->er_size == dp_idx) {
702 DPRINTF("xhci: ER %d full, drop event\n", v);
62c6ae04 703 } else {
962d11e1 704 xhci_write_event(xhci, event, v);
62c6ae04
HM		 705 }
706
962d11e1 707 xhci_intr_raise(xhci, v);
62c6ae04
HM		 708}
709
710static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
59a70ccd 711 dma_addr_t base)
62c6ae04 712{
62c6ae04
HM		 713 ring->dequeue = base;
714 ring->ccs = 1;
715}
716
717static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
59a70ccd 718 dma_addr_t *addr)
62c6ae04 719{
9b7d3334 720 PCIDevice *pci_dev = PCI_DEVICE(xhci);
05f43d44 721 uint32_t link_cnt = 0;
9b7d3334 722
62c6ae04
HM		 723 while (1) {
724 TRBType type;
9b7d3334 725 pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE);
62c6ae04
HM		 726 trb->addr = ring->dequeue;
727 trb->ccs = ring->ccs;
728 le64_to_cpus(&trb->parameter);
729 le32_to_cpus(&trb->status);
730 le32_to_cpus(&trb->control);
731
0703a4a7
GH		 732 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb),
733 trb->parameter, trb->status, trb->control);
62c6ae04
HM		 734
735 if ((trb->control & TRB_C) != ring->ccs) {
736 return 0;
737 }
738
739 type = TRB_TYPE(*trb);
740
741 if (type != TR_LINK) {
742 if (addr) {
743 *addr = ring->dequeue;
744 }
745 ring->dequeue += TRB_SIZE;
746 return type;
747 } else {
05f43d44 748 if (++link_cnt > TRB_LINK_LIMIT) {
f89b60f6 749 trace_usb_xhci_enforced_limit("trb-link");
05f43d44
GH		 750 return 0;
751 }
62c6ae04
HM		 752 ring->dequeue = xhci_mask64(trb->parameter);
753 if (trb->control & TRB_LK_TC) {
754 ring->ccs = !ring->ccs;
755 }
756 }
757 }
758}
759
760static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
761{
9b7d3334 762 PCIDevice *pci_dev = PCI_DEVICE(xhci);
62c6ae04
HM		 763 XHCITRB trb;
764 int length = 0;
59a70ccd 765 dma_addr_t dequeue = ring->dequeue;
62c6ae04
HM		 766 bool ccs = ring->ccs;
767 /* hack to bundle together the two/three TDs that make a setup transfer */
768 bool control_td_set = 0;
05f43d44 769 uint32_t link_cnt = 0;
62c6ae04
HM		 770
771 while (1) {
772 TRBType type;
9b7d3334 773 pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE);
62c6ae04
HM		 774 le64_to_cpus(&trb.parameter);
775 le32_to_cpus(&trb.status);
776 le32_to_cpus(&trb.control);
777
62c6ae04
HM		 778 if ((trb.control & TRB_C) != ccs) {
779 return -length;
780 }
781
782 type = TRB_TYPE(trb);
783
784 if (type == TR_LINK) {
05f43d44
GH		 785 if (++link_cnt > TRB_LINK_LIMIT) {
786 return -length;
787 }
62c6ae04
HM		 788 dequeue = xhci_mask64(trb.parameter);
789 if (trb.control & TRB_LK_TC) {
790 ccs = !ccs;
791 }
792 continue;
793 }
794
795 length += 1;
796 dequeue += TRB_SIZE;
797
798 if (type == TR_SETUP) {
799 control_td_set = 1;
800 } else if (type == TR_STATUS) {
801 control_td_set = 0;
802 }
803
804 if (!control_td_set && !(trb.control & TRB_TR_CH)) {
805 return length;
806 }
807 }
808}
809
962d11e1 810static void xhci_er_reset(XHCIState *xhci, int v)
62c6ae04 811{
962d11e1 812 XHCIInterrupter *intr = &xhci->intr[v];
62c6ae04 813 XHCIEvRingSeg seg;
6100dda7 814 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high);
62c6ae04 815
6100dda7 816 if (intr->erstsz == 0 || erstba == 0) {
e099ad4b
GH		 817 /* disabled */
818 intr->er_start = 0;
819 intr->er_size = 0;
820 return;
821 }
62c6ae04 822 /* cache the (sole) event ring segment location */
962d11e1 823 if (intr->erstsz != 1) {
d6bb65fc 824 DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr->erstsz);
62c6ae04
HM		 825 xhci_die(xhci);
826 return;
827 }
9b7d3334 828 pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg));
62c6ae04
HM		 829 le32_to_cpus(&seg.addr_low);
830 le32_to_cpus(&seg.addr_high);
831 le32_to_cpus(&seg.size);
832 if (seg.size < 16 || seg.size > 4096) {
d6bb65fc 833 DPRINTF("xhci: invalid value for segment size: %d\n", seg.size);
62c6ae04
HM		 834 xhci_die(xhci);
835 return;
836 }
962d11e1
GH		 837 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
838 intr->er_size = seg.size;
62c6ae04 839
962d11e1
GH		 840 intr->er_ep_idx = 0;
841 intr->er_pcs = 1;
62c6ae04 842
962d11e1
GH		 843 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n",
844 v, intr->er_start, intr->er_size);
62c6ae04
HM		 845}
846
847static void xhci_run(XHCIState *xhci)
848{
fc0ddaca 849 trace_usb_xhci_run();
62c6ae04 850 xhci->usbsts &= ~USBSTS_HCH;
bc72ad67 851 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
62c6ae04
HM		 852}
853
854static void xhci_stop(XHCIState *xhci)
855{
fc0ddaca 856 trace_usb_xhci_stop();
62c6ae04
HM		 857 xhci->usbsts |= USBSTS_HCH;
858 xhci->crcr_low &= ~CRCR_CRR;
859}
860
024426ac
GH		 861static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count,
862 dma_addr_t base)
863{
864 XHCIStreamContext *stctx;
865 unsigned int i;
866
867 stctx = g_new0(XHCIStreamContext, count);
868 for (i = 0; i < count; i++) {
869 stctx[i].pctx = base + i * 16;
870 stctx[i].sct = -1;
871 }
872 return stctx;
873}
874
875static void xhci_reset_streams(XHCIEPContext *epctx)
876{
877 unsigned int i;
878
879 for (i = 0; i < epctx->nr_pstreams; i++) {
880 epctx->pstreams[i].sct = -1;
024426ac
GH		 881 }
882}
883
884static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base)
885{
886 assert(epctx->pstreams == NULL);
f90e160b 887 epctx->nr_pstreams = 2 << epctx->max_pstreams;
024426ac
GH		 888 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base);
889}
890
891static void xhci_free_streams(XHCIEPContext *epctx)
892{
024426ac
GH		 893 assert(epctx->pstreams != NULL);
894
024426ac
GH		 895 g_free(epctx->pstreams);
896 epctx->pstreams = NULL;
897 epctx->nr_pstreams = 0;
898}
899
72391da5
HG		 900static int xhci_epmask_to_eps_with_streams(XHCIState *xhci,
901 unsigned int slotid,
902 uint32_t epmask,
903 XHCIEPContext **epctxs,
904 USBEndpoint **eps)
905{
906 XHCISlot *slot;
907 XHCIEPContext *epctx;
908 USBEndpoint *ep;
909 int i, j;
910
911 assert(slotid >= 1 && slotid <= xhci->numslots);
912
913 slot = &xhci->slots[slotid - 1];
914
915 for (i = 2, j = 0; i <= 31; i++) {
3d80365b 916 if (!(epmask & (1u << i))) {
72391da5
HG		 917 continue;
918 }
919
920 epctx = slot->eps[i - 1];
070eeef9 921 ep = xhci_epid_to_usbep(epctx);
72391da5
HG		 922 if (!epctx || !epctx->nr_pstreams || !ep) {
923 continue;
924 }
925
926 if (epctxs) {
927 epctxs[j] = epctx;
928 }
929 eps[j++] = ep;
930 }
931 return j;
932}
933
934static void xhci_free_device_streams(XHCIState *xhci, unsigned int slotid,
935 uint32_t epmask)
936{
937 USBEndpoint *eps[30];
938 int nr_eps;
939
940 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, NULL, eps);
941 if (nr_eps) {
942 usb_device_free_streams(eps[0]->dev, eps, nr_eps);
943 }
944}
945
946static TRBCCode xhci_alloc_device_streams(XHCIState *xhci, unsigned int slotid,
947 uint32_t epmask)
948{
949 XHCIEPContext *epctxs[30];
950 USBEndpoint *eps[30];
951 int i, r, nr_eps, req_nr_streams, dev_max_streams;
952
953 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, epctxs,
954 eps);
955 if (nr_eps == 0) {
956 return CC_SUCCESS;
957 }
958
959 req_nr_streams = epctxs[0]->nr_pstreams;
960 dev_max_streams = eps[0]->max_streams;
961
962 for (i = 1; i < nr_eps; i++) {
963 /*
964 * HdG: I don't expect these to ever trigger, but if they do we need
965 * to come up with another solution, ie group identical endpoints
966 * together and make an usb_device_alloc_streams call per group.
967 */
968 if (epctxs[i]->nr_pstreams != req_nr_streams) {
969 FIXME("guest streams config not identical for all eps");
970 return CC_RESOURCE_ERROR;
971 }
972 if (eps[i]->max_streams != dev_max_streams) {
973 FIXME("device streams config not identical for all eps");
974 return CC_RESOURCE_ERROR;
975 }
976 }
977
978 /*
979 * max-streams in both the device descriptor and in the controller is a
980 * power of 2. But stream id 0 is reserved, so if a device can do up to 4
981 * streams the guest will ask for 5 rounded up to the next power of 2 which
982 * becomes 8. For emulated devices usb_device_alloc_streams is a nop.
983 *
984 * For redirected devices however this is an issue, as there we must ask
985 * the real xhci controller to alloc streams, and the host driver for the
986 * real xhci controller will likely disallow allocating more streams then
987 * the device can handle.
988 *
989 * So we limit the requested nr_streams to the maximum number the device
990 * can handle.
991 */
992 if (req_nr_streams > dev_max_streams) {
993 req_nr_streams = dev_max_streams;
994 }
995
996 r = usb_device_alloc_streams(eps[0]->dev, eps, nr_eps, req_nr_streams);
997 if (r != 0) {
d6bb65fc 998 DPRINTF("xhci: alloc streams failed\n");
72391da5
HG		 999 return CC_RESOURCE_ERROR;
1000 }
1001
1002 return CC_SUCCESS;
1003}
1004
024426ac
GH		 1005static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx,
1006 unsigned int streamid,
1007 uint32_t *cc_error)
1008{
1009 XHCIStreamContext *sctx;
1010 dma_addr_t base;
1011 uint32_t ctx[2], sct;
1012
1013 assert(streamid != 0);
1014 if (epctx->lsa) {
1015 if (streamid >= epctx->nr_pstreams) {
1016 *cc_error = CC_INVALID_STREAM_ID_ERROR;
1017 return NULL;
1018 }
1019 sctx = epctx->pstreams + streamid;
1020 } else {
1021 FIXME("secondary streams not implemented yet");
1022 }
1023
1024 if (sctx->sct == -1) {
1025 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx));
024426ac
GH		 1026 sct = (ctx[0] >> 1) & 0x07;
1027 if (epctx->lsa && sct != 1) {
1028 *cc_error = CC_INVALID_STREAM_TYPE_ERROR;
1029 return NULL;
1030 }
1031 sctx->sct = sct;
1032 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]);
1033 xhci_ring_init(epctx->xhci, &sctx->ring, base);
1034 }
1035 return sctx;
1036}
1037
62c6ae04 1038static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
024426ac 1039 XHCIStreamContext *sctx, uint32_t state)
62c6ae04 1040{
c90daa1c 1041 XHCIRing *ring = NULL;
62c6ae04 1042 uint32_t ctx[5];
024426ac 1043 uint32_t ctx2[2];
62c6ae04 1044
616b5d53 1045 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
62c6ae04
HM		 1046 ctx[0] &= ~EP_STATE_MASK;
1047 ctx[0] |= state;
024426ac
GH		 1048
1049 /* update ring dequeue ptr */
1050 if (epctx->nr_pstreams) {
1051 if (sctx != NULL) {
c90daa1c 1052 ring = &sctx->ring;
024426ac
GH		 1053 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1054 ctx2[0] &= 0xe;
1055 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs;
1056 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16;
1057 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1058 }
1059 } else {
c90daa1c
HG		 1060 ring = &epctx->ring;
1061 }
1062 if (ring) {
1063 ctx[2] = ring->dequeue | ring->ccs;
1064 ctx[3] = (ring->dequeue >> 16) >> 16;
1065
024426ac
GH		 1066 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n",
1067 epctx->pctx, state, ctx[3], ctx[2]);
1068 }
1069
616b5d53 1070 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1c82392a
GH		 1071 if (epctx->state != state) {
1072 trace_usb_xhci_ep_state(epctx->slotid, epctx->epid,
1073 ep_state_name(epctx->state),
1074 ep_state_name(state));
1075 }
62c6ae04
HM		 1076 epctx->state = state;
1077}
1078
3d139684
GH		 1079static void xhci_ep_kick_timer(void *opaque)
1080{
1081 XHCIEPContext *epctx = opaque;
3a533ee8 1082 xhci_kick_epctx(epctx, 0);
3d139684
GH		 1083}
1084
492b21f6
GH		 1085static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci,
1086 unsigned int slotid,
1087 unsigned int epid)
1088{
1089 XHCIEPContext *epctx;
492b21f6
GH		 1090
1091 epctx = g_new0(XHCIEPContext, 1);
1092 epctx->xhci = xhci;
1093 epctx->slotid = slotid;
1094 epctx->epid = epid;
1095
94b037f2 1096 QTAILQ_INIT(&epctx->transfers);
bc72ad67 1097 epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx);
492b21f6
GH		 1098
1099 return epctx;
1100}
1101
003e15a1
GH		 1102static void xhci_init_epctx(XHCIEPContext *epctx,
1103 dma_addr_t pctx, uint32_t *ctx)
62c6ae04 1104{
59a70ccd 1105 dma_addr_t dequeue;
62c6ae04 1106
62c6ae04 1107 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
62c6ae04
HM		 1108
1109 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
62c6ae04
HM		 1110 epctx->pctx = pctx;
1111 epctx->max_psize = ctx[1]>>16;
1112 epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
2aa6bfcb 1113 epctx->max_pstreams = (ctx[0] >> 10) & epctx->xhci->max_pstreams_mask;
024426ac 1114 epctx->lsa = (ctx[0] >> 15) & 1;
024426ac
GH		 1115 if (epctx->max_pstreams) {
1116 xhci_alloc_streams(epctx, dequeue);
1117 } else {
003e15a1 1118 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue);
024426ac
GH		 1119 epctx->ring.ccs = ctx[2] & 1;
1120 }
62c6ae04 1121
ca716278 1122 epctx->interval = 1 << ((ctx[0] >> 16) & 0xff);
003e15a1
GH		 1123}
1124
1125static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
1126 unsigned int epid, dma_addr_t pctx,
1127 uint32_t *ctx)
1128{
1129 XHCISlot *slot;
1130 XHCIEPContext *epctx;
1131
1132 trace_usb_xhci_ep_enable(slotid, epid);
1133 assert(slotid >= 1 && slotid <= xhci->numslots);
1134 assert(epid >= 1 && epid <= 31);
1135
1136 slot = &xhci->slots[slotid-1];
1137 if (slot->eps[epid-1]) {
1138 xhci_disable_ep(xhci, slotid, epid);
1139 }
1140
1141 epctx = xhci_alloc_epctx(xhci, slotid, epid);
1142 slot->eps[epid-1] = epctx;
1143 xhci_init_epctx(epctx, pctx, ctx);
1144
8c244210
GA		 1145 DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) "
1146 "size is %d\n", epid/2, epid%2, epctx->type, epctx->max_psize);
1147
3d139684 1148 epctx->mfindex_last = 0;
3d139684 1149
62c6ae04
HM		 1150 epctx->state = EP_RUNNING;
1151 ctx[0] &= ~EP_STATE_MASK;
1152 ctx[0] |= EP_RUNNING;
1153
1154 return CC_SUCCESS;
1155}
1156
94b037f2
GH		 1157static XHCITransfer *xhci_ep_alloc_xfer(XHCIEPContext *epctx,
1158 uint32_t length)
1159{
1160 uint32_t limit = epctx->nr_pstreams + 16;
1161 XHCITransfer *xfer;
1162
1163 if (epctx->xfer_count >= limit) {
1164 return NULL;
1165 }
1166
1167 xfer = g_new0(XHCITransfer, 1);
94b037f2 1168 xfer->epctx = epctx;
94b037f2
GH		 1169 xfer->trbs = g_new(XHCITRB, length);
1170 xfer->trb_count = length;
1171 usb_packet_init(&xfer->packet);
1172
1173 QTAILQ_INSERT_TAIL(&epctx->transfers, xfer, next);
1174 epctx->xfer_count++;
1175
1176 return xfer;
1177}
1178
1179static void xhci_ep_free_xfer(XHCITransfer *xfer)
1180{
1181 QTAILQ_REMOVE(&xfer->epctx->transfers, xfer, next);
1182 xfer->epctx->xfer_count--;
1183
1184 usb_packet_cleanup(&xfer->packet);
1185 g_free(xfer->trbs);
1186 g_free(xfer);
1187}
1188
582d6f4a 1189static int xhci_ep_nuke_one_xfer(XHCITransfer *t, TRBCCode report)
3151f209
HG		 1190{
1191 int killed = 0;
1192
582d6f4a
HG		 1193 if (report && (t->running_async || t->running_retry)) {
1194 t->status = report;
1195 xhci_xfer_report(t);
1196 }
1197
3151f209
HG		 1198 if (t->running_async) {
1199 usb_cancel_packet(&t->packet);
1200 t->running_async = 0;
3151f209
HG		 1201 killed = 1;
1202 }
1203 if (t->running_retry) {
5612564e
GH		 1204 if (t->epctx) {
1205 t->epctx->retry = NULL;
1206 timer_del(t->epctx->kick_timer);
3151f209
HG		 1207 }
1208 t->running_retry = 0;
582d6f4a 1209 killed = 1;
3151f209 1210 }
ef1e1e07 1211 g_free(t->trbs);
3151f209
HG		 1212
1213 t->trbs = NULL;
94b037f2 1214 t->trb_count = 0;
3151f209
HG		 1215
1216 return killed;
1217}
1218
62c6ae04 1219static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
582d6f4a 1220 unsigned int epid, TRBCCode report)
62c6ae04
HM		 1221{
1222 XHCISlot *slot;
1223 XHCIEPContext *epctx;
94b037f2
GH		 1224 XHCITransfer *xfer;
1225 int killed = 0;
f79738b0 1226 USBEndpoint *ep = NULL;
91062ae0 1227 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04
HM		 1228 assert(epid >= 1 && epid <= 31);
1229
1230 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
1231
1232 slot = &xhci->slots[slotid-1];
1233
1234 if (!slot->eps[epid-1]) {
1235 return 0;
1236 }
1237
1238 epctx = slot->eps[epid-1];
1239
94b037f2
GH		 1240 for (;;) {
1241 xfer = QTAILQ_FIRST(&epctx->transfers);
1242 if (xfer == NULL) {
1243 break;
1244 }
1245 killed += xhci_ep_nuke_one_xfer(xfer, report);
582d6f4a
HG		 1246 if (killed) {
1247 report = 0; /* Only report once */
1248 }
94b037f2 1249 xhci_ep_free_xfer(xfer);
62c6ae04 1250 }
518ad5f2 1251
070eeef9 1252 ep = xhci_epid_to_usbep(epctx);
f79738b0
HG		 1253 if (ep) {
1254 usb_device_ep_stopped(ep->dev, ep);
1255 }
62c6ae04
HM		 1256 return killed;
1257}
1258
1259static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
1260 unsigned int epid)
1261{
1262 XHCISlot *slot;
1263 XHCIEPContext *epctx;
1264
c1f6b493 1265 trace_usb_xhci_ep_disable(slotid, epid);
91062ae0 1266 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04
HM		 1267 assert(epid >= 1 && epid <= 31);
1268
62c6ae04
HM		 1269 slot = &xhci->slots[slotid-1];
1270
1271 if (!slot->eps[epid-1]) {
1272 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
1273 return CC_SUCCESS;
1274 }
1275
582d6f4a 1276 xhci_ep_nuke_xfers(xhci, slotid, epid, 0);
62c6ae04
HM		 1277
1278 epctx = slot->eps[epid-1];
1279
024426ac
GH		 1280 if (epctx->nr_pstreams) {
1281 xhci_free_streams(epctx);
1282 }
1283
491d68d9
RK		 1284 /* only touch guest RAM if we're not resetting the HC */
1285 if (xhci->dcbaap_low || xhci->dcbaap_high) {
1286 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED);
1287 }
62c6ae04 1288
bc72ad67 1289 timer_free(epctx->kick_timer);
62c6ae04
HM		 1290 g_free(epctx);
1291 slot->eps[epid-1] = NULL;
1292
1293 return CC_SUCCESS;
1294}
1295
1296static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
1297 unsigned int epid)
1298{
1299 XHCISlot *slot;
1300 XHCIEPContext *epctx;
1301
c1f6b493 1302 trace_usb_xhci_ep_stop(slotid, epid);
91062ae0 1303 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04
HM		 1304
1305 if (epid < 1 || epid > 31) {
d6bb65fc 1306 DPRINTF("xhci: bad ep %d\n", epid);
62c6ae04
HM		 1307 return CC_TRB_ERROR;
1308 }
1309
1310 slot = &xhci->slots[slotid-1];
1311
1312 if (!slot->eps[epid-1]) {
1313 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1314 return CC_EP_NOT_ENABLED_ERROR;
1315 }
1316
582d6f4a 1317 if (xhci_ep_nuke_xfers(xhci, slotid, epid, CC_STOPPED) > 0) {
d6bb65fc 1318 DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, "
62c6ae04
HM		 1319 "data might be lost\n");
1320 }
1321
1322 epctx = slot->eps[epid-1];
1323
024426ac
GH		 1324 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1325
1326 if (epctx->nr_pstreams) {
1327 xhci_reset_streams(epctx);
1328 }
62c6ae04
HM		 1329
1330 return CC_SUCCESS;
1331}
1332
1333static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
1334 unsigned int epid)
1335{
1336 XHCISlot *slot;
1337 XHCIEPContext *epctx;
62c6ae04 1338
c1f6b493 1339 trace_usb_xhci_ep_reset(slotid, epid);
91062ae0 1340 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04 1341
62c6ae04 1342 if (epid < 1 || epid > 31) {
d6bb65fc 1343 DPRINTF("xhci: bad ep %d\n", epid);
62c6ae04
HM		 1344 return CC_TRB_ERROR;
1345 }
1346
1347 slot = &xhci->slots[slotid-1];
1348
1349 if (!slot->eps[epid-1]) {
1350 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1351 return CC_EP_NOT_ENABLED_ERROR;
1352 }
1353
1354 epctx = slot->eps[epid-1];
1355
1356 if (epctx->state != EP_HALTED) {
d6bb65fc 1357 DPRINTF("xhci: reset EP while EP %d not halted (%d)\n",
62c6ae04
HM		 1358 epid, epctx->state);
1359 return CC_CONTEXT_STATE_ERROR;
1360 }
1361
582d6f4a 1362 if (xhci_ep_nuke_xfers(xhci, slotid, epid, 0) > 0) {
d6bb65fc 1363 DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, "
62c6ae04
HM		 1364 "data might be lost\n");
1365 }
1366
75cc1c1f 1367 if (!xhci->slots[slotid-1].uport ||
de9de157
HG		 1368 !xhci->slots[slotid-1].uport->dev ||
1369 !xhci->slots[slotid-1].uport->dev->attached) {
62c6ae04
HM		 1370 return CC_USB_TRANSACTION_ERROR;
1371 }
1372
024426ac
GH		 1373 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1374
1375 if (epctx->nr_pstreams) {
1376 xhci_reset_streams(epctx);
1377 }
62c6ae04
HM		 1378
1379 return CC_SUCCESS;
1380}
1381
1382static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
024426ac
GH		 1383 unsigned int epid, unsigned int streamid,
1384 uint64_t pdequeue)
62c6ae04
HM		 1385{
1386 XHCISlot *slot;
1387 XHCIEPContext *epctx;
024426ac 1388 XHCIStreamContext *sctx;
59a70ccd 1389 dma_addr_t dequeue;
62c6ae04 1390
91062ae0 1391 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04
HM		 1392
1393 if (epid < 1 || epid > 31) {
d6bb65fc 1394 DPRINTF("xhci: bad ep %d\n", epid);
62c6ae04
HM		 1395 return CC_TRB_ERROR;
1396 }
1397
024426ac 1398 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue);
62c6ae04
HM		 1399 dequeue = xhci_mask64(pdequeue);
1400
1401 slot = &xhci->slots[slotid-1];
1402
1403 if (!slot->eps[epid-1]) {
1404 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1405 return CC_EP_NOT_ENABLED_ERROR;
1406 }
1407
1408 epctx = slot->eps[epid-1];
1409
62c6ae04 1410 if (epctx->state != EP_STOPPED) {
d6bb65fc 1411 DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
62c6ae04
HM		 1412 return CC_CONTEXT_STATE_ERROR;
1413 }
1414
024426ac
GH		 1415 if (epctx->nr_pstreams) {
1416 uint32_t err;
1417 sctx = xhci_find_stream(epctx, streamid, &err);
1418 if (sctx == NULL) {
1419 return err;
1420 }
1421 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf);
1422 sctx->ring.ccs = dequeue & 1;
1423 } else {
1424 sctx = NULL;
1425 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1426 epctx->ring.ccs = dequeue & 1;
1427 }
62c6ae04 1428
024426ac 1429 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED);
62c6ae04
HM		 1430
1431 return CC_SUCCESS;
1432}
1433
a6fb2ddb 1434static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer)
62c6ae04 1435{
5612564e 1436 XHCIState *xhci = xfer->epctx->xhci;
d5a15814 1437 int i;
62c6ae04 1438
a6fb2ddb 1439 xfer->int_req = false;
9b7d3334 1440 pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count);
62c6ae04
HM		 1441 for (i = 0; i < xfer->trb_count; i++) {
1442 XHCITRB *trb = &xfer->trbs[i];
59a70ccd 1443 dma_addr_t addr;
62c6ae04
HM		 1444 unsigned int chunk = 0;
1445
a6fb2ddb
HG		 1446 if (trb->control & TRB_TR_IOC) {
1447 xfer->int_req = true;
1448 }
1449
62c6ae04
HM		 1450 switch (TRB_TYPE(*trb)) {
1451 case TR_DATA:
1452 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
d6bb65fc 1453 DPRINTF("xhci: data direction mismatch for TR_DATA\n");
d5a15814 1454 goto err;
62c6ae04
HM		 1455 }
1456 /* fallthrough */
1457 case TR_NORMAL:
1458 case TR_ISOCH:
1459 addr = xhci_mask64(trb->parameter);
d5a15814
GH		 1460 chunk = trb->status & 0x1ffff;
1461 if (trb->control & TRB_TR_IDT) {
1462 if (chunk > 8 || in_xfer) {
d6bb65fc 1463 DPRINTF("xhci: invalid immediate data TRB\n");
d5a15814
GH		 1464 goto err;
1465 }
1466 qemu_sglist_add(&xfer->sgl, trb->addr, chunk);
1467 } else {
1468 qemu_sglist_add(&xfer->sgl, addr, chunk);
1469 }
1470 break;
1471 }
1472 }
1473
d5a15814
GH		 1474 return 0;
1475
1476err:
1477 qemu_sglist_destroy(&xfer->sgl);
1478 xhci_die(xhci);
1479 return -1;
1480}
1481
1482static void xhci_xfer_unmap(XHCITransfer *xfer)
1483{
1484 usb_packet_unmap(&xfer->packet, &xfer->sgl);
1485 qemu_sglist_destroy(&xfer->sgl);
1486}
1487
1488static void xhci_xfer_report(XHCITransfer *xfer)
1489{
1490 uint32_t edtla = 0;
1491 unsigned int left;
1492 bool reported = 0;
1493 bool shortpkt = 0;
1494 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
5612564e 1495 XHCIState *xhci = xfer->epctx->xhci;
d5a15814
GH		 1496 int i;
1497
9b8251c5 1498 left = xfer->packet.actual_length;
d5a15814
GH		 1499
1500 for (i = 0; i < xfer->trb_count; i++) {
1501 XHCITRB *trb = &xfer->trbs[i];
1502 unsigned int chunk = 0;
1503
1504 switch (TRB_TYPE(*trb)) {
b66ad1f1
HPS		 1505 case TR_SETUP:
1506 chunk = trb->status & 0x1ffff;
1507 if (chunk > 8) {
1508 chunk = 8;
1509 }
1510 break;
d5a15814
GH		 1511 case TR_DATA:
1512 case TR_NORMAL:
1513 case TR_ISOCH:
62c6ae04
HM		 1514 chunk = trb->status & 0x1ffff;
1515 if (chunk > left) {
1516 chunk = left;
d5a15814
GH		 1517 if (xfer->status == CC_SUCCESS) {
1518 shortpkt = 1;
62c6ae04
HM		 1519 }
1520 }
1521 left -= chunk;
62c6ae04 1522 edtla += chunk;
62c6ae04
HM		 1523 break;
1524 case TR_STATUS:
1525 reported = 0;
1526 shortpkt = 0;
1527 break;
1528 }
1529
88dbed3f
GH		 1530 if (!reported && ((trb->control & TRB_TR_IOC) ||
1531 (shortpkt && (trb->control & TRB_TR_ISP)) ||
1532 (xfer->status != CC_SUCCESS && left == 0))) {
d6fcb293
GH		 1533 event.slotid = xfer->epctx->slotid;
1534 event.epid = xfer->epctx->epid;
62c6ae04
HM		 1535 event.length = (trb->status & 0x1ffff) - chunk;
1536 event.flags = 0;
1537 event.ptr = trb->addr;
1538 if (xfer->status == CC_SUCCESS) {
1539 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1540 } else {
1541 event.ccode = xfer->status;
1542 }
1543 if (TRB_TYPE(*trb) == TR_EVDATA) {
1544 event.ptr = trb->parameter;
1545 event.flags |= TRB_EV_ED;
1546 event.length = edtla & 0xffffff;
1547 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
1548 edtla = 0;
1549 }
2d1de850 1550 xhci_event(xhci, &event, TRB_INTR(*trb));
62c6ae04 1551 reported = 1;
d5a15814
GH		 1552 if (xfer->status != CC_SUCCESS) {
1553 return;
1554 }
62c6ae04 1555 }
df0f1692
GH		 1556
1557 switch (TRB_TYPE(*trb)) {
1558 case TR_SETUP:
1559 reported = 0;
1560 shortpkt = 0;
1561 break;
1562 }
1563
62c6ae04 1564 }
62c6ae04
HM		 1565}
1566
1567static void xhci_stall_ep(XHCITransfer *xfer)
1568{
5612564e
GH		 1569 XHCIEPContext *epctx = xfer->epctx;
1570 XHCIState *xhci = epctx->xhci;
024426ac
GH		 1571 uint32_t err;
1572 XHCIStreamContext *sctx;
62c6ae04 1573
024426ac
GH		 1574 if (epctx->nr_pstreams) {
1575 sctx = xhci_find_stream(epctx, xfer->streamid, &err);
1576 if (sctx == NULL) {
1577 return;
1578 }
1579 sctx->ring.dequeue = xfer->trbs[0].addr;
1580 sctx->ring.ccs = xfer->trbs[0].ccs;
1581 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED);
1582 } else {
1583 epctx->ring.dequeue = xfer->trbs[0].addr;
1584 epctx->ring.ccs = xfer->trbs[0].ccs;
1585 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED);
1586 }
62c6ae04
HM		 1587}
1588
5c08106f
GH		 1589static int xhci_setup_packet(XHCITransfer *xfer)
1590{
079d0b7f
GH		 1591 USBEndpoint *ep;
1592 int dir;
1593
1594 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT;
5c08106f
GH		 1595
1596 if (xfer->packet.ep) {
1597 ep = xfer->packet.ep;
5c08106f 1598 } else {
070eeef9 1599 ep = xhci_epid_to_usbep(xfer->epctx);
518ad5f2 1600 if (!ep) {
d6bb65fc 1601 DPRINTF("xhci: slot %d has no device\n",
ee56264a 1602 xfer->epctx->slotid);
5c08106f
GH		 1603 return -1;
1604 }
5c08106f
GH		 1605 }
1606
a6fb2ddb 1607 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */
024426ac 1608 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid,
8550a02d 1609 xfer->trbs[0].addr, false, xfer->int_req);
a6fb2ddb 1610 usb_packet_map(&xfer->packet, &xfer->sgl);
62c6ae04 1611 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
518ad5f2 1612 xfer->packet.pid, ep->dev->addr, ep->nr);
62c6ae04
HM		 1613 return 0;
1614}
1615
13e8ff7a 1616static int xhci_try_complete_packet(XHCITransfer *xfer)
62c6ae04 1617{
9a77a0f5 1618 if (xfer->packet.status == USB_RET_ASYNC) {
97df650b 1619 trace_usb_xhci_xfer_async(xfer);
7c605a23
GH		 1620 xfer->running_async = 1;
1621 xfer->running_retry = 0;
1622 xfer->complete = 0;
7c605a23 1623 return 0;
9a77a0f5 1624 } else if (xfer->packet.status == USB_RET_NAK) {
97df650b 1625 trace_usb_xhci_xfer_nak(xfer);
7c605a23
GH		 1626 xfer->running_async = 0;
1627 xfer->running_retry = 1;
62c6ae04 1628 xfer->complete = 0;
62c6ae04
HM		 1629 return 0;
1630 } else {
7c605a23
GH		 1631 xfer->running_async = 0;
1632 xfer->running_retry = 0;
62c6ae04 1633 xfer->complete = 1;
d5a15814 1634 xhci_xfer_unmap(xfer);
62c6ae04
HM		 1635 }
1636
9a77a0f5
HG		 1637 if (xfer->packet.status == USB_RET_SUCCESS) {
1638 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length);
d5a15814
GH		 1639 xfer->status = CC_SUCCESS;
1640 xhci_xfer_report(xfer);
62c6ae04
HM		 1641 return 0;
1642 }
1643
1644 /* error */
9a77a0f5
HG		 1645 trace_usb_xhci_xfer_error(xfer, xfer->packet.status);
1646 switch (xfer->packet.status) {
62c6ae04 1647 case USB_RET_NODEV:
ed60ff02 1648 case USB_RET_IOERROR:
62c6ae04 1649 xfer->status = CC_USB_TRANSACTION_ERROR;
d5a15814 1650 xhci_xfer_report(xfer);
62c6ae04
HM		 1651 xhci_stall_ep(xfer);
1652 break;
1653 case USB_RET_STALL:
1654 xfer->status = CC_STALL_ERROR;
d5a15814 1655 xhci_xfer_report(xfer);
62c6ae04
HM		 1656 xhci_stall_ep(xfer);
1657 break;
4e906d56
GH		 1658 case USB_RET_BABBLE:
1659 xfer->status = CC_BABBLE_DETECTED;
1660 xhci_xfer_report(xfer);
1661 xhci_stall_ep(xfer);
1662 break;
62c6ae04 1663 default:
d6bb65fc 1664 DPRINTF("%s: FIXME: status = %d\n", __func__,
9a77a0f5 1665 xfer->packet.status);
024426ac 1666 FIXME("unhandled USB_RET_*");
62c6ae04
HM		 1667 }
1668 return 0;
1669}
1670
1671static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1672{
1673 XHCITRB *trb_setup, *trb_status;
2850ca9e 1674 uint8_t bmRequestType;
62c6ae04 1675
62c6ae04
HM		 1676 trb_setup = &xfer->trbs[0];
1677 trb_status = &xfer->trbs[xfer->trb_count-1];
1678
d6fcb293
GH		 1679 trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid,
1680 xfer->epctx->epid, xfer->streamid);
97df650b 1681
62c6ae04
HM		 1682 /* at most one Event Data TRB allowed after STATUS */
1683 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) {
1684 trb_status--;
1685 }
1686
1687 /* do some sanity checks */
1688 if (TRB_TYPE(*trb_setup) != TR_SETUP) {
d6bb65fc 1689 DPRINTF("xhci: ep0 first TD not SETUP: %d\n",
62c6ae04
HM		 1690 TRB_TYPE(*trb_setup));
1691 return -1;
1692 }
1693 if (TRB_TYPE(*trb_status) != TR_STATUS) {
d6bb65fc 1694 DPRINTF("xhci: ep0 last TD not STATUS: %d\n",
62c6ae04
HM		 1695 TRB_TYPE(*trb_status));
1696 return -1;
1697 }
1698 if (!(trb_setup->control & TRB_TR_IDT)) {
d6bb65fc 1699 DPRINTF("xhci: Setup TRB doesn't have IDT set\n");
62c6ae04
HM		 1700 return -1;
1701 }
1702 if ((trb_setup->status & 0x1ffff) != 8) {
d6bb65fc 1703 DPRINTF("xhci: Setup TRB has bad length (%d)\n",
62c6ae04
HM		 1704 (trb_setup->status & 0x1ffff));
1705 return -1;
1706 }
1707
1708 bmRequestType = trb_setup->parameter;
62c6ae04 1709
62c6ae04
HM		 1710 xfer->in_xfer = bmRequestType & USB_DIR_IN;
1711 xfer->iso_xfer = false;
4d7a81c0 1712 xfer->timed_xfer = false;
62c6ae04 1713
5c08106f
GH		 1714 if (xhci_setup_packet(xfer) < 0) {
1715 return -1;
1716 }
2850ca9e 1717 xfer->packet.parameter = trb_setup->parameter;
2850ca9e 1718
9a77a0f5 1719 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
13e8ff7a 1720 xhci_try_complete_packet(xfer);
62c6ae04
HM		 1721 return 0;
1722}
1723
4d7a81c0
GH		 1724static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer,
1725 XHCIEPContext *epctx, uint64_t mfindex)
1726{
1727 uint64_t asap = ((mfindex + epctx->interval - 1) &
1728 ~(epctx->interval-1));
1729 uint64_t kick = epctx->mfindex_last + epctx->interval;
1730
1731 assert(epctx->interval != 0);
1732 xfer->mfindex_kick = MAX(asap, kick);
1733}
1734
3d139684
GH		 1735static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1736 XHCIEPContext *epctx, uint64_t mfindex)
1737{
1738 if (xfer->trbs[0].control & TRB_TR_SIA) {
1739 uint64_t asap = ((mfindex + epctx->interval - 1) &
1740 ~(epctx->interval-1));
1741 if (asap >= epctx->mfindex_last &&
1742 asap <= epctx->mfindex_last + epctx->interval * 4) {
1743 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval;
1744 } else {
1745 xfer->mfindex_kick = asap;
1746 }
1747 } else {
786ad214
GH		 1748 xfer->mfindex_kick = ((xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT)
1749 & TRB_TR_FRAMEID_MASK) << 3;
3d139684 1750 xfer->mfindex_kick |= mfindex & ~0x3fff;
cc03ff9d 1751 if (xfer->mfindex_kick + 0x100 < mfindex) {
3d139684
GH		 1752 xfer->mfindex_kick += 0x4000;
1753 }
1754 }
1755}
1756
4d7a81c0
GH		 1757static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1758 XHCIEPContext *epctx, uint64_t mfindex)
3d139684
GH		 1759{
1760 if (xfer->mfindex_kick > mfindex) {
bc72ad67 1761 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
3d139684
GH		 1762 (xfer->mfindex_kick - mfindex) * 125000);
1763 xfer->running_retry = 1;
1764 } else {
1765 epctx->mfindex_last = xfer->mfindex_kick;
bc72ad67 1766 timer_del(epctx->kick_timer);
3d139684
GH		 1767 xfer->running_retry = 0;
1768 }
1769}
1770
1771
62c6ae04
HM		 1772static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1773{
3d139684 1774 uint64_t mfindex;
62c6ae04 1775
ee56264a 1776 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", epctx->slotid, epctx->epid);
62c6ae04
HM		 1777
1778 xfer->in_xfer = epctx->type>>2;
62c6ae04 1779
62c6ae04
HM		 1780 switch(epctx->type) {
1781 case ET_INTR_OUT:
1782 case ET_INTR_IN:
4d7a81c0
GH		 1783 xfer->pkts = 0;
1784 xfer->iso_xfer = false;
1785 xfer->timed_xfer = true;
1786 mfindex = xhci_mfindex_get(xhci);
1787 xhci_calc_intr_kick(xhci, xfer, epctx, mfindex);
1788 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
1789 if (xfer->running_retry) {
1790 return -1;
1791 }
1792 break;
62c6ae04
HM		 1793 case ET_BULK_OUT:
1794 case ET_BULK_IN:
3d139684
GH		 1795 xfer->pkts = 0;
1796 xfer->iso_xfer = false;
4d7a81c0 1797 xfer->timed_xfer = false;
62c6ae04
HM		 1798 break;
1799 case ET_ISO_OUT:
1800 case ET_ISO_IN:
3d139684
GH		 1801 xfer->pkts = 1;
1802 xfer->iso_xfer = true;
4d7a81c0 1803 xfer->timed_xfer = true;
3d139684
GH		 1804 mfindex = xhci_mfindex_get(xhci);
1805 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex);
4d7a81c0 1806 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
3d139684
GH		 1807 if (xfer->running_retry) {
1808 return -1;
1809 }
62c6ae04
HM		 1810 break;
1811 default:
4f9cc734 1812 trace_usb_xhci_unimplemented("endpoint type", epctx->type);
62c6ae04
HM		 1813 return -1;
1814 }
1815
5c08106f
GH		 1816 if (xhci_setup_packet(xfer) < 0) {
1817 return -1;
1818 }
9a77a0f5 1819 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
13e8ff7a 1820 xhci_try_complete_packet(xfer);
62c6ae04
HM		 1821 return 0;
1822}
1823
1824static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1825{
d6fcb293
GH		 1826 trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid,
1827 xfer->epctx->epid, xfer->streamid);
331e9406 1828 return xhci_submit(xhci, xfer, epctx);
62c6ae04
HM		 1829}
1830
024426ac
GH		 1831static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
1832 unsigned int epid, unsigned int streamid)
62c6ae04
HM		 1833{
1834 XHCIEPContext *epctx;
62c6ae04 1835
91062ae0 1836 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04 1837 assert(epid >= 1 && epid <= 31);
62c6ae04
HM		 1838
1839 if (!xhci->slots[slotid-1].enabled) {
d6bb65fc 1840 DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid);
62c6ae04
HM		 1841 return;
1842 }
1843 epctx = xhci->slots[slotid-1].eps[epid-1];
1844 if (!epctx) {
d6bb65fc 1845 DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
62c6ae04
HM		 1846 epid, slotid);
1847 return;
1848 }
1849
96d87bdd
GH		 1850 if (epctx->kick_active) {
1851 return;
1852 }
3a533ee8
GH		 1853 xhci_kick_epctx(epctx, streamid);
1854}
1855
1856static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid)
1857{
1858 XHCIState *xhci = epctx->xhci;
243afe85 1859 XHCIStreamContext *stctx = NULL;
3a533ee8
GH		 1860 XHCITransfer *xfer;
1861 XHCIRing *ring;
1862 USBEndpoint *ep = NULL;
1863 uint64_t mfindex;
f89b60f6 1864 unsigned int count = 0;
3a533ee8
GH		 1865 int length;
1866 int i;
1867
1868 trace_usb_xhci_ep_kick(epctx->slotid, epctx->epid, streamid);
96d87bdd 1869 assert(!epctx->kick_active);
3a533ee8 1870
de9de157
HG		 1871 /* If the device has been detached, but the guest has not noticed this
1872 yet the 2 above checks will succeed, but we must NOT continue */
3a533ee8
GH		 1873 if (!xhci->slots[epctx->slotid - 1].uport ||
1874 !xhci->slots[epctx->slotid - 1].uport->dev ||
1875 !xhci->slots[epctx->slotid - 1].uport->dev->attached) {
de9de157
HG		 1876 return;
1877 }
1878
7c605a23 1879 if (epctx->retry) {
7c605a23 1880 XHCITransfer *xfer = epctx->retry;
7c605a23 1881
97df650b 1882 trace_usb_xhci_xfer_retry(xfer);
7c605a23 1883 assert(xfer->running_retry);
4d7a81c0
GH		 1884 if (xfer->timed_xfer) {
1885 /* time to kick the transfer? */
3d139684 1886 mfindex = xhci_mfindex_get(xhci);
4d7a81c0 1887 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
3d139684
GH		 1888 if (xfer->running_retry) {
1889 return;
1890 }
4d7a81c0
GH		 1891 xfer->timed_xfer = 0;
1892 xfer->running_retry = 1;
1893 }
1894 if (xfer->iso_xfer) {
1895 /* retry iso transfer */
3d139684
GH		 1896 if (xhci_setup_packet(xfer) < 0) {
1897 return;
1898 }
9a77a0f5
HG		 1899 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1900 assert(xfer->packet.status != USB_RET_NAK);
13e8ff7a 1901 xhci_try_complete_packet(xfer);
3d139684
GH		 1902 } else {
1903 /* retry nak'ed transfer */
1904 if (xhci_setup_packet(xfer) < 0) {
1905 return;
1906 }
9a77a0f5
HG		 1907 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1908 if (xfer->packet.status == USB_RET_NAK) {
3d139684
GH		 1909 return;
1910 }
13e8ff7a 1911 xhci_try_complete_packet(xfer);
7c605a23 1912 }
7c605a23 1913 assert(!xfer->running_retry);
f94d18d6 1914 if (xfer->complete) {
d54fddea
GH		 1915 /* update ring dequeue ptr */
1916 xhci_set_ep_state(xhci, epctx, stctx, epctx->state);
f94d18d6
GH		 1917 xhci_ep_free_xfer(epctx->retry);
1918 }
7c605a23
GH		 1919 epctx->retry = NULL;
1920 }
1921
62c6ae04
HM		 1922 if (epctx->state == EP_HALTED) {
1923 DPRINTF("xhci: ep halted, not running schedule\n");
1924 return;
1925 }
1926
024426ac
GH		 1927
1928 if (epctx->nr_pstreams) {
1929 uint32_t err;
1930 stctx = xhci_find_stream(epctx, streamid, &err);
1931 if (stctx == NULL) {
1932 return;
1933 }
1934 ring = &stctx->ring;
1935 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING);
1936 } else {
1937 ring = &epctx->ring;
1938 streamid = 0;
1939 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING);
1940 }
7d04c2b7 1941 assert(ring->dequeue != 0);
62c6ae04 1942
96d87bdd 1943 epctx->kick_active++;
62c6ae04 1944 while (1) {
024426ac 1945 length = xhci_ring_chain_length(xhci, ring);
94b037f2 1946 if (length <= 0) {
62c6ae04 1947 break;
62c6ae04 1948 }
94b037f2
GH		 1949 xfer = xhci_ep_alloc_xfer(epctx, length);
1950 if (xfer == NULL) {
1951 break;
62c6ae04 1952 }
62c6ae04
HM		 1953
1954 for (i = 0; i < length; i++) {
f81bb347
AK		 1955 TRBType type;
1956 type = xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL);
1957 assert(type);
62c6ae04 1958 }
024426ac 1959 xfer->streamid = streamid;
62c6ae04 1960
3a533ee8 1961 if (epctx->epid == 1) {
94b037f2 1962 xhci_fire_ctl_transfer(xhci, xfer);
62c6ae04 1963 } else {
94b037f2
GH		 1964 xhci_fire_transfer(xhci, xfer, epctx);
1965 }
1966 if (xfer->complete) {
d54fddea
GH		 1967 /* update ring dequeue ptr */
1968 xhci_set_ep_state(xhci, epctx, stctx, epctx->state);
94b037f2
GH		 1969 xhci_ep_free_xfer(xfer);
1970 xfer = NULL;
62c6ae04
HM		 1971 }
1972
3c4866e0 1973 if (epctx->state == EP_HALTED) {
3c4866e0
GH		 1974 break;
1975 }
94b037f2 1976 if (xfer != NULL && xfer->running_retry) {
7c605a23
GH		 1977 DPRINTF("xhci: xfer nacked, stopping schedule\n");
1978 epctx->retry = xfer;
1979 break;
1980 }
f89b60f6
GH		 1981 if (count++ > TRANSFER_LIMIT) {
1982 trace_usb_xhci_enforced_limit("transfers");
1983 break;
1984 }
62c6ae04 1985 }
96d87bdd 1986 epctx->kick_active--;
518ad5f2 1987
070eeef9 1988 ep = xhci_epid_to_usbep(epctx);
36dfe324
HG		 1989 if (ep) {
1990 usb_device_flush_ep_queue(ep->dev, ep);
1991 }
62c6ae04
HM		 1992}
1993
1994static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
1995{
348f1037 1996 trace_usb_xhci_slot_enable(slotid);
91062ae0 1997 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04 1998 xhci->slots[slotid-1].enabled = 1;
ccaf87a0 1999 xhci->slots[slotid-1].uport = NULL;
62c6ae04
HM		 2000 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
2001
2002 return CC_SUCCESS;
2003}
2004
2005static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
2006{
2007 int i;
2008
348f1037 2009 trace_usb_xhci_slot_disable(slotid);
91062ae0 2010 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04
HM		 2011
2012 for (i = 1; i <= 31; i++) {
2013 if (xhci->slots[slotid-1].eps[i-1]) {
2014 xhci_disable_ep(xhci, slotid, i);
2015 }
2016 }
2017
2018 xhci->slots[slotid-1].enabled = 0;
4034e693 2019 xhci->slots[slotid-1].addressed = 0;
5c67dd7b 2020 xhci->slots[slotid-1].uport = NULL;
62c6ae04
HM		 2021 return CC_SUCCESS;
2022}
2023
ccaf87a0
GH		 2024static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx)
2025{
2026 USBPort *uport;
2027 char path[32];
2028 int i, pos, port;
2029
2030 port = (slot_ctx[1]>>16) & 0xFF;
f2ad97ff
GH		 2031 if (port < 1 || port > xhci->numports) {
2032 return NULL;
2033 }
ccaf87a0
GH		 2034 port = xhci->ports[port-1].uport->index+1;
2035 pos = snprintf(path, sizeof(path), "%d", port);
2036 for (i = 0; i < 5; i++) {
2037 port = (slot_ctx[0] >> 4*i) & 0x0f;
2038 if (!port) {
2039 break;
2040 }
2041 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port);
2042 }
2043
2044 QTAILQ_FOREACH(uport, &xhci->bus.used, next) {
2045 if (strcmp(uport->path, path) == 0) {
2046 return uport;
2047 }
2048 }
2049 return NULL;
2050}
2051
62c6ae04
HM		 2052static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
2053 uint64_t pictx, bool bsr)
2054{
2055 XHCISlot *slot;
ccaf87a0 2056 USBPort *uport;
62c6ae04 2057 USBDevice *dev;
59a70ccd 2058 dma_addr_t ictx, octx, dcbaap;
62c6ae04
HM		 2059 uint64_t poctx;
2060 uint32_t ictl_ctx[2];
2061 uint32_t slot_ctx[4];
2062 uint32_t ep0_ctx[5];
62c6ae04
HM		 2063 int i;
2064 TRBCCode res;
2065
91062ae0 2066 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04
HM		 2067
2068 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
9b7d3334 2069 poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid);
62c6ae04 2070 ictx = xhci_mask64(pictx);
616b5d53 2071 octx = xhci_mask64(poctx);
62c6ae04 2072
59a70ccd
DG		 2073 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2074 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
62c6ae04 2075
616b5d53 2076 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
62c6ae04
HM		 2077
2078 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {
d6bb65fc 2079 DPRINTF("xhci: invalid input context control %08x %08x\n",
62c6ae04
HM		 2080 ictl_ctx[0], ictl_ctx[1]);
2081 return CC_TRB_ERROR;
2082 }
2083
616b5d53
DG		 2084 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx));
2085 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx));
62c6ae04
HM		 2086
2087 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2088 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2089
2090 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2091 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2092
ccaf87a0
GH		 2093 uport = xhci_lookup_uport(xhci, slot_ctx);
2094 if (uport == NULL) {
d6bb65fc 2095 DPRINTF("xhci: port not found\n");
62c6ae04 2096 return CC_TRB_ERROR;
ccaf87a0 2097 }
65d81ed4 2098 trace_usb_xhci_slot_address(slotid, uport->path);
ccaf87a0
GH		 2099
2100 dev = uport->dev;
de9de157 2101 if (!dev || !dev->attached) {
d6bb65fc 2102 DPRINTF("xhci: port %s not connected\n", uport->path);
62c6ae04
HM		 2103 return CC_USB_TRANSACTION_ERROR;
2104 }
2105
91062ae0 2106 for (i = 0; i < xhci->numslots; i++) {
0bc85da6
GH		 2107 if (i == slotid-1) {
2108 continue;
2109 }
ccaf87a0 2110 if (xhci->slots[i].uport == uport) {
d6bb65fc 2111 DPRINTF("xhci: port %s already assigned to slot %d\n",
ccaf87a0 2112 uport->path, i+1);
62c6ae04
HM		 2113 return CC_TRB_ERROR;
2114 }
2115 }
2116
2117 slot = &xhci->slots[slotid-1];
ccaf87a0 2118 slot->uport = uport;
62c6ae04
HM		 2119 slot->ctx = octx;
2120
a4055d85
ZS		 2121 /* Make sure device is in USB_STATE_DEFAULT state */
2122 usb_device_reset(dev);
62c6ae04
HM		 2123 if (bsr) {
2124 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
2125 } else {
a820b575 2126 USBPacket p;
a6718874
GH		 2127 uint8_t buf[1];
2128
af203be3 2129 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid;
a6718874
GH		 2130 memset(&p, 0, sizeof(p));
2131 usb_packet_addbuf(&p, buf, sizeof(buf));
a820b575 2132 usb_packet_setup(&p, USB_TOKEN_OUT,
8550a02d 2133 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0,
a820b575
GH		 2134 0, false, false);
2135 usb_device_handle_control(dev, &p,
62c6ae04 2136 DeviceOutRequest | USB_REQ_SET_ADDRESS,
af203be3 2137 slotid, 0, 0, NULL);
a820b575 2138 assert(p.status != USB_RET_ASYNC);
62c6ae04
HM		 2139 }
2140
2141 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
2142
2143 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2144 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2145 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2146 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2147
616b5d53
DG		 2148 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2149 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
62c6ae04 2150
4034e693 2151 xhci->slots[slotid-1].addressed = 1;
62c6ae04
HM		 2152 return res;
2153}
2154
2155
2156static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
2157 uint64_t pictx, bool dc)
2158{
59a70ccd 2159 dma_addr_t ictx, octx;
62c6ae04
HM		 2160 uint32_t ictl_ctx[2];
2161 uint32_t slot_ctx[4];
2162 uint32_t islot_ctx[4];
2163 uint32_t ep_ctx[5];
2164 int i;
2165 TRBCCode res;
2166
348f1037 2167 trace_usb_xhci_slot_configure(slotid);
91062ae0 2168 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04
HM		 2169
2170 ictx = xhci_mask64(pictx);
2171 octx = xhci->slots[slotid-1].ctx;
2172
59a70ccd
DG		 2173 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2174 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
62c6ae04
HM		 2175
2176 if (dc) {
2177 for (i = 2; i <= 31; i++) {
2178 if (xhci->slots[slotid-1].eps[i-1]) {
2179 xhci_disable_ep(xhci, slotid, i);
2180 }
2181 }
2182
616b5d53 2183 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 2184 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2185 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
2186 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2187 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
616b5d53 2188 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 2189
2190 return CC_SUCCESS;
2191 }
2192
616b5d53 2193 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
62c6ae04
HM		 2194
2195 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {
d6bb65fc 2196 DPRINTF("xhci: invalid input context control %08x %08x\n",
62c6ae04
HM		 2197 ictl_ctx[0], ictl_ctx[1]);
2198 return CC_TRB_ERROR;
2199 }
2200
616b5d53
DG		 2201 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2202 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 2203
2204 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) {
d6bb65fc 2205 DPRINTF("xhci: invalid slot state %08x\n", slot_ctx[3]);
62c6ae04
HM		 2206 return CC_CONTEXT_STATE_ERROR;
2207 }
2208
72391da5
HG		 2209 xhci_free_device_streams(xhci, slotid, ictl_ctx[0] | ictl_ctx[1]);
2210
62c6ae04
HM		 2211 for (i = 2; i <= 31; i++) {
2212 if (ictl_ctx[0] & (1<<i)) {
2213 xhci_disable_ep(xhci, slotid, i);
2214 }
2215 if (ictl_ctx[1] & (1<<i)) {
616b5d53 2216 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx));
62c6ae04
HM		 2217 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2218 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2219 ep_ctx[3], ep_ctx[4]);
2220 xhci_disable_ep(xhci, slotid, i);
2221 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
2222 if (res != CC_SUCCESS) {
2223 return res;
2224 }
2225 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2226 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2227 ep_ctx[3], ep_ctx[4]);
616b5d53 2228 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx));
62c6ae04
HM		 2229 }
2230 }
2231
72391da5
HG		 2232 res = xhci_alloc_device_streams(xhci, slotid, ictl_ctx[1]);
2233 if (res != CC_SUCCESS) {
2234 for (i = 2; i <= 31; i++) {
3d80365b 2235 if (ictl_ctx[1] & (1u << i)) {
72391da5
HG		 2236 xhci_disable_ep(xhci, slotid, i);
2237 }
2238 }
2239 return res;
2240 }
2241
62c6ae04
HM		 2242 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2243 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
2244 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
2245 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK <<
2246 SLOT_CONTEXT_ENTRIES_SHIFT);
2247 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2248 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2249
616b5d53 2250 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 2251
2252 return CC_SUCCESS;
2253}
2254
2255
2256static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
2257 uint64_t pictx)
2258{
59a70ccd 2259 dma_addr_t ictx, octx;
62c6ae04
HM		 2260 uint32_t ictl_ctx[2];
2261 uint32_t iep0_ctx[5];
2262 uint32_t ep0_ctx[5];
2263 uint32_t islot_ctx[4];
2264 uint32_t slot_ctx[4];
2265
348f1037 2266 trace_usb_xhci_slot_evaluate(slotid);
91062ae0 2267 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04
HM		 2268
2269 ictx = xhci_mask64(pictx);
2270 octx = xhci->slots[slotid-1].ctx;
2271
59a70ccd
DG		 2272 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2273 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
62c6ae04 2274
616b5d53 2275 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
62c6ae04
HM		 2276
2277 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {
d6bb65fc 2278 DPRINTF("xhci: invalid input context control %08x %08x\n",
62c6ae04
HM		 2279 ictl_ctx[0], ictl_ctx[1]);
2280 return CC_TRB_ERROR;
2281 }
2282
2283 if (ictl_ctx[1] & 0x1) {
616b5d53 2284 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
62c6ae04
HM		 2285
2286 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2287 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]);
2288
616b5d53 2289 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 2290
2291 slot_ctx[1] &= ~0xFFFF; /* max exit latency */
2292 slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
2293 slot_ctx[2] &= ~0xFF00000; /* interrupter target */
2294 slot_ctx[2] |= islot_ctx[2] & 0xFF000000;
2295
2296 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2297 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2298
616b5d53 2299 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 2300 }
2301
2302 if (ictl_ctx[1] & 0x2) {
616b5d53 2303 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx));
62c6ae04
HM		 2304
2305 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2306 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],
2307 iep0_ctx[3], iep0_ctx[4]);
2308
616b5d53 2309 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
62c6ae04
HM		 2310
2311 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
2312 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
2313
2314 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2315 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2316
616b5d53 2317 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
62c6ae04
HM		 2318 }
2319
2320 return CC_SUCCESS;
2321}
2322
2323static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
2324{
2325 uint32_t slot_ctx[4];
59a70ccd 2326 dma_addr_t octx;
62c6ae04
HM		 2327 int i;
2328
348f1037 2329 trace_usb_xhci_slot_reset(slotid);
91062ae0 2330 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04
HM		 2331
2332 octx = xhci->slots[slotid-1].ctx;
2333
59a70ccd 2334 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
62c6ae04
HM		 2335
2336 for (i = 2; i <= 31; i++) {
2337 if (xhci->slots[slotid-1].eps[i-1]) {
2338 xhci_disable_ep(xhci, slotid, i);
2339 }
2340 }
2341
616b5d53 2342 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 2343 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2344 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
2345 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2346 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
616b5d53 2347 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 2348
2349 return CC_SUCCESS;
2350}
2351
2352static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
2353{
2354 unsigned int slotid;
2355 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK;
91062ae0 2356 if (slotid < 1 || slotid > xhci->numslots) {
d6bb65fc 2357 DPRINTF("xhci: bad slot id %d\n", slotid);
62c6ae04
HM		 2358 event->ccode = CC_TRB_ERROR;
2359 return 0;
2360 } else if (!xhci->slots[slotid-1].enabled) {
d6bb65fc 2361 DPRINTF("xhci: slot id %d not enabled\n", slotid);
62c6ae04
HM		 2362 event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
2363 return 0;
2364 }
2365 return slotid;
2366}
2367
81251841
GH		 2368/* cleanup slot state on usb device detach */
2369static void xhci_detach_slot(XHCIState *xhci, USBPort *uport)
2370{
0cb41e2c 2371 int slot, ep;
81251841
GH		 2372
2373 for (slot = 0; slot < xhci->numslots; slot++) {
2374 if (xhci->slots[slot].uport == uport) {
2375 break;
2376 }
2377 }
2378 if (slot == xhci->numslots) {
2379 return;
2380 }
2381
0cb41e2c
GH		 2382 for (ep = 0; ep < 31; ep++) {
2383 if (xhci->slots[slot].eps[ep]) {
582d6f4a 2384 xhci_ep_nuke_xfers(xhci, slot + 1, ep + 1, 0);
0cb41e2c
GH		 2385 }
2386 }
81251841
GH		 2387 xhci->slots[slot].uport = NULL;
2388}
2389
62c6ae04
HM		 2390static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
2391{
59a70ccd 2392 dma_addr_t ctx;
0846e635 2393 uint8_t bw_ctx[xhci->numports+1];
62c6ae04
HM		 2394
2395 DPRINTF("xhci_get_port_bandwidth()\n");
2396
2397 ctx = xhci_mask64(pctx);
2398
59a70ccd 2399 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx);
62c6ae04
HM		 2400
2401 /* TODO: actually implement real values here */
2402 bw_ctx[0] = 0;
0846e635 2403 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
9b7d3334 2404 pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx));
62c6ae04
HM		 2405
2406 return CC_SUCCESS;
2407}
2408
2409static uint32_t rotl(uint32_t v, unsigned count)
2410{
2411 count &= 31;
2412 return (v << count) | (v >> (32 - count));
2413}
2414
2415
2416static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
2417{
2418 uint32_t val;
2419 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
2420 val += rotl(lo + 0x49434878, hi & 0x1F);
2421 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
2422 return ~val;
2423}
2424
62c6ae04
HM		 2425static void xhci_process_commands(XHCIState *xhci)
2426{
2427 XHCITRB trb;
2428 TRBType type;
2429 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
59a70ccd 2430 dma_addr_t addr;
f89b60f6 2431 unsigned int i, slotid = 0, count = 0;
62c6ae04
HM		 2432
2433 DPRINTF("xhci_process_commands()\n");
2434 if (!xhci_running(xhci)) {
2435 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2436 return;
2437 }
2438
2439 xhci->crcr_low |= CRCR_CRR;
2440
2441 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
2442 event.ptr = addr;
2443 switch (type) {
2444 case CR_ENABLE_SLOT:
91062ae0 2445 for (i = 0; i < xhci->numslots; i++) {
62c6ae04
HM		 2446 if (!xhci->slots[i].enabled) {
2447 break;
2448 }
2449 }
91062ae0 2450 if (i >= xhci->numslots) {
d6bb65fc 2451 DPRINTF("xhci: no device slots available\n");
62c6ae04
HM		 2452 event.ccode = CC_NO_SLOTS_ERROR;
2453 } else {
2454 slotid = i+1;
2455 event.ccode = xhci_enable_slot(xhci, slotid);
2456 }
2457 break;
2458 case CR_DISABLE_SLOT:
2459 slotid = xhci_get_slot(xhci, &event, &trb);
2460 if (slotid) {
2461 event.ccode = xhci_disable_slot(xhci, slotid);
2462 }
2463 break;
2464 case CR_ADDRESS_DEVICE:
2465 slotid = xhci_get_slot(xhci, &event, &trb);
2466 if (slotid) {
2467 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
2468 trb.control & TRB_CR_BSR);
2469 }
2470 break;
2471 case CR_CONFIGURE_ENDPOINT:
2472 slotid = xhci_get_slot(xhci, &event, &trb);
2473 if (slotid) {
2474 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
2475 trb.control & TRB_CR_DC);
2476 }
2477 break;
2478 case CR_EVALUATE_CONTEXT:
2479 slotid = xhci_get_slot(xhci, &event, &trb);
2480 if (slotid) {
2481 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
2482 }
2483 break;
2484 case CR_STOP_ENDPOINT:
2485 slotid = xhci_get_slot(xhci, &event, &trb);
2486 if (slotid) {
2487 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2488 & TRB_CR_EPID_MASK;
2489 event.ccode = xhci_stop_ep(xhci, slotid, epid);
2490 }
2491 break;
2492 case CR_RESET_ENDPOINT:
2493 slotid = xhci_get_slot(xhci, &event, &trb);
2494 if (slotid) {
2495 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2496 & TRB_CR_EPID_MASK;
2497 event.ccode = xhci_reset_ep(xhci, slotid, epid);
2498 }
2499 break;
2500 case CR_SET_TR_DEQUEUE:
2501 slotid = xhci_get_slot(xhci, &event, &trb);
2502 if (slotid) {
2503 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2504 & TRB_CR_EPID_MASK;
024426ac
GH		 2505 unsigned int streamid = (trb.status >> 16) & 0xffff;
2506 event.ccode = xhci_set_ep_dequeue(xhci, slotid,
2507 epid, streamid,
62c6ae04
HM		 2508 trb.parameter);
2509 }
2510 break;
2511 case CR_RESET_DEVICE:
2512 slotid = xhci_get_slot(xhci, &event, &trb);
2513 if (slotid) {
2514 event.ccode = xhci_reset_slot(xhci, slotid);
2515 }
2516 break;
2517 case CR_GET_PORT_BANDWIDTH:
2518 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2519 break;
62c6ae04 2520 case CR_VENDOR_NEC_FIRMWARE_REVISION:
2992d6b4
GH		 2521 if (xhci->nec_quirks) {
2522 event.type = 48; /* NEC reply */
2523 event.length = 0x3025;
2524 } else {
2525 event.ccode = CC_TRB_ERROR;
2526 }
62c6ae04
HM		 2527 break;
2528 case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2992d6b4
GH		 2529 if (xhci->nec_quirks) {
2530 uint32_t chi = trb.parameter >> 32;
2531 uint32_t clo = trb.parameter;
2532 uint32_t val = xhci_nec_challenge(chi, clo);
2533 event.length = val & 0xFFFF;
2534 event.epid = val >> 16;
2535 slotid = val >> 24;
2536 event.type = 48; /* NEC reply */
2537 } else {
2538 event.ccode = CC_TRB_ERROR;
2539 }
2540 break;
62c6ae04 2541 default:
0ab966cf 2542 trace_usb_xhci_unimplemented("command", type);
62c6ae04
HM		 2543 event.ccode = CC_TRB_ERROR;
2544 break;
2545 }
2546 event.slotid = slotid;
2d1de850 2547 xhci_event(xhci, &event, 0);
f89b60f6
GH		 2548
2549 if (count++ > COMMAND_LIMIT) {
2550 trace_usb_xhci_enforced_limit("commands");
2551 return;
2552 }
62c6ae04
HM		 2553 }
2554}
2555
6a32f80f
GH		 2556static bool xhci_port_have_device(XHCIPort *port)
2557{
2558 if (!port->uport->dev || !port->uport->dev->attached) {
2559 return false; /* no device present */
2560 }
2561 if (!((1 << port->uport->dev->speed) & port->speedmask)) {
2562 return false; /* speed mismatch */
2563 }
2564 return true;
2565}
2566
f705a362
GH		 2567static void xhci_port_notify(XHCIPort *port, uint32_t bits)
2568{
2569 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,
2570 port->portnr << 24 };
2571
2572 if ((port->portsc & bits) == bits) {
2573 return;
2574 }
bdfce20d 2575 trace_usb_xhci_port_notify(port->portnr, bits);
f705a362
GH		 2576 port->portsc |= bits;
2577 if (!xhci_running(port->xhci)) {
2578 return;
2579 }
2580 xhci_event(port->xhci, &ev, 0);
2581}
2582
f3214027 2583static void xhci_port_update(XHCIPort *port, int is_detach)
62c6ae04 2584{
b62b0828
GH		 2585 uint32_t pls = PLS_RX_DETECT;
2586
62c6ae04 2587 port->portsc = PORTSC_PP;
6a32f80f 2588 if (!is_detach && xhci_port_have_device(port)) {
62c6ae04 2589 port->portsc |= PORTSC_CCS;
0846e635 2590 switch (port->uport->dev->speed) {
62c6ae04
HM		 2591 case USB_SPEED_LOW:
2592 port->portsc |= PORTSC_SPEED_LOW;
b62b0828 2593 pls = PLS_POLLING;
62c6ae04
HM		 2594 break;
2595 case USB_SPEED_FULL:
2596 port->portsc |= PORTSC_SPEED_FULL;
b62b0828 2597 pls = PLS_POLLING;
62c6ae04
HM		 2598 break;
2599 case USB_SPEED_HIGH:
2600 port->portsc |= PORTSC_SPEED_HIGH;
b62b0828 2601 pls = PLS_POLLING;
62c6ae04 2602 break;
0846e635
GH		 2603 case USB_SPEED_SUPER:
2604 port->portsc |= PORTSC_SPEED_SUPER;
b62b0828
GH		 2605 port->portsc |= PORTSC_PED;
2606 pls = PLS_U0;
0846e635 2607 break;
62c6ae04
HM		 2608 }
2609 }
b62b0828 2610 set_field(&port->portsc, pls, PORTSC_PLS);
4f47f0f8 2611 trace_usb_xhci_port_link(port->portnr, pls);
f705a362 2612 xhci_port_notify(port, PORTSC_CSC);
62c6ae04
HM		 2613}
2614
dad5b9ea 2615static void xhci_port_reset(XHCIPort *port, bool warm_reset)
40030130 2616{
7bd3055f 2617 trace_usb_xhci_port_reset(port->portnr, warm_reset);
4f47f0f8 2618
b62b0828
GH		 2619 if (!xhci_port_have_device(port)) {
2620 return;
2621 }
2622
40030130 2623 usb_device_reset(port->uport->dev);
b62b0828
GH		 2624
2625 switch (port->uport->dev->speed) {
dad5b9ea
GH		 2626 case USB_SPEED_SUPER:
2627 if (warm_reset) {
2628 port->portsc |= PORTSC_WRC;
2629 }
2630 /* fall through */
b62b0828
GH		 2631 case USB_SPEED_LOW:
2632 case USB_SPEED_FULL:
2633 case USB_SPEED_HIGH:
2634 set_field(&port->portsc, PLS_U0, PORTSC_PLS);
4f47f0f8 2635 trace_usb_xhci_port_link(port->portnr, PLS_U0);
b62b0828
GH		 2636 port->portsc |= PORTSC_PED;
2637 break;
2638 }
2639
2640 port->portsc &= ~PORTSC_PR;
2641 xhci_port_notify(port, PORTSC_PRC);
40030130
GH		 2642}
2643
64619739 2644static void xhci_reset(DeviceState *dev)
62c6ae04 2645{
37034575 2646 XHCIState *xhci = XHCI(dev);
62c6ae04
HM		 2647 int i;
2648
2d754a10 2649 trace_usb_xhci_reset();
62c6ae04 2650 if (!(xhci->usbsts & USBSTS_HCH)) {
d6bb65fc 2651 DPRINTF("xhci: reset while running!\n");
62c6ae04
HM		 2652 }
2653
2654 xhci->usbcmd = 0;
2655 xhci->usbsts = USBSTS_HCH;
2656 xhci->dnctrl = 0;
2657 xhci->crcr_low = 0;
2658 xhci->crcr_high = 0;
2659 xhci->dcbaap_low = 0;
2660 xhci->dcbaap_high = 0;
2661 xhci->config = 0;
62c6ae04 2662
91062ae0 2663 for (i = 0; i < xhci->numslots; i++) {
62c6ae04
HM		 2664 xhci_disable_slot(xhci, i+1);
2665 }
2666
0846e635 2667 for (i = 0; i < xhci->numports; i++) {
f3214027 2668 xhci_port_update(xhci->ports + i, 0);
62c6ae04
HM		 2669 }
2670
91062ae0 2671 for (i = 0; i < xhci->numintrs; i++) {
962d11e1
GH		 2672 xhci->intr[i].iman = 0;
2673 xhci->intr[i].imod = 0;
2674 xhci->intr[i].erstsz = 0;
2675 xhci->intr[i].erstba_low = 0;
2676 xhci->intr[i].erstba_high = 0;
2677 xhci->intr[i].erdp_low = 0;
2678 xhci->intr[i].erdp_high = 0;
2679 xhci->intr[i].msix_used = 0;
62c6ae04 2680
962d11e1
GH		 2681 xhci->intr[i].er_ep_idx = 0;
2682 xhci->intr[i].er_pcs = 1;
962d11e1
GH		 2683 xhci->intr[i].ev_buffer_put = 0;
2684 xhci->intr[i].ev_buffer_get = 0;
2685 }
01546fa6 2686
bc72ad67 2687 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
01546fa6 2688 xhci_mfwrap_update(xhci);
62c6ae04
HM		 2689}
2690
a8170e5e 2691static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size)
62c6ae04 2692{
1b067564 2693 XHCIState *xhci = ptr;
2d754a10 2694 uint32_t ret;
62c6ae04
HM		 2695
2696 switch (reg) {
2697 case 0x00: /* HCIVERSION, CAPLENGTH */
2d754a10
GH		 2698 ret = 0x01000000 | LEN_CAP;
2699 break;
62c6ae04 2700 case 0x04: /* HCSPARAMS 1 */
0846e635 2701 ret = ((xhci->numports_2+xhci->numports_3)<<24)
91062ae0 2702 | (xhci->numintrs<<8) | xhci->numslots;
2d754a10 2703 break;
62c6ae04 2704 case 0x08: /* HCSPARAMS 2 */
2d754a10
GH		 2705 ret = 0x0000000f;
2706 break;
62c6ae04 2707 case 0x0c: /* HCSPARAMS 3 */
2d754a10
GH		 2708 ret = 0x00000000;
2709 break;
62c6ae04 2710 case 0x10: /* HCCPARAMS */
2d754a10 2711 if (sizeof(dma_addr_t) == 4) {
2aa6bfcb 2712 ret = 0x00080000 | (xhci->max_pstreams_mask << 12);
2d754a10 2713 } else {
2aa6bfcb 2714 ret = 0x00080001 | (xhci->max_pstreams_mask << 12);
2d754a10
GH		 2715 }
2716 break;
62c6ae04 2717 case 0x14: /* DBOFF */
2d754a10
GH		 2718 ret = OFF_DOORBELL;
2719 break;
62c6ae04 2720 case 0x18: /* RTSOFF */
2d754a10
GH		 2721 ret = OFF_RUNTIME;
2722 break;
62c6ae04
HM		 2723
2724 /* extended capabilities */
2725 case 0x20: /* Supported Protocol:00 */
2d754a10
GH		 2726 ret = 0x02000402; /* USB 2.0 */
2727 break;
62c6ae04 2728 case 0x24: /* Supported Protocol:04 */
0ebfb144 2729 ret = 0x20425355; /* "USB " */
2d754a10 2730 break;
62c6ae04 2731 case 0x28: /* Supported Protocol:08 */
7bafd888
GH		 2732 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
2733 ret = (xhci->numports_2<<8) | (xhci->numports_3+1);
2734 } else {
2735 ret = (xhci->numports_2<<8) | 1;
2736 }
2d754a10 2737 break;
62c6ae04 2738 case 0x2c: /* Supported Protocol:0c */
2d754a10
GH		 2739 ret = 0x00000000; /* reserved */
2740 break;
62c6ae04 2741 case 0x30: /* Supported Protocol:00 */
2d754a10
GH		 2742 ret = 0x03000002; /* USB 3.0 */
2743 break;
62c6ae04 2744 case 0x34: /* Supported Protocol:04 */
0ebfb144 2745 ret = 0x20425355; /* "USB " */
2d754a10 2746 break;
62c6ae04 2747 case 0x38: /* Supported Protocol:08 */
7bafd888
GH		 2748 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
2749 ret = (xhci->numports_3<<8) | 1;
2750 } else {
2751 ret = (xhci->numports_3<<8) | (xhci->numports_2+1);
2752 }
2d754a10 2753 break;
62c6ae04 2754 case 0x3c: /* Supported Protocol:0c */
2d754a10
GH		 2755 ret = 0x00000000; /* reserved */
2756 break;
62c6ae04 2757 default:
0ab966cf 2758 trace_usb_xhci_unimplemented("cap read", reg);
2d754a10 2759 ret = 0;
62c6ae04 2760 }
2d754a10
GH		 2761
2762 trace_usb_xhci_cap_read(reg, ret);
2763 return ret;
62c6ae04
HM		 2764}
2765
a8170e5e 2766static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size)
62c6ae04 2767{
1d8a4e69 2768 XHCIPort *port = ptr;
2d754a10
GH		 2769 uint32_t ret;
2770
1d8a4e69 2771 switch (reg) {
62c6ae04 2772 case 0x00: /* PORTSC */
1d8a4e69 2773 ret = port->portsc;
2d754a10 2774 break;
62c6ae04
HM		 2775 case 0x04: /* PORTPMSC */
2776 case 0x08: /* PORTLI */
2d754a10
GH		 2777 ret = 0;
2778 break;
62c6ae04
HM		 2779 case 0x0c: /* reserved */
2780 default:
0ab966cf 2781 trace_usb_xhci_unimplemented("port read", reg);
2d754a10 2782 ret = 0;
62c6ae04 2783 }
2d754a10 2784
1d8a4e69 2785 trace_usb_xhci_port_read(port->portnr, reg, ret);
2d754a10 2786 return ret;
62c6ae04
HM		 2787}
2788
a8170e5e 2789static void xhci_port_write(void *ptr, hwaddr reg,
1d8a4e69 2790 uint64_t val, unsigned size)
62c6ae04 2791{
1d8a4e69 2792 XHCIPort *port = ptr;
bdfce20d 2793 uint32_t portsc, notify;
62c6ae04 2794
1d8a4e69 2795 trace_usb_xhci_port_write(port->portnr, reg, val);
2d754a10 2796
1d8a4e69 2797 switch (reg) {
62c6ae04 2798 case 0x00: /* PORTSC */
bdfce20d 2799 /* write-1-to-start bits */
dad5b9ea
GH		 2800 if (val & PORTSC_WPR) {
2801 xhci_port_reset(port, true);
2802 break;
2803 }
bdfce20d 2804 if (val & PORTSC_PR) {
dad5b9ea 2805 xhci_port_reset(port, false);
bdfce20d
GH		 2806 break;
2807 }
2808
1d8a4e69 2809 portsc = port->portsc;
bdfce20d 2810 notify = 0;
62c6ae04
HM		 2811 /* write-1-to-clear bits*/
2812 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
2813 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
2814 if (val & PORTSC_LWS) {
2815 /* overwrite PLS only when LWS=1 */
bdfce20d
GH		 2816 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS);
2817 uint32_t new_pls = get_field(val, PORTSC_PLS);
2818 switch (new_pls) {
2819 case PLS_U0:
2820 if (old_pls != PLS_U0) {
2821 set_field(&portsc, new_pls, PORTSC_PLS);
2822 trace_usb_xhci_port_link(port->portnr, new_pls);
2823 notify = PORTSC_PLC;
2824 }
2825 break;
2826 case PLS_U3:
2827 if (old_pls < PLS_U3) {
2828 set_field(&portsc, new_pls, PORTSC_PLS);
2829 trace_usb_xhci_port_link(port->portnr, new_pls);
2830 }
2831 break;
2832 case PLS_RESUME:
2833 /* windows does this for some reason, don't spam stderr */
2834 break;
2835 default:
d6bb65fc 2836 DPRINTF("%s: ignore pls write (old %d, new %d)\n",
bdfce20d
GH		 2837 __func__, old_pls, new_pls);
2838 break;
2839 }
62c6ae04
HM		 2840 }
2841 /* read/write bits */
2842 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
2843 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
40030130 2844 port->portsc = portsc;
bdfce20d
GH		 2845 if (notify) {
2846 xhci_port_notify(port, notify);
62c6ae04 2847 }
62c6ae04
HM		 2848 break;
2849 case 0x04: /* PORTPMSC */
2850 case 0x08: /* PORTLI */
2851 default:
0ab966cf 2852 trace_usb_xhci_unimplemented("port write", reg);
62c6ae04
HM		 2853 }
2854}
2855
a8170e5e 2856static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
62c6ae04 2857{
1b067564 2858 XHCIState *xhci = ptr;
2d754a10 2859 uint32_t ret;
62c6ae04 2860
62c6ae04
HM		 2861 switch (reg) {
2862 case 0x00: /* USBCMD */
2d754a10
GH		 2863 ret = xhci->usbcmd;
2864 break;
62c6ae04 2865 case 0x04: /* USBSTS */
2d754a10
GH		 2866 ret = xhci->usbsts;
2867 break;
62c6ae04 2868 case 0x08: /* PAGESIZE */
2d754a10
GH		 2869 ret = 1; /* 4KiB */
2870 break;
62c6ae04 2871 case 0x14: /* DNCTRL */
2d754a10
GH		 2872 ret = xhci->dnctrl;
2873 break;
62c6ae04 2874 case 0x18: /* CRCR low */
2d754a10
GH		 2875 ret = xhci->crcr_low & ~0xe;
2876 break;
62c6ae04 2877 case 0x1c: /* CRCR high */
2d754a10
GH		 2878 ret = xhci->crcr_high;
2879 break;
62c6ae04 2880 case 0x30: /* DCBAAP low */
2d754a10
GH		 2881 ret = xhci->dcbaap_low;
2882 break;
62c6ae04 2883 case 0x34: /* DCBAAP high */
2d754a10
GH		 2884 ret = xhci->dcbaap_high;
2885 break;
62c6ae04 2886 case 0x38: /* CONFIG */
2d754a10
GH		 2887 ret = xhci->config;
2888 break;
62c6ae04 2889 default:
0ab966cf 2890 trace_usb_xhci_unimplemented("oper read", reg);
2d754a10 2891 ret = 0;
62c6ae04 2892 }
2d754a10
GH		 2893
2894 trace_usb_xhci_oper_read(reg, ret);
2895 return ret;
62c6ae04
HM		 2896}
2897
a8170e5e 2898static void xhci_oper_write(void *ptr, hwaddr reg,
1b067564 2899 uint64_t val, unsigned size)
62c6ae04 2900{
1b067564 2901 XHCIState *xhci = ptr;
37034575 2902 DeviceState *d = DEVICE(ptr);
1b067564 2903
2d754a10
GH		 2904 trace_usb_xhci_oper_write(reg, val);
2905
62c6ae04
HM		 2906 switch (reg) {
2907 case 0x00: /* USBCMD */
2908 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
2909 xhci_run(xhci);
2910 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {
2911 xhci_stop(xhci);
2912 }
f1f8bc21
GH		 2913 if (val & USBCMD_CSS) {
2914 /* save state */
2915 xhci->usbsts &= ~USBSTS_SRE;
2916 }
2917 if (val & USBCMD_CRS) {
2918 /* restore state */
2919 xhci->usbsts |= USBSTS_SRE;
2920 }
62c6ae04 2921 xhci->usbcmd = val & 0xc0f;
01546fa6 2922 xhci_mfwrap_update(xhci);
62c6ae04 2923 if (val & USBCMD_HCRST) {
37034575 2924 xhci_reset(d);
62c6ae04 2925 }
4c4abe7c 2926 xhci_intx_update(xhci);
62c6ae04
HM		 2927 break;
2928
2929 case 0x04: /* USBSTS */
2930 /* these bits are write-1-to-clear */
2931 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
4c4abe7c 2932 xhci_intx_update(xhci);
62c6ae04
HM		 2933 break;
2934
2935 case 0x14: /* DNCTRL */
2936 xhci->dnctrl = val & 0xffff;
2937 break;
2938 case 0x18: /* CRCR low */
2939 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
2940 break;
2941 case 0x1c: /* CRCR high */
2942 xhci->crcr_high = val;
2943 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
2944 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
2945 xhci->crcr_low &= ~CRCR_CRR;
2d1de850 2946 xhci_event(xhci, &event, 0);
62c6ae04
HM		 2947 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
2948 } else {
59a70ccd 2949 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
62c6ae04
HM		 2950 xhci_ring_init(xhci, &xhci->cmd_ring, base);
2951 }
2952 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
2953 break;
2954 case 0x30: /* DCBAAP low */
2955 xhci->dcbaap_low = val & 0xffffffc0;
2956 break;
2957 case 0x34: /* DCBAAP high */
2958 xhci->dcbaap_high = val;
2959 break;
2960 case 0x38: /* CONFIG */
2961 xhci->config = val & 0xff;
2962 break;
2963 default:
0ab966cf 2964 trace_usb_xhci_unimplemented("oper write", reg);
62c6ae04
HM		 2965 }
2966}
2967
a8170e5e 2968static uint64_t xhci_runtime_read(void *ptr, hwaddr reg,
1b067564 2969 unsigned size)
62c6ae04 2970{
1b067564 2971 XHCIState *xhci = ptr;
43d9d604 2972 uint32_t ret = 0;
62c6ae04 2973
43d9d604
GH		 2974 if (reg < 0x20) {
2975 switch (reg) {
2976 case 0x00: /* MFINDEX */
2977 ret = xhci_mfindex_get(xhci) & 0x3fff;
2978 break;
2979 default:
0ab966cf 2980 trace_usb_xhci_unimplemented("runtime read", reg);
43d9d604
GH		 2981 break;
2982 }
2983 } else {
2984 int v = (reg - 0x20) / 0x20;
2985 XHCIInterrupter *intr = &xhci->intr[v];
2986 switch (reg & 0x1f) {
2987 case 0x00: /* IMAN */
2988 ret = intr->iman;
2989 break;
2990 case 0x04: /* IMOD */
2991 ret = intr->imod;
2992 break;
2993 case 0x08: /* ERSTSZ */
2994 ret = intr->erstsz;
2995 break;
2996 case 0x10: /* ERSTBA low */
2997 ret = intr->erstba_low;
2998 break;
2999 case 0x14: /* ERSTBA high */
3000 ret = intr->erstba_high;
3001 break;
3002 case 0x18: /* ERDP low */
3003 ret = intr->erdp_low;
3004 break;
3005 case 0x1c: /* ERDP high */
3006 ret = intr->erdp_high;
3007 break;
3008 }
62c6ae04 3009 }
2d754a10
GH		 3010
3011 trace_usb_xhci_runtime_read(reg, ret);
3012 return ret;
62c6ae04
HM		 3013}
3014
a8170e5e 3015static void xhci_runtime_write(void *ptr, hwaddr reg,
1b067564 3016 uint64_t val, unsigned size)
62c6ae04 3017{
1b067564 3018 XHCIState *xhci = ptr;
43d9d604
GH		 3019 int v = (reg - 0x20) / 0x20;
3020 XHCIInterrupter *intr = &xhci->intr[v];
8e9f18b6 3021 trace_usb_xhci_runtime_write(reg, val);
62c6ae04 3022
43d9d604 3023 if (reg < 0x20) {
0ab966cf 3024 trace_usb_xhci_unimplemented("runtime write", reg);
43d9d604
GH		 3025 return;
3026 }
3027
3028 switch (reg & 0x1f) {
3029 case 0x00: /* IMAN */
62c6ae04 3030 if (val & IMAN_IP) {
962d11e1 3031 intr->iman &= ~IMAN_IP;
62c6ae04 3032 }
962d11e1
GH		 3033 intr->iman &= ~IMAN_IE;
3034 intr->iman |= val & IMAN_IE;
43d9d604
GH		 3035 if (v == 0) {
3036 xhci_intx_update(xhci);
3037 }
3038 xhci_msix_update(xhci, v);
62c6ae04 3039 break;
43d9d604 3040 case 0x04: /* IMOD */
962d11e1 3041 intr->imod = val;
62c6ae04 3042 break;
43d9d604 3043 case 0x08: /* ERSTSZ */
962d11e1 3044 intr->erstsz = val & 0xffff;
62c6ae04 3045 break;
43d9d604 3046 case 0x10: /* ERSTBA low */
2992d6b4
GH		 3047 if (xhci->nec_quirks) {
3048 /* NEC driver bug: it doesn't align this to 64 bytes */
3049 intr->erstba_low = val & 0xfffffff0;
3050 } else {
3051 intr->erstba_low = val & 0xffffffc0;
3052 }
62c6ae04 3053 break;
43d9d604 3054 case 0x14: /* ERSTBA high */
962d11e1 3055 intr->erstba_high = val;
43d9d604 3056 xhci_er_reset(xhci, v);
62c6ae04 3057 break;
43d9d604 3058 case 0x18: /* ERDP low */
62c6ae04 3059 if (val & ERDP_EHB) {
962d11e1 3060 intr->erdp_low &= ~ERDP_EHB;
62c6ae04 3061 }
962d11e1 3062 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB);
7da76e12
GH		 3063 if (val & ERDP_EHB) {
3064 dma_addr_t erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
3065 unsigned int dp_idx = (erdp - intr->er_start) / TRB_SIZE;
3066 if (erdp >= intr->er_start &&
3067 erdp < (intr->er_start + TRB_SIZE * intr->er_size) &&
3068 dp_idx != intr->er_ep_idx) {
3069 xhci_intr_raise(xhci, v);
3070 }
3071 }
62c6ae04 3072 break;
43d9d604 3073 case 0x1c: /* ERDP high */
962d11e1 3074 intr->erdp_high = val;
62c6ae04
HM		 3075 break;
3076 default:
0ab966cf 3077 trace_usb_xhci_unimplemented("oper write", reg);
62c6ae04
HM		 3078 }
3079}
3080
a8170e5e 3081static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg,
1b067564 3082 unsigned size)
62c6ae04 3083{
62c6ae04 3084 /* doorbells always read as 0 */
2d754a10 3085 trace_usb_xhci_doorbell_read(reg, 0);
62c6ae04
HM		 3086 return 0;
3087}
3088
a8170e5e 3089static void xhci_doorbell_write(void *ptr, hwaddr reg,
1b067564 3090 uint64_t val, unsigned size)
62c6ae04 3091{
1b067564 3092 XHCIState *xhci = ptr;
024426ac 3093 unsigned int epid, streamid;
1b067564 3094
2d754a10 3095 trace_usb_xhci_doorbell_write(reg, val);
62c6ae04
HM		 3096
3097 if (!xhci_running(xhci)) {
d6bb65fc 3098 DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n");
62c6ae04
HM		 3099 return;
3100 }
3101
3102 reg >>= 2;
3103
3104 if (reg == 0) {
3105 if (val == 0) {
3106 xhci_process_commands(xhci);
3107 } else {
d6bb65fc 3108 DPRINTF("xhci: bad doorbell 0 write: 0x%x\n",
1b067564 3109 (uint32_t)val);
62c6ae04
HM		 3110 }
3111 } else {
024426ac
GH		 3112 epid = val & 0xff;
3113 streamid = (val >> 16) & 0xffff;
91062ae0 3114 if (reg > xhci->numslots) {
d6bb65fc 3115 DPRINTF("xhci: bad doorbell %d\n", (int)reg);
024426ac 3116 } else if (epid > 31) {
d6bb65fc 3117 DPRINTF("xhci: bad doorbell %d write: 0x%x\n",
1b067564 3118 (int)reg, (uint32_t)val);
62c6ae04 3119 } else {
024426ac 3120 xhci_kick_ep(xhci, reg, epid, streamid);
62c6ae04
HM		 3121 }
3122 }
3123}
3124
6d3bc22e
GH		 3125static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val,
3126 unsigned width)
3127{
3128 /* nothing */
3129}
3130
1b067564
GH		 3131static const MemoryRegionOps xhci_cap_ops = {
3132 .read = xhci_cap_read,
6d3bc22e 3133 .write = xhci_cap_write,
6ee021d4 3134 .valid.min_access_size = 1,
1b067564 3135 .valid.max_access_size = 4,
6ee021d4
GH		 3136 .impl.min_access_size = 4,
3137 .impl.max_access_size = 4,
1b067564
GH		 3138 .endianness = DEVICE_LITTLE_ENDIAN,
3139};
62c6ae04 3140
1b067564
GH		 3141static const MemoryRegionOps xhci_oper_ops = {
3142 .read = xhci_oper_read,
3143 .write = xhci_oper_write,
3144 .valid.min_access_size = 4,
3145 .valid.max_access_size = 4,
3146 .endianness = DEVICE_LITTLE_ENDIAN,
3147};
62c6ae04 3148
1d8a4e69
GH		 3149static const MemoryRegionOps xhci_port_ops = {
3150 .read = xhci_port_read,
3151 .write = xhci_port_write,
3152 .valid.min_access_size = 4,
3153 .valid.max_access_size = 4,
3154 .endianness = DEVICE_LITTLE_ENDIAN,
3155};
3156
1b067564
GH		 3157static const MemoryRegionOps xhci_runtime_ops = {
3158 .read = xhci_runtime_read,
3159 .write = xhci_runtime_write,
3160 .valid.min_access_size = 4,
3161 .valid.max_access_size = 4,
3162 .endianness = DEVICE_LITTLE_ENDIAN,
3163};
62c6ae04 3164
1b067564
GH		 3165static const MemoryRegionOps xhci_doorbell_ops = {
3166 .read = xhci_doorbell_read,
3167 .write = xhci_doorbell_write,
62c6ae04
HM		 3168 .valid.min_access_size = 4,
3169 .valid.max_access_size = 4,
3170 .endianness = DEVICE_LITTLE_ENDIAN,
3171};
3172
3173static void xhci_attach(USBPort *usbport)
3174{
3175 XHCIState *xhci = usbport->opaque;
0846e635 3176 XHCIPort *port = xhci_lookup_port(xhci, usbport);
62c6ae04 3177
f3214027 3178 xhci_port_update(port, 0);
62c6ae04
HM		 3179}
3180
3181static void xhci_detach(USBPort *usbport)
3182{
3183 XHCIState *xhci = usbport->opaque;
0846e635 3184 XHCIPort *port = xhci_lookup_port(xhci, usbport);
62c6ae04 3185
f3dcf638 3186 xhci_detach_slot(xhci, usbport);
f3214027 3187 xhci_port_update(port, 1);
62c6ae04
HM		 3188}
3189
8c735e43
GH		 3190static void xhci_wakeup(USBPort *usbport)
3191{
3192 XHCIState *xhci = usbport->opaque;
0846e635 3193 XHCIPort *port = xhci_lookup_port(xhci, usbport);
8c735e43 3194
85e05d82 3195 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) {
8c735e43
GH		 3196 return;
3197 }
85e05d82 3198 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS);
f705a362 3199 xhci_port_notify(port, PORTSC_PLC);
8c735e43
GH		 3200}
3201
62c6ae04
HM		 3202static void xhci_complete(USBPort *port, USBPacket *packet)
3203{
3204 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet);
3205
9a77a0f5 3206 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
582d6f4a 3207 xhci_ep_nuke_one_xfer(xfer, 0);
0cae7b1a
HG		 3208 return;
3209 }
13e8ff7a 3210 xhci_try_complete_packet(xfer);
3a533ee8 3211 xhci_kick_epctx(xfer->epctx, xfer->streamid);
94b037f2
GH		 3212 if (xfer->complete) {
3213 xhci_ep_free_xfer(xfer);
3214 }
62c6ae04
HM		 3215}
3216
ccaf87a0 3217static void xhci_child_detach(USBPort *uport, USBDevice *child)
62c6ae04 3218{
ccaf87a0
GH		 3219 USBBus *bus = usb_bus_from_device(child);
3220 XHCIState *xhci = container_of(bus, XHCIState, bus);
ccaf87a0 3221
463c534d 3222 xhci_detach_slot(xhci, child->port);
62c6ae04
HM		 3223}
3224
1d8a4e69 3225static USBPortOps xhci_uport_ops = {
62c6ae04
HM		 3226 .attach = xhci_attach,
3227 .detach = xhci_detach,
8c735e43 3228 .wakeup = xhci_wakeup,
62c6ae04
HM		 3229 .complete = xhci_complete,
3230 .child_detach = xhci_child_detach,
3231};
3232
7c605a23
GH		 3233static int xhci_find_epid(USBEndpoint *ep)
3234{
3235 if (ep->nr == 0) {
3236 return 1;
3237 }
3238 if (ep->pid == USB_TOKEN_IN) {
3239 return ep->nr * 2 + 1;
3240 } else {
3241 return ep->nr * 2;
3242 }
3243}
3244
070eeef9 3245static USBEndpoint *xhci_epid_to_usbep(XHCIEPContext *epctx)
518ad5f2 3246{
070eeef9
GH		 3247 USBPort *uport;
3248 uint32_t token;
518ad5f2 3249
070eeef9 3250 if (!epctx) {
518ad5f2
HG		 3251 return NULL;
3252 }
070eeef9
GH		 3253 uport = epctx->xhci->slots[epctx->slotid - 1].uport;
3254 token = (epctx->epid & 1) ? USB_TOKEN_IN : USB_TOKEN_OUT;
3255 if (!uport) {
3256 return NULL;
3257 }
3258 return usb_ep_get(uport->dev, token, epctx->epid >> 1);
518ad5f2
HG		 3259}
3260
8550a02d
GH		 3261static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep,
3262 unsigned int stream)
7c605a23
GH		 3263{
3264 XHCIState *xhci = container_of(bus, XHCIState, bus);
3265 int slotid;
3266
3267 DPRINTF("%s\n", __func__);
af203be3 3268 slotid = ep->dev->addr;
7c605a23
GH		 3269 if (slotid == 0 || !xhci->slots[slotid-1].enabled) {
3270 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr);
3271 return;
3272 }
024426ac 3273 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream);
7c605a23
GH		 3274}
3275
62c6ae04 3276static USBBusOps xhci_bus_ops = {
7c605a23 3277 .wakeup_endpoint = xhci_wakeup_endpoint,
62c6ae04
HM		 3278};
3279
37034575 3280static void usb_xhci_init(XHCIState *xhci)
62c6ae04 3281{
37034575 3282 DeviceState *dev = DEVICE(xhci);
0846e635
GH		 3283 XHCIPort *port;
3284 int i, usbports, speedmask;
62c6ae04
HM		 3285
3286 xhci->usbsts = USBSTS_HCH;
3287
0846e635
GH		 3288 if (xhci->numports_2 > MAXPORTS_2) {
3289 xhci->numports_2 = MAXPORTS_2;
3290 }
3291 if (xhci->numports_3 > MAXPORTS_3) {
3292 xhci->numports_3 = MAXPORTS_3;
3293 }
3294 usbports = MAX(xhci->numports_2, xhci->numports_3);
3295 xhci->numports = xhci->numports_2 + xhci->numports_3;
3296
c889b3a5 3297 usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, dev);
62c6ae04 3298
0846e635
GH		 3299 for (i = 0; i < usbports; i++) {
3300 speedmask = 0;
3301 if (i < xhci->numports_2) {
7bafd888
GH		 3302 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
3303 port = &xhci->ports[i + xhci->numports_3];
3304 port->portnr = i + 1 + xhci->numports_3;
3305 } else {
3306 port = &xhci->ports[i];
3307 port->portnr = i + 1;
3308 }
0846e635
GH		 3309 port->uport = &xhci->uports[i];
3310 port->speedmask =
3311 USB_SPEED_MASK_LOW |
3312 USB_SPEED_MASK_FULL |
3313 USB_SPEED_MASK_HIGH;
1d8a4e69 3314 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1);
0846e635
GH		 3315 speedmask |= port->speedmask;
3316 }
3317 if (i < xhci->numports_3) {
7bafd888
GH		 3318 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
3319 port = &xhci->ports[i];
3320 port->portnr = i + 1;
3321 } else {
3322 port = &xhci->ports[i + xhci->numports_2];
3323 port->portnr = i + 1 + xhci->numports_2;
3324 }
0846e635
GH		 3325 port->uport = &xhci->uports[i];
3326 port->speedmask = USB_SPEED_MASK_SUPER;
1d8a4e69 3327 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1);
0846e635
GH		 3328 speedmask |= port->speedmask;
3329 }
3330 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i,
1d8a4e69 3331 &xhci_uport_ops, speedmask);
62c6ae04 3332 }
62c6ae04
HM		 3333}
3334
9af21dbe 3335static void usb_xhci_realize(struct PCIDevice *dev, Error **errp)
62c6ae04 3336{
1d8a4e69 3337 int i, ret;
1108b2f8 3338 Error *err = NULL;
62c6ae04 3339
37034575 3340 XHCIState *xhci = XHCI(dev);
62c6ae04 3341
9b7d3334
AF		 3342 dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */
3343 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
3344 dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
3345 dev->config[0x60] = 0x30; /* release number */
62c6ae04 3346
2992d6b4
GH		 3347 if (strcmp(object_get_typename(OBJECT(dev)), TYPE_NEC_XHCI) == 0) {
3348 xhci->nec_quirks = true;
3349 }
91062ae0
GH		 3350 if (xhci->numintrs > MAXINTRS) {
3351 xhci->numintrs = MAXINTRS;
3352 }
c94a7c69
GH		 3353 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */
3354 xhci->numintrs++;
3355 }
91062ae0
GH		 3356 if (xhci->numintrs < 1) {
3357 xhci->numintrs = 1;
3358 }
3359 if (xhci->numslots > MAXSLOTS) {
3360 xhci->numslots = MAXSLOTS;
3361 }
3362 if (xhci->numslots < 1) {
3363 xhci->numslots = 1;
3364 }
2aa6bfcb
GH		 3365 if (xhci_get_flag(xhci, XHCI_FLAG_ENABLE_STREAMS)) {
3366 xhci->max_pstreams_mask = 7; /* == 256 primary streams */
3367 } else {
3368 xhci->max_pstreams_mask = 0;
3369 }
91062ae0 3370
20729dbd
C		 3371 if (xhci->msi != ON_OFF_AUTO_OFF) {
3372 ret = msi_init(dev, 0x70, xhci->numintrs, true, false, &err);
3373 /* Any error other than -ENOTSUP(board's MSI support is broken)
3374 * is a programming error */
3375 assert(!ret || ret == -ENOTSUP);
3376 if (ret && xhci->msi == ON_OFF_AUTO_ON) {
3377 /* Can't satisfy user's explicit msi=on request, fail */
3378 error_append_hint(&err, "You have to use msi=auto (default) or "
3379 "msi=off with this machine type.\n");
3380 error_propagate(errp, err);
3381 return;
3382 }
3383 assert(!err || xhci->msi == ON_OFF_AUTO_AUTO);
3384 /* With msi=auto, we fall back to MSI off silently */
3385 error_free(err);
3386 }
3387
3388 usb_xhci_init(xhci);
bc72ad67 3389 xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci);
01546fa6 3390
22fc860b
PB		 3391 memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS);
3392 memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci,
1b067564 3393 "capabilities", LEN_CAP);
22fc860b 3394 memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci,
1d8a4e69 3395 "operational", 0x400);
22fc860b 3396 memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci,
1b067564 3397 "runtime", LEN_RUNTIME);
22fc860b 3398 memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci,
1b067564
GH		 3399 "doorbell", LEN_DOORBELL);
3400
3401 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap);
3402 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper);
3403 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime);
3404 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell);
3405
1d8a4e69
GH		 3406 for (i = 0; i < xhci->numports; i++) {
3407 XHCIPort *port = &xhci->ports[i];
3408 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i;
3409 port->xhci = xhci;
22fc860b 3410 memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port,
1d8a4e69
GH		 3411 port->name, 0x10);
3412 memory_region_add_subregion(&xhci->mem, offset, &port->mem);
3413 }
3414
9b7d3334 3415 pci_register_bar(dev, 0,
62c6ae04
HM		 3416 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
3417 &xhci->mem);
3418
fd56e061 3419 if (pci_bus_is_express(pci_get_bus(dev)) ||
e6043e92 3420 xhci_get_flag(xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) {
058fdcf5 3421 ret = pcie_endpoint_cap_init(dev, 0xa0);
9a815774 3422 assert(ret > 0);
058fdcf5 3423 }
62c6ae04 3424
290fd20d 3425 if (xhci->msix != ON_OFF_AUTO_OFF) {
ee640c62 3426 /* TODO check for errors, and should fail when msix=on */
9b7d3334 3427 msix_init(dev, xhci->numintrs,
4c47f800
GH		 3428 &xhci->mem, 0, OFF_MSIX_TABLE,
3429 &xhci->mem, 0, OFF_MSIX_PBA,
ee640c62 3430 0x90, NULL);
4c47f800 3431 }
62c6ae04
HM		 3432}
3433
53c30545
GA		 3434static void usb_xhci_exit(PCIDevice *dev)
3435{
3436 int i;
3437 XHCIState *xhci = XHCI(dev);
3438
d733f74c
GA		 3439 trace_usb_xhci_exit();
3440
53c30545
GA		 3441 for (i = 0; i < xhci->numslots; i++) {
3442 xhci_disable_slot(xhci, i + 1);
3443 }
3444
3445 if (xhci->mfwrap_timer) {
3446 timer_del(xhci->mfwrap_timer);
3447 timer_free(xhci->mfwrap_timer);
3448 xhci->mfwrap_timer = NULL;
3449 }
3450
3451 memory_region_del_subregion(&xhci->mem, &xhci->mem_cap);
3452 memory_region_del_subregion(&xhci->mem, &xhci->mem_oper);
3453 memory_region_del_subregion(&xhci->mem, &xhci->mem_runtime);
3454 memory_region_del_subregion(&xhci->mem, &xhci->mem_doorbell);
3455
3456 for (i = 0; i < xhci->numports; i++) {
3457 XHCIPort *port = &xhci->ports[i];
3458 memory_region_del_subregion(&xhci->mem, &port->mem);
3459 }
3460
3461 /* destroy msix memory region */
3462 if (dev->msix_table && dev->msix_pba
3463 && dev->msix_entry_used) {
b53dd449 3464 msix_uninit(dev, &xhci->mem, &xhci->mem);
53c30545
GA		 3465 }
3466
3467 usb_bus_release(&xhci->bus);
3468}
3469
37352df3
GH		 3470static int usb_xhci_post_load(void *opaque, int version_id)
3471{
3472 XHCIState *xhci = opaque;
9b7d3334 3473 PCIDevice *pci_dev = PCI_DEVICE(xhci);
37352df3
GH		 3474 XHCISlot *slot;
3475 XHCIEPContext *epctx;
3476 dma_addr_t dcbaap, pctx;
3477 uint32_t slot_ctx[4];
3478 uint32_t ep_ctx[5];
3479 int slotid, epid, state, intr;
3480
3481 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
3482
3483 for (slotid = 1; slotid <= xhci->numslots; slotid++) {
3484 slot = &xhci->slots[slotid-1];
3485 if (!slot->addressed) {
3486 continue;
3487 }
3488 slot->ctx =
9b7d3334 3489 xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid));
37352df3
GH		 3490 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx));
3491 slot->uport = xhci_lookup_uport(xhci, slot_ctx);
f2ad97ff
GH		 3492 if (!slot->uport) {
3493 /* should not happen, but may trigger on guest bugs */
3494 slot->enabled = 0;
3495 slot->addressed = 0;
3496 continue;
3497 }
37352df3
GH		 3498 assert(slot->uport && slot->uport->dev);
3499
f6969b9f 3500 for (epid = 1; epid <= 31; epid++) {
37352df3
GH		 3501 pctx = slot->ctx + 32 * epid;
3502 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx));
3503 state = ep_ctx[0] & EP_STATE_MASK;
3504 if (state == EP_DISABLED) {
3505 continue;
3506 }
3507 epctx = xhci_alloc_epctx(xhci, slotid, epid);
3508 slot->eps[epid-1] = epctx;
3509 xhci_init_epctx(epctx, pctx, ep_ctx);
3510 epctx->state = state;
3511 if (state == EP_RUNNING) {
3512 /* kick endpoint after vmload is finished */
bc72ad67 3513 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
37352df3
GH		 3514 }
3515 }
3516 }
3517
3518 for (intr = 0; intr < xhci->numintrs; intr++) {
3519 if (xhci->intr[intr].msix_used) {
9b7d3334 3520 msix_vector_use(pci_dev, intr);
37352df3 3521 } else {
9b7d3334 3522 msix_vector_unuse(pci_dev, intr);
37352df3
GH		 3523 }
3524 }
3525
3526 return 0;
3527}
3528
3529static const VMStateDescription vmstate_xhci_ring = {
3530 .name = "xhci-ring",
3531 .version_id = 1,
3532 .fields = (VMStateField[]) {
3533 VMSTATE_UINT64(dequeue, XHCIRing),
3534 VMSTATE_BOOL(ccs, XHCIRing),
3535 VMSTATE_END_OF_LIST()
3536 }
3537};
3538
3539static const VMStateDescription vmstate_xhci_port = {
3540 .name = "xhci-port",
3541 .version_id = 1,
3542 .fields = (VMStateField[]) {
3543 VMSTATE_UINT32(portsc, XHCIPort),
3544 VMSTATE_END_OF_LIST()
3545 }
3546};
3547
3548static const VMStateDescription vmstate_xhci_slot = {
3549 .name = "xhci-slot",
3550 .version_id = 1,
3551 .fields = (VMStateField[]) {
3552 VMSTATE_BOOL(enabled, XHCISlot),
3553 VMSTATE_BOOL(addressed, XHCISlot),
3554 VMSTATE_END_OF_LIST()
3555 }
3556};
3557
3558static const VMStateDescription vmstate_xhci_event = {
3559 .name = "xhci-event",
3560 .version_id = 1,
3561 .fields = (VMStateField[]) {
3562 VMSTATE_UINT32(type, XHCIEvent),
3563 VMSTATE_UINT32(ccode, XHCIEvent),
3564 VMSTATE_UINT64(ptr, XHCIEvent),
3565 VMSTATE_UINT32(length, XHCIEvent),
3566 VMSTATE_UINT32(flags, XHCIEvent),
3567 VMSTATE_UINT8(slotid, XHCIEvent),
3568 VMSTATE_UINT8(epid, XHCIEvent),
3afca1d6 3569 VMSTATE_END_OF_LIST()
37352df3
GH		 3570 }
3571};
3572
3573static bool xhci_er_full(void *opaque, int version_id)
3574{
898248a3 3575 return false;
37352df3
GH		 3576}
3577
3578static const VMStateDescription vmstate_xhci_intr = {
3579 .name = "xhci-intr",
3580 .version_id = 1,
3581 .fields = (VMStateField[]) {
3582 /* registers */
3583 VMSTATE_UINT32(iman, XHCIInterrupter),
3584 VMSTATE_UINT32(imod, XHCIInterrupter),
3585 VMSTATE_UINT32(erstsz, XHCIInterrupter),
3586 VMSTATE_UINT32(erstba_low, XHCIInterrupter),
3587 VMSTATE_UINT32(erstba_high, XHCIInterrupter),
3588 VMSTATE_UINT32(erdp_low, XHCIInterrupter),
3589 VMSTATE_UINT32(erdp_high, XHCIInterrupter),
3590
3591 /* state */
3592 VMSTATE_BOOL(msix_used, XHCIInterrupter),
3593 VMSTATE_BOOL(er_pcs, XHCIInterrupter),
3594 VMSTATE_UINT64(er_start, XHCIInterrupter),
3595 VMSTATE_UINT32(er_size, XHCIInterrupter),
3596 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter),
3597
3598 /* event queue (used if ring is full) */
898248a3 3599 VMSTATE_BOOL(er_full_unused, XHCIInterrupter),
37352df3
GH		 3600 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full),
3601 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full),
3602 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE,
3603 xhci_er_full, 1,
3604 vmstate_xhci_event, XHCIEvent),
3605
3606 VMSTATE_END_OF_LIST()
3607 }
3608};
3609
62c6ae04
HM		 3610static const VMStateDescription vmstate_xhci = {
3611 .name = "xhci",
37352df3
GH		 3612 .version_id = 1,
3613 .post_load = usb_xhci_post_load,
3614 .fields = (VMStateField[]) {
20daa90a 3615 VMSTATE_PCI_DEVICE(parent_obj, XHCIState),
9b7d3334 3616 VMSTATE_MSIX(parent_obj, XHCIState),
37352df3
GH		 3617
3618 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1,
3619 vmstate_xhci_port, XHCIPort),
3620 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1,
3621 vmstate_xhci_slot, XHCISlot),
3622 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1,
3623 vmstate_xhci_intr, XHCIInterrupter),
3624
3625 /* Operational Registers */
3626 VMSTATE_UINT32(usbcmd, XHCIState),
3627 VMSTATE_UINT32(usbsts, XHCIState),
3628 VMSTATE_UINT32(dnctrl, XHCIState),
3629 VMSTATE_UINT32(crcr_low, XHCIState),
3630 VMSTATE_UINT32(crcr_high, XHCIState),
3631 VMSTATE_UINT32(dcbaap_low, XHCIState),
3632 VMSTATE_UINT32(dcbaap_high, XHCIState),
3633 VMSTATE_UINT32(config, XHCIState),
3634
3635 /* Runtime Registers & state */
3636 VMSTATE_INT64(mfindex_start, XHCIState),
e720677e 3637 VMSTATE_TIMER_PTR(mfwrap_timer, XHCIState),
37352df3
GH		 3638 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing),
3639
3640 VMSTATE_END_OF_LIST()
3641 }
62c6ae04
HM		 3642};
3643
4f72b8d2
GH		 3644static Property xhci_properties[] = {
3645 DEFINE_PROP_BIT("streams", XHCIState, flags,
3646 XHCI_FLAG_ENABLE_STREAMS, true),
91062ae0
GH		 3647 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4),
3648 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4),
39bffca2
AL		 3649 DEFINE_PROP_END_OF_LIST(),
3650};
3651
d61a363d
YB		 3652static void xhci_instance_init(Object *obj)
3653{
3654 /* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command
3655 * line, therefore, no need to wait to realize like other devices */
3656 PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS;
3657}
3658
40021f08
AL		 3659static void xhci_class_init(ObjectClass *klass, void *data)
3660{
3661 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
39bffca2 3662 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 3663
39bffca2
AL		 3664 dc->vmsd = &vmstate_xhci;
3665 dc->props = xhci_properties;
64619739 3666 dc->reset = xhci_reset;
125ee0ed 3667 set_bit(DEVICE_CATEGORY_USB, dc->categories);
9af21dbe 3668 k->realize = usb_xhci_realize;
53c30545 3669 k->exit = usb_xhci_exit;
40021f08 3670 k->class_id = PCI_CLASS_SERIAL_USB;
40021f08
AL		 3671}
3672
8c43a6f0 3673static const TypeInfo xhci_info = {
37034575 3674 .name = TYPE_XHCI,
39bffca2
AL		 3675 .parent = TYPE_PCI_DEVICE,
3676 .instance_size = sizeof(XHCIState),
3677 .class_init = xhci_class_init,
d61a363d 3678 .instance_init = xhci_instance_init,
72a810f4 3679 .abstract = true,
a5fa336f
EH		 3680 .interfaces = (InterfaceInfo[]) {
3681 { INTERFACE_PCIE_DEVICE },
3682 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
3683 { }
3684 },
72a810f4
GH		 3685};
3686
72a810f4
GH		 3687static void qemu_xhci_class_init(ObjectClass *klass, void *data)
3688{
3689 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3690
3691 k->vendor_id = PCI_VENDOR_ID_REDHAT;
3692 k->device_id = PCI_DEVICE_ID_REDHAT_XHCI;
3693 k->revision = 0x01;
3694}
3695
4f72b8d2
GH		 3696static void qemu_xhci_instance_init(Object *obj)
3697{
3698 XHCIState *xhci = XHCI(obj);
3699
3700 xhci->msi = ON_OFF_AUTO_OFF;
3701 xhci->msix = ON_OFF_AUTO_AUTO;
3702 xhci->numintrs = MAXINTRS;
3703 xhci->numslots = MAXSLOTS;
3704 xhci_set_flag(xhci, XHCI_FLAG_SS_FIRST);
3705}
3706
72a810f4
GH		 3707static const TypeInfo qemu_xhci_info = {
3708 .name = TYPE_QEMU_XHCI,
3709 .parent = TYPE_XHCI,
3710 .class_init = qemu_xhci_class_init,
4f72b8d2 3711 .instance_init = qemu_xhci_instance_init,
62c6ae04
HM		 3712};
3713
83f7d43a 3714static void xhci_register_types(void)
62c6ae04 3715{
39bffca2 3716 type_register_static(&xhci_info);
72a810f4 3717 type_register_static(&qemu_xhci_info);
62c6ae04 3718}
83f7d43a
AF		 3719
3720type_init(xhci_register_types)
Empty description
This page took 1.081954 seconds and 4 git commands to generate.