[qemu.git] / hw / char / imx_serial.c

/*
 * IMX31 UARTS
 *
 * Copyright (c) 2008 OKL
 * Originally Written by Hans Jiang
 * Copyright (c) 2011 NICTA Pty Ltd.
 * Updated by Jean-Christophe Dubois <[email protected]>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 *
 * This is a `bare-bones' implementation of the IMX series serial ports.
 * TODO:
 *  -- implement FIFOs.  The real hardware has 32 word transmit
 *                       and receive FIFOs; we currently use a 1-char buffer
 *  -- implement DMA
 *  -- implement BAUD-rate and modem lines, for when the backend
 *     is a real serial device.
 */

#include "qemu/osdep.h"
#include "hw/char/imx_serial.h"
#include "sysemu/sysemu.h"
#include "sysemu/char.h"
#include "qemu/log.h"

#ifndef DEBUG_IMX_UART
#define DEBUG_IMX_UART 0
#endif

#define DPRINTF(fmt, args...) \
    do { \
        if (DEBUG_IMX_UART) { \
            fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \
                                             __func__, ##args); \
        } \
    } while (0)

static const VMStateDescription vmstate_imx_serial = {
    .name = TYPE_IMX_SERIAL,
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_INT32(readbuff, IMXSerialState),
        VMSTATE_UINT32(usr1, IMXSerialState),
        VMSTATE_UINT32(usr2, IMXSerialState),
        VMSTATE_UINT32(ucr1, IMXSerialState),
        VMSTATE_UINT32(uts1, IMXSerialState),
        VMSTATE_UINT32(onems, IMXSerialState),
        VMSTATE_UINT32(ufcr, IMXSerialState),
        VMSTATE_UINT32(ubmr, IMXSerialState),
        VMSTATE_UINT32(ubrc, IMXSerialState),
        VMSTATE_UINT32(ucr3, IMXSerialState),
        VMSTATE_END_OF_LIST()
    },
};

static void imx_update(IMXSerialState *s)
{
    uint32_t flags;

    flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
    if (s->ucr1 & UCR1_TXMPTYEN) {
        flags |= (s->uts1 & UTS1_TXEMPTY);
    } else {
        flags &= ~USR1_TRDY;
    }

    qemu_set_irq(s->irq, !!flags);
}

static void imx_serial_reset(IMXSerialState *s)
{

    s->usr1 = USR1_TRDY | USR1_RXDS;
    /*
     * Fake attachment of a terminal: assert RTS.
     */
    s->usr1 |= USR1_RTSS;
    s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN;
    s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY;
    s->ucr1 = 0;
    s->ucr2 = UCR2_SRST;
    s->ucr3 = 0x700;
    s->ubmr = 0;
    s->ubrc = 4;
    s->readbuff = URXD_ERR;
}

static void imx_serial_reset_at_boot(DeviceState *dev)
{
    IMXSerialState *s = IMX_SERIAL(dev);

    imx_serial_reset(s);

    /*
     * enable the uart on boot, so messages from the linux decompresser
     * are visible.  On real hardware this is done by the boot rom
     * before anything else is loaded.
     */
    s->ucr1 = UCR1_UARTEN;
    s->ucr2 = UCR2_TXEN;

}

static uint64_t imx_serial_read(void *opaque, hwaddr offset,
                                unsigned size)
{
    IMXSerialState *s = (IMXSerialState *)opaque;
    uint32_t c;

    DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset);

    switch (offset >> 2) {
    case 0x0: /* URXD */
        c = s->readbuff;
        if (!(s->uts1 & UTS1_RXEMPTY)) {
            /* Character is valid */
            c |= URXD_CHARRDY;
            s->usr1 &= ~USR1_RRDY;
            s->usr2 &= ~USR2_RDR;
            s->uts1 |= UTS1_RXEMPTY;
            imx_update(s);
            qemu_chr_fe_accept_input(&s->chr);
        }
        return c;

    case 0x20: /* UCR1 */
        return s->ucr1;

    case 0x21: /* UCR2 */
        return s->ucr2;

    case 0x25: /* USR1 */
        return s->usr1;

    case 0x26: /* USR2 */
        return s->usr2;

    case 0x2A: /* BRM Modulator */
        return s->ubmr;

    case 0x2B: /* Baud Rate Count */
        return s->ubrc;

    case 0x2d: /* Test register */
        return s->uts1;

    case 0x24: /* UFCR */
        return s->ufcr;

    case 0x2c:
        return s->onems;

    case 0x22: /* UCR3 */
        return s->ucr3;

    case 0x23: /* UCR4 */
    case 0x29: /* BRM Incremental */
        return 0x0; /* TODO */

    default:
        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
                      HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
        return 0;
    }
}

static void imx_serial_write(void *opaque, hwaddr offset,
                             uint64_t value, unsigned size)
{
    IMXSerialState *s = (IMXSerialState *)opaque;
    CharDriverState *chr = qemu_chr_fe_get_driver(&s->chr);
    unsigned char ch;

    DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n",
            offset, (unsigned int)value, chr ? chr->label : "NODEV");

    switch (offset >> 2) {
    case 0x10: /* UTXD */
        ch = value;
        if (s->ucr2 & UCR2_TXEN) {
            /* XXX this blocks entire thread. Rewrite to use
             * qemu_chr_fe_write and background I/O callbacks */
            qemu_chr_fe_write_all(&s->chr, &ch, 1);
            s->usr1 &= ~USR1_TRDY;
            imx_update(s);
            s->usr1 |= USR1_TRDY;
            imx_update(s);
        }
        break;

    case 0x20: /* UCR1 */
        s->ucr1 = value & 0xffff;

        DPRINTF("write(ucr1=%x)\n", (unsigned int)value);

        imx_update(s);
        break;

    case 0x21: /* UCR2 */
        /*
         * Only a few bits in control register 2 are implemented as yet.
         * If it's intended to use a real serial device as a back-end, this
         * register will have to be implemented more fully.
         */
        if (!(value & UCR2_SRST)) {
            imx_serial_reset(s);
            imx_update(s);
            value |= UCR2_SRST;
        }
        if (value & UCR2_RXEN) {
            if (!(s->ucr2 & UCR2_RXEN)) {
                qemu_chr_fe_accept_input(&s->chr);
            }
        }
        s->ucr2 = value & 0xffff;
        break;

    case 0x25: /* USR1 */
        value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM |
                 USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER;
        s->usr1 &= ~value;
        break;

    case 0x26: /* USR2 */
        /*
         * Writing 1 to some bits clears them; all other
         * values are ignored
         */
        value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST |
                 USR2_RIDELT | USR2_IRINT | USR2_WAKE |
                 USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE;
        s->usr2 &= ~value;
        break;

    /*
     * Linux expects to see what it writes to these registers
     * We don't currently alter the baud rate
     */
    case 0x29: /* UBIR */
        s->ubrc = value & 0xffff;
        break;

    case 0x2a: /* UBMR */
        s->ubmr = value & 0xffff;
        break;

    case 0x2c: /* One ms reg */
        s->onems = value & 0xffff;
        break;

    case 0x24: /* FIFO control register */
        s->ufcr = value & 0xffff;
        break;

    case 0x22: /* UCR3 */
        s->ucr3 = value & 0xffff;
        break;

    case 0x2d: /* UTS1 */
    case 0x23: /* UCR4 */
        qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
                      HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
        /* TODO */
        break;

    default:
        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
                      HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
    }
}

static int imx_can_receive(void *opaque)
{
    IMXSerialState *s = (IMXSerialState *)opaque;
    return !(s->usr1 & USR1_RRDY);
}

static void imx_put_data(void *opaque, uint32_t value)
{
    IMXSerialState *s = (IMXSerialState *)opaque;

    DPRINTF("received char\n");

    s->usr1 |= USR1_RRDY;
    s->usr2 |= USR2_RDR;
    s->uts1 &= ~UTS1_RXEMPTY;
    s->readbuff = value;
    imx_update(s);
}

static void imx_receive(void *opaque, const uint8_t *buf, int size)
{
    imx_put_data(opaque, *buf);
}

static void imx_event(void *opaque, int event)
{
    if (event == CHR_EVENT_BREAK) {
        imx_put_data(opaque, URXD_BRK);
    }
}


static const struct MemoryRegionOps imx_serial_ops = {
    .read = imx_serial_read,
    .write = imx_serial_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void imx_serial_realize(DeviceState *dev, Error **errp)
{
    IMXSerialState *s = IMX_SERIAL(dev);

    DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr));

    qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive,
                             imx_event, s, NULL, true);
}

static void imx_serial_init(Object *obj)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    IMXSerialState *s = IMX_SERIAL(obj);

    memory_region_init_io(&s->iomem, obj, &imx_serial_ops, s,
                          TYPE_IMX_SERIAL, 0x1000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq);
}

static Property imx_serial_properties[] = {
    DEFINE_PROP_CHR("chardev", IMXSerialState, chr),
    DEFINE_PROP_END_OF_LIST(),
};

static void imx_serial_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = imx_serial_realize;
    dc->vmsd = &vmstate_imx_serial;
    dc->reset = imx_serial_reset_at_boot;
    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
    dc->desc = "i.MX series UART";
    dc->props = imx_serial_properties;
}

static const TypeInfo imx_serial_info = {
    .name           = TYPE_IMX_SERIAL,
    .parent         = TYPE_SYS_BUS_DEVICE,
    .instance_size  = sizeof(IMXSerialState),
    .instance_init  = imx_serial_init,
    .class_init     = imx_serial_class_init,
};

static void imx_serial_register_types(void)
{
    type_register_static(&imx_serial_info);
}

type_init(imx_serial_register_types)
Commit	Line	Data
40b6f911 PC	1	/*
	2	* IMX31 UARTS
	3	*
	4	* Copyright (c) 2008 OKL
	5	* Originally Written by Hans Jiang
	6	* Copyright (c) 2011 NICTA Pty Ltd.
cd0bda20	7	* Updated by Jean-Christophe Dubois <[email protected]>
40b6f911 PC	8	*
	9	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	10	* See the COPYING file in the top-level directory.
	11	*
	12	* This is a `bare-bones' implementation of the IMX series serial ports.
	13	* TODO:
	14	* -- implement FIFOs. The real hardware has 32 word transmit
	15	* and receive FIFOs; we currently use a 1-char buffer
	16	* -- implement DMA
	17	* -- implement BAUD-rate and modem lines, for when the backend
	18	* is a real serial device.
	19	*/
	20
8ef94f0b	21	#include "qemu/osdep.h"
cd0bda20	22	#include "hw/char/imx_serial.h"
9c17d615	23	#include "sysemu/sysemu.h"
dccfcd0e	24	#include "sysemu/char.h"
03dd024f	25	#include "qemu/log.h"
40b6f911	26
8ccce77c JCD	27	#ifndef DEBUG_IMX_UART
8ccce77c JCD	28	#define DEBUG_IMX_UART 0
40b6f911 PC	29	#endif
40b6f911 PC	30
8ccce77c JCD	31	#define DPRINTF(fmt, args...) \
	32	do { \
	33	if (DEBUG_IMX_UART) { \
	34	fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \
	35	__func__, ##args); \
	36	} \
	37	} while (0)
40b6f911	38
40b6f911	39	static const VMStateDescription vmstate_imx_serial = {
fa2650a3	40	.name = TYPE_IMX_SERIAL,
40b6f911 PC	41	.version_id = 1,
40b6f911 PC	42	.minimum_version_id = 1,
40b6f911 PC	43	.fields = (VMStateField[]) {
	44	VMSTATE_INT32(readbuff, IMXSerialState),
	45	VMSTATE_UINT32(usr1, IMXSerialState),
	46	VMSTATE_UINT32(usr2, IMXSerialState),
	47	VMSTATE_UINT32(ucr1, IMXSerialState),
	48	VMSTATE_UINT32(uts1, IMXSerialState),
	49	VMSTATE_UINT32(onems, IMXSerialState),
	50	VMSTATE_UINT32(ufcr, IMXSerialState),
	51	VMSTATE_UINT32(ubmr, IMXSerialState),
	52	VMSTATE_UINT32(ubrc, IMXSerialState),
	53	VMSTATE_UINT32(ucr3, IMXSerialState),
	54	VMSTATE_END_OF_LIST()
	55	},
	56	};
	57
40b6f911 PC	58	static void imx_update(IMXSerialState *s)
	59	{
	60	uint32_t flags;
	61
	62	flags = (s->usr1 & s->ucr1) & (USR1_TRDY\|USR1_RRDY);
dc144220 GR	63	if (s->ucr1 & UCR1_TXMPTYEN) {
	64	flags \|= (s->uts1 & UTS1_TXEMPTY);
	65	} else {
40b6f911 PC	66	flags &= ~USR1_TRDY;
	67	}
	68
	69	qemu_set_irq(s->irq, !!flags);
	70	}
	71
	72	static void imx_serial_reset(IMXSerialState *s)
	73	{
	74
	75	s->usr1 = USR1_TRDY \| USR1_RXDS;
	76	/*
	77	* Fake attachment of a terminal: assert RTS.
	78	*/
	79	s->usr1 \|= USR1_RTSS;
	80	s->usr2 = USR2_TXFE \| USR2_TXDC \| USR2_DCDIN;
	81	s->uts1 = UTS1_RXEMPTY \| UTS1_TXEMPTY;
	82	s->ucr1 = 0;
	83	s->ucr2 = UCR2_SRST;
	84	s->ucr3 = 0x700;
	85	s->ubmr = 0;
	86	s->ubrc = 4;
	87	s->readbuff = URXD_ERR;
	88	}
	89
	90	static void imx_serial_reset_at_boot(DeviceState *dev)
	91	{
8d8e3481	92	IMXSerialState *s = IMX_SERIAL(dev);
40b6f911 PC	93
	94	imx_serial_reset(s);
	95
	96	/*
	97	* enable the uart on boot, so messages from the linux decompresser
	98	* are visible. On real hardware this is done by the boot rom
	99	* before anything else is loaded.
	100	*/
	101	s->ucr1 = UCR1_UARTEN;
	102	s->ucr2 = UCR2_TXEN;
	103
	104	}
	105
a8170e5e	106	static uint64_t imx_serial_read(void *opaque, hwaddr offset,
40b6f911 PC	107	unsigned size)
	108	{
	109	IMXSerialState s = (IMXSerialState )opaque;
	110	uint32_t c;
	111
8ccce77c JCD	112	DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset);
8ccce77c JCD	113
40b6f911 PC	114	switch (offset >> 2) {
	115	case 0x0: /* URXD */
	116	c = s->readbuff;
	117	if (!(s->uts1 & UTS1_RXEMPTY)) {
	118	/* Character is valid */
	119	c \|= URXD_CHARRDY;
	120	s->usr1 &= ~USR1_RRDY;
	121	s->usr2 &= ~USR2_RDR;
	122	s->uts1 \|= UTS1_RXEMPTY;
	123	imx_update(s);
fa394ed6	124	qemu_chr_fe_accept_input(&s->chr);
40b6f911 PC	125	}
	126	return c;
	127
	128	case 0x20: /* UCR1 */
	129	return s->ucr1;
	130
	131	case 0x21: /* UCR2 */
	132	return s->ucr2;
	133
	134	case 0x25: /* USR1 */
	135	return s->usr1;
	136
	137	case 0x26: /* USR2 */
	138	return s->usr2;
	139
	140	case 0x2A: /* BRM Modulator */
	141	return s->ubmr;
	142
	143	case 0x2B: /* Baud Rate Count */
	144	return s->ubrc;
	145
	146	case 0x2d: /* Test register */
	147	return s->uts1;
	148
	149	case 0x24: /* UFCR */
	150	return s->ufcr;
	151
	152	case 0x2c:
	153	return s->onems;
	154
	155	case 0x22: /* UCR3 */
	156	return s->ucr3;
	157
	158	case 0x23: /* UCR4 */
	159	case 0x29: /* BRM Incremental */
	160	return 0x0; /* TODO */
	161
	162	default:
8ccce77c JCD	163	qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
8ccce77c JCD	164	HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
40b6f911 PC	165	return 0;
	166	}
	167	}
	168
a8170e5e	169	static void imx_serial_write(void *opaque, hwaddr offset,
fa2650a3	170	uint64_t value, unsigned size)
40b6f911 PC	171	{
40b6f911 PC	172	IMXSerialState s = (IMXSerialState )opaque;
5345fdb4	173	CharDriverState *chr = qemu_chr_fe_get_driver(&s->chr);
40b6f911 PC	174	unsigned char ch;
40b6f911 PC	175
8ccce77c	176	DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n",
5345fdb4	177	offset, (unsigned int)value, chr ? chr->label : "NODEV");
40b6f911 PC	178
	179	switch (offset >> 2) {
	180	case 0x10: /* UTXD */
	181	ch = value;
	182	if (s->ucr2 & UCR2_TXEN) {
fa394ed6 MAL	183	/* XXX this blocks entire thread. Rewrite to use
	184	* qemu_chr_fe_write and background I/O callbacks */
	185	qemu_chr_fe_write_all(&s->chr, &ch, 1);
40b6f911 PC	186	s->usr1 &= ~USR1_TRDY;
	187	imx_update(s);
	188	s->usr1 \|= USR1_TRDY;
	189	imx_update(s);
	190	}
	191	break;
	192
	193	case 0x20: /* UCR1 */
	194	s->ucr1 = value & 0xffff;
8ccce77c	195
40b6f911	196	DPRINTF("write(ucr1=%x)\n", (unsigned int)value);
8ccce77c	197
40b6f911 PC	198	imx_update(s);
	199	break;
	200
	201	case 0x21: /* UCR2 */
	202	/*
	203	* Only a few bits in control register 2 are implemented as yet.
	204	* If it's intended to use a real serial device as a back-end, this
	205	* register will have to be implemented more fully.
	206	*/
	207	if (!(value & UCR2_SRST)) {
	208	imx_serial_reset(s);
	209	imx_update(s);
	210	value \|= UCR2_SRST;
	211	}
	212	if (value & UCR2_RXEN) {
	213	if (!(s->ucr2 & UCR2_RXEN)) {
fa394ed6	214	qemu_chr_fe_accept_input(&s->chr);
40b6f911 PC	215	}
	216	}
	217	s->ucr2 = value & 0xffff;
	218	break;
	219
	220	case 0x25: /* USR1 */
	221	value &= USR1_AWAKE \| USR1_AIRINT \| USR1_DTRD \| USR1_AGTIM \|
fa2650a3	222	USR1_FRAMERR \| USR1_ESCF \| USR1_RTSD \| USR1_PARTYER;
40b6f911 PC	223	s->usr1 &= ~value;
	224	break;
	225
	226	case 0x26: /* USR2 */
fa2650a3 JCD	227	/*
	228	* Writing 1 to some bits clears them; all other
	229	* values are ignored
	230	*/
40b6f911	231	value &= USR2_ADET \| USR2_DTRF \| USR2_IDLE \| USR2_ACST \|
fa2650a3 JCD	232	USR2_RIDELT \| USR2_IRINT \| USR2_WAKE \|
fa2650a3 JCD	233	USR2_DCDDELT \| USR2_RTSF \| USR2_BRCD \| USR2_ORE;
40b6f911 PC	234	s->usr2 &= ~value;
	235	break;
	236
fa2650a3 JCD	237	/*
	238	* Linux expects to see what it writes to these registers
	239	* We don't currently alter the baud rate
	240	*/
40b6f911 PC	241	case 0x29: /* UBIR */
	242	s->ubrc = value & 0xffff;
	243	break;
	244
	245	case 0x2a: /* UBMR */
	246	s->ubmr = value & 0xffff;
	247	break;
	248
	249	case 0x2c: /* One ms reg */
	250	s->onems = value & 0xffff;
	251	break;
	252
	253	case 0x24: /* FIFO control register */
	254	s->ufcr = value & 0xffff;
	255	break;
	256
	257	case 0x22: /* UCR3 */
	258	s->ucr3 = value & 0xffff;
	259	break;
	260
	261	case 0x2d: /* UTS1 */
	262	case 0x23: /* UCR4 */
8ccce77c JCD	263	qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
8ccce77c JCD	264	HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
40b6f911 PC	265	/* TODO */
	266	break;
	267
	268	default:
8ccce77c JCD	269	qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
8ccce77c JCD	270	HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
40b6f911 PC	271	}
	272	}
	273
	274	static int imx_can_receive(void *opaque)
	275	{
	276	IMXSerialState s = (IMXSerialState )opaque;
	277	return !(s->usr1 & USR1_RRDY);
	278	}
	279
	280	static void imx_put_data(void *opaque, uint32_t value)
	281	{
	282	IMXSerialState s = (IMXSerialState )opaque;
8ccce77c	283
40b6f911	284	DPRINTF("received char\n");
8ccce77c	285
40b6f911 PC	286	s->usr1 \|= USR1_RRDY;
	287	s->usr2 \|= USR2_RDR;
	288	s->uts1 &= ~UTS1_RXEMPTY;
	289	s->readbuff = value;
	290	imx_update(s);
	291	}
	292
	293	static void imx_receive(void opaque, const uint8_t buf, int size)
	294	{
	295	imx_put_data(opaque, *buf);
	296	}
	297
	298	static void imx_event(void *opaque, int event)
	299	{
	300	if (event == CHR_EVENT_BREAK) {
	301	imx_put_data(opaque, URXD_BRK);
	302	}
	303	}
	304
	305
	306	static const struct MemoryRegionOps imx_serial_ops = {
	307	.read = imx_serial_read,
	308	.write = imx_serial_write,
	309	.endianness = DEVICE_NATIVE_ENDIAN,
	310	};
	311
f6c64000	312	static void imx_serial_realize(DeviceState dev, Error *errp)
40b6f911	313	{
8d8e3481	314	IMXSerialState *s = IMX_SERIAL(dev);
40b6f911	315
fa394ed6 MAL	316	DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr));
	317
	318	qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive,
39ab61c6	319	imx_event, s, NULL, true);
f6c64000 JCD	320	}
	321
	322	static void imx_serial_init(Object *obj)
	323	{
	324	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
	325	IMXSerialState *s = IMX_SERIAL(obj);
40b6f911	326
f6c64000 JCD	327	memory_region_init_io(&s->iomem, obj, &imx_serial_ops, s,
	328	TYPE_IMX_SERIAL, 0x1000);
	329	sysbus_init_mmio(sbd, &s->iomem);
	330	sysbus_init_irq(sbd, &s->irq);
40b6f911 PC	331	}
40b6f911 PC	332
f6c64000	333	static Property imx_serial_properties[] = {
40b6f911 PC	334	DEFINE_PROP_CHR("chardev", IMXSerialState, chr),
	335	DEFINE_PROP_END_OF_LIST(),
	336	};
	337
	338	static void imx_serial_class_init(ObjectClass klass, void data)
	339	{
	340	DeviceClass *dc = DEVICE_CLASS(klass);
40b6f911	341
f6c64000	342	dc->realize = imx_serial_realize;
40b6f911 PC	343	dc->vmsd = &vmstate_imx_serial;
40b6f911 PC	344	dc->reset = imx_serial_reset_at_boot;
125ee0ed	345	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
40b6f911	346	dc->desc = "i.MX series UART";
f6c64000	347	dc->props = imx_serial_properties;
40b6f911 PC	348	}
40b6f911 PC	349
8c43a6f0	350	static const TypeInfo imx_serial_info = {
f6c64000 JCD	351	.name = TYPE_IMX_SERIAL,
	352	.parent = TYPE_SYS_BUS_DEVICE,
	353	.instance_size = sizeof(IMXSerialState),
	354	.instance_init = imx_serial_init,
	355	.class_init = imx_serial_class_init,
40b6f911 PC	356	};
	357
	358	static void imx_serial_register_types(void)
	359	{
	360	type_register_static(&imx_serial_info);
	361	}
	362
	363	type_init(imx_serial_register_types)