[qemu.git] / hw / slavio_intctl.c

/*
 * QEMU Sparc SLAVIO interrupt controller emulation
 * 
 * Copyright (c) 2003-2005 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"
//#define DEBUG_IRQ_COUNT
//#define DEBUG_IRQ

#ifdef DEBUG_IRQ
#define DPRINTF(fmt, args...) \
do { printf("IRQ: " fmt , ##args); } while (0)
#else
#define DPRINTF(fmt, args...)
#endif

/*
 * Registers of interrupt controller in sun4m.
 *
 * This is the interrupt controller part of chip STP2001 (Slave I/O), also
 * produced as NCR89C105. See
 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
 *
 * There is a system master controller and one for each cpu.
 * 
 */

#define MAX_CPUS 16

typedef struct SLAVIO_INTCTLState {
    uint32_t intreg_pending[MAX_CPUS];
    uint32_t intregm_pending;
    uint32_t intregm_disabled;
    uint32_t target_cpu;
#ifdef DEBUG_IRQ_COUNT
    uint64_t irq_count[32];
#endif
    CPUState *cpu_envs[MAX_CPUS];
    const uint32_t *intbit_to_level;
} SLAVIO_INTCTLState;

#define INTCTL_MAXADDR 0xf
#define INTCTLM_MAXADDR 0xf
static void slavio_check_interrupts(void *opaque);

// per-cpu interrupt controller
static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t saddr;
    int cpu;

    cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
    saddr = (addr & INTCTL_MAXADDR) >> 2;
    switch (saddr) {
    case 0:
	return s->intreg_pending[cpu];
    default:
	break;
    }
    return 0;
}

static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t saddr;
    int cpu;

    cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
    saddr = (addr & INTCTL_MAXADDR) >> 2;
    switch (saddr) {
    case 1: // clear pending softints
	if (val & 0x4000)
	    val |= 80000000;
	val &= 0xfffe0000;
	s->intreg_pending[cpu] &= ~val;
	DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
	break;
    case 2: // set softint
	val &= 0xfffe0000;
	s->intreg_pending[cpu] |= val;
        slavio_check_interrupts(s);
	DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
	break;
    default:
	break;
    }
}

static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
    slavio_intctl_mem_readl,
    slavio_intctl_mem_readl,
    slavio_intctl_mem_readl,
};

static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
    slavio_intctl_mem_writel,
    slavio_intctl_mem_writel,
    slavio_intctl_mem_writel,
};

// master system interrupt controller
static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t saddr;

    saddr = (addr & INTCTLM_MAXADDR) >> 2;
    switch (saddr) {
    case 0:
	return s->intregm_pending & 0x7fffffff;
    case 1:
	return s->intregm_disabled;
    case 4:
	return s->target_cpu;
    default:
	break;
    }
    return 0;
}

static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t saddr;

    saddr = (addr & INTCTLM_MAXADDR) >> 2;
    switch (saddr) {
    case 2: // clear (enable)
	// Force clear unused bits
	val &= ~0x4fb2007f;
	s->intregm_disabled &= ~val;
	DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
	slavio_check_interrupts(s);
	break;
    case 3: // set (disable, clear pending)
	// Force clear unused bits
	val &= ~0x4fb2007f;
	s->intregm_disabled |= val;
	s->intregm_pending &= ~val;
	DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
	break;
    case 4:
	s->target_cpu = val & (MAX_CPUS - 1);
	DPRINTF("Set master irq cpu %d\n", s->target_cpu);
	break;
    default:
	break;
    }
}

static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
    slavio_intctlm_mem_readl,
    slavio_intctlm_mem_readl,
    slavio_intctlm_mem_readl,
};

static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
    slavio_intctlm_mem_writel,
    slavio_intctlm_mem_writel,
    slavio_intctlm_mem_writel,
};

void slavio_pic_info(void *opaque)
{
    SLAVIO_INTCTLState *s = opaque;
    int i;

    for (i = 0; i < MAX_CPUS; i++) {
	term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
    }
    term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
}

void slavio_irq_info(void *opaque)
{
#ifndef DEBUG_IRQ_COUNT
    term_printf("irq statistic code not compiled.\n");
#else
    SLAVIO_INTCTLState *s = opaque;
    int i;
    int64_t count;

    term_printf("IRQ statistics:\n");
    for (i = 0; i < 32; i++) {
        count = s->irq_count[i];
        if (count > 0)
            term_printf("%2d: %" PRId64 "\n", i, count);
    }
#endif
}

static void slavio_check_interrupts(void *opaque)
{
    CPUState *env;
    SLAVIO_INTCTLState *s = opaque;
    uint32_t pending = s->intregm_pending;
    unsigned int i, j, max = 0;

    pending &= ~s->intregm_disabled;

    if (pending && !(s->intregm_disabled & 0x80000000)) {
	for (i = 0; i < 32; i++) {
	    if (pending & (1 << i)) {
		if (max < s->intbit_to_level[i])
		    max = s->intbit_to_level[i];
	    }
	}
        env = s->cpu_envs[s->target_cpu];
        if (!env) {
	    DPRINTF("No CPU %d, not triggered (pending %x)\n", s->target_cpu, pending);
        }
	else {
            if (env->halted)
                env->halted = 0;
            if (env->interrupt_index == 0) {
                DPRINTF("Triggered CPU %d pil %d\n", s->target_cpu, max);
#ifdef DEBUG_IRQ_COUNT
                s->irq_count[max]++;
#endif
                env->interrupt_index = TT_EXTINT | max;
                cpu_interrupt(env, CPU_INTERRUPT_HARD);
            }
            else
                DPRINTF("Not triggered (pending %x), pending exception %x\n", pending, env->interrupt_index);
	}
    }
    else
	DPRINTF("Not triggered (pending %x), disabled %x\n", pending, s->intregm_disabled);
    
    for (i = 0; i < MAX_CPUS; i++) {
        max = 0;
        env = s->cpu_envs[i];
        if (!env)
            continue;
        for (j = 17; j < 32; j++) {
            if (s->intreg_pending[i] & (1 << j)) {
                if (max < j - 16)
                    max = j - 16;
            }
        }
	if (max > 0) {
            if (env->halted)
                env->halted = 0;
            if (env->interrupt_index == 0) {
                DPRINTF("Triggered softint %d for cpu %d (pending %x)\n", max, i, pending);
#ifdef DEBUG_IRQ_COUNT
                s->irq_count[max]++;
#endif
                env->interrupt_index = TT_EXTINT | max;
                cpu_interrupt(env, CPU_INTERRUPT_HARD);
            }
        }
    }
}

/*
 * "irq" here is the bit number in the system interrupt register to
 * separate serial and keyboard interrupts sharing a level.
 */
void slavio_set_irq(void *opaque, int irq, int level)
{
    SLAVIO_INTCTLState *s = opaque;

    DPRINTF("Set cpu %d irq %d level %d\n", s->target_cpu, irq, level);
    if (irq < 32) {
	uint32_t mask = 1 << irq;
	uint32_t pil = s->intbit_to_level[irq];
	if (pil > 0) {
	    if (level) {
		s->intregm_pending |= mask;
		s->intreg_pending[s->target_cpu] |= 1 << pil;
		slavio_check_interrupts(s);
	    }
	    else {
		s->intregm_pending &= ~mask;
		s->intreg_pending[s->target_cpu] &= ~(1 << pil);
	    }
	}
    }
}

void pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu)
{
    SLAVIO_INTCTLState *s = opaque;

    DPRINTF("Set cpu %d local irq %d level %d\n", cpu, irq, level);
    if (cpu == (unsigned int)-1) {
        slavio_set_irq(opaque, irq, level);
        return;
    }
    if (irq < 32) {
	uint32_t pil = s->intbit_to_level[irq];
    	if (pil > 0) {
	    if (level) {
		s->intreg_pending[cpu] |= 1 << pil;
	    }
	    else {
		s->intreg_pending[cpu] &= ~(1 << pil);
	    }
	}
    }
    slavio_check_interrupts(s);
}

static void slavio_intctl_save(QEMUFile *f, void *opaque)
{
    SLAVIO_INTCTLState *s = opaque;
    int i;
    
    for (i = 0; i < MAX_CPUS; i++) {
	qemu_put_be32s(f, &s->intreg_pending[i]);
    }
    qemu_put_be32s(f, &s->intregm_pending);
    qemu_put_be32s(f, &s->intregm_disabled);
    qemu_put_be32s(f, &s->target_cpu);
}

static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
{
    SLAVIO_INTCTLState *s = opaque;
    int i;

    if (version_id != 1)
        return -EINVAL;

    for (i = 0; i < MAX_CPUS; i++) {
	qemu_get_be32s(f, &s->intreg_pending[i]);
    }
    qemu_get_be32s(f, &s->intregm_pending);
    qemu_get_be32s(f, &s->intregm_disabled);
    qemu_get_be32s(f, &s->target_cpu);
    return 0;
}

static void slavio_intctl_reset(void *opaque)
{
    SLAVIO_INTCTLState *s = opaque;
    int i;

    for (i = 0; i < MAX_CPUS; i++) {
	s->intreg_pending[i] = 0;
    }
    s->intregm_disabled = ~0xffb2007f;
    s->intregm_pending = 0;
    s->target_cpu = 0;
}

void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env)
{
    SLAVIO_INTCTLState *s = opaque;
    s->cpu_envs[cpu] = env;
}

void *slavio_intctl_init(uint32_t addr, uint32_t addrg,
                         const uint32_t *intbit_to_level,
                         qemu_irq **irq)
{
    int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
    SLAVIO_INTCTLState *s;

    s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
    if (!s)
        return NULL;

    s->intbit_to_level = intbit_to_level;
    for (i = 0; i < MAX_CPUS; i++) {
	slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
	cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_MAXADDR, slavio_intctl_io_memory);
    }

    slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
    cpu_register_physical_memory(addrg, INTCTLM_MAXADDR, slavio_intctlm_io_memory);

    register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
    qemu_register_reset(slavio_intctl_reset, s);
    *irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
    slavio_intctl_reset(s);
    return s;
}
Commit	Line	Data
e80cfcfc FB	1	/*
	2	* QEMU Sparc SLAVIO interrupt controller emulation
	3	*
66321a11	4	* Copyright (c) 2003-2005 Fabrice Bellard
e80cfcfc FB	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "vl.h"
	25	//#define DEBUG_IRQ_COUNT
66321a11 FB	26	//#define DEBUG_IRQ
	27
	28	#ifdef DEBUG_IRQ
	29	#define DPRINTF(fmt, args...) \
	30	do { printf("IRQ: " fmt , ##args); } while (0)
	31	#else
	32	#define DPRINTF(fmt, args...)
	33	#endif
e80cfcfc FB	34
	35	/*
	36	* Registers of interrupt controller in sun4m.
	37	*
	38	* This is the interrupt controller part of chip STP2001 (Slave I/O), also
	39	* produced as NCR89C105. See
	40	* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
	41	*
	42	* There is a system master controller and one for each cpu.
	43	*
	44	*/
	45
	46	#define MAX_CPUS 16
	47
	48	typedef struct SLAVIO_INTCTLState {
	49	uint32_t intreg_pending[MAX_CPUS];
	50	uint32_t intregm_pending;
	51	uint32_t intregm_disabled;
	52	uint32_t target_cpu;
	53	#ifdef DEBUG_IRQ_COUNT
	54	uint64_t irq_count[32];
	55	#endif
ba3c64fb	56	CPUState *cpu_envs[MAX_CPUS];
e0353fe2	57	const uint32_t *intbit_to_level;
e80cfcfc FB	58	} SLAVIO_INTCTLState;
	59
	60	#define INTCTL_MAXADDR 0xf
	61	#define INTCTLM_MAXADDR 0xf
66321a11	62	static void slavio_check_interrupts(void *opaque);
e80cfcfc FB	63
	64	// per-cpu interrupt controller
	65	static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
	66	{
	67	SLAVIO_INTCTLState *s = opaque;
	68	uint32_t saddr;
	69	int cpu;
	70
	71	cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
	72	saddr = (addr & INTCTL_MAXADDR) >> 2;
	73	switch (saddr) {
	74	case 0:
	75	return s->intreg_pending[cpu];
	76	default:
	77	break;
	78	}
	79	return 0;
	80	}
	81
	82	static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	83	{
	84	SLAVIO_INTCTLState *s = opaque;
	85	uint32_t saddr;
	86	int cpu;
	87
	88	cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
	89	saddr = (addr & INTCTL_MAXADDR) >> 2;
	90	switch (saddr) {
	91	case 1: // clear pending softints
	92	if (val & 0x4000)
	93	val \|= 80000000;
	94	val &= 0xfffe0000;
	95	s->intreg_pending[cpu] &= ~val;
66321a11	96	DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
e80cfcfc FB	97	break;
	98	case 2: // set softint
	99	val &= 0xfffe0000;
	100	s->intreg_pending[cpu] \|= val;
ba3c64fb	101	slavio_check_interrupts(s);
66321a11	102	DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
e80cfcfc FB	103	break;
	104	default:
	105	break;
	106	}
	107	}
	108
	109	static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
	110	slavio_intctl_mem_readl,
	111	slavio_intctl_mem_readl,
	112	slavio_intctl_mem_readl,
	113	};
	114
	115	static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
	116	slavio_intctl_mem_writel,
	117	slavio_intctl_mem_writel,
	118	slavio_intctl_mem_writel,
	119	};
	120
	121	// master system interrupt controller
	122	static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
	123	{
	124	SLAVIO_INTCTLState *s = opaque;
	125	uint32_t saddr;
	126
	127	saddr = (addr & INTCTLM_MAXADDR) >> 2;
	128	switch (saddr) {
	129	case 0:
6bae7071	130	return s->intregm_pending & 0x7fffffff;
e80cfcfc FB	131	case 1:
	132	return s->intregm_disabled;
	133	case 4:
	134	return s->target_cpu;
	135	default:
	136	break;
	137	}
	138	return 0;
	139	}
	140
	141	static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	142	{
	143	SLAVIO_INTCTLState *s = opaque;
	144	uint32_t saddr;
	145
	146	saddr = (addr & INTCTLM_MAXADDR) >> 2;
	147	switch (saddr) {
	148	case 2: // clear (enable)
6bae7071	149	// Force clear unused bits
3475187d	150	val &= ~0x4fb2007f;
e80cfcfc	151	s->intregm_disabled &= ~val;
66321a11 FB	152	DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
66321a11 FB	153	slavio_check_interrupts(s);
e80cfcfc FB	154	break;
e80cfcfc FB	155	case 3: // set (disable, clear pending)
6bae7071	156	// Force clear unused bits
3475187d	157	val &= ~0x4fb2007f;
e80cfcfc FB	158	s->intregm_disabled \|= val;
e80cfcfc FB	159	s->intregm_pending &= ~val;
66321a11	160	DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
e80cfcfc FB	161	break;
	162	case 4:
	163	s->target_cpu = val & (MAX_CPUS - 1);
66321a11	164	DPRINTF("Set master irq cpu %d\n", s->target_cpu);
e80cfcfc FB	165	break;
	166	default:
	167	break;
	168	}
	169	}
	170
	171	static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
	172	slavio_intctlm_mem_readl,
	173	slavio_intctlm_mem_readl,
	174	slavio_intctlm_mem_readl,
	175	};
	176
	177	static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
	178	slavio_intctlm_mem_writel,
	179	slavio_intctlm_mem_writel,
	180	slavio_intctlm_mem_writel,
	181	};
	182
	183	void slavio_pic_info(void *opaque)
	184	{
	185	SLAVIO_INTCTLState *s = opaque;
	186	int i;
	187
	188	for (i = 0; i < MAX_CPUS; i++) {
	189	term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
	190	}
	191	term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
	192	}
	193
	194	void slavio_irq_info(void *opaque)
	195	{
	196	#ifndef DEBUG_IRQ_COUNT
	197	term_printf("irq statistic code not compiled.\n");
	198	#else
	199	SLAVIO_INTCTLState *s = opaque;
	200	int i;
	201	int64_t count;
	202
	203	term_printf("IRQ statistics:\n");
	204	for (i = 0; i < 32; i++) {
	205	count = s->irq_count[i];
	206	if (count > 0)
26a76461	207	term_printf("%2d: %" PRId64 "\n", i, count);
e80cfcfc FB	208	}
	209	#endif
	210	}
	211
66321a11 FB	212	static void slavio_check_interrupts(void *opaque)
66321a11 FB	213	{
c68ea704	214	CPUState *env;
66321a11 FB	215	SLAVIO_INTCTLState *s = opaque;
66321a11 FB	216	uint32_t pending = s->intregm_pending;
ba3c64fb	217	unsigned int i, j, max = 0;
66321a11 FB	218
	219	pending &= ~s->intregm_disabled;
	220
	221	if (pending && !(s->intregm_disabled & 0x80000000)) {
	222	for (i = 0; i < 32; i++) {
	223	if (pending & (1 << i)) {
e0353fe2 BS	224	if (max < s->intbit_to_level[i])
e0353fe2 BS	225	max = s->intbit_to_level[i];
66321a11 FB	226	}
66321a11 FB	227	}
ba3c64fb FB	228	env = s->cpu_envs[s->target_cpu];
	229	if (!env) {
	230	DPRINTF("No CPU %d, not triggered (pending %x)\n", s->target_cpu, pending);
	231	}
	232	else {
	233	if (env->halted)
	234	env->halted = 0;
	235	if (env->interrupt_index == 0) {
	236	DPRINTF("Triggered CPU %d pil %d\n", s->target_cpu, max);
66321a11	237	#ifdef DEBUG_IRQ_COUNT
ba3c64fb	238	s->irq_count[max]++;
66321a11	239	#endif
ba3c64fb FB	240	env->interrupt_index = TT_EXTINT \| max;
	241	cpu_interrupt(env, CPU_INTERRUPT_HARD);
	242	}
	243	else
	244	DPRINTF("Not triggered (pending %x), pending exception %x\n", pending, env->interrupt_index);
66321a11	245	}
66321a11 FB	246	}
	247	else
	248	DPRINTF("Not triggered (pending %x), disabled %x\n", pending, s->intregm_disabled);
ba3c64fb FB	249
	250	for (i = 0; i < MAX_CPUS; i++) {
	251	max = 0;
	252	env = s->cpu_envs[i];
	253	if (!env)
	254	continue;
	255	for (j = 17; j < 32; j++) {
	256	if (s->intreg_pending[i] & (1 << j)) {
	257	if (max < j - 16)
	258	max = j - 16;
	259	}
	260	}
	261	if (max > 0) {
	262	if (env->halted)
	263	env->halted = 0;
	264	if (env->interrupt_index == 0) {
	265	DPRINTF("Triggered softint %d for cpu %d (pending %x)\n", max, i, pending);
	266	#ifdef DEBUG_IRQ_COUNT
	267	s->irq_count[max]++;
	268	#endif
	269	env->interrupt_index = TT_EXTINT \| max;
	270	cpu_interrupt(env, CPU_INTERRUPT_HARD);
	271	}
	272	}
	273	}
66321a11 FB	274	}
66321a11 FB	275
e80cfcfc FB	276	/*
	277	* "irq" here is the bit number in the system interrupt register to
	278	* separate serial and keyboard interrupts sharing a level.
	279	*/
d537cf6c	280	void slavio_set_irq(void *opaque, int irq, int level)
e80cfcfc FB	281	{
	282	SLAVIO_INTCTLState *s = opaque;
	283
ba3c64fb	284	DPRINTF("Set cpu %d irq %d level %d\n", s->target_cpu, irq, level);
e80cfcfc FB	285	if (irq < 32) {
e80cfcfc FB	286	uint32_t mask = 1 << irq;
e0353fe2	287	uint32_t pil = s->intbit_to_level[irq];
e80cfcfc FB	288	if (pil > 0) {
	289	if (level) {
	290	s->intregm_pending \|= mask;
	291	s->intreg_pending[s->target_cpu] \|= 1 << pil;
491730f3	292	slavio_check_interrupts(s);
e80cfcfc FB	293	}
	294	else {
	295	s->intregm_pending &= ~mask;
	296	s->intreg_pending[s->target_cpu] &= ~(1 << pil);
	297	}
e80cfcfc FB	298	}
	299	}
	300	}
	301
52cc07d0	302	void pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu)
ba3c64fb FB	303	{
	304	SLAVIO_INTCTLState *s = opaque;
	305
	306	DPRINTF("Set cpu %d local irq %d level %d\n", cpu, irq, level);
	307	if (cpu == (unsigned int)-1) {
d537cf6c	308	slavio_set_irq(opaque, irq, level);
ba3c64fb FB	309	return;
	310	}
	311	if (irq < 32) {
e0353fe2	312	uint32_t pil = s->intbit_to_level[irq];
ba3c64fb FB	313	if (pil > 0) {
	314	if (level) {
	315	s->intreg_pending[cpu] \|= 1 << pil;
	316	}
	317	else {
	318	s->intreg_pending[cpu] &= ~(1 << pil);
	319	}
	320	}
	321	}
	322	slavio_check_interrupts(s);
	323	}
	324
e80cfcfc FB	325	static void slavio_intctl_save(QEMUFile f, void opaque)
	326	{
	327	SLAVIO_INTCTLState *s = opaque;
	328	int i;
	329
	330	for (i = 0; i < MAX_CPUS; i++) {
	331	qemu_put_be32s(f, &s->intreg_pending[i]);
	332	}
	333	qemu_put_be32s(f, &s->intregm_pending);
	334	qemu_put_be32s(f, &s->intregm_disabled);
	335	qemu_put_be32s(f, &s->target_cpu);
	336	}
	337
	338	static int slavio_intctl_load(QEMUFile f, void opaque, int version_id)
	339	{
	340	SLAVIO_INTCTLState *s = opaque;
	341	int i;
	342
	343	if (version_id != 1)
	344	return -EINVAL;
	345
	346	for (i = 0; i < MAX_CPUS; i++) {
	347	qemu_get_be32s(f, &s->intreg_pending[i]);
	348	}
	349	qemu_get_be32s(f, &s->intregm_pending);
	350	qemu_get_be32s(f, &s->intregm_disabled);
	351	qemu_get_be32s(f, &s->target_cpu);
	352	return 0;
	353	}
	354
	355	static void slavio_intctl_reset(void *opaque)
	356	{
	357	SLAVIO_INTCTLState *s = opaque;
	358	int i;
	359
	360	for (i = 0; i < MAX_CPUS; i++) {
	361	s->intreg_pending[i] = 0;
	362	}
6bae7071	363	s->intregm_disabled = ~0xffb2007f;
e80cfcfc FB	364	s->intregm_pending = 0;
	365	s->target_cpu = 0;
	366	}
	367
ba3c64fb FB	368	void slavio_intctl_set_cpu(void opaque, unsigned int cpu, CPUState env)
	369	{
	370	SLAVIO_INTCTLState *s = opaque;
	371	s->cpu_envs[cpu] = env;
	372	}
	373
e0353fe2	374	void *slavio_intctl_init(uint32_t addr, uint32_t addrg,
d537cf6c PB	375	const uint32_t *intbit_to_level,
d537cf6c PB	376	qemu_irq **irq)
e80cfcfc FB	377	{
	378	int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
	379	SLAVIO_INTCTLState *s;
	380
	381	s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
	382	if (!s)
	383	return NULL;
	384
e0353fe2	385	s->intbit_to_level = intbit_to_level;
e80cfcfc FB	386	for (i = 0; i < MAX_CPUS; i++) {
	387	slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
	388	cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_MAXADDR, slavio_intctl_io_memory);
	389	}
	390
	391	slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
	392	cpu_register_physical_memory(addrg, INTCTLM_MAXADDR, slavio_intctlm_io_memory);
	393
	394	register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
	395	qemu_register_reset(slavio_intctl_reset, s);
d537cf6c	396	*irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
e80cfcfc FB	397	slavio_intctl_reset(s);
	398	return s;
	399	}
	400