[qemu.git] / hw / parallel.c

/*
 * QEMU Parallel PORT emulation
 * 
 * Copyright (c) 2003-2005 Fabrice Bellard
 * Copyright (c) 2007 Marko Kohtala
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

//#define DEBUG_PARALLEL

#ifdef DEBUG_PARALLEL
#define pdebug(fmt, arg...) printf("pp: " fmt, ##arg)
#else
#define pdebug(fmt, arg...) ((void)0)
#endif

#define PARA_REG_DATA 0
#define PARA_REG_STS 1
#define PARA_REG_CTR 2
#define PARA_REG_EPP_ADDR 3
#define PARA_REG_EPP_DATA 4

/*
 * These are the definitions for the Printer Status Register
 */
#define PARA_STS_BUSY	0x80	/* Busy complement */
#define PARA_STS_ACK	0x40	/* Acknowledge */
#define PARA_STS_PAPER	0x20	/* Out of paper */
#define PARA_STS_ONLINE	0x10	/* Online */
#define PARA_STS_ERROR	0x08	/* Error complement */
#define PARA_STS_TMOUT	0x01	/* EPP timeout */

/*
 * These are the definitions for the Printer Control Register
 */
#define PARA_CTR_DIR	0x20	/* Direction (1=read, 0=write) */
#define PARA_CTR_INTEN	0x10	/* IRQ Enable */
#define PARA_CTR_SELECT	0x08	/* Select In complement */
#define PARA_CTR_INIT	0x04	/* Initialize Printer complement */
#define PARA_CTR_AUTOLF	0x02	/* Auto linefeed complement */
#define PARA_CTR_STROBE	0x01	/* Strobe complement */

#define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)

struct ParallelState {
    uint8_t dataw;
    uint8_t datar;
    uint8_t status;
    uint8_t control;
    qemu_irq irq;
    int irq_pending;
    CharDriverState *chr;
    int hw_driver;
    int epp_timeout;
    uint32_t last_read_offset; /* For debugging */
};

static void parallel_update_irq(ParallelState *s)
{
    if (s->irq_pending)
        qemu_irq_raise(s->irq);
    else
        qemu_irq_lower(s->irq);
}

static void
parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    
    pdebug("write addr=0x%02x val=0x%02x\n", addr, val);

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
	s->dataw = val;
	parallel_update_irq(s);
        break;
    case PARA_REG_CTR:
	if ((val & PARA_CTR_INIT) == 0 ) {
	    s->status = PARA_STS_BUSY;
	    s->status |= PARA_STS_ACK;
	    s->status |= PARA_STS_ONLINE;
	    s->status |= PARA_STS_ERROR;
	}
	else if (val & PARA_CTR_SELECT) {
	    if (val & PARA_CTR_STROBE) {
		s->status &= ~PARA_STS_BUSY;
		if ((s->control & PARA_CTR_STROBE) == 0)
		    qemu_chr_write(s->chr, &s->dataw, 1);
	    } else {
		if (s->control & PARA_CTR_INTEN) {
		    s->irq_pending = 1;
		}
	    }
	}
	parallel_update_irq(s);
	s->control = val;
        break;
    }
}

static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint8_t parm = val;

    /* Sometimes programs do several writes for timing purposes on old
       HW. Take care not to waste time on writes that do nothing. */

    s->last_read_offset = ~0U;

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        if (s->dataw == val)
	    return;
	pdebug("wd%02x\n", val);
	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
	s->dataw = val;
        break;
    case PARA_REG_STS:
	pdebug("ws%02x\n", val);
	if (val & PARA_STS_TMOUT)
	    s->epp_timeout = 0;
	break;
    case PARA_REG_CTR:
        val |= 0xc0;
        if (s->control == val)
	    return;
	pdebug("wc%02x\n", val);
	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
	s->control = val;
        break;
    case PARA_REG_EPP_ADDR:
	if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
	    /* Controls not correct for EPP address cycle, so do nothing */
	    pdebug("wa%02x s\n", val);
	else {
	    struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
	    if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
		s->epp_timeout = 1;
		pdebug("wa%02x t\n", val);
	    }
	    else
		pdebug("wa%02x\n", val);
	}
	break;
    case PARA_REG_EPP_DATA:
	if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
	    /* Controls not correct for EPP data cycle, so do nothing */
	    pdebug("we%02x s\n", val);
	else {
	    struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
	    if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
		s->epp_timeout = 1;
		pdebug("we%02x t\n", val);
	    }
	    else
		pdebug("we%02x\n", val);
	}
	break;
    }
}

static void
parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint16_t eppdata = cpu_to_le16(val);
    int err;
    struct ParallelIOArg ioarg = {
	.buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
	/* Controls not correct for EPP data cycle, so do nothing */
	pdebug("we%04x s\n", val);
	return;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
    if (err) {
	s->epp_timeout = 1;
	pdebug("we%04x t\n", val);
    }
    else
	pdebug("we%04x\n", val);
}

static void
parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint32_t eppdata = cpu_to_le32(val);
    int err;
    struct ParallelIOArg ioarg = {
	.buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
	/* Controls not correct for EPP data cycle, so do nothing */
	pdebug("we%08x s\n", val);
	return;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
    if (err) {
	s->epp_timeout = 1;
	pdebug("we%08x t\n", val);
    }
    else
	pdebug("we%08x\n", val);
}

static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret = 0xff;

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
	if (s->control & PARA_CTR_DIR)
	    ret = s->datar;
	else
	    ret = s->dataw;
        break;
    case PARA_REG_STS:
	ret = s->status;
	s->irq_pending = 0;
	if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
	    /* XXX Fixme: wait 5 microseconds */
	    if (s->status & PARA_STS_ACK)
		s->status &= ~PARA_STS_ACK;
	    else {
		/* XXX Fixme: wait 5 microseconds */
		s->status |= PARA_STS_ACK;
		s->status |= PARA_STS_BUSY;
	    }
	}
	parallel_update_irq(s);
        break;
    case PARA_REG_CTR:
        ret = s->control;
        break;
    }
    pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
    return ret;
}

static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint8_t ret = 0xff;
    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
	if (s->last_read_offset != addr || s->datar != ret)
	    pdebug("rd%02x\n", ret);
        s->datar = ret;
        break;
    case PARA_REG_STS:
	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
	ret &= ~PARA_STS_TMOUT;
	if (s->epp_timeout)
	    ret |= PARA_STS_TMOUT;
	if (s->last_read_offset != addr || s->status != ret)
	    pdebug("rs%02x\n", ret);
	s->status = ret;
        break;
    case PARA_REG_CTR:
        /* s->control has some bits fixed to 1. It is zero only when
	   it has not been yet written to.  */
	if (s->control == 0) {
	    qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
	    if (s->last_read_offset != addr)
		pdebug("rc%02x\n", ret);
	    s->control = ret;
	}
	else {
	    ret = s->control;
	    if (s->last_read_offset != addr)
		pdebug("rc%02x\n", ret);
	}
        break;
    case PARA_REG_EPP_ADDR:
	if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
	    /* Controls not correct for EPP addr cycle, so do nothing */
	    pdebug("ra%02x s\n", ret);
	else {
	    struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
	    if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
		s->epp_timeout = 1;
		pdebug("ra%02x t\n", ret);
	    }
	    else
		pdebug("ra%02x\n", ret);
	}
	break;
    case PARA_REG_EPP_DATA:
	if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
	    /* Controls not correct for EPP data cycle, so do nothing */
	    pdebug("re%02x s\n", ret);
	else {
	    struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
	    if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
		s->epp_timeout = 1;
		pdebug("re%02x t\n", ret);
	    }
	    else
		pdebug("re%02x\n", ret);
	}
	break;
    }
    s->last_read_offset = addr;
    return ret;
}

static uint32_t
parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret;
    uint16_t eppdata = ~0;
    int err;
    struct ParallelIOArg ioarg = {
	.buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
	/* Controls not correct for EPP data cycle, so do nothing */
	pdebug("re%04x s\n", eppdata);
	return eppdata;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
    ret = le16_to_cpu(eppdata);

    if (err) {
	s->epp_timeout = 1;
	pdebug("re%04x t\n", ret);
    }
    else
	pdebug("re%04x\n", ret);
    return ret;
}

static uint32_t
parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret;
    uint32_t eppdata = ~0U;
    int err;
    struct ParallelIOArg ioarg = {
	.buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
	/* Controls not correct for EPP data cycle, so do nothing */
	pdebug("re%08x s\n", eppdata);
	return eppdata;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
    ret = le32_to_cpu(eppdata);

    if (err) {
	s->epp_timeout = 1;
	pdebug("re%08x t\n", ret);
    }
    else
	pdebug("re%08x\n", ret);
    return ret;
}

static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
{
    addr &= 7;
    pdebug("wecp%d=%02x\n", addr, val);
}

static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
{
    uint8_t ret = 0xff;
    addr &= 7;
    pdebug("recp%d:%02x\n", addr, ret);
    return ret;
}

/* If fd is zero, it means that the parallel device uses the console */
ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
{
    ParallelState *s;
    uint8_t dummy;

    s = qemu_mallocz(sizeof(ParallelState));
    if (!s)
        return NULL;
    s->datar = ~0;
    s->dataw = ~0;
    s->status = PARA_STS_BUSY;
    s->status |= PARA_STS_ACK;
    s->status |= PARA_STS_ONLINE;
    s->status |= PARA_STS_ERROR;
    s->control = PARA_CTR_SELECT;
    s->control |= PARA_CTR_INIT;
    s->irq = irq;
    s->irq_pending = 0;
    s->chr = chr;
    s->hw_driver = 0;
    s->epp_timeout = 0;
    s->last_read_offset = ~0U;

    if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
        s->hw_driver = 1;
	s->status = dummy;
    }

    if (s->hw_driver) {
	register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
	register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
	register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
	register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
	register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
	register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
	register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
	register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
    }
    else {
	register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
	register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
    }
    return s;
}
Commit	Line	Data
6508fe59 FB	1	/*
	2	* QEMU Parallel PORT emulation
	3	*
e57a8c0e	4	* Copyright (c) 2003-2005 Fabrice Bellard
5867c88a	5	* Copyright (c) 2007 Marko Kohtala
6508fe59 FB	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25	#include "vl.h"
	26
	27	//#define DEBUG_PARALLEL
	28
5867c88a TS	29	#ifdef DEBUG_PARALLEL
	30	#define pdebug(fmt, arg...) printf("pp: " fmt, ##arg)
	31	#else
	32	#define pdebug(fmt, arg...) ((void)0)
	33	#endif
	34
	35	#define PARA_REG_DATA 0
	36	#define PARA_REG_STS 1
	37	#define PARA_REG_CTR 2
	38	#define PARA_REG_EPP_ADDR 3
	39	#define PARA_REG_EPP_DATA 4
	40
6508fe59 FB	41	/*
	42	* These are the definitions for the Printer Status Register
	43	*/
	44	#define PARA_STS_BUSY 0x80 /* Busy complement */
	45	#define PARA_STS_ACK 0x40 /* Acknowledge */
	46	#define PARA_STS_PAPER 0x20 /* Out of paper */
	47	#define PARA_STS_ONLINE 0x10 /* Online */
	48	#define PARA_STS_ERROR 0x08 /* Error complement */
5867c88a	49	#define PARA_STS_TMOUT 0x01 /* EPP timeout */
6508fe59 FB	50
	51	/*
	52	* These are the definitions for the Printer Control Register
	53	*/
5867c88a	54	#define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */
6508fe59 FB	55	#define PARA_CTR_INTEN 0x10 /* IRQ Enable */
	56	#define PARA_CTR_SELECT 0x08 /* Select In complement */
	57	#define PARA_CTR_INIT 0x04 /* Initialize Printer complement */
	58	#define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */
	59	#define PARA_CTR_STROBE 0x01 /* Strobe complement */
	60
5867c88a TS	61	#define PARA_CTR_SIGNAL (PARA_CTR_SELECT\|PARA_CTR_INIT\|PARA_CTR_AUTOLF\|PARA_CTR_STROBE)
5867c88a TS	62
6508fe59	63	struct ParallelState {
5867c88a TS	64	uint8_t dataw;
	65	uint8_t datar;
	66	uint8_t status;
6508fe59	67	uint8_t control;
d537cf6c	68	qemu_irq irq;
6508fe59 FB	69	int irq_pending;
6508fe59 FB	70	CharDriverState *chr;
e57a8c0e	71	int hw_driver;
5867c88a TS	72	int epp_timeout;
5867c88a TS	73	uint32_t last_read_offset; /* For debugging */
6508fe59 FB	74	};
	75
	76	static void parallel_update_irq(ParallelState *s)
	77	{
	78	if (s->irq_pending)
d537cf6c	79	qemu_irq_raise(s->irq);
6508fe59	80	else
d537cf6c	81	qemu_irq_lower(s->irq);
6508fe59 FB	82	}
6508fe59 FB	83
5867c88a TS	84	static void
5867c88a TS	85	parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
6508fe59 FB	86	{
	87	ParallelState *s = opaque;
	88
5867c88a TS	89	pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
	90
	91	addr &= 7;
	92	switch(addr) {
	93	case PARA_REG_DATA:
	94	s->dataw = val;
	95	parallel_update_irq(s);
	96	break;
	97	case PARA_REG_CTR:
	98	if ((val & PARA_CTR_INIT) == 0 ) {
	99	s->status = PARA_STS_BUSY;
	100	s->status \|= PARA_STS_ACK;
	101	s->status \|= PARA_STS_ONLINE;
	102	s->status \|= PARA_STS_ERROR;
	103	}
	104	else if (val & PARA_CTR_SELECT) {
	105	if (val & PARA_CTR_STROBE) {
	106	s->status &= ~PARA_STS_BUSY;
	107	if ((s->control & PARA_CTR_STROBE) == 0)
	108	qemu_chr_write(s->chr, &s->dataw, 1);
	109	} else {
	110	if (s->control & PARA_CTR_INTEN) {
	111	s->irq_pending = 1;
	112	}
	113	}
	114	}
	115	parallel_update_irq(s);
	116	s->control = val;
	117	break;
	118	}
	119	}
	120
	121	static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
	122	{
	123	ParallelState *s = opaque;
	124	uint8_t parm = val;
	125
	126	/* Sometimes programs do several writes for timing purposes on old
	127	HW. Take care not to waste time on writes that do nothing. */
	128
	129	s->last_read_offset = ~0U;
	130
6508fe59	131	addr &= 7;
6508fe59	132	switch(addr) {
5867c88a TS	133	case PARA_REG_DATA:
	134	if (s->dataw == val)
	135	return;
	136	pdebug("wd%02x\n", val);
	137	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
	138	s->dataw = val;
6508fe59	139	break;
5867c88a TS	140	case PARA_REG_STS:
	141	pdebug("ws%02x\n", val);
	142	if (val & PARA_STS_TMOUT)
	143	s->epp_timeout = 0;
	144	break;
	145	case PARA_REG_CTR:
	146	val \|= 0xc0;
	147	if (s->control == val)
	148	return;
	149	pdebug("wc%02x\n", val);
	150	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
	151	s->control = val;
6508fe59	152	break;
5867c88a TS	153	case PARA_REG_EPP_ADDR:
	154	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
	155	/* Controls not correct for EPP address cycle, so do nothing */
	156	pdebug("wa%02x s\n", val);
	157	else {
	158	struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
	159	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
	160	s->epp_timeout = 1;
	161	pdebug("wa%02x t\n", val);
	162	}
	163	else
	164	pdebug("wa%02x\n", val);
	165	}
	166	break;
	167	case PARA_REG_EPP_DATA:
	168	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
	169	/* Controls not correct for EPP data cycle, so do nothing */
	170	pdebug("we%02x s\n", val);
	171	else {
	172	struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
	173	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
	174	s->epp_timeout = 1;
	175	pdebug("we%02x t\n", val);
	176	}
	177	else
	178	pdebug("we%02x\n", val);
	179	}
	180	break;
	181	}
	182	}
	183
	184	static void
	185	parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
	186	{
	187	ParallelState *s = opaque;
	188	uint16_t eppdata = cpu_to_le16(val);
	189	int err;
	190	struct ParallelIOArg ioarg = {
	191	.buffer = &eppdata, .count = sizeof(eppdata)
	192	};
	193	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
	194	/* Controls not correct for EPP data cycle, so do nothing */
	195	pdebug("we%04x s\n", val);
	196	return;
	197	}
	198	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
	199	if (err) {
	200	s->epp_timeout = 1;
	201	pdebug("we%04x t\n", val);
	202	}
	203	else
	204	pdebug("we%04x\n", val);
	205	}
	206
	207	static void
	208	parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
	209	{
	210	ParallelState *s = opaque;
	211	uint32_t eppdata = cpu_to_le32(val);
	212	int err;
	213	struct ParallelIOArg ioarg = {
	214	.buffer = &eppdata, .count = sizeof(eppdata)
	215	};
	216	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
217	/* Controls not correct for EPP data cycle, so do nothing */
218	pdebug("we%08x s\n", val);
219	return;
220	}
221	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
222	if (err) {
223	s->epp_timeout = 1;
224	pdebug("we%08x t\n", val);
6508fe59	225	}
5867c88a TS	226	else
5867c88a TS	227	pdebug("we%08x\n", val);
6508fe59 FB	228	}
6508fe59 FB	229
5867c88a	230	static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
6508fe59 FB	231	{
	232	ParallelState *s = opaque;
	233	uint32_t ret = 0xff;
	234
	235	addr &= 7;
	236	switch(addr) {
5867c88a TS	237	case PARA_REG_DATA:
	238	if (s->control & PARA_CTR_DIR)
	239	ret = s->datar;
	240	else
	241	ret = s->dataw;
6508fe59	242	break;
5867c88a TS	243	case PARA_REG_STS:
	244	ret = s->status;
	245	s->irq_pending = 0;
	246	if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
	247	/* XXX Fixme: wait 5 microseconds */
	248	if (s->status & PARA_STS_ACK)
	249	s->status &= ~PARA_STS_ACK;
	250	else {
	251	/* XXX Fixme: wait 5 microseconds */
	252	s->status \|= PARA_STS_ACK;
	253	s->status \|= PARA_STS_BUSY;
	254	}
	255	}
	256	parallel_update_irq(s);
6508fe59	257	break;
5867c88a	258	case PARA_REG_CTR:
6508fe59 FB	259	ret = s->control;
	260	break;
	261	}
5867c88a TS	262	pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
	263	return ret;
	264	}
	265
	266	static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
	267	{
	268	ParallelState *s = opaque;
	269	uint8_t ret = 0xff;
	270	addr &= 7;
	271	switch(addr) {
	272	case PARA_REG_DATA:
	273	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
	274	if (s->last_read_offset != addr \|\| s->datar != ret)
	275	pdebug("rd%02x\n", ret);
	276	s->datar = ret;
	277	break;
	278	case PARA_REG_STS:
	279	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
	280	ret &= ~PARA_STS_TMOUT;
	281	if (s->epp_timeout)
	282	ret \|= PARA_STS_TMOUT;
	283	if (s->last_read_offset != addr \|\| s->status != ret)
	284	pdebug("rs%02x\n", ret);
	285	s->status = ret;
	286	break;
	287	case PARA_REG_CTR:
	288	/* s->control has some bits fixed to 1. It is zero only when
	289	it has not been yet written to. */
	290	if (s->control == 0) {
	291	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
	292	if (s->last_read_offset != addr)
	293	pdebug("rc%02x\n", ret);
	294	s->control = ret;
	295	}
	296	else {
	297	ret = s->control;
	298	if (s->last_read_offset != addr)
	299	pdebug("rc%02x\n", ret);
	300	}
	301	break;
	302	case PARA_REG_EPP_ADDR:
	303	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT))
	304	/* Controls not correct for EPP addr cycle, so do nothing */
	305	pdebug("ra%02x s\n", ret);
	306	else {
	307	struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
	308	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
	309	s->epp_timeout = 1;
	310	pdebug("ra%02x t\n", ret);
	311	}
	312	else
	313	pdebug("ra%02x\n", ret);
	314	}
	315	break;
	316	case PARA_REG_EPP_DATA:
	317	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT))
	318	/* Controls not correct for EPP data cycle, so do nothing */
	319	pdebug("re%02x s\n", ret);
	320	else {
	321	struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
	322	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
	323	s->epp_timeout = 1;
	324	pdebug("re%02x t\n", ret);
	325	}
326	else
327	pdebug("re%02x\n", ret);
328	}
329	break;
330	}
331	s->last_read_offset = addr;
332	return ret;
333	}
334
335	static uint32_t
336	parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
337	{
338	ParallelState *s = opaque;
339	uint32_t ret;
340	uint16_t eppdata = ~0;
341	int err;
342	struct ParallelIOArg ioarg = {
343	.buffer = &eppdata, .count = sizeof(eppdata)
344	};
345	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT)) {
346	/* Controls not correct for EPP data cycle, so do nothing */
347	pdebug("re%04x s\n", eppdata);
348	return eppdata;
349	}
350	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
351	ret = le16_to_cpu(eppdata);
352
353	if (err) {
354	s->epp_timeout = 1;
355	pdebug("re%04x t\n", ret);
356	}
357	else
358	pdebug("re%04x\n", ret);
359	return ret;
360	}
361
362	static uint32_t
363	parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
364	{
365	ParallelState *s = opaque;
366	uint32_t ret;
367	uint32_t eppdata = ~0U;
368	int err;
369	struct ParallelIOArg ioarg = {
370	.buffer = &eppdata, .count = sizeof(eppdata)
371	};
372	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT)) {
373	/* Controls not correct for EPP data cycle, so do nothing */
374	pdebug("re%08x s\n", eppdata);
375	return eppdata;
376	}
377	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
378	ret = le32_to_cpu(eppdata);
379
380	if (err) {
381	s->epp_timeout = 1;
382	pdebug("re%08x t\n", ret);
383	}
384	else
385	pdebug("re%08x\n", ret);
386	return ret;
387	}
388
389	static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
390	{
391	addr &= 7;
392	pdebug("wecp%d=%02x\n", addr, val);
393	}
394
395	static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
396	{
397	uint8_t ret = 0xff;
398	addr &= 7;
399	pdebug("recp%d:%02x\n", addr, ret);
6508fe59 FB	400	return ret;
	401	}
	402
6508fe59	403	/* If fd is zero, it means that the parallel device uses the console */
d537cf6c	404	ParallelState parallel_init(int base, qemu_irq irq, CharDriverState chr)
6508fe59 FB	405	{
6508fe59 FB	406	ParallelState *s;
e57a8c0e	407	uint8_t dummy;
6508fe59 FB	408
	409	s = qemu_mallocz(sizeof(ParallelState));
	410	if (!s)
	411	return NULL;
5867c88a TS	412	s->datar = ~0;
5867c88a TS	413	s->dataw = ~0;
6508fe59 FB	414	s->status = PARA_STS_BUSY;
	415	s->status \|= PARA_STS_ACK;
	416	s->status \|= PARA_STS_ONLINE;
	417	s->status \|= PARA_STS_ERROR;
	418	s->control = PARA_CTR_SELECT;
	419	s->control \|= PARA_CTR_INIT;
5867c88a TS	420	s->irq = irq;
	421	s->irq_pending = 0;
	422	s->chr = chr;
	423	s->hw_driver = 0;
	424	s->epp_timeout = 0;
	425	s->last_read_offset = ~0U;
6508fe59	426
5867c88a TS	427	if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
	428	s->hw_driver = 1;
	429	s->status = dummy;
	430	}
	431
	432	if (s->hw_driver) {
	433	register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
	434	register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
	435	register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
	436	register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
	437	register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
	438	register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
	439	register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
	440	register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
	441	}
	442	else {
	443	register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
	444	register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
	445	}
6508fe59 FB	446	return s;
6508fe59 FB	447	}