[qemu.git] / hw / hppa / lasi.c

/*
 * HP-PARISC Lasi chipset emulation.
 *
 * (C) 2019 by Helge Deller <[email protected]>
 *
 * This work is licensed under the GNU GPL license version 2 or later.
 *
 * Documentation available at:
 * https://parisc.wiki.kernel.org/images-parisc/7/79/Lasi_ers.pdf
 */

#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "cpu.h"
#include "trace.h"
#include "hw/hw.h"
#include "hw/irq.h"
#include "sysemu/sysemu.h"
#include "sysemu/runstate.h"
#include "hppa_sys.h"
#include "hw/net/lasi_82596.h"
#include "hw/char/parallel.h"
#include "hw/char/serial.h"
#include "hw/input/lasips2.h"
#include "exec/address-spaces.h"
#include "migration/vmstate.h"

#define TYPE_LASI_CHIP "lasi-chip"

#define LASI_IRR        0x00    /* RO */
#define LASI_IMR        0x04
#define LASI_IPR        0x08
#define LASI_ICR        0x0c
#define LASI_IAR        0x10

#define LASI_PCR        0x0C000 /* LASI Power Control register */
#define LASI_ERRLOG     0x0C004 /* LASI Error Logging register */
#define LASI_VER        0x0C008 /* LASI Version Control register */
#define LASI_IORESET    0x0C00C /* LASI I/O Reset register */
#define LASI_AMR        0x0C010 /* LASI Arbitration Mask register */
#define LASI_IO_CONF    0x7FFFE /* LASI primary configuration register */
#define LASI_IO_CONF2   0x7FFFF /* LASI secondary configuration register */

#define LASI_BIT(x)     (1ul << (x))
#define LASI_IRQ_BITS   (LASI_BIT(5) | LASI_BIT(7) | LASI_BIT(8) | LASI_BIT(9) \
            | LASI_BIT(13) | LASI_BIT(14) | LASI_BIT(16) | LASI_BIT(17) \
            | LASI_BIT(18) | LASI_BIT(19) | LASI_BIT(20) | LASI_BIT(21) \
            | LASI_BIT(26))

#define ICR_BUS_ERROR_BIT  LASI_BIT(8)  /* bit 8 in ICR */
#define ICR_TOC_BIT        LASI_BIT(1)  /* bit 1 in ICR */

#define LASI_CHIP(obj) \
    OBJECT_CHECK(LasiState, (obj), TYPE_LASI_CHIP)

#define LASI_RTC_HPA    (LASI_HPA + 0x9000)

typedef struct LasiState {
    PCIHostState parent_obj;

    uint32_t irr;
    uint32_t imr;
    uint32_t ipr;
    uint32_t icr;
    uint32_t iar;

    uint32_t errlog;
    uint32_t amr;
    uint32_t rtc;
    time_t rtc_ref;

    MemoryRegion this_mem;
} LasiState;

static bool lasi_chip_mem_valid(void *opaque, hwaddr addr,
                                unsigned size, bool is_write,
                                MemTxAttrs attrs)
{
    bool ret = false;

    switch (addr) {
    case LASI_IRR:
    case LASI_IMR:
    case LASI_IPR:
    case LASI_ICR:
    case LASI_IAR:

    case (LASI_LAN_HPA - LASI_HPA):
    case (LASI_LPT_HPA - LASI_HPA):
    case (LASI_UART_HPA - LASI_HPA):
    case (LASI_RTC_HPA - LASI_HPA):

    case LASI_PCR ... LASI_AMR:
        ret = true;
    }

    trace_lasi_chip_mem_valid(addr, ret);
    return ret;
}

static MemTxResult lasi_chip_read_with_attrs(void *opaque, hwaddr addr,
                                             uint64_t *data, unsigned size,
                                             MemTxAttrs attrs)
{
    LasiState *s = opaque;
    MemTxResult ret = MEMTX_OK;
    uint32_t val;

    switch (addr) {
    case LASI_IRR:
        val = s->irr;
        break;
    case LASI_IMR:
        val = s->imr;
        break;
    case LASI_IPR:
        val = s->ipr;
        /* Any read to IPR clears the register.  */
        s->ipr = 0;
        break;
    case LASI_ICR:
        val = s->icr & ICR_BUS_ERROR_BIT; /* bus_error */
        break;
    case LASI_IAR:
        val = s->iar;
        break;

    case (LASI_LAN_HPA - LASI_HPA):
    case (LASI_LPT_HPA - LASI_HPA):
    case (LASI_UART_HPA - LASI_HPA):
        val = 0;
        break;
    case (LASI_RTC_HPA - LASI_HPA):
        val = time(NULL);
        val += s->rtc_ref;
        break;

    case LASI_PCR:
    case LASI_VER:      /* only version 0 existed. */
    case LASI_IORESET:
        val = 0;
        break;
    case LASI_ERRLOG:
        val = s->errlog;
        break;
    case LASI_AMR:
        val = s->amr;
        break;

    default:
        /* Controlled by lasi_chip_mem_valid above. */
        g_assert_not_reached();
    }

    trace_lasi_chip_read(addr, val);

    *data = val;
    return ret;
}

static MemTxResult lasi_chip_write_with_attrs(void *opaque, hwaddr addr,
                                              uint64_t val, unsigned size,
                                              MemTxAttrs attrs)
{
    LasiState *s = opaque;

    trace_lasi_chip_write(addr, val);

    switch (addr) {
    case LASI_IRR:
        /* read-only.  */
        break;
    case LASI_IMR:
        s->imr = val;  /* 0x20 ?? */
        assert((val & LASI_IRQ_BITS) == val);
        break;
    case LASI_IPR:
        /* Any write to IPR clears the register. */
        s->ipr = 0;
        break;
    case LASI_ICR:
        s->icr = val;
        /* if (val & ICR_TOC_BIT) issue_toc(); */
        break;
    case LASI_IAR:
        s->iar = val;
        break;

    case (LASI_LAN_HPA - LASI_HPA):
        /* XXX: reset LAN card */
        break;
    case (LASI_LPT_HPA - LASI_HPA):
        /* XXX: reset parallel port */
        break;
    case (LASI_UART_HPA - LASI_HPA):
        /* XXX: reset serial port */
        break;
    case (LASI_RTC_HPA - LASI_HPA):
        s->rtc_ref = val - time(NULL);
        break;

    case LASI_PCR:
        if (val == 0x02) /* immediately power off */
            qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
        break;
    case LASI_ERRLOG:
        s->errlog = val;
        break;
    case LASI_VER:
        /* read-only.  */
        break;
    case LASI_IORESET:
        break;  /* XXX: TODO: Reset various devices. */
    case LASI_AMR:
        s->amr = val;
        break;

    default:
        /* Controlled by lasi_chip_mem_valid above. */
        g_assert_not_reached();
    }
    return MEMTX_OK;
}

static const MemoryRegionOps lasi_chip_ops = {
    .read_with_attrs = lasi_chip_read_with_attrs,
    .write_with_attrs = lasi_chip_write_with_attrs,
    .endianness = DEVICE_BIG_ENDIAN,
    .valid = {
        .min_access_size = 1,
        .max_access_size = 4,
        .accepts = lasi_chip_mem_valid,
    },
    .impl = {
        .min_access_size = 1,
        .max_access_size = 4,
    },
};

static const VMStateDescription vmstate_lasi = {
    .name = "Lasi",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(irr, LasiState),
        VMSTATE_UINT32(imr, LasiState),
        VMSTATE_UINT32(ipr, LasiState),
        VMSTATE_UINT32(icr, LasiState),
        VMSTATE_UINT32(iar, LasiState),
        VMSTATE_UINT32(errlog, LasiState),
        VMSTATE_UINT32(amr, LasiState),
        VMSTATE_END_OF_LIST()
    }
};


static void lasi_set_irq(void *opaque, int irq, int level)
{
    LasiState *s = opaque;
    uint32_t bit = 1u << irq;

    if (level) {
        s->ipr |= bit;
        if (bit & s->imr) {
            uint32_t iar = s->iar;
            s->irr |= bit;
            if ((s->icr & ICR_BUS_ERROR_BIT) == 0) {
                stl_be_phys(&address_space_memory, iar & -32, iar & 31);
            }
        }
    }
}

static int lasi_get_irq(unsigned long hpa)
{
    switch (hpa) {
    case LASI_HPA:
        return 14;
    case LASI_UART_HPA:
        return 5;
    case LASI_LPT_HPA:
        return 7;
    case LASI_LAN_HPA:
        return 8;
    case LASI_SCSI_HPA:
        return 9;
    case LASI_AUDIO_HPA:
        return 13;
    case LASI_PS2KBD_HPA:
    case LASI_PS2MOU_HPA:
        return 26;
    default:
        g_assert_not_reached();
    }
}

DeviceState *lasi_init(MemoryRegion *address_space)
{
    DeviceState *dev;
    LasiState *s;

    dev = qdev_create(NULL, TYPE_LASI_CHIP);
    s = LASI_CHIP(dev);
    s->iar = CPU_HPA + 3;

    /* Lasi access from main memory.  */
    memory_region_init_io(&s->this_mem, OBJECT(s), &lasi_chip_ops,
                          s, "lasi", 0x100000);
    memory_region_add_subregion(address_space, LASI_HPA, &s->this_mem);

    qdev_init_nofail(dev);

    /* LAN */
    if (enable_lasi_lan()) {
        qemu_irq lan_irq = qemu_allocate_irq(lasi_set_irq, s,
                lasi_get_irq(LASI_LAN_HPA));
        lasi_82596_init(address_space, LASI_LAN_HPA, lan_irq);
    }

    /* Parallel port */
    qemu_irq lpt_irq = qemu_allocate_irq(lasi_set_irq, s,
            lasi_get_irq(LASI_LPT_HPA));
    parallel_mm_init(address_space, LASI_LPT_HPA + 0x800, 0,
                     lpt_irq, parallel_hds[0]);

    /* Real time clock (RTC), it's only one 32-bit counter @9000 */

    s->rtc = time(NULL);
    s->rtc_ref = 0;

    if (serial_hd(1)) {
        /* Serial port */
        qemu_irq serial_irq = qemu_allocate_irq(lasi_set_irq, s,
                lasi_get_irq(LASI_UART_HPA));
        serial_mm_init(address_space, LASI_UART_HPA + 0x800, 0,
                serial_irq, 8000000 / 16,
                serial_hd(0), DEVICE_NATIVE_ENDIAN);
    }

    /* PS/2 Keyboard/Mouse */
    qemu_irq ps2kbd_irq = qemu_allocate_irq(lasi_set_irq, s,
            lasi_get_irq(LASI_PS2KBD_HPA));
    lasips2_init(address_space, LASI_PS2KBD_HPA,  ps2kbd_irq);

    return dev;
}

static void lasi_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->vmsd = &vmstate_lasi;
}

static const TypeInfo lasi_pcihost_info = {
    .name          = TYPE_LASI_CHIP,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(LasiState),
    .class_init    = lasi_class_init,
};

static void lasi_register_types(void)
{
    type_register_static(&lasi_pcihost_info);
}

type_init(lasi_register_types)
Commit	Line	Data
376b8519 HD	1	/*
	2	* HP-PARISC Lasi chipset emulation.
	3	*
	4	* (C) 2019 by Helge Deller <[email protected]>
	5	*
	6	* This work is licensed under the GNU GPL license version 2 or later.
	7	*
	8	* Documentation available at:
	9	* https://parisc.wiki.kernel.org/images-parisc/7/79/Lasi_ers.pdf
	10	*/
	11
	12	#include "qemu/osdep.h"
	13	#include "qemu/units.h"
	14	#include "qapi/error.h"
	15	#include "cpu.h"
	16	#include "trace.h"
	17	#include "hw/hw.h"
	18	#include "hw/irq.h"
	19	#include "sysemu/sysemu.h"
	20	#include "sysemu/runstate.h"
	21	#include "hppa_sys.h"
	22	#include "hw/net/lasi_82596.h"
	23	#include "hw/char/parallel.h"
	24	#include "hw/char/serial.h"
2a6505b0	25	#include "hw/input/lasips2.h"
376b8519 HD	26	#include "exec/address-spaces.h"
	27	#include "migration/vmstate.h"
	28
	29	#define TYPE_LASI_CHIP "lasi-chip"
	30
	31	#define LASI_IRR 0x00 /* RO */
	32	#define LASI_IMR 0x04
	33	#define LASI_IPR 0x08
	34	#define LASI_ICR 0x0c
	35	#define LASI_IAR 0x10
	36
	37	#define LASI_PCR 0x0C000 /* LASI Power Control register */
	38	#define LASI_ERRLOG 0x0C004 /* LASI Error Logging register */
	39	#define LASI_VER 0x0C008 /* LASI Version Control register */
	40	#define LASI_IORESET 0x0C00C /* LASI I/O Reset register */
	41	#define LASI_AMR 0x0C010 /* LASI Arbitration Mask register */
	42	#define LASI_IO_CONF 0x7FFFE /* LASI primary configuration register */
	43	#define LASI_IO_CONF2 0x7FFFF /* LASI secondary configuration register */
	44
	45	#define LASI_BIT(x) (1ul << (x))
	46	#define LASI_IRQ_BITS (LASI_BIT(5) \| LASI_BIT(7) \| LASI_BIT(8) \| LASI_BIT(9) \
	47	\| LASI_BIT(13) \| LASI_BIT(14) \| LASI_BIT(16) \| LASI_BIT(17) \
	48	\| LASI_BIT(18) \| LASI_BIT(19) \| LASI_BIT(20) \| LASI_BIT(21) \
	49	\| LASI_BIT(26))
	50
	51	#define ICR_BUS_ERROR_BIT LASI_BIT(8) /* bit 8 in ICR */
	52	#define ICR_TOC_BIT LASI_BIT(1) /* bit 1 in ICR */
	53
	54	#define LASI_CHIP(obj) \
	55	OBJECT_CHECK(LasiState, (obj), TYPE_LASI_CHIP)
	56
	57	#define LASI_RTC_HPA (LASI_HPA + 0x9000)
	58
	59	typedef struct LasiState {
	60	PCIHostState parent_obj;
	61
	62	uint32_t irr;
	63	uint32_t imr;
	64	uint32_t ipr;
	65	uint32_t icr;
	66	uint32_t iar;
	67
	68	uint32_t errlog;
	69	uint32_t amr;
	70	uint32_t rtc;
	71	time_t rtc_ref;
	72
	73	MemoryRegion this_mem;
	74	} LasiState;
	75
	76	static bool lasi_chip_mem_valid(void *opaque, hwaddr addr,
	77	unsigned size, bool is_write,
	78	MemTxAttrs attrs)
	79	{
	80	bool ret = false;
	81
	82	switch (addr) {
	83	case LASI_IRR:
	84	case LASI_IMR:
	85	case LASI_IPR:
	86	case LASI_ICR:
	87	case LASI_IAR:
	88
	89	case (LASI_LAN_HPA - LASI_HPA):
90	case (LASI_LPT_HPA - LASI_HPA):
91	case (LASI_UART_HPA - LASI_HPA):
92	case (LASI_RTC_HPA - LASI_HPA):
93
94	case LASI_PCR ... LASI_AMR:
95	ret = true;
96	}
97
98	trace_lasi_chip_mem_valid(addr, ret);
99	return ret;
100	}
101
102	static MemTxResult lasi_chip_read_with_attrs(void *opaque, hwaddr addr,
103	uint64_t *data, unsigned size,
104	MemTxAttrs attrs)
105	{
106	LasiState *s = opaque;
107	MemTxResult ret = MEMTX_OK;
108	uint32_t val;
109
110	switch (addr) {
111	case LASI_IRR:
112	val = s->irr;
113	break;
114	case LASI_IMR:
115	val = s->imr;
116	break;
117	case LASI_IPR:
118	val = s->ipr;
119	/* Any read to IPR clears the register. */
120	s->ipr = 0;
121	break;
122	case LASI_ICR:
123	val = s->icr & ICR_BUS_ERROR_BIT; /* bus_error */
124	break;
125	case LASI_IAR:
126	val = s->iar;
127	break;
128
129	case (LASI_LAN_HPA - LASI_HPA):
130	case (LASI_LPT_HPA - LASI_HPA):
131	case (LASI_UART_HPA - LASI_HPA):
132	val = 0;
133	break;
134	case (LASI_RTC_HPA - LASI_HPA):
135	val = time(NULL);
136	val += s->rtc_ref;
137	break;
138
139	case LASI_PCR:
140	case LASI_VER: /* only version 0 existed. */
141	case LASI_IORESET:
142	val = 0;
143	break;
144	case LASI_ERRLOG:
145	val = s->errlog;
146	break;
147	case LASI_AMR:
148	val = s->amr;
149	break;
150
151	default:
152	/* Controlled by lasi_chip_mem_valid above. */
153	g_assert_not_reached();
154	}
155
156	trace_lasi_chip_read(addr, val);
157
158	*data = val;
159	return ret;
160	}
161
162	static MemTxResult lasi_chip_write_with_attrs(void *opaque, hwaddr addr,
163	uint64_t val, unsigned size,
164	MemTxAttrs attrs)
165	{
166	LasiState *s = opaque;
167
168	trace_lasi_chip_write(addr, val);
169
170	switch (addr) {
171	case LASI_IRR:
172	/* read-only. */
173	break;
174	case LASI_IMR:
175	s->imr = val; /* 0x20 ?? */
176	assert((val & LASI_IRQ_BITS) == val);
177	break;
178	case LASI_IPR:
179	/* Any write to IPR clears the register. */
180	s->ipr = 0;
181	break;
182	case LASI_ICR:
183	s->icr = val;
184	/* if (val & ICR_TOC_BIT) issue_toc(); */
185	break;
186	case LASI_IAR:
187	s->iar = val;
188	break;
189
190	case (LASI_LAN_HPA - LASI_HPA):
191	/* XXX: reset LAN card */
192	break;
193	case (LASI_LPT_HPA - LASI_HPA):
194	/* XXX: reset parallel port */
195	break;
196	case (LASI_UART_HPA - LASI_HPA):
197	/* XXX: reset serial port */
198	break;
199	case (LASI_RTC_HPA - LASI_HPA):
200	s->rtc_ref = val - time(NULL);
201	break;
202
203	case LASI_PCR:
204	if (val == 0x02) /* immediately power off */
205	qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
206	break;
207	case LASI_ERRLOG:
208	s->errlog = val;
209	break;
210	case LASI_VER:
211	/* read-only. */
212	break;
213	case LASI_IORESET:
214	break; /* XXX: TODO: Reset various devices. */
215	case LASI_AMR:
216	s->amr = val;
217	break;
218
219	default:
220	/* Controlled by lasi_chip_mem_valid above. */
221	g_assert_not_reached();
222	}
223	return MEMTX_OK;
224	}
225
226	static const MemoryRegionOps lasi_chip_ops = {
227	.read_with_attrs = lasi_chip_read_with_attrs,
228	.write_with_attrs = lasi_chip_write_with_attrs,
229	.endianness = DEVICE_BIG_ENDIAN,
230	.valid = {
231	.min_access_size = 1,
232	.max_access_size = 4,
233	.accepts = lasi_chip_mem_valid,
234	},
235	.impl = {
236	.min_access_size = 1,
237	.max_access_size = 4,
238	},
239	};
240
241	static const VMStateDescription vmstate_lasi = {
242	.name = "Lasi",
243	.version_id = 1,
244	.minimum_version_id = 1,
245	.fields = (VMStateField[]) {
246	VMSTATE_UINT32(irr, LasiState),
247	VMSTATE_UINT32(imr, LasiState),
248	VMSTATE_UINT32(ipr, LasiState),
249	VMSTATE_UINT32(icr, LasiState),
250	VMSTATE_UINT32(iar, LasiState),
251	VMSTATE_UINT32(errlog, LasiState),
252	VMSTATE_UINT32(amr, LasiState),
253	VMSTATE_END_OF_LIST()
254	}
255	};
256
257
258	static void lasi_set_irq(void *opaque, int irq, int level)
259	{
260	LasiState *s = opaque;
261	uint32_t bit = 1u << irq;
262
263	if (level) {
264	s->ipr \|= bit;
265	if (bit & s->imr) {
266	uint32_t iar = s->iar;
267	s->irr \|= bit;
268	if ((s->icr & ICR_BUS_ERROR_BIT) == 0) {
269	stl_be_phys(&address_space_memory, iar & -32, iar & 31);
270	}
271	}
272	}
273	}
274
275	static int lasi_get_irq(unsigned long hpa)
276	{
277	switch (hpa) {
278	case LASI_HPA:
279	return 14;
280	case LASI_UART_HPA:
281	return 5;
282	case LASI_LPT_HPA:
283	return 7;
284	case LASI_LAN_HPA:
285	return 8;
286	case LASI_SCSI_HPA:
287	return 9;
288	case LASI_AUDIO_HPA:
289	return 13;
290	case LASI_PS2KBD_HPA:
291	case LASI_PS2MOU_HPA:
292	return 26;
293	default:
294	g_assert_not_reached();
295	}
296	}
297
298	DeviceState lasi_init(MemoryRegion address_space)
299	{
300	DeviceState *dev;
301	LasiState *s;
302
303	dev = qdev_create(NULL, TYPE_LASI_CHIP);
304	s = LASI_CHIP(dev);
305	s->iar = CPU_HPA + 3;
306
307	/* Lasi access from main memory. */
308	memory_region_init_io(&s->this_mem, OBJECT(s), &lasi_chip_ops,
309	s, "lasi", 0x100000);
310	memory_region_add_subregion(address_space, LASI_HPA, &s->this_mem);
311
312	qdev_init_nofail(dev);
313
314	/* LAN */
315	if (enable_lasi_lan()) {
316	qemu_irq lan_irq = qemu_allocate_irq(lasi_set_irq, s,
317	lasi_get_irq(LASI_LAN_HPA));
318	lasi_82596_init(address_space, LASI_LAN_HPA, lan_irq);
319	}
320
321	/* Parallel port */
322	qemu_irq lpt_irq = qemu_allocate_irq(lasi_set_irq, s,
323	lasi_get_irq(LASI_LPT_HPA));
324	parallel_mm_init(address_space, LASI_LPT_HPA + 0x800, 0,
325	lpt_irq, parallel_hds[0]);
326
327	/* Real time clock (RTC), it's only one 32-bit counter @9000 */
2a6505b0	328
376b8519 HD	329	s->rtc = time(NULL);
	330	s->rtc_ref = 0;
	331
	332	if (serial_hd(1)) {
	333	/* Serial port */
	334	qemu_irq serial_irq = qemu_allocate_irq(lasi_set_irq, s,
	335	lasi_get_irq(LASI_UART_HPA));
	336	serial_mm_init(address_space, LASI_UART_HPA + 0x800, 0,
	337	serial_irq, 8000000 / 16,
2a6505b0	338	serial_hd(0), DEVICE_NATIVE_ENDIAN);
376b8519	339	}
2a6505b0 SS	340
	341	/* PS/2 Keyboard/Mouse */
	342	qemu_irq ps2kbd_irq = qemu_allocate_irq(lasi_set_irq, s,
	343	lasi_get_irq(LASI_PS2KBD_HPA));
	344	lasips2_init(address_space, LASI_PS2KBD_HPA, ps2kbd_irq);
	345
376b8519 HD	346	return dev;
	347	}
	348
	349	static void lasi_class_init(ObjectClass klass, void data)
	350	{
	351	DeviceClass *dc = DEVICE_CLASS(klass);
	352
	353	dc->vmsd = &vmstate_lasi;
	354	}
	355
	356	static const TypeInfo lasi_pcihost_info = {
	357	.name = TYPE_LASI_CHIP,
	358	.parent = TYPE_SYS_BUS_DEVICE,
	359	.instance_size = sizeof(LasiState),
	360	.class_init = lasi_class_init,
	361	};
	362
	363	static void lasi_register_types(void)
	364	{
	365	type_register_static(&lasi_pcihost_info);
	366	}
	367
	368	type_init(lasi_register_types)