[qemu.git] / target-unicore32 / helper.c

/*
 * Copyright (C) 2010-2012 Guan Xuetao
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Contributions from 2012-04-01 on are considered under GPL version 2,
 * or (at your option) any later version.
 */

#include "cpu.h"
#include "exec/gdbstub.h"
#include "exec/helper-proto.h"
#include "qemu/host-utils.h"
#ifndef CONFIG_USER_ONLY
#include "ui/console.h"
#endif

#undef DEBUG_UC32

#ifdef DEBUG_UC32
#define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
#else
#define DPRINTF(fmt, ...) do {} while (0)
#endif

UniCore32CPU *uc32_cpu_init(const char *cpu_model)
{
    return UNICORE32_CPU(cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model));
}

uint32_t HELPER(clo)(uint32_t x)
{
    return clo32(x);
}

uint32_t HELPER(clz)(uint32_t x)
{
    return clz32(x);
}

#ifndef CONFIG_USER_ONLY
void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
        uint32_t cop)
{
    UniCore32CPU *cpu = uc32_env_get_cpu(env);

    /*
     * movc pp.nn, rn, #imm9
     *      rn: UCOP_REG_D
     *      nn: UCOP_REG_N
     *          1: sys control reg.
     *          2: page table base reg.
     *          3: data fault status reg.
     *          4: insn fault status reg.
     *          5: cache op. reg.
     *          6: tlb op. reg.
     *      imm9: split UCOP_IMM10 with bit5 is 0
     */
    switch (creg) {
    case 1:
        if (cop != 0) {
            goto unrecognized;
        }
        env->cp0.c1_sys = val;
        break;
    case 2:
        if (cop != 0) {
            goto unrecognized;
        }
        env->cp0.c2_base = val;
        break;
    case 3:
        if (cop != 0) {
            goto unrecognized;
        }
        env->cp0.c3_faultstatus = val;
        break;
    case 4:
        if (cop != 0) {
            goto unrecognized;
        }
        env->cp0.c4_faultaddr = val;
        break;
    case 5:
        switch (cop) {
        case 28:
            DPRINTF("Invalidate Entire I&D cache\n");
            return;
        case 20:
            DPRINTF("Invalidate Entire Icache\n");
            return;
        case 12:
            DPRINTF("Invalidate Entire Dcache\n");
            return;
        case 10:
            DPRINTF("Clean Entire Dcache\n");
            return;
        case 14:
            DPRINTF("Flush Entire Dcache\n");
            return;
        case 13:
            DPRINTF("Invalidate Dcache line\n");
            return;
        case 11:
            DPRINTF("Clean Dcache line\n");
            return;
        case 15:
            DPRINTF("Flush Dcache line\n");
            return;
        }
        break;
    case 6:
        if ((cop <= 6) && (cop >= 2)) {
            /* invalid all tlb */
            tlb_flush(CPU(cpu), 1);
            return;
        }
        break;
    default:
        goto unrecognized;
    }
    return;
unrecognized:
    DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
            creg, cop);
}

uint32_t helper_cp0_get(CPUUniCore32State *env, uint32_t creg, uint32_t cop)
{
    /*
     * movc rd, pp.nn, #imm9
     *      rd: UCOP_REG_D
     *      nn: UCOP_REG_N
     *          0: cpuid and cachetype
     *          1: sys control reg.
     *          2: page table base reg.
     *          3: data fault status reg.
     *          4: insn fault status reg.
     *      imm9: split UCOP_IMM10 with bit5 is 0
     */
    switch (creg) {
    case 0:
        switch (cop) {
        case 0:
            return env->cp0.c0_cpuid;
        case 1:
            return env->cp0.c0_cachetype;
        }
        break;
    case 1:
        if (cop == 0) {
            return env->cp0.c1_sys;
        }
        break;
    case 2:
        if (cop == 0) {
            return env->cp0.c2_base;
        }
        break;
    case 3:
        if (cop == 0) {
            return env->cp0.c3_faultstatus;
        }
        break;
    case 4:
        if (cop == 0) {
            return env->cp0.c4_faultaddr;
        }
        break;
    }
    DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
            creg, cop);
    return 0;
}

#ifdef CONFIG_CURSES
/*
 * FIXME:
 *     1. curses windows will be blank when switching back
 *     2. backspace is not handled yet
 */
static void putc_on_screen(unsigned char ch)
{
    static WINDOW *localwin;
    static int init;

    if (!init) {
        /* Assume 80 * 30 screen to minimize the implementation */
        localwin = newwin(30, 80, 0, 0);
        scrollok(localwin, TRUE);
        init = TRUE;
    }

    if (isprint(ch)) {
        wprintw(localwin, "%c", ch);
    } else {
        switch (ch) {
        case '\n':
            wprintw(localwin, "%c", ch);
            break;
        case '\r':
            /* If '\r' is put before '\n', the curses window will destroy the
             * last print line. And meanwhile, '\n' implifies '\r' inside. */
            break;
        default: /* Not handled, so just print it hex code */
            wprintw(localwin, "-- 0x%x --", ch);
        }
    }

    wrefresh(localwin);
}
#else
#define putc_on_screen(c)               do { } while (0)
#endif

void helper_cp1_putc(target_ulong x)
{
    putc_on_screen((unsigned char)x);   /* Output to screen */
    DPRINTF("%c", x);                   /* Output to stdout */
}
#endif

#ifdef CONFIG_USER_ONLY
void switch_mode(CPUUniCore32State *env, int mode)
{
    UniCore32CPU *cpu = uc32_env_get_cpu(env);

    if (mode != ASR_MODE_USER) {
        cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
    }
}

void uc32_cpu_do_interrupt(CPUState *cs)
{
    cpu_abort(cs, "NO interrupt in user mode\n");
}

int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
                              int access_type, int mmu_idx)
{
    cpu_abort(cs, "NO mmu fault in user mode\n");
    return 1;
}
#endif

bool uc32_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
    if (interrupt_request & CPU_INTERRUPT_HARD) {
        UniCore32CPU *cpu = UNICORE32_CPU(cs);
        CPUUniCore32State *env = &cpu->env;

        if (!(env->uncached_asr & ASR_I)) {
            cs->exception_index = UC32_EXCP_INTR;
            uc32_cpu_do_interrupt(cs);
            return true;
        }
    }
    return false;
}
Commit	Line	Data
6e64da3c	1	/*
4f23a1e6	2	* Copyright (C) 2010-2012 Guan Xuetao
6e64da3c GX	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
c3a8baa9 AF	7	*
	8	* Contributions from 2012-04-01 on are considered under GPL version 2,
	9	* or (at your option) any later version.
6e64da3c	10	*/
6e64da3c GX	11
6e64da3c GX	12	#include "cpu.h"
022c62cb	13	#include "exec/gdbstub.h"
2ef6175a	14	#include "exec/helper-proto.h"
1de7afc9	15	#include "qemu/host-utils.h"
74880fe2	16	#ifndef CONFIG_USER_ONLY
28ecbaee	17	#include "ui/console.h"
74880fe2	18	#endif
6e64da3c	19
527d9979 GX	20	#undef DEBUG_UC32
	21
	22	#ifdef DEBUG_UC32
	23	#define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
	24	#else
	25	#define DPRINTF(fmt, ...) do {} while (0)
	26	#endif
	27
41979669	28	UniCore32CPU uc32_cpu_init(const char cpu_model)
6e64da3c	29	{
41979669	30	return UNICORE32_CPU(cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model));
6e64da3c GX	31	}
	32
	33	uint32_t HELPER(clo)(uint32_t x)
	34	{
	35	return clo32(x);
	36	}
	37
	38	uint32_t HELPER(clz)(uint32_t x)
	39	{
	40	return clz32(x);
	41	}
	42
527d9979 GX	43	#ifndef CONFIG_USER_ONLY
	44	void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
	45	uint32_t cop)
4f23a1e6	46	{
00c8cb0a AF	47	UniCore32CPU *cpu = uc32_env_get_cpu(env);
00c8cb0a AF	48
527d9979 GX	49	/*
	50	* movc pp.nn, rn, #imm9
	51	* rn: UCOP_REG_D
	52	* nn: UCOP_REG_N
	53	* 1: sys control reg.
	54	* 2: page table base reg.
	55	* 3: data fault status reg.
	56	* 4: insn fault status reg.
	57	* 5: cache op. reg.
	58	* 6: tlb op. reg.
	59	* imm9: split UCOP_IMM10 with bit5 is 0
	60	*/
	61	switch (creg) {
	62	case 1:
	63	if (cop != 0) {
	64	goto unrecognized;
	65	}
	66	env->cp0.c1_sys = val;
	67	break;
	68	case 2:
	69	if (cop != 0) {
	70	goto unrecognized;
	71	}
	72	env->cp0.c2_base = val;
	73	break;
	74	case 3:
	75	if (cop != 0) {
	76	goto unrecognized;
	77	}
	78	env->cp0.c3_faultstatus = val;
	79	break;
	80	case 4:
	81	if (cop != 0) {
	82	goto unrecognized;
	83	}
	84	env->cp0.c4_faultaddr = val;
	85	break;
	86	case 5:
	87	switch (cop) {
	88	case 28:
	89	DPRINTF("Invalidate Entire I&D cache\n");
	90	return;
	91	case 20:
	92	DPRINTF("Invalidate Entire Icache\n");
	93	return;
	94	case 12:
	95	DPRINTF("Invalidate Entire Dcache\n");
	96	return;
	97	case 10:
	98	DPRINTF("Clean Entire Dcache\n");
	99	return;
	100	case 14:
	101	DPRINTF("Flush Entire Dcache\n");
	102	return;
	103	case 13:
	104	DPRINTF("Invalidate Dcache line\n");
	105	return;
	106	case 11:
	107	DPRINTF("Clean Dcache line\n");
	108	return;
	109	case 15:
	110	DPRINTF("Flush Dcache line\n");
	111	return;
	112	}
113	break;
114	case 6:
115	if ((cop <= 6) && (cop >= 2)) {
116	/* invalid all tlb */
00c8cb0a	117	tlb_flush(CPU(cpu), 1);
527d9979 GX	118	return;
	119	}
	120	break;
	121	default:
	122	goto unrecognized;
4f23a1e6	123	}
6e64da3c	124	return;
527d9979 GX	125	unrecognized:
	126	DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
	127	creg, cop);
6e64da3c GX	128	}
6e64da3c GX	129
527d9979	130	uint32_t helper_cp0_get(CPUUniCore32State *env, uint32_t creg, uint32_t cop)
6e64da3c	131	{
527d9979 GX	132	/*
	133	* movc rd, pp.nn, #imm9
	134	* rd: UCOP_REG_D
	135	* nn: UCOP_REG_N
	136	* 0: cpuid and cachetype
	137	* 1: sys control reg.
	138	* 2: page table base reg.
	139	* 3: data fault status reg.
	140	* 4: insn fault status reg.
	141	* imm9: split UCOP_IMM10 with bit5 is 0
	142	*/
	143	switch (creg) {
	144	case 0:
	145	switch (cop) {
	146	case 0:
	147	return env->cp0.c0_cpuid;
	148	case 1:
	149	return env->cp0.c0_cachetype;
	150	}
	151	break;
	152	case 1:
	153	if (cop == 0) {
	154	return env->cp0.c1_sys;
	155	}
	156	break;
	157	case 2:
	158	if (cop == 0) {
	159	return env->cp0.c2_base;
	160	}
	161	break;
	162	case 3:
	163	if (cop == 0) {
	164	return env->cp0.c3_faultstatus;
	165	}
	166	break;
	167	case 4:
	168	if (cop == 0) {
	169	return env->cp0.c4_faultaddr;
	170	}
	171	break;
	172	}
	173	DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
	174	creg, cop);
6e64da3c GX	175	return 0;
	176	}
	177
ff5928d0 GX	178	#ifdef CONFIG_CURSES
	179	/*
	180	* FIXME:
	181	* 1. curses windows will be blank when switching back
	182	* 2. backspace is not handled yet
	183	*/
	184	static void putc_on_screen(unsigned char ch)
	185	{
	186	static WINDOW *localwin;
	187	static int init;
	188
	189	if (!init) {
	190	/* Assume 80 * 30 screen to minimize the implementation */
	191	localwin = newwin(30, 80, 0, 0);
	192	scrollok(localwin, TRUE);
	193	init = TRUE;
	194	}
	195
	196	if (isprint(ch)) {
	197	wprintw(localwin, "%c", ch);
	198	} else {
	199	switch (ch) {
	200	case '\n':
	201	wprintw(localwin, "%c", ch);
	202	break;
	203	case '\r':
	204	/* If '\r' is put before '\n', the curses window will destroy the
	205	* last print line. And meanwhile, '\n' implifies '\r' inside. */
	206	break;
	207	default: /* Not handled, so just print it hex code */
	208	wprintw(localwin, "-- 0x%x --", ch);
	209	}
	210	}
	211
	212	wrefresh(localwin);
	213	}
	214	#else
	215	#define putc_on_screen(c) do { } while (0)
	216	#endif
	217
527d9979	218	void helper_cp1_putc(target_ulong x)
6e64da3c	219	{
ff5928d0 GX	220	putc_on_screen((unsigned char)x); /* Output to screen */
ff5928d0 GX	221	DPRINTF("%c", x); /* Output to stdout */
6e64da3c	222	}
527d9979	223	#endif
6e64da3c	224
527d9979 GX	225	#ifdef CONFIG_USER_ONLY
527d9979 GX	226	void switch_mode(CPUUniCore32State *env, int mode)
6e64da3c	227	{
a47dddd7 AF	228	UniCore32CPU *cpu = uc32_env_get_cpu(env);
a47dddd7 AF	229
527d9979	230	if (mode != ASR_MODE_USER) {
a47dddd7	231	cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
527d9979	232	}
6e64da3c GX	233	}
6e64da3c GX	234
97a8ea5a	235	void uc32_cpu_do_interrupt(CPUState *cs)
6e64da3c	236	{
a47dddd7	237	cpu_abort(cs, "NO interrupt in user mode\n");
6e64da3c GX	238	}
6e64da3c GX	239
7510454e	240	int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
527d9979	241	int access_type, int mmu_idx)
6e64da3c	242	{
a47dddd7	243	cpu_abort(cs, "NO mmu fault in user mode\n");
527d9979	244	return 1;
6e64da3c	245	}
527d9979	246	#endif
d8bb9159 RH	247
	248	bool uc32_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
	249	{
	250	if (interrupt_request & CPU_INTERRUPT_HARD) {
	251	UniCore32CPU *cpu = UNICORE32_CPU(cs);
	252	CPUUniCore32State *env = &cpu->env;
	253
	254	if (!(env->uncached_asr & ASR_I)) {
	255	cs->exception_index = UC32_EXCP_INTR;
	256	uc32_cpu_do_interrupt(cs);
	257	return true;
	258	}
	259	}
	260	return false;
	261	}