[qemu.git] / hw / char / parallel.c

/*
 * QEMU Parallel PORT emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 * Copyright (c) 2007 Marko Kohtala
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw/hw.h"
#include "sysemu/char.h"
#include "hw/isa/isa.h"
#include "hw/i386/pc.h"
#include "sysemu/sysemu.h"

//#define DEBUG_PARALLEL

#ifdef DEBUG_PARALLEL
#define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__)
#else
#define pdebug(fmt, ...) ((void)0)
#endif

#define PARA_REG_DATA 0
#define PARA_REG_STS 1
#define PARA_REG_CTR 2
#define PARA_REG_EPP_ADDR 3
#define PARA_REG_EPP_DATA 4

/*
 * These are the definitions for the Printer Status Register
 */
#define PARA_STS_BUSY	0x80	/* Busy complement */
#define PARA_STS_ACK	0x40	/* Acknowledge */
#define PARA_STS_PAPER	0x20	/* Out of paper */
#define PARA_STS_ONLINE	0x10	/* Online */
#define PARA_STS_ERROR	0x08	/* Error complement */
#define PARA_STS_TMOUT	0x01	/* EPP timeout */

/*
 * These are the definitions for the Printer Control Register
 */
#define PARA_CTR_DIR	0x20	/* Direction (1=read, 0=write) */
#define PARA_CTR_INTEN	0x10	/* IRQ Enable */
#define PARA_CTR_SELECT	0x08	/* Select In complement */
#define PARA_CTR_INIT	0x04	/* Initialize Printer complement */
#define PARA_CTR_AUTOLF	0x02	/* Auto linefeed complement */
#define PARA_CTR_STROBE	0x01	/* Strobe complement */

#define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)

typedef struct ParallelState {
    MemoryRegion iomem;
    uint8_t dataw;
    uint8_t datar;
    uint8_t status;
    uint8_t control;
    qemu_irq irq;
    int irq_pending;
    CharDriverState *chr;
    int hw_driver;
    int epp_timeout;
    uint32_t last_read_offset; /* For debugging */
    /* Memory-mapped interface */
    int it_shift;
} ParallelState;

#define TYPE_ISA_PARALLEL "isa-parallel"
#define ISA_PARALLEL(obj) \
    OBJECT_CHECK(ISAParallelState, (obj), TYPE_ISA_PARALLEL)

typedef struct ISAParallelState {
    ISADevice parent_obj;

    uint32_t index;
    uint32_t iobase;
    uint32_t isairq;
    ParallelState state;
} ISAParallelState;

static void parallel_update_irq(ParallelState *s)
{
    if (s->irq_pending)
        qemu_irq_raise(s->irq);
    else
        qemu_irq_lower(s->irq);
}

static void
parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;

    pdebug("write addr=0x%02x val=0x%02x\n", addr, val);

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        s->dataw = val;
        parallel_update_irq(s);
        break;
    case PARA_REG_CTR:
        val |= 0xc0;
        if ((val & PARA_CTR_INIT) == 0 ) {
            s->status = PARA_STS_BUSY;
            s->status |= PARA_STS_ACK;
            s->status |= PARA_STS_ONLINE;
            s->status |= PARA_STS_ERROR;
        }
        else if (val & PARA_CTR_SELECT) {
            if (val & PARA_CTR_STROBE) {
                s->status &= ~PARA_STS_BUSY;
                if ((s->control & PARA_CTR_STROBE) == 0)
                    qemu_chr_fe_write(s->chr, &s->dataw, 1);
            } else {
                if (s->control & PARA_CTR_INTEN) {
                    s->irq_pending = 1;
                }
            }
        }
        parallel_update_irq(s);
        s->control = val;
        break;
    }
}

static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint8_t parm = val;
    int dir;

    /* Sometimes programs do several writes for timing purposes on old
       HW. Take care not to waste time on writes that do nothing. */

    s->last_read_offset = ~0U;

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        if (s->dataw == val)
            return;
        pdebug("wd%02x\n", val);
        qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
        s->dataw = val;
        break;
    case PARA_REG_STS:
        pdebug("ws%02x\n", val);
        if (val & PARA_STS_TMOUT)
            s->epp_timeout = 0;
        break;
    case PARA_REG_CTR:
        val |= 0xc0;
        if (s->control == val)
            return;
        pdebug("wc%02x\n", val);

        if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
            if (val & PARA_CTR_DIR) {
                dir = 1;
            } else {
                dir = 0;
            }
            qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
            parm &= ~PARA_CTR_DIR;
        }

        qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
        s->control = val;
        break;
    case PARA_REG_EPP_ADDR:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
            /* Controls not correct for EPP address cycle, so do nothing */
            pdebug("wa%02x s\n", val);
        else {
            struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
            if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("wa%02x t\n", val);
            }
            else
                pdebug("wa%02x\n", val);
        }
        break;
    case PARA_REG_EPP_DATA:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
            /* Controls not correct for EPP data cycle, so do nothing */
            pdebug("we%02x s\n", val);
        else {
            struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
            if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("we%02x t\n", val);
            }
            else
                pdebug("we%02x\n", val);
        }
        break;
    }
}

static void
parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint16_t eppdata = cpu_to_le16(val);
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("we%04x s\n", val);
        return;
    }
    err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
    if (err) {
        s->epp_timeout = 1;
        pdebug("we%04x t\n", val);
    }
    else
        pdebug("we%04x\n", val);
}

static void
parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint32_t eppdata = cpu_to_le32(val);
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("we%08x s\n", val);
        return;
    }
    err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
    if (err) {
        s->epp_timeout = 1;
        pdebug("we%08x t\n", val);
    }
    else
        pdebug("we%08x\n", val);
}

static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret = 0xff;

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        if (s->control & PARA_CTR_DIR)
            ret = s->datar;
        else
            ret = s->dataw;
        break;
    case PARA_REG_STS:
        ret = s->status;
        s->irq_pending = 0;
        if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
            /* XXX Fixme: wait 5 microseconds */
            if (s->status & PARA_STS_ACK)
                s->status &= ~PARA_STS_ACK;
            else {
                /* XXX Fixme: wait 5 microseconds */
                s->status |= PARA_STS_ACK;
                s->status |= PARA_STS_BUSY;
            }
        }
        parallel_update_irq(s);
        break;
    case PARA_REG_CTR:
        ret = s->control;
        break;
    }
    pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
    return ret;
}

static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint8_t ret = 0xff;
    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
        if (s->last_read_offset != addr || s->datar != ret)
            pdebug("rd%02x\n", ret);
        s->datar = ret;
        break;
    case PARA_REG_STS:
        qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
        ret &= ~PARA_STS_TMOUT;
        if (s->epp_timeout)
            ret |= PARA_STS_TMOUT;
        if (s->last_read_offset != addr || s->status != ret)
            pdebug("rs%02x\n", ret);
        s->status = ret;
        break;
    case PARA_REG_CTR:
        /* s->control has some bits fixed to 1. It is zero only when
           it has not been yet written to.  */
        if (s->control == 0) {
            qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
            if (s->last_read_offset != addr)
                pdebug("rc%02x\n", ret);
            s->control = ret;
        }
        else {
            ret = s->control;
            if (s->last_read_offset != addr)
                pdebug("rc%02x\n", ret);
        }
        break;
    case PARA_REG_EPP_ADDR:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
            /* Controls not correct for EPP addr cycle, so do nothing */
            pdebug("ra%02x s\n", ret);
        else {
            struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
            if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("ra%02x t\n", ret);
            }
            else
                pdebug("ra%02x\n", ret);
        }
        break;
    case PARA_REG_EPP_DATA:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
            /* Controls not correct for EPP data cycle, so do nothing */
            pdebug("re%02x s\n", ret);
        else {
            struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
            if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("re%02x t\n", ret);
            }
            else
                pdebug("re%02x\n", ret);
        }
        break;
    }
    s->last_read_offset = addr;
    return ret;
}

static uint32_t
parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret;
    uint16_t eppdata = ~0;
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("re%04x s\n", eppdata);
        return eppdata;
    }
    err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
    ret = le16_to_cpu(eppdata);

    if (err) {
        s->epp_timeout = 1;
        pdebug("re%04x t\n", ret);
    }
    else
        pdebug("re%04x\n", ret);
    return ret;
}

static uint32_t
parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret;
    uint32_t eppdata = ~0U;
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("re%08x s\n", eppdata);
        return eppdata;
    }
    err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
    ret = le32_to_cpu(eppdata);

    if (err) {
        s->epp_timeout = 1;
        pdebug("re%08x t\n", ret);
    }
    else
        pdebug("re%08x\n", ret);
    return ret;
}

static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
{
    pdebug("wecp%d=%02x\n", addr & 7, val);
}

static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
{
    uint8_t ret = 0xff;

    pdebug("recp%d:%02x\n", addr & 7, ret);
    return ret;
}

static void parallel_reset(void *opaque)
{
    ParallelState *s = opaque;

    s->datar = ~0;
    s->dataw = ~0;
    s->status = PARA_STS_BUSY;
    s->status |= PARA_STS_ACK;
    s->status |= PARA_STS_ONLINE;
    s->status |= PARA_STS_ERROR;
    s->status |= PARA_STS_TMOUT;
    s->control = PARA_CTR_SELECT;
    s->control |= PARA_CTR_INIT;
    s->control |= 0xc0;
    s->irq_pending = 0;
    s->hw_driver = 0;
    s->epp_timeout = 0;
    s->last_read_offset = ~0U;
}

static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };

static const MemoryRegionPortio isa_parallel_portio_hw_list[] = {
    { 0, 8, 1,
      .read = parallel_ioport_read_hw,
      .write = parallel_ioport_write_hw },
    { 4, 1, 2,
      .read = parallel_ioport_eppdata_read_hw2,
      .write = parallel_ioport_eppdata_write_hw2 },
    { 4, 1, 4,
      .read = parallel_ioport_eppdata_read_hw4,
      .write = parallel_ioport_eppdata_write_hw4 },
    { 0x400, 8, 1,
      .read = parallel_ioport_ecp_read,
      .write = parallel_ioport_ecp_write },
    PORTIO_END_OF_LIST(),
};

static const MemoryRegionPortio isa_parallel_portio_sw_list[] = {
    { 0, 8, 1,
      .read = parallel_ioport_read_sw,
      .write = parallel_ioport_write_sw },
    PORTIO_END_OF_LIST(),
};

static void parallel_isa_realizefn(DeviceState *dev, Error **errp)
{
    static int index;
    ISADevice *isadev = ISA_DEVICE(dev);
    ISAParallelState *isa = ISA_PARALLEL(dev);
    ParallelState *s = &isa->state;
    int base;
    uint8_t dummy;

    if (!s->chr) {
        error_setg(errp, "Can't create parallel device, empty char device");
        return;
    }

    if (isa->index == -1) {
        isa->index = index;
    }
    if (isa->index >= MAX_PARALLEL_PORTS) {
        error_setg(errp, "Max. supported number of parallel ports is %d.",
                   MAX_PARALLEL_PORTS);
        return;
    }
    if (isa->iobase == -1) {
        isa->iobase = isa_parallel_io[isa->index];
    }
    index++;

    base = isa->iobase;
    isa_init_irq(isadev, &s->irq, isa->isairq);
    qemu_register_reset(parallel_reset, s);

    if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
        s->hw_driver = 1;
        s->status = dummy;
    }

    isa_register_portio_list(isadev, base,
                             (s->hw_driver
                              ? &isa_parallel_portio_hw_list[0]
                              : &isa_parallel_portio_sw_list[0]),
                             s, "parallel");
}

/* Memory mapped interface */
static uint32_t parallel_mm_readb (void *opaque, hwaddr addr)
{
    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF;
}

static void parallel_mm_writeb (void *opaque,
                                hwaddr addr, uint32_t value)
{
    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
}

static uint32_t parallel_mm_readw (void *opaque, hwaddr addr)
{
    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF;
}

static void parallel_mm_writew (void *opaque,
                                hwaddr addr, uint32_t value)
{
    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
}

static uint32_t parallel_mm_readl (void *opaque, hwaddr addr)
{
    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, addr >> s->it_shift);
}

static void parallel_mm_writel (void *opaque,
                                hwaddr addr, uint32_t value)
{
    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, addr >> s->it_shift, value);
}

static const MemoryRegionOps parallel_mm_ops = {
    .old_mmio = {
        .read = { parallel_mm_readb, parallel_mm_readw, parallel_mm_readl },
        .write = { parallel_mm_writeb, parallel_mm_writew, parallel_mm_writel },
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

/* If fd is zero, it means that the parallel device uses the console */
bool parallel_mm_init(MemoryRegion *address_space,
                      hwaddr base, int it_shift, qemu_irq irq,
                      CharDriverState *chr)
{
    ParallelState *s;

    s = g_malloc0(sizeof(ParallelState));
    s->irq = irq;
    s->chr = chr;
    s->it_shift = it_shift;
    qemu_register_reset(parallel_reset, s);

    memory_region_init_io(&s->iomem, NULL, &parallel_mm_ops, s,
                          "parallel", 8 << it_shift);
    memory_region_add_subregion(address_space, base, &s->iomem);
    return true;
}

static Property parallel_isa_properties[] = {
    DEFINE_PROP_UINT32("index", ISAParallelState, index,   -1),
    DEFINE_PROP_UINT32("iobase", ISAParallelState, iobase,  -1),
    DEFINE_PROP_UINT32("irq",   ISAParallelState, isairq,  7),
    DEFINE_PROP_CHR("chardev",  ISAParallelState, state.chr),
    DEFINE_PROP_END_OF_LIST(),
};

static void parallel_isa_class_initfn(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = parallel_isa_realizefn;
    dc->props = parallel_isa_properties;
    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}

static const TypeInfo parallel_isa_info = {
    .name          = TYPE_ISA_PARALLEL,
    .parent        = TYPE_ISA_DEVICE,
    .instance_size = sizeof(ISAParallelState),
    .class_init    = parallel_isa_class_initfn,
};

static void parallel_register_types(void)
{
    type_register_static(&parallel_isa_info);
}

type_init(parallel_register_types)
Commit	Line	Data
6508fe59 FB	1	/*
6508fe59 FB	2	* QEMU Parallel PORT emulation
5fafdf24	3	*
e57a8c0e	4	* Copyright (c) 2003-2005 Fabrice Bellard
5867c88a	5	* Copyright (c) 2007 Marko Kohtala
5fafdf24	6	*
6508fe59 FB	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
83c9f4ca	25	#include "hw/hw.h"
dccfcd0e	26	#include "sysemu/char.h"
0d09e41a PB	27	#include "hw/isa/isa.h"
0d09e41a PB	28	#include "hw/i386/pc.h"
9c17d615	29	#include "sysemu/sysemu.h"
6508fe59 FB	30
	31	//#define DEBUG_PARALLEL
	32
5867c88a	33	#ifdef DEBUG_PARALLEL
001faf32	34	#define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__)
5867c88a	35	#else
001faf32	36	#define pdebug(fmt, ...) ((void)0)
5867c88a TS	37	#endif
	38
	39	#define PARA_REG_DATA 0
	40	#define PARA_REG_STS 1
	41	#define PARA_REG_CTR 2
	42	#define PARA_REG_EPP_ADDR 3
	43	#define PARA_REG_EPP_DATA 4
	44
6508fe59 FB	45	/*
	46	* These are the definitions for the Printer Status Register
	47	*/
	48	#define PARA_STS_BUSY 0x80 /* Busy complement */
	49	#define PARA_STS_ACK 0x40 /* Acknowledge */
	50	#define PARA_STS_PAPER 0x20 /* Out of paper */
	51	#define PARA_STS_ONLINE 0x10 /* Online */
	52	#define PARA_STS_ERROR 0x08 /* Error complement */
5867c88a	53	#define PARA_STS_TMOUT 0x01 /* EPP timeout */
6508fe59 FB	54
	55	/*
	56	* These are the definitions for the Printer Control Register
	57	*/
5867c88a	58	#define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */
6508fe59 FB	59	#define PARA_CTR_INTEN 0x10 /* IRQ Enable */
	60	#define PARA_CTR_SELECT 0x08 /* Select In complement */
	61	#define PARA_CTR_INIT 0x04 /* Initialize Printer complement */
	62	#define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */
	63	#define PARA_CTR_STROBE 0x01 /* Strobe complement */
	64
5867c88a TS	65	#define PARA_CTR_SIGNAL (PARA_CTR_SELECT\|PARA_CTR_INIT\|PARA_CTR_AUTOLF\|PARA_CTR_STROBE)
5867c88a TS	66
defdb20e	67	typedef struct ParallelState {
63858cd9	68	MemoryRegion iomem;
5867c88a TS	69	uint8_t dataw;
	70	uint8_t datar;
	71	uint8_t status;
6508fe59	72	uint8_t control;
d537cf6c	73	qemu_irq irq;
6508fe59 FB	74	int irq_pending;
6508fe59 FB	75	CharDriverState *chr;
e57a8c0e	76	int hw_driver;
5867c88a TS	77	int epp_timeout;
5867c88a TS	78	uint32_t last_read_offset; /* For debugging */
d60532ca	79	/* Memory-mapped interface */
d60532ca	80	int it_shift;
defdb20e	81	} ParallelState;
6508fe59	82
b0dc5ee6 AF	83	#define TYPE_ISA_PARALLEL "isa-parallel"
	84	#define ISA_PARALLEL(obj) \
	85	OBJECT_CHECK(ISAParallelState, (obj), TYPE_ISA_PARALLEL)
	86
021f0674	87	typedef struct ISAParallelState {
b0dc5ee6 AF	88	ISADevice parent_obj;
b0dc5ee6 AF	89
e8ee28fb	90	uint32_t index;
021f0674 GH	91	uint32_t iobase;
	92	uint32_t isairq;
	93	ParallelState state;
	94	} ISAParallelState;
	95
6508fe59 FB	96	static void parallel_update_irq(ParallelState *s)
	97	{
	98	if (s->irq_pending)
d537cf6c	99	qemu_irq_raise(s->irq);
6508fe59	100	else
d537cf6c	101	qemu_irq_lower(s->irq);
6508fe59 FB	102	}
6508fe59 FB	103
5867c88a TS	104	static void
5867c88a TS	105	parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
6508fe59 FB	106	{
6508fe59 FB	107	ParallelState *s = opaque;
3b46e624	108
5867c88a TS	109	pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
	110
	111	addr &= 7;
	112	switch(addr) {
	113	case PARA_REG_DATA:
0fa7f157 TS	114	s->dataw = val;
0fa7f157 TS	115	parallel_update_irq(s);
5867c88a TS	116	break;
5867c88a TS	117	case PARA_REG_CTR:
52ccc5e0	118	val \|= 0xc0;
0fa7f157 TS	119	if ((val & PARA_CTR_INIT) == 0 ) {
	120	s->status = PARA_STS_BUSY;
	121	s->status \|= PARA_STS_ACK;
	122	s->status \|= PARA_STS_ONLINE;
	123	s->status \|= PARA_STS_ERROR;
	124	}
	125	else if (val & PARA_CTR_SELECT) {
	126	if (val & PARA_CTR_STROBE) {
	127	s->status &= ~PARA_STS_BUSY;
	128	if ((s->control & PARA_CTR_STROBE) == 0)
2cc6e0a1	129	qemu_chr_fe_write(s->chr, &s->dataw, 1);
0fa7f157 TS	130	} else {
	131	if (s->control & PARA_CTR_INTEN) {
	132	s->irq_pending = 1;
	133	}
	134	}
	135	}
	136	parallel_update_irq(s);
	137	s->control = val;
5867c88a TS	138	break;
	139	}
	140	}
	141
	142	static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
	143	{
	144	ParallelState *s = opaque;
	145	uint8_t parm = val;
563e3c6e	146	int dir;
5867c88a TS	147
	148	/* Sometimes programs do several writes for timing purposes on old
	149	HW. Take care not to waste time on writes that do nothing. */
	150
	151	s->last_read_offset = ~0U;
	152
6508fe59	153	addr &= 7;
6508fe59	154	switch(addr) {
5867c88a TS	155	case PARA_REG_DATA:
5867c88a TS	156	if (s->dataw == val)
0fa7f157 TS	157	return;
0fa7f157 TS	158	pdebug("wd%02x\n", val);
41084f1b	159	qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
0fa7f157	160	s->dataw = val;
6508fe59	161	break;
5867c88a	162	case PARA_REG_STS:
0fa7f157 TS	163	pdebug("ws%02x\n", val);
	164	if (val & PARA_STS_TMOUT)
	165	s->epp_timeout = 0;
	166	break;
5867c88a TS	167	case PARA_REG_CTR:
	168	val \|= 0xc0;
	169	if (s->control == val)
0fa7f157 TS	170	return;
0fa7f157 TS	171	pdebug("wc%02x\n", val);
563e3c6e AJ	172
	173	if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
	174	if (val & PARA_CTR_DIR) {
	175	dir = 1;
	176	} else {
	177	dir = 0;
	178	}
41084f1b	179	qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
563e3c6e AJ	180	parm &= ~PARA_CTR_DIR;
	181	}
	182
41084f1b	183	qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
0fa7f157	184	s->control = val;
6508fe59	185	break;
5867c88a	186	case PARA_REG_EPP_ADDR:
0fa7f157 TS	187	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
	188	/* Controls not correct for EPP address cycle, so do nothing */
	189	pdebug("wa%02x s\n", val);
	190	else {
	191	struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
41084f1b	192	if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
0fa7f157 TS	193	s->epp_timeout = 1;
	194	pdebug("wa%02x t\n", val);
	195	}
	196	else
	197	pdebug("wa%02x\n", val);
	198	}
	199	break;
5867c88a	200	case PARA_REG_EPP_DATA:
0fa7f157 TS	201	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
	202	/* Controls not correct for EPP data cycle, so do nothing */
	203	pdebug("we%02x s\n", val);
	204	else {
	205	struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
41084f1b	206	if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
0fa7f157 TS	207	s->epp_timeout = 1;
	208	pdebug("we%02x t\n", val);
	209	}
	210	else
	211	pdebug("we%02x\n", val);
	212	}
	213	break;
5867c88a TS	214	}
	215	}
	216
	217	static void
	218	parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
	219	{
	220	ParallelState *s = opaque;
	221	uint16_t eppdata = cpu_to_le16(val);
	222	int err;
	223	struct ParallelIOArg ioarg = {
0fa7f157	224	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	225	};
5867c88a TS	226	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
0fa7f157 TS	227	/* Controls not correct for EPP data cycle, so do nothing */
	228	pdebug("we%04x s\n", val);
	229	return;
5867c88a	230	}
41084f1b	231	err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
5867c88a	232	if (err) {
0fa7f157 TS	233	s->epp_timeout = 1;
0fa7f157 TS	234	pdebug("we%04x t\n", val);
5867c88a TS	235	}
5867c88a TS	236	else
0fa7f157	237	pdebug("we%04x\n", val);
5867c88a TS	238	}
	239
	240	static void
	241	parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
	242	{
	243	ParallelState *s = opaque;
	244	uint32_t eppdata = cpu_to_le32(val);
	245	int err;
	246	struct ParallelIOArg ioarg = {
0fa7f157	247	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	248	};
5867c88a TS	249	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
0fa7f157 TS	250	/* Controls not correct for EPP data cycle, so do nothing */
	251	pdebug("we%08x s\n", val);
	252	return;
5867c88a	253	}
41084f1b	254	err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
5867c88a	255	if (err) {
0fa7f157 TS	256	s->epp_timeout = 1;
0fa7f157 TS	257	pdebug("we%08x t\n", val);
6508fe59	258	}
5867c88a	259	else
0fa7f157	260	pdebug("we%08x\n", val);
6508fe59 FB	261	}
6508fe59 FB	262
5867c88a	263	static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
6508fe59 FB	264	{
	265	ParallelState *s = opaque;
	266	uint32_t ret = 0xff;
	267
	268	addr &= 7;
	269	switch(addr) {
5867c88a	270	case PARA_REG_DATA:
0fa7f157 TS	271	if (s->control & PARA_CTR_DIR)
	272	ret = s->datar;
	273	else
	274	ret = s->dataw;
6508fe59	275	break;
5867c88a	276	case PARA_REG_STS:
0fa7f157 TS	277	ret = s->status;
	278	s->irq_pending = 0;
	279	if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
	280	/* XXX Fixme: wait 5 microseconds */
	281	if (s->status & PARA_STS_ACK)
	282	s->status &= ~PARA_STS_ACK;
	283	else {
	284	/* XXX Fixme: wait 5 microseconds */
	285	s->status \|= PARA_STS_ACK;
	286	s->status \|= PARA_STS_BUSY;
	287	}
	288	}
	289	parallel_update_irq(s);
6508fe59	290	break;
5867c88a	291	case PARA_REG_CTR:
6508fe59 FB	292	ret = s->control;
	293	break;
	294	}
5867c88a TS	295	pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
	296	return ret;
	297	}
	298
	299	static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
	300	{
	301	ParallelState *s = opaque;
	302	uint8_t ret = 0xff;
	303	addr &= 7;
	304	switch(addr) {
	305	case PARA_REG_DATA:
41084f1b	306	qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
0fa7f157 TS	307	if (s->last_read_offset != addr \|\| s->datar != ret)
0fa7f157 TS	308	pdebug("rd%02x\n", ret);
5867c88a TS	309	s->datar = ret;
	310	break;
	311	case PARA_REG_STS:
41084f1b	312	qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
0fa7f157 TS	313	ret &= ~PARA_STS_TMOUT;
	314	if (s->epp_timeout)
	315	ret \|= PARA_STS_TMOUT;
	316	if (s->last_read_offset != addr \|\| s->status != ret)
	317	pdebug("rs%02x\n", ret);
	318	s->status = ret;
5867c88a TS	319	break;
	320	case PARA_REG_CTR:
	321	/* s->control has some bits fixed to 1. It is zero only when
0fa7f157 TS	322	it has not been yet written to. */
0fa7f157 TS	323	if (s->control == 0) {
41084f1b	324	qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
0fa7f157 TS	325	if (s->last_read_offset != addr)
	326	pdebug("rc%02x\n", ret);
	327	s->control = ret;
	328	}
	329	else {
	330	ret = s->control;
	331	if (s->last_read_offset != addr)
	332	pdebug("rc%02x\n", ret);
	333	}
5867c88a TS	334	break;
5867c88a TS	335	case PARA_REG_EPP_ADDR:
0fa7f157 TS	336	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT))
	337	/* Controls not correct for EPP addr cycle, so do nothing */
	338	pdebug("ra%02x s\n", ret);
	339	else {
	340	struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
41084f1b	341	if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
0fa7f157 TS	342	s->epp_timeout = 1;
	343	pdebug("ra%02x t\n", ret);
	344	}
	345	else
	346	pdebug("ra%02x\n", ret);
	347	}
	348	break;
5867c88a	349	case PARA_REG_EPP_DATA:
0fa7f157 TS	350	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT))
	351	/* Controls not correct for EPP data cycle, so do nothing */
	352	pdebug("re%02x s\n", ret);
	353	else {
	354	struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
41084f1b	355	if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
0fa7f157 TS	356	s->epp_timeout = 1;
	357	pdebug("re%02x t\n", ret);
	358	}
	359	else
	360	pdebug("re%02x\n", ret);
	361	}
	362	break;
5867c88a TS	363	}
	364	s->last_read_offset = addr;
	365	return ret;
	366	}
	367
	368	static uint32_t
	369	parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
	370	{
	371	ParallelState *s = opaque;
	372	uint32_t ret;
	373	uint16_t eppdata = ~0;
	374	int err;
	375	struct ParallelIOArg ioarg = {
0fa7f157	376	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	377	};
5867c88a TS	378	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT)) {
0fa7f157 TS	379	/* Controls not correct for EPP data cycle, so do nothing */
	380	pdebug("re%04x s\n", eppdata);
	381	return eppdata;
5867c88a	382	}
41084f1b	383	err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
5867c88a TS	384	ret = le16_to_cpu(eppdata);
	385
	386	if (err) {
0fa7f157 TS	387	s->epp_timeout = 1;
0fa7f157 TS	388	pdebug("re%04x t\n", ret);
5867c88a TS	389	}
5867c88a TS	390	else
0fa7f157	391	pdebug("re%04x\n", ret);
5867c88a TS	392	return ret;
	393	}
	394
	395	static uint32_t
	396	parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
	397	{
	398	ParallelState *s = opaque;
	399	uint32_t ret;
	400	uint32_t eppdata = ~0U;
	401	int err;
	402	struct ParallelIOArg ioarg = {
0fa7f157	403	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	404	};
5867c88a TS	405	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT)) {
0fa7f157 TS	406	/* Controls not correct for EPP data cycle, so do nothing */
	407	pdebug("re%08x s\n", eppdata);
	408	return eppdata;
5867c88a	409	}
41084f1b	410	err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
5867c88a TS	411	ret = le32_to_cpu(eppdata);
	412
	413	if (err) {
0fa7f157 TS	414	s->epp_timeout = 1;
0fa7f157 TS	415	pdebug("re%08x t\n", ret);
5867c88a TS	416	}
5867c88a TS	417	else
0fa7f157	418	pdebug("re%08x\n", ret);
5867c88a TS	419	return ret;
	420	}
	421
	422	static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
	423	{
7f5b7d3e	424	pdebug("wecp%d=%02x\n", addr & 7, val);
5867c88a TS	425	}
	426
	427	static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
	428	{
	429	uint8_t ret = 0xff;
7f5b7d3e BS	430
7f5b7d3e BS	431	pdebug("recp%d:%02x\n", addr & 7, ret);
6508fe59 FB	432	return ret;
	433	}
	434
33093a0a	435	static void parallel_reset(void *opaque)
6508fe59	436	{
33093a0a AJ	437	ParallelState *s = opaque;
33093a0a AJ	438
5867c88a TS	439	s->datar = ~0;
5867c88a TS	440	s->dataw = ~0;
6508fe59 FB	441	s->status = PARA_STS_BUSY;
	442	s->status \|= PARA_STS_ACK;
	443	s->status \|= PARA_STS_ONLINE;
	444	s->status \|= PARA_STS_ERROR;
52ccc5e0	445	s->status \|= PARA_STS_TMOUT;
6508fe59 FB	446	s->control = PARA_CTR_SELECT;
6508fe59 FB	447	s->control \|= PARA_CTR_INIT;
52ccc5e0	448	s->control \|= 0xc0;
5867c88a	449	s->irq_pending = 0;
5867c88a TS	450	s->hw_driver = 0;
	451	s->epp_timeout = 0;
	452	s->last_read_offset = ~0U;
d60532ca TS	453	}
d60532ca TS	454
e8ee28fb GH	455	static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
e8ee28fb GH	456
1922abd0 RH	457	static const MemoryRegionPortio isa_parallel_portio_hw_list[] = {
	458	{ 0, 8, 1,
	459	.read = parallel_ioport_read_hw,
	460	.write = parallel_ioport_write_hw },
	461	{ 4, 1, 2,
	462	.read = parallel_ioport_eppdata_read_hw2,
	463	.write = parallel_ioport_eppdata_write_hw2 },
	464	{ 4, 1, 4,
	465	.read = parallel_ioport_eppdata_read_hw4,
	466	.write = parallel_ioport_eppdata_write_hw4 },
	467	{ 0x400, 8, 1,
	468	.read = parallel_ioport_ecp_read,
	469	.write = parallel_ioport_ecp_write },
	470	PORTIO_END_OF_LIST(),
	471	};
	472
	473	static const MemoryRegionPortio isa_parallel_portio_sw_list[] = {
	474	{ 0, 8, 1,
	475	.read = parallel_ioport_read_sw,
	476	.write = parallel_ioport_write_sw },
	477	PORTIO_END_OF_LIST(),
	478	};
	479
db895a1e	480	static void parallel_isa_realizefn(DeviceState dev, Error *errp)
d60532ca	481	{
e8ee28fb	482	static int index;
db895a1e	483	ISADevice *isadev = ISA_DEVICE(dev);
b0dc5ee6	484	ISAParallelState *isa = ISA_PARALLEL(dev);
021f0674	485	ParallelState *s = &isa->state;
e8ee28fb	486	int base;
d60532ca TS	487	uint8_t dummy;
d60532ca TS	488
021f0674	489	if (!s->chr) {
db895a1e AF	490	error_setg(errp, "Can't create parallel device, empty char device");
db895a1e AF	491	return;
021f0674 GH	492	}
021f0674 GH	493
db895a1e	494	if (isa->index == -1) {
e8ee28fb	495	isa->index = index;
db895a1e AF	496	}
	497	if (isa->index >= MAX_PARALLEL_PORTS) {
	498	error_setg(errp, "Max. supported number of parallel ports is %d.",
	499	MAX_PARALLEL_PORTS);
	500	return;
	501	}
	502	if (isa->iobase == -1) {
e8ee28fb	503	isa->iobase = isa_parallel_io[isa->index];
db895a1e	504	}
e8ee28fb GH	505	index++;
	506
	507	base = isa->iobase;
db895a1e	508	isa_init_irq(isadev, &s->irq, isa->isairq);
a08d4367	509	qemu_register_reset(parallel_reset, s);
6508fe59	510
41084f1b	511	if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
5867c88a	512	s->hw_driver = 1;
0fa7f157	513	s->status = dummy;
5867c88a TS	514	}
5867c88a TS	515
db895a1e	516	isa_register_portio_list(isadev, base,
1922abd0 RH	517	(s->hw_driver
	518	? &isa_parallel_portio_hw_list[0]
	519	: &isa_parallel_portio_sw_list[0]),
	520	s, "parallel");
021f0674 GH	521	}
021f0674 GH	522
d60532ca	523	/* Memory mapped interface */
a8170e5e	524	static uint32_t parallel_mm_readb (void *opaque, hwaddr addr)
d60532ca TS	525	{
	526	ParallelState *s = opaque;
	527
8da3ff18	528	return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF;
d60532ca TS	529	}
d60532ca TS	530
9596ebb7	531	static void parallel_mm_writeb (void *opaque,
a8170e5e	532	hwaddr addr, uint32_t value)
d60532ca TS	533	{
	534	ParallelState *s = opaque;
	535
8da3ff18	536	parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
d60532ca TS	537	}
d60532ca TS	538
a8170e5e	539	static uint32_t parallel_mm_readw (void *opaque, hwaddr addr)
d60532ca TS	540	{
	541	ParallelState *s = opaque;
	542
8da3ff18	543	return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF;
d60532ca TS	544	}
d60532ca TS	545
9596ebb7	546	static void parallel_mm_writew (void *opaque,
a8170e5e	547	hwaddr addr, uint32_t value)
d60532ca TS	548	{
	549	ParallelState *s = opaque;
	550
8da3ff18	551	parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
d60532ca TS	552	}
d60532ca TS	553
a8170e5e	554	static uint32_t parallel_mm_readl (void *opaque, hwaddr addr)
d60532ca TS	555	{
	556	ParallelState *s = opaque;
	557
8da3ff18	558	return parallel_ioport_read_sw(s, addr >> s->it_shift);
d60532ca TS	559	}
d60532ca TS	560
9596ebb7	561	static void parallel_mm_writel (void *opaque,
a8170e5e	562	hwaddr addr, uint32_t value)
d60532ca TS	563	{
	564	ParallelState *s = opaque;
	565
8da3ff18	566	parallel_ioport_write_sw(s, addr >> s->it_shift, value);
d60532ca TS	567	}
d60532ca TS	568
63858cd9 AK	569	static const MemoryRegionOps parallel_mm_ops = {
	570	.old_mmio = {
	571	.read = { parallel_mm_readb, parallel_mm_readw, parallel_mm_readl },
	572	.write = { parallel_mm_writeb, parallel_mm_writew, parallel_mm_writel },
	573	},
	574	.endianness = DEVICE_NATIVE_ENDIAN,
d60532ca TS	575	};
	576
	577	/* If fd is zero, it means that the parallel device uses the console */
63858cd9	578	bool parallel_mm_init(MemoryRegion *address_space,
a8170e5e	579	hwaddr base, int it_shift, qemu_irq irq,
defdb20e	580	CharDriverState *chr)
d60532ca TS	581	{
d60532ca TS	582	ParallelState *s;
d60532ca	583
7267c094	584	s = g_malloc0(sizeof(ParallelState));
33093a0a AJ	585	s->irq = irq;
33093a0a AJ	586	s->chr = chr;
d60532ca	587	s->it_shift = it_shift;
a08d4367	588	qemu_register_reset(parallel_reset, s);
d60532ca	589
2c9b15ca	590	memory_region_init_io(&s->iomem, NULL, &parallel_mm_ops, s,
63858cd9 AK	591	"parallel", 8 << it_shift);
63858cd9 AK	592	memory_region_add_subregion(address_space, base, &s->iomem);
defdb20e	593	return true;
d60532ca	594	}
021f0674	595
39bffca2 AL	596	static Property parallel_isa_properties[] = {
39bffca2 AL	597	DEFINE_PROP_UINT32("index", ISAParallelState, index, -1),
c7bcc85d	598	DEFINE_PROP_UINT32("iobase", ISAParallelState, iobase, -1),
39bffca2 AL	599	DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7),
	600	DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr),
	601	DEFINE_PROP_END_OF_LIST(),
	602	};
	603
8f04ee08 AL	604	static void parallel_isa_class_initfn(ObjectClass klass, void data)
8f04ee08 AL	605	{
39bffca2	606	DeviceClass *dc = DEVICE_CLASS(klass);
db895a1e AF	607
db895a1e AF	608	dc->realize = parallel_isa_realizefn;
39bffca2	609	dc->props = parallel_isa_properties;
125ee0ed	610	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
8f04ee08 AL	611	}
8f04ee08 AL	612
8c43a6f0	613	static const TypeInfo parallel_isa_info = {
b0dc5ee6	614	.name = TYPE_ISA_PARALLEL,
39bffca2 AL	615	.parent = TYPE_ISA_DEVICE,
	616	.instance_size = sizeof(ISAParallelState),
	617	.class_init = parallel_isa_class_initfn,
021f0674 GH	618	};
021f0674 GH	619
83f7d43a	620	static void parallel_register_types(void)
021f0674	621	{
39bffca2	622	type_register_static(&parallel_isa_info);
021f0674 GH	623	}
021f0674 GH	624
83f7d43a	625	type_init(parallel_register_types)