[qemu.git] / hw / intc / grlib_irqmp.c

/*
 * QEMU GRLIB IRQMP Emulator
 *
 * (Multiprocessor and extended interrupt not supported)
 *
 * Copyright (c) 2010-2011 AdaCore
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "hw/sysbus.h"
#include "cpu.h"

#include "hw/sparc/grlib.h"

#include "trace.h"

#define IRQMP_MAX_CPU 16
#define IRQMP_REG_SIZE 256      /* Size of memory mapped registers */

/* Memory mapped register offsets */
#define LEVEL_OFFSET     0x00
#define PENDING_OFFSET   0x04
#define FORCE0_OFFSET    0x08
#define CLEAR_OFFSET     0x0C
#define MP_STATUS_OFFSET 0x10
#define BROADCAST_OFFSET 0x14
#define MASK_OFFSET      0x40
#define FORCE_OFFSET     0x80
#define EXTENDED_OFFSET  0xC0

#define TYPE_GRLIB_IRQMP "grlib,irqmp"
#define GRLIB_IRQMP(obj) OBJECT_CHECK(IRQMP, (obj), TYPE_GRLIB_IRQMP)

typedef struct IRQMPState IRQMPState;

typedef struct IRQMP {
    SysBusDevice parent_obj;

    MemoryRegion iomem;

    void *set_pil_in;
    void *set_pil_in_opaque;

    IRQMPState *state;
} IRQMP;

struct IRQMPState {
    uint32_t level;
    uint32_t pending;
    uint32_t clear;
    uint32_t broadcast;

    uint32_t mask[IRQMP_MAX_CPU];
    uint32_t force[IRQMP_MAX_CPU];
    uint32_t extended[IRQMP_MAX_CPU];

    IRQMP    *parent;
};

static void grlib_irqmp_check_irqs(IRQMPState *state)
{
    uint32_t      pend   = 0;
    uint32_t      level0 = 0;
    uint32_t      level1 = 0;
    set_pil_in_fn set_pil_in;

    assert(state != NULL);
    assert(state->parent != NULL);

    /* IRQ for CPU 0 (no SMP support) */
    pend = (state->pending | state->force[0])
        & state->mask[0];

    level0 = pend & ~state->level;
    level1 = pend &  state->level;

    trace_grlib_irqmp_check_irqs(state->pending, state->force[0],
                                 state->mask[0], level1, level0);

    set_pil_in = (set_pil_in_fn)state->parent->set_pil_in;

    /* Trigger level1 interrupt first and level0 if there is no level1 */
    if (level1 != 0) {
        set_pil_in(state->parent->set_pil_in_opaque, level1);
    } else {
        set_pil_in(state->parent->set_pil_in_opaque, level0);
    }
}

void grlib_irqmp_ack(DeviceState *dev, int intno)
{
    IRQMP        *irqmp = GRLIB_IRQMP(dev);
    IRQMPState   *state;
    uint32_t      mask;

    state = irqmp->state;
    assert(state != NULL);

    intno &= 15;
    mask = 1 << intno;

    trace_grlib_irqmp_ack(intno);

    /* Clear registers */
    state->pending  &= ~mask;
    state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */

    grlib_irqmp_check_irqs(state);
}

void grlib_irqmp_set_irq(void *opaque, int irq, int level)
{
    IRQMP      *irqmp = GRLIB_IRQMP(opaque);
    IRQMPState *s;
    int         i = 0;

    s = irqmp->state;
    assert(s         != NULL);
    assert(s->parent != NULL);


    if (level) {
        trace_grlib_irqmp_set_irq(irq);

        if (s->broadcast & 1 << irq) {
            /* Broadcasted IRQ */
            for (i = 0; i < IRQMP_MAX_CPU; i++) {
                s->force[i] |= 1 << irq;
            }
        } else {
            s->pending |= 1 << irq;
        }
        grlib_irqmp_check_irqs(s);

    }
}

static uint64_t grlib_irqmp_read(void *opaque, hwaddr addr,
                                 unsigned size)
{
    IRQMP      *irqmp = opaque;
    IRQMPState *state;

    assert(irqmp != NULL);
    state = irqmp->state;
    assert(state != NULL);

    addr &= 0xff;

    /* global registers */
    switch (addr) {
    case LEVEL_OFFSET:
        return state->level;

    case PENDING_OFFSET:
        return state->pending;

    case FORCE0_OFFSET:
        /* This register is an "alias" for the force register of CPU 0 */
        return state->force[0];

    case CLEAR_OFFSET:
    case MP_STATUS_OFFSET:
        /* Always read as 0 */
        return 0;

    case BROADCAST_OFFSET:
        return state->broadcast;

    default:
        break;
    }

    /* mask registers */
    if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) {
        int cpu = (addr - MASK_OFFSET) / 4;
        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);

        return state->mask[cpu];
    }

    /* force registers */
    if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) {
        int cpu = (addr - FORCE_OFFSET) / 4;
        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);

        return state->force[cpu];
    }

    /* extended (not supported) */
    if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) {
        int cpu = (addr - EXTENDED_OFFSET) / 4;
        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);

        return state->extended[cpu];
    }

    trace_grlib_irqmp_readl_unknown(addr);
    return 0;
}

static void grlib_irqmp_write(void *opaque, hwaddr addr,
                              uint64_t value, unsigned size)
{
    IRQMP      *irqmp = opaque;
    IRQMPState *state;

    assert(irqmp != NULL);
    state = irqmp->state;
    assert(state != NULL);

    addr &= 0xff;

    /* global registers */
    switch (addr) {
    case LEVEL_OFFSET:
        value &= 0xFFFF << 1; /* clean up the value */
        state->level = value;
        return;

    case PENDING_OFFSET:
        /* Read Only */
        return;

    case FORCE0_OFFSET:
        /* This register is an "alias" for the force register of CPU 0 */

        value &= 0xFFFE; /* clean up the value */
        state->force[0] = value;
        grlib_irqmp_check_irqs(irqmp->state);
        return;

    case CLEAR_OFFSET:
        value &= ~1; /* clean up the value */
        state->pending &= ~value;
        return;

    case MP_STATUS_OFFSET:
        /* Read Only (no SMP support) */
        return;

    case BROADCAST_OFFSET:
        value &= 0xFFFE; /* clean up the value */
        state->broadcast = value;
        return;

    default:
        break;
    }

    /* mask registers */
    if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) {
        int cpu = (addr - MASK_OFFSET) / 4;
        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);

        value &= ~1; /* clean up the value */
        state->mask[cpu] = value;
        grlib_irqmp_check_irqs(irqmp->state);
        return;
    }

    /* force registers */
    if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) {
        int cpu = (addr - FORCE_OFFSET) / 4;
        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);

        uint32_t force = value & 0xFFFE;
        uint32_t clear = (value >> 16) & 0xFFFE;
        uint32_t old   = state->force[cpu];

        state->force[cpu] = (old | force) & ~clear;
        grlib_irqmp_check_irqs(irqmp->state);
        return;
    }

    /* extended (not supported) */
    if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) {
        int cpu = (addr - EXTENDED_OFFSET) / 4;
        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);

        value &= 0xF; /* clean up the value */
        state->extended[cpu] = value;
        return;
    }

    trace_grlib_irqmp_writel_unknown(addr, value);
}

static const MemoryRegionOps grlib_irqmp_ops = {
    .read = grlib_irqmp_read,
    .write = grlib_irqmp_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static void grlib_irqmp_reset(DeviceState *d)
{
    IRQMP *irqmp = GRLIB_IRQMP(d);
    assert(irqmp->state != NULL);

    memset(irqmp->state, 0, sizeof *irqmp->state);
    irqmp->state->parent = irqmp;
}

static int grlib_irqmp_init(SysBusDevice *dev)
{
    IRQMP *irqmp = GRLIB_IRQMP(dev);

    /* Check parameters */
    if (irqmp->set_pil_in == NULL) {
        return -1;
    }

    memory_region_init_io(&irqmp->iomem, OBJECT(dev), &grlib_irqmp_ops, irqmp,
                          "irqmp", IRQMP_REG_SIZE);

    irqmp->state = g_malloc0(sizeof *irqmp->state);

    sysbus_init_mmio(dev, &irqmp->iomem);

    return 0;
}

static Property grlib_irqmp_properties[] = {
    DEFINE_PROP_PTR("set_pil_in", IRQMP, set_pil_in),
    DEFINE_PROP_PTR("set_pil_in_opaque", IRQMP, set_pil_in_opaque),
    DEFINE_PROP_END_OF_LIST(),
};

static void grlib_irqmp_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = grlib_irqmp_init;
    dc->reset = grlib_irqmp_reset;
    dc->props = grlib_irqmp_properties;
    /* Reason: pointer properties "set_pil_in", "set_pil_in_opaque" */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo grlib_irqmp_info = {
    .name          = TYPE_GRLIB_IRQMP,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(IRQMP),
    .class_init    = grlib_irqmp_class_init,
};

static void grlib_irqmp_register_types(void)
{
    type_register_static(&grlib_irqmp_info);
}

type_init(grlib_irqmp_register_types)
Commit	Line	Data
3f10bcbb FC	1	/*
	2	* QEMU GRLIB IRQMP Emulator
	3	*
	4	* (Multiprocessor and extended interrupt not supported)
	5	*
	6	* Copyright (c) 2010-2011 AdaCore
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*/
	26
83c9f4ca	27	#include "hw/sysbus.h"
3f10bcbb FC	28	#include "cpu.h"
3f10bcbb FC	29
0d09e41a	30	#include "hw/sparc/grlib.h"
3f10bcbb FC	31
	32	#include "trace.h"
	33
	34	#define IRQMP_MAX_CPU 16
	35	#define IRQMP_REG_SIZE 256 /* Size of memory mapped registers */
	36
	37	/* Memory mapped register offsets */
	38	#define LEVEL_OFFSET 0x00
	39	#define PENDING_OFFSET 0x04
	40	#define FORCE0_OFFSET 0x08
	41	#define CLEAR_OFFSET 0x0C
	42	#define MP_STATUS_OFFSET 0x10
	43	#define BROADCAST_OFFSET 0x14
	44	#define MASK_OFFSET 0x40
	45	#define FORCE_OFFSET 0x80
	46	#define EXTENDED_OFFSET 0xC0
	47
730bf932 AF	48	#define TYPE_GRLIB_IRQMP "grlib,irqmp"
	49	#define GRLIB_IRQMP(obj) OBJECT_CHECK(IRQMP, (obj), TYPE_GRLIB_IRQMP)
	50
3f10bcbb FC	51	typedef struct IRQMPState IRQMPState;
	52
	53	typedef struct IRQMP {
730bf932 AF	54	SysBusDevice parent_obj;
730bf932 AF	55
847b52c1	56	MemoryRegion iomem;
3f10bcbb FC	57
	58	void *set_pil_in;
	59	void *set_pil_in_opaque;
	60
	61	IRQMPState *state;
	62	} IRQMP;
	63
	64	struct IRQMPState {
	65	uint32_t level;
	66	uint32_t pending;
	67	uint32_t clear;
	68	uint32_t broadcast;
	69
	70	uint32_t mask[IRQMP_MAX_CPU];
	71	uint32_t force[IRQMP_MAX_CPU];
	72	uint32_t extended[IRQMP_MAX_CPU];
	73
	74	IRQMP *parent;
	75	};
	76
	77	static void grlib_irqmp_check_irqs(IRQMPState *state)
	78	{
	79	uint32_t pend = 0;
	80	uint32_t level0 = 0;
	81	uint32_t level1 = 0;
	82	set_pil_in_fn set_pil_in;
	83
	84	assert(state != NULL);
	85	assert(state->parent != NULL);
	86
	87	/* IRQ for CPU 0 (no SMP support) */
	88	pend = (state->pending \| state->force[0])
	89	& state->mask[0];
	90
	91	level0 = pend & ~state->level;
	92	level1 = pend & state->level;
	93
	94	trace_grlib_irqmp_check_irqs(state->pending, state->force[0],
	95	state->mask[0], level1, level0);
	96
	97	set_pil_in = (set_pil_in_fn)state->parent->set_pil_in;
	98
	99	/* Trigger level1 interrupt first and level0 if there is no level1 */
	100	if (level1 != 0) {
	101	set_pil_in(state->parent->set_pil_in_opaque, level1);
	102	} else {
	103	set_pil_in(state->parent->set_pil_in_opaque, level0);
	104	}
	105	}
	106
	107	void grlib_irqmp_ack(DeviceState *dev, int intno)
	108	{
730bf932	109	IRQMP *irqmp = GRLIB_IRQMP(dev);
3f10bcbb FC	110	IRQMPState *state;
	111	uint32_t mask;
	112
3f10bcbb FC	113	state = irqmp->state;
	114	assert(state != NULL);
	115
	116	intno &= 15;
	117	mask = 1 << intno;
	118
	119	trace_grlib_irqmp_ack(intno);
	120
	121	/* Clear registers */
	122	state->pending &= ~mask;
	123	state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */
	124
	125	grlib_irqmp_check_irqs(state);
	126	}
	127
	128	void grlib_irqmp_set_irq(void *opaque, int irq, int level)
	129	{
730bf932	130	IRQMP *irqmp = GRLIB_IRQMP(opaque);
3f10bcbb FC	131	IRQMPState *s;
	132	int i = 0;
	133
3f10bcbb FC	134	s = irqmp->state;
	135	assert(s != NULL);
	136	assert(s->parent != NULL);
	137
	138
	139	if (level) {
	140	trace_grlib_irqmp_set_irq(irq);
	141
	142	if (s->broadcast & 1 << irq) {
	143	/* Broadcasted IRQ */
	144	for (i = 0; i < IRQMP_MAX_CPU; i++) {
	145	s->force[i] \|= 1 << irq;
	146	}
	147	} else {
	148	s->pending \|= 1 << irq;
	149	}
	150	grlib_irqmp_check_irqs(s);
	151
	152	}
	153	}
	154
a8170e5e	155	static uint64_t grlib_irqmp_read(void *opaque, hwaddr addr,
847b52c1	156	unsigned size)
3f10bcbb FC	157	{
	158	IRQMP *irqmp = opaque;
	159	IRQMPState *state;
	160
	161	assert(irqmp != NULL);
	162	state = irqmp->state;
	163	assert(state != NULL);
	164
	165	addr &= 0xff;
	166
	167	/* global registers */
	168	switch (addr) {
	169	case LEVEL_OFFSET:
	170	return state->level;
	171
	172	case PENDING_OFFSET:
	173	return state->pending;
	174
	175	case FORCE0_OFFSET:
	176	/* This register is an "alias" for the force register of CPU 0 */
	177	return state->force[0];
	178
	179	case CLEAR_OFFSET:
	180	case MP_STATUS_OFFSET:
	181	/* Always read as 0 */
	182	return 0;
	183
	184	case BROADCAST_OFFSET:
	185	return state->broadcast;
	186
	187	default:
	188	break;
	189	}
	190
	191	/* mask registers */
	192	if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) {
	193	int cpu = (addr - MASK_OFFSET) / 4;
	194	assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
	195
	196	return state->mask[cpu];
	197	}
	198
	199	/* force registers */
	200	if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) {
	201	int cpu = (addr - FORCE_OFFSET) / 4;
	202	assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
	203
	204	return state->force[cpu];
	205	}
	206
	207	/* extended (not supported) */
	208	if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) {
	209	int cpu = (addr - EXTENDED_OFFSET) / 4;
	210	assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
	211
	212	return state->extended[cpu];
	213	}
	214
b4548fcc	215	trace_grlib_irqmp_readl_unknown(addr);
3f10bcbb FC	216	return 0;
	217	}
	218
a8170e5e	219	static void grlib_irqmp_write(void *opaque, hwaddr addr,
847b52c1	220	uint64_t value, unsigned size)
3f10bcbb FC	221	{
	222	IRQMP *irqmp = opaque;
	223	IRQMPState *state;
	224
	225	assert(irqmp != NULL);
	226	state = irqmp->state;
	227	assert(state != NULL);
	228
	229	addr &= 0xff;
	230
	231	/* global registers */
	232	switch (addr) {
	233	case LEVEL_OFFSET:
	234	value &= 0xFFFF << 1; /* clean up the value */
	235	state->level = value;
	236	return;
	237
	238	case PENDING_OFFSET:
	239	/* Read Only */
	240	return;
	241
	242	case FORCE0_OFFSET:
	243	/* This register is an "alias" for the force register of CPU 0 */
	244
	245	value &= 0xFFFE; /* clean up the value */
	246	state->force[0] = value;
	247	grlib_irqmp_check_irqs(irqmp->state);
	248	return;
	249
	250	case CLEAR_OFFSET:
	251	value &= ~1; /* clean up the value */
	252	state->pending &= ~value;
	253	return;
	254
	255	case MP_STATUS_OFFSET:
	256	/* Read Only (no SMP support) */
	257	return;
	258
	259	case BROADCAST_OFFSET:
	260	value &= 0xFFFE; /* clean up the value */
	261	state->broadcast = value;
	262	return;
	263
	264	default:
	265	break;
	266	}
	267
	268	/* mask registers */
	269	if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) {
	270	int cpu = (addr - MASK_OFFSET) / 4;
	271	assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
	272
	273	value &= ~1; /* clean up the value */
	274	state->mask[cpu] = value;
	275	grlib_irqmp_check_irqs(irqmp->state);
	276	return;
	277	}
	278
	279	/* force registers */
	280	if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) {
	281	int cpu = (addr - FORCE_OFFSET) / 4;
	282	assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
	283
	284	uint32_t force = value & 0xFFFE;
285	uint32_t clear = (value >> 16) & 0xFFFE;
286	uint32_t old = state->force[cpu];
287
288	state->force[cpu] = (old \| force) & ~clear;
289	grlib_irqmp_check_irqs(irqmp->state);
290	return;
291	}
292
293	/* extended (not supported) */
294	if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) {
295	int cpu = (addr - EXTENDED_OFFSET) / 4;
296	assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
297
298	value &= 0xF; /* clean up the value */
299	state->extended[cpu] = value;
300	return;
301	}
302
b4548fcc	303	trace_grlib_irqmp_writel_unknown(addr, value);
3f10bcbb FC	304	}
3f10bcbb FC	305
847b52c1 AK	306	static const MemoryRegionOps grlib_irqmp_ops = {
	307	.read = grlib_irqmp_read,
	308	.write = grlib_irqmp_write,
	309	.endianness = DEVICE_NATIVE_ENDIAN,
	310	.valid = {
	311	.min_access_size = 4,
	312	.max_access_size = 4,
	313	},
3f10bcbb FC	314	};
	315
	316	static void grlib_irqmp_reset(DeviceState *d)
	317	{
730bf932	318	IRQMP *irqmp = GRLIB_IRQMP(d);
3f10bcbb FC	319	assert(irqmp->state != NULL);
	320
	321	memset(irqmp->state, 0, sizeof *irqmp->state);
	322	irqmp->state->parent = irqmp;
	323	}
	324
	325	static int grlib_irqmp_init(SysBusDevice *dev)
	326	{
730bf932	327	IRQMP *irqmp = GRLIB_IRQMP(dev);
3f10bcbb FC	328
	329	/* Check parameters */
	330	if (irqmp->set_pil_in == NULL) {
	331	return -1;
	332	}
	333
1437c94b	334	memory_region_init_io(&irqmp->iomem, OBJECT(dev), &grlib_irqmp_ops, irqmp,
847b52c1	335	"irqmp", IRQMP_REG_SIZE);
3f10bcbb	336
7267c094	337	irqmp->state = g_malloc0(sizeof *irqmp->state);
3f10bcbb	338
750ecd44	339	sysbus_init_mmio(dev, &irqmp->iomem);
3f10bcbb FC	340
	341	return 0;
	342	}
	343
999e12bb AL	344	static Property grlib_irqmp_properties[] = {
	345	DEFINE_PROP_PTR("set_pil_in", IRQMP, set_pil_in),
	346	DEFINE_PROP_PTR("set_pil_in_opaque", IRQMP, set_pil_in_opaque),
	347	DEFINE_PROP_END_OF_LIST(),
	348	};
	349
	350	static void grlib_irqmp_class_init(ObjectClass klass, void data)
	351	{
39bffca2	352	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	353	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	354
	355	k->init = grlib_irqmp_init;
39bffca2 AL	356	dc->reset = grlib_irqmp_reset;
39bffca2 AL	357	dc->props = grlib_irqmp_properties;
1b111dc1 MA	358	/* Reason: pointer properties "set_pil_in", "set_pil_in_opaque" */
1b111dc1 MA	359	dc->cannot_instantiate_with_device_add_yet = true;
999e12bb AL	360	}
999e12bb AL	361
8c43a6f0	362	static const TypeInfo grlib_irqmp_info = {
730bf932	363	.name = TYPE_GRLIB_IRQMP,
39bffca2 AL	364	.parent = TYPE_SYS_BUS_DEVICE,
	365	.instance_size = sizeof(IRQMP),
	366	.class_init = grlib_irqmp_class_init,
3f10bcbb FC	367	};
3f10bcbb FC	368
83f7d43a	369	static void grlib_irqmp_register_types(void)
3f10bcbb	370	{
39bffca2	371	type_register_static(&grlib_irqmp_info);
3f10bcbb FC	372	}
3f10bcbb FC	373
83f7d43a	374	type_init(grlib_irqmp_register_types)