[qemu.git] / target-sparc / helper.c

/*
 *  sparc helpers
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include "exec.h"

//#define DEBUG_PCALL
//#define DEBUG_MMU

/* Sparc MMU emulation */

/* thread support */

spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;

void cpu_lock(void)
{
    spin_lock(&global_cpu_lock);
}

void cpu_unlock(void)
{
    spin_unlock(&global_cpu_lock);
}

#if defined(CONFIG_USER_ONLY) 

int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
                               int is_user, int is_softmmu)
{
    env->mmuregs[4] = address;
    if (rw & 2)
        env->exception_index = TT_TFAULT;
    else
        env->exception_index = TT_DFAULT;
    return 1;
}

#else

#define MMUSUFFIX _mmu
#define GETPC() (__builtin_return_address(0))

#define SHIFT 0
#include "softmmu_template.h"

#define SHIFT 1
#include "softmmu_template.h"

#define SHIFT 2
#include "softmmu_template.h"

#define SHIFT 3
#include "softmmu_template.h"


/* try to fill the TLB and return an exception if error. If retaddr is
   NULL, it means that the function was called in C code (i.e. not
   from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
{
    TranslationBlock *tb;
    int ret;
    unsigned long pc;
    CPUState *saved_env;

    /* XXX: hack to restore env in all cases, even if not called from
       generated code */
    saved_env = env;
    env = cpu_single_env;

    ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, is_user, 1);
    if (ret) {
        if (retaddr) {
            /* now we have a real cpu fault */
            pc = (unsigned long)retaddr;
            tb = tb_find_pc(pc);
            if (tb) {
                /* the PC is inside the translated code. It means that we have
                   a virtual CPU fault */
                cpu_restore_state(tb, env, pc, (void *)T2);
            }
        }
        cpu_loop_exit();
    }
    env = saved_env;
}

static const int access_table[8][8] = {
    { 0, 0, 0, 0, 2, 0, 3, 3 },
    { 0, 0, 0, 0, 2, 0, 0, 0 },
    { 2, 2, 0, 0, 0, 2, 3, 3 },
    { 2, 2, 0, 0, 0, 2, 0, 0 },
    { 2, 0, 2, 0, 2, 2, 3, 3 },
    { 2, 0, 2, 0, 2, 0, 2, 0 },
    { 2, 2, 2, 0, 2, 2, 3, 3 },
    { 2, 2, 2, 0, 2, 2, 2, 0 }
};

/* 1 = write OK */
static const int rw_table[2][8] = {
    { 0, 1, 0, 1, 0, 1, 0, 1 },
    { 0, 1, 0, 1, 0, 0, 0, 0 }
};

int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
			  int *access_index, target_ulong address, int rw,
			  int is_user)
{
    int access_perms = 0;
    target_phys_addr_t pde_ptr;
    uint32_t pde;
    target_ulong virt_addr;
    int error_code = 0, is_dirty;
    unsigned long page_offset;

    virt_addr = address & TARGET_PAGE_MASK;
    if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
	*physical = address;
        *prot = PAGE_READ | PAGE_WRITE;
        return 0;
    }

    *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
    *physical = 0xfffff000;

    /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
    /* Context base + context number */
    pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 4);
    pde = ldl_phys(pde_ptr);

    /* Ctx pde */
    switch (pde & PTE_ENTRYTYPE_MASK) {
    default:
    case 0: /* Invalid */
	return 1 << 2;
    case 2: /* L0 PTE, maybe should not happen? */
    case 3: /* Reserved */
        return 4 << 2;
    case 1: /* L0 PDE */
	pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
        pde = ldl_phys(pde_ptr);

	switch (pde & PTE_ENTRYTYPE_MASK) {
	default:
	case 0: /* Invalid */
	    return (1 << 8) | (1 << 2);
	case 3: /* Reserved */
	    return (1 << 8) | (4 << 2);
	case 1: /* L1 PDE */
	    pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
            pde = ldl_phys(pde_ptr);

	    switch (pde & PTE_ENTRYTYPE_MASK) {
	    default:
	    case 0: /* Invalid */
		return (2 << 8) | (1 << 2);
	    case 3: /* Reserved */
		return (2 << 8) | (4 << 2);
	    case 1: /* L2 PDE */
		pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
                pde = ldl_phys(pde_ptr);

		switch (pde & PTE_ENTRYTYPE_MASK) {
		default:
		case 0: /* Invalid */
		    return (3 << 8) | (1 << 2);
		case 1: /* PDE, should not happen */
		case 3: /* Reserved */
		    return (3 << 8) | (4 << 2);
		case 2: /* L3 PTE */
		    virt_addr = address & TARGET_PAGE_MASK;
		    page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
		}
		break;
	    case 2: /* L2 PTE */
		virt_addr = address & ~0x3ffff;
		page_offset = address & 0x3ffff;
	    }
	    break;
	case 2: /* L1 PTE */
	    virt_addr = address & ~0xffffff;
	    page_offset = address & 0xffffff;
	}
    }

    /* update page modified and dirty bits */
    is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
    if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
	pde |= PG_ACCESSED_MASK;
	if (is_dirty)
	    pde |= PG_MODIFIED_MASK;
        stl_phys_notdirty(pde_ptr, pde);
    }
    /* check access */
    access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
    error_code = access_table[*access_index][access_perms];
    if (error_code && !(env->mmuregs[0] & MMU_NF))
	return error_code;

    /* the page can be put in the TLB */
    *prot = PAGE_READ;
    if (pde & PG_MODIFIED_MASK) {
        /* only set write access if already dirty... otherwise wait
           for dirty access */
	if (rw_table[is_user][access_perms])
	        *prot |= PAGE_WRITE;
    }

    /* Even if large ptes, we map only one 4KB page in the cache to
       avoid filling it too fast */
    *physical = ((pde & PTE_ADDR_MASK) << 4) + page_offset;
    return error_code;
}

/* Perform address translation */
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                              int is_user, int is_softmmu)
{
    target_ulong virt_addr;
    target_phys_addr_t paddr;
    unsigned long vaddr;
    int error_code = 0, prot, ret = 0, access_index;

    error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
    if (error_code == 0) {
	virt_addr = address & TARGET_PAGE_MASK;
	vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
	ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
	return ret;
    }

    if (env->mmuregs[3]) /* Fault status register */
	env->mmuregs[3] = 1; /* overflow (not read before another fault) */
    env->mmuregs[3] |= (access_index << 5) | error_code | 2;
    env->mmuregs[4] = address; /* Fault address register */

    if ((env->mmuregs[0] & MMU_NF) || env->psret == 0)  {
        // No fault mode: if a mapping is available, just override
        // permissions. If no mapping is available, redirect accesses to
        // neverland. Fake/overridden mappings will be flushed when
        // switching to normal mode.
	vaddr = address & TARGET_PAGE_MASK;
        prot = PAGE_READ | PAGE_WRITE;
        ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
	return ret;
    } else {
        if (rw & 2)
            env->exception_index = TT_TFAULT;
        else
            env->exception_index = TT_DFAULT;
        return 1;
    }
}
#endif

void memcpy32(target_ulong *dst, const target_ulong *src)
{
    dst[0] = src[0];
    dst[1] = src[1];
    dst[2] = src[2];
    dst[3] = src[3];
    dst[4] = src[4];
    dst[5] = src[5];
    dst[6] = src[6];
    dst[7] = src[7];
}

void set_cwp(int new_cwp)
{
    /* put the modified wrap registers at their proper location */
    if (env->cwp == (NWINDOWS - 1))
        memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
    env->cwp = new_cwp;
    /* put the wrap registers at their temporary location */
    if (new_cwp == (NWINDOWS - 1))
        memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
    env->regwptr = env->regbase + (new_cwp * 16);
}

void cpu_set_cwp(CPUState *env1, int new_cwp)
{
    CPUState *saved_env;
    saved_env = env;
    env = env1;
    set_cwp(new_cwp);
    env = saved_env;
}

void do_interrupt(int intno)
{
    int cwp;

#ifdef DEBUG_PCALL
    if (loglevel & CPU_LOG_INT) {
	static int count;
	fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
                count, intno,
                env->pc,
                env->npc, env->regwptr[6]);
	cpu_dump_state(env, logfile, fprintf, 0);
#if 0
	{
	    int i;
	    uint8_t *ptr;

	    fprintf(logfile, "       code=");
	    ptr = (uint8_t *)env->pc;
	    for(i = 0; i < 16; i++) {
		fprintf(logfile, " %02x", ldub(ptr + i));
	    }
	    fprintf(logfile, "\n");
	}
#endif
	count++;
    }
#endif
#if !defined(CONFIG_USER_ONLY) 
    if (env->psret == 0) {
        cpu_abort(cpu_single_env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
	return;
    }
#endif
    env->psret = 0;
    cwp = (env->cwp - 1) & (NWINDOWS - 1); 
    set_cwp(cwp);
    env->regwptr[9] = env->pc;
    env->regwptr[10] = env->npc;
    env->psrps = env->psrs;
    env->psrs = 1;
    env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
    env->pc = env->tbr;
    env->npc = env->pc + 4;
    env->exception_index = 0;
}

target_ulong mmu_probe(target_ulong address, int mmulev)
{
    target_phys_addr_t pde_ptr;
    uint32_t pde;

    /* Context base + context number */
    pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 4);
    pde = ldl_phys(pde_ptr);

    switch (pde & PTE_ENTRYTYPE_MASK) {
    default:
    case 0: /* Invalid */
    case 2: /* PTE, maybe should not happen? */
    case 3: /* Reserved */
	return 0;
    case 1: /* L1 PDE */
	if (mmulev == 3)
	    return pde;
	pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
        pde = ldl_phys(pde_ptr);

	switch (pde & PTE_ENTRYTYPE_MASK) {
	default:
	case 0: /* Invalid */
	case 3: /* Reserved */
	    return 0;
	case 2: /* L1 PTE */
	    return pde;
	case 1: /* L2 PDE */
	    if (mmulev == 2)
		return pde;
	    pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
            pde = ldl_phys(pde_ptr);

	    switch (pde & PTE_ENTRYTYPE_MASK) {
	    default:
	    case 0: /* Invalid */
	    case 3: /* Reserved */
		return 0;
	    case 2: /* L2 PTE */
		return pde;
	    case 1: /* L3 PDE */
		if (mmulev == 1)
		    return pde;
		pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
                pde = ldl_phys(pde_ptr);

		switch (pde & PTE_ENTRYTYPE_MASK) {
		default:
		case 0: /* Invalid */
		case 1: /* PDE, should not happen */
		case 3: /* Reserved */
		    return 0;
		case 2: /* L3 PTE */
		    return pde;
		}
	    }
	}
    }
    return 0;
}

#ifdef DEBUG_MMU
void dump_mmu(void)
{
     target_ulong va, va1, va2;
     unsigned int n, m, o;
     target_phys_addr_t pde_ptr, pa;
    uint32_t pde;

    printf("MMU dump:\n");
    pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 4);
    pde = ldl_phys(pde_ptr);
    printf("Root ptr: " TARGET_FMT_lx ", ctx: %d\n", env->mmuregs[1] << 4, env->mmuregs[2]);
    for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
	pde_ptr = mmu_probe(va, 2);
	if (pde_ptr) {
	    pa = cpu_get_phys_page_debug(env, va);
 	    printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va, pa, pde_ptr);
	    for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
		pde_ptr = mmu_probe(va1, 1);
		if (pde_ptr) {
		    pa = cpu_get_phys_page_debug(env, va1);
 		    printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va1, pa, pde_ptr);
		    for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
			pde_ptr = mmu_probe(va2, 0);
			if (pde_ptr) {
			    pa = cpu_get_phys_page_debug(env, va2);
 			    printf("  VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PTE: " TARGET_FMT_lx "\n", va2, pa, pde_ptr);
			}
		    }
		}
	    }
	}
    }
    printf("MMU dump ends\n");
}
#endif
Commit	Line	Data
e8af50a3 FB	1	/*
	2	* sparc helpers
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#include "exec.h"
	21
e80cfcfc FB	22	//#define DEBUG_PCALL
e80cfcfc FB	23	//#define DEBUG_MMU
e8af50a3	24
e8af50a3	25	/* Sparc MMU emulation */
e8af50a3	26
e8af50a3 FB	27	/* thread support */
	28
	29	spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
	30
	31	void cpu_lock(void)
	32	{
	33	spin_lock(&global_cpu_lock);
	34	}
	35
	36	void cpu_unlock(void)
	37	{
	38	spin_unlock(&global_cpu_lock);
	39	}
	40
9d893301 FB	41	#if defined(CONFIG_USER_ONLY)
	42
	43	int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
	44	int is_user, int is_softmmu)
	45	{
	46	env->mmuregs[4] = address;
878d3096 FB	47	if (rw & 2)
	48	env->exception_index = TT_TFAULT;
	49	else
	50	env->exception_index = TT_DFAULT;
9d893301 FB	51	return 1;
	52	}
	53
	54	#else
e8af50a3 FB	55
	56	#define MMUSUFFIX _mmu
	57	#define GETPC() (__builtin_return_address(0))
	58
	59	#define SHIFT 0
	60	#include "softmmu_template.h"
	61
	62	#define SHIFT 1
	63	#include "softmmu_template.h"
	64
	65	#define SHIFT 2
	66	#include "softmmu_template.h"
	67
	68	#define SHIFT 3
	69	#include "softmmu_template.h"
	70
	71
	72	/* try to fill the TLB and return an exception if error. If retaddr is
	73	NULL, it means that the function was called in C code (i.e. not
	74	from generated code or from helper.c) */
	75	/* XXX: fix it to restore all registers */
0fa85d43	76	void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
e8af50a3 FB	77	{
	78	TranslationBlock *tb;
	79	int ret;
	80	unsigned long pc;
	81	CPUState *saved_env;
	82
	83	/* XXX: hack to restore env in all cases, even if not called from
	84	generated code */
	85	saved_env = env;
	86	env = cpu_single_env;
	87
	88	ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, is_user, 1);
	89	if (ret) {
	90	if (retaddr) {
	91	/* now we have a real cpu fault */
	92	pc = (unsigned long)retaddr;
	93	tb = tb_find_pc(pc);
	94	if (tb) {
	95	/* the PC is inside the translated code. It means that we have
	96	a virtual CPU fault */
c3278b7b	97	cpu_restore_state(tb, env, pc, (void *)T2);
e8af50a3 FB	98	}
e8af50a3 FB	99	}
878d3096	100	cpu_loop_exit();
e8af50a3 FB	101	}
	102	env = saved_env;
	103	}
e8af50a3 FB	104
	105	static const int access_table[8][8] = {
	106	{ 0, 0, 0, 0, 2, 0, 3, 3 },
	107	{ 0, 0, 0, 0, 2, 0, 0, 0 },
	108	{ 2, 2, 0, 0, 0, 2, 3, 3 },
	109	{ 2, 2, 0, 0, 0, 2, 0, 0 },
	110	{ 2, 0, 2, 0, 2, 2, 3, 3 },
	111	{ 2, 0, 2, 0, 2, 0, 2, 0 },
	112	{ 2, 2, 2, 0, 2, 2, 3, 3 },
	113	{ 2, 2, 2, 0, 2, 2, 2, 0 }
	114	};
	115
	116	/* 1 = write OK */
	117	static const int rw_table[2][8] = {
	118	{ 0, 1, 0, 1, 0, 1, 0, 1 },
	119	{ 0, 1, 0, 1, 0, 0, 0, 0 }
	120	};
	121
af7bf89b FB	122	int get_physical_address (CPUState env, target_phys_addr_t physical, int *prot,
af7bf89b FB	123	int *access_index, target_ulong address, int rw,
e80cfcfc	124	int is_user)
e8af50a3	125	{
e80cfcfc FB	126	int access_perms = 0;
e80cfcfc FB	127	target_phys_addr_t pde_ptr;
af7bf89b FB	128	uint32_t pde;
af7bf89b FB	129	target_ulong virt_addr;
e80cfcfc FB	130	int error_code = 0, is_dirty;
e80cfcfc FB	131	unsigned long page_offset;
e8af50a3 FB	132
	133	virt_addr = address & TARGET_PAGE_MASK;
	134	if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
e80cfcfc FB	135	*physical = address;
	136	*prot = PAGE_READ \| PAGE_WRITE;
	137	return 0;
e8af50a3 FB	138	}
e8af50a3 FB	139
7483750d	140	*access_index = ((rw & 1) << 2) \| (rw & 2) \| (is_user? 0 : 1);
6f7e9aec	141	*physical = 0xfffff000;
7483750d	142
e8af50a3 FB	143	/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
e8af50a3 FB	144	/* Context base + context number */
e80cfcfc	145	pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 4);
49be8030	146	pde = ldl_phys(pde_ptr);
e8af50a3 FB	147
	148	/* Ctx pde */
	149	switch (pde & PTE_ENTRYTYPE_MASK) {
e80cfcfc	150	default:
e8af50a3	151	case 0: /* Invalid */
7483750d	152	return 1 << 2;
e80cfcfc	153	case 2: /* L0 PTE, maybe should not happen? */
e8af50a3	154	case 3: /* Reserved */
7483750d	155	return 4 << 2;
e80cfcfc FB	156	case 1: /* L0 PDE */
e80cfcfc FB	157	pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
49be8030	158	pde = ldl_phys(pde_ptr);
e8af50a3 FB	159
e8af50a3 FB	160	switch (pde & PTE_ENTRYTYPE_MASK) {
e80cfcfc	161	default:
e8af50a3	162	case 0: /* Invalid */
7483750d	163	return (1 << 8) \| (1 << 2);
e8af50a3	164	case 3: /* Reserved */
7483750d	165	return (1 << 8) \| (4 << 2);
e80cfcfc FB	166	case 1: /* L1 PDE */
e80cfcfc FB	167	pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
49be8030	168	pde = ldl_phys(pde_ptr);
e8af50a3 FB	169
e8af50a3 FB	170	switch (pde & PTE_ENTRYTYPE_MASK) {
e80cfcfc	171	default:
e8af50a3	172	case 0: /* Invalid */
7483750d	173	return (2 << 8) \| (1 << 2);
e8af50a3	174	case 3: /* Reserved */
7483750d	175	return (2 << 8) \| (4 << 2);
e80cfcfc FB	176	case 1: /* L2 PDE */
e80cfcfc FB	177	pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
49be8030	178	pde = ldl_phys(pde_ptr);
e8af50a3 FB	179
e8af50a3 FB	180	switch (pde & PTE_ENTRYTYPE_MASK) {
e80cfcfc	181	default:
e8af50a3	182	case 0: /* Invalid */
7483750d	183	return (3 << 8) \| (1 << 2);
e8af50a3 FB	184	case 1: /* PDE, should not happen */
e8af50a3 FB	185	case 3: /* Reserved */
7483750d	186	return (3 << 8) \| (4 << 2);
e8af50a3 FB	187	case 2: /* L3 PTE */
	188	virt_addr = address & TARGET_PAGE_MASK;
	189	page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
	190	}
	191	break;
	192	case 2: /* L2 PTE */
	193	virt_addr = address & ~0x3ffff;
	194	page_offset = address & 0x3ffff;
	195	}
	196	break;
	197	case 2: /* L1 PTE */
	198	virt_addr = address & ~0xffffff;
	199	page_offset = address & 0xffffff;
	200	}
	201	}
	202
	203	/* update page modified and dirty bits */
b769d8fe	204	is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
e8af50a3 FB	205	if (!(pde & PG_ACCESSED_MASK) \|\| is_dirty) {
	206	pde \|= PG_ACCESSED_MASK;
	207	if (is_dirty)
	208	pde \|= PG_MODIFIED_MASK;
49be8030	209	stl_phys_notdirty(pde_ptr, pde);
e8af50a3	210	}
e8af50a3	211	/* check access */
e8af50a3	212	access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
e80cfcfc	213	error_code = access_table[*access_index][access_perms];
6f7e9aec	214	if (error_code && !(env->mmuregs[0] & MMU_NF))
e80cfcfc	215	return error_code;
e8af50a3 FB	216
e8af50a3 FB	217	/* the page can be put in the TLB */
e80cfcfc	218	*prot = PAGE_READ;
e8af50a3 FB	219	if (pde & PG_MODIFIED_MASK) {
	220	/* only set write access if already dirty... otherwise wait
	221	for dirty access */
	222	if (rw_table[is_user][access_perms])
e80cfcfc	223	*prot \|= PAGE_WRITE;
e8af50a3 FB	224	}
	225
	226	/* Even if large ptes, we map only one 4KB page in the cache to
	227	avoid filling it too fast */
e80cfcfc	228	*physical = ((pde & PTE_ADDR_MASK) << 4) + page_offset;
6f7e9aec	229	return error_code;
e80cfcfc FB	230	}
	231
	232	/* Perform address translation */
af7bf89b	233	int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
e80cfcfc FB	234	int is_user, int is_softmmu)
e80cfcfc FB	235	{
af7bf89b FB	236	target_ulong virt_addr;
af7bf89b FB	237	target_phys_addr_t paddr;
e80cfcfc FB	238	unsigned long vaddr;
e80cfcfc FB	239	int error_code = 0, prot, ret = 0, access_index;
e8af50a3	240
e80cfcfc FB	241	error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
	242	if (error_code == 0) {
	243	virt_addr = address & TARGET_PAGE_MASK;
	244	vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
	245	ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
	246	return ret;
	247	}
e8af50a3	248
e8af50a3 FB	249	if (env->mmuregs[3]) /* Fault status register */
e8af50a3 FB	250	env->mmuregs[3] = 1; /* overflow (not read before another fault) */
7483750d	251	env->mmuregs[3] \|= (access_index << 5) \| error_code \| 2;
e8af50a3 FB	252	env->mmuregs[4] = address; /* Fault address register */
e8af50a3 FB	253
878d3096	254	if ((env->mmuregs[0] & MMU_NF) \|\| env->psret == 0) {
6f7e9aec FB	255	// No fault mode: if a mapping is available, just override
	256	// permissions. If no mapping is available, redirect accesses to
	257	// neverland. Fake/overridden mappings will be flushed when
	258	// switching to normal mode.
7483750d	259	vaddr = address & TARGET_PAGE_MASK;
7483750d FB	260	prot = PAGE_READ \| PAGE_WRITE;
	261	ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
	262	return ret;
7483750d FB	263	} else {
	264	if (rw & 2)
	265	env->exception_index = TT_TFAULT;
	266	else
	267	env->exception_index = TT_DFAULT;
	268	return 1;
878d3096	269	}
e8af50a3	270	}
9d893301	271	#endif
e8af50a3	272
af7bf89b	273	void memcpy32(target_ulong dst, const target_ulong src)
e8af50a3 FB	274	{
	275	dst[0] = src[0];
	276	dst[1] = src[1];
	277	dst[2] = src[2];
	278	dst[3] = src[3];
	279	dst[4] = src[4];
	280	dst[5] = src[5];
	281	dst[6] = src[6];
	282	dst[7] = src[7];
	283	}
	284
	285	void set_cwp(int new_cwp)
	286	{
	287	/* put the modified wrap registers at their proper location */
	288	if (env->cwp == (NWINDOWS - 1))
	289	memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
	290	env->cwp = new_cwp;
	291	/* put the wrap registers at their temporary location */
	292	if (new_cwp == (NWINDOWS - 1))
	293	memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
	294	env->regwptr = env->regbase + (new_cwp * 16);
	295	}
	296
0fa85d43 FB	297	void cpu_set_cwp(CPUState *env1, int new_cwp)
	298	{
	299	CPUState *saved_env;
	300	saved_env = env;
	301	env = env1;
	302	set_cwp(new_cwp);
	303	env = saved_env;
	304	}
	305
878d3096	306	void do_interrupt(int intno)
e8af50a3 FB	307	{
	308	int cwp;
	309
	310	#ifdef DEBUG_PCALL
	311	if (loglevel & CPU_LOG_INT) {
	312	static int count;
878d3096 FB	313	fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
878d3096 FB	314	count, intno,
9d893301 FB	315	env->pc,
9d893301 FB	316	env->npc, env->regwptr[6]);
7fe48483	317	cpu_dump_state(env, logfile, fprintf, 0);
6f7e9aec	318	#if 0
e8af50a3 FB	319	{
	320	int i;
	321	uint8_t *ptr;
e80cfcfc	322
e8af50a3	323	fprintf(logfile, " code=");
e80cfcfc	324	ptr = (uint8_t *)env->pc;
e8af50a3 FB	325	for(i = 0; i < 16; i++) {
	326	fprintf(logfile, " %02x", ldub(ptr + i));
	327	}
	328	fprintf(logfile, "\n");
	329	}
	330	#endif
	331	count++;
	332	}
e80cfcfc FB	333	#endif
	334	#if !defined(CONFIG_USER_ONLY)
	335	if (env->psret == 0) {
878d3096	336	cpu_abort(cpu_single_env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
e80cfcfc FB	337	return;
e80cfcfc FB	338	}
e8af50a3 FB	339	#endif
	340	env->psret = 0;
	341	cwp = (env->cwp - 1) & (NWINDOWS - 1);
	342	set_cwp(cwp);
878d3096 FB	343	env->regwptr[9] = env->pc;
878d3096 FB	344	env->regwptr[10] = env->npc;
e8af50a3 FB	345	env->psrps = env->psrs;
	346	env->psrs = 1;
	347	env->tbr = (env->tbr & TBR_BASE_MASK) \| (intno << 4);
	348	env->pc = env->tbr;
	349	env->npc = env->pc + 4;
	350	env->exception_index = 0;
	351	}
	352
af7bf89b	353	target_ulong mmu_probe(target_ulong address, int mmulev)
e80cfcfc FB	354	{
	355	target_phys_addr_t pde_ptr;
	356	uint32_t pde;
	357
	358	/* Context base + context number */
	359	pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 4);
49be8030 FB	360	pde = ldl_phys(pde_ptr);
49be8030 FB	361
e80cfcfc FB	362	switch (pde & PTE_ENTRYTYPE_MASK) {
	363	default:
	364	case 0: /* Invalid */
	365	case 2: /* PTE, maybe should not happen? */
	366	case 3: /* Reserved */
	367	return 0;
	368	case 1: /* L1 PDE */
	369	if (mmulev == 3)
	370	return pde;
	371	pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
49be8030	372	pde = ldl_phys(pde_ptr);
e80cfcfc FB	373
	374	switch (pde & PTE_ENTRYTYPE_MASK) {
	375	default:
	376	case 0: /* Invalid */
	377	case 3: /* Reserved */
	378	return 0;
	379	case 2: /* L1 PTE */
	380	return pde;
	381	case 1: /* L2 PDE */
	382	if (mmulev == 2)
	383	return pde;
	384	pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
49be8030	385	pde = ldl_phys(pde_ptr);
e80cfcfc FB	386
	387	switch (pde & PTE_ENTRYTYPE_MASK) {
	388	default:
	389	case 0: /* Invalid */
	390	case 3: /* Reserved */
	391	return 0;
	392	case 2: /* L2 PTE */
	393	return pde;
	394	case 1: /* L3 PDE */
	395	if (mmulev == 1)
	396	return pde;
	397	pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
49be8030	398	pde = ldl_phys(pde_ptr);
e80cfcfc FB	399
	400	switch (pde & PTE_ENTRYTYPE_MASK) {
	401	default:
	402	case 0: /* Invalid */
	403	case 1: /* PDE, should not happen */
	404	case 3: /* Reserved */
	405	return 0;
	406	case 2: /* L3 PTE */
	407	return pde;
	408	}
	409	}
	410	}
	411	}
	412	return 0;
	413	}
	414
55754d9e	415	#ifdef DEBUG_MMU
e80cfcfc FB	416	void dump_mmu(void)
e80cfcfc FB	417	{
af7bf89b FB	418	target_ulong va, va1, va2;
	419	unsigned int n, m, o;
	420	target_phys_addr_t pde_ptr, pa;
e80cfcfc FB	421	uint32_t pde;
	422
	423	printf("MMU dump:\n");
	424	pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 4);
49be8030	425	pde = ldl_phys(pde_ptr);
af7bf89b	426	printf("Root ptr: " TARGET_FMT_lx ", ctx: %d\n", env->mmuregs[1] << 4, env->mmuregs[2]);
e80cfcfc FB	427	for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
	428	pde_ptr = mmu_probe(va, 2);
	429	if (pde_ptr) {
	430	pa = cpu_get_phys_page_debug(env, va);
af7bf89b	431	printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va, pa, pde_ptr);
e80cfcfc FB	432	for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
	433	pde_ptr = mmu_probe(va1, 1);
	434	if (pde_ptr) {
	435	pa = cpu_get_phys_page_debug(env, va1);
af7bf89b	436	printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va1, pa, pde_ptr);
e80cfcfc FB	437	for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
	438	pde_ptr = mmu_probe(va2, 0);
	439	if (pde_ptr) {
	440	pa = cpu_get_phys_page_debug(env, va2);
af7bf89b	441	printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PTE: " TARGET_FMT_lx "\n", va2, pa, pde_ptr);
e80cfcfc FB	442	}
	443	}
	444	}
	445	}
	446	}
	447	}
	448	printf("MMU dump ends\n");
e80cfcfc	449	}
55754d9e	450	#endif