[qemu.git] / hw / timer / exynos4210_pwm.c

/*
 * Samsung exynos4210 Pulse Width Modulation Timer
 *
 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
 * All rights reserved.
 *
 * Evgeny Voevodin <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See the GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "qemu-common.h"
#include "qemu/main-loop.h"
#include "hw/ptimer.h"

#include "hw/arm/exynos4210.h"

//#define DEBUG_PWM

#ifdef DEBUG_PWM
#define DPRINTF(fmt, ...) \
        do { fprintf(stdout, "PWM: [%24s:%5d] " fmt, __func__, __LINE__, \
                ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...) do {} while (0)
#endif

#define     EXYNOS4210_PWM_TIMERS_NUM      5
#define     EXYNOS4210_PWM_REG_MEM_SIZE    0x50

#define     TCFG0        0x0000
#define     TCFG1        0x0004
#define     TCON         0x0008
#define     TCNTB0       0x000C
#define     TCMPB0       0x0010
#define     TCNTO0       0x0014
#define     TCNTB1       0x0018
#define     TCMPB1       0x001C
#define     TCNTO1       0x0020
#define     TCNTB2       0x0024
#define     TCMPB2       0x0028
#define     TCNTO2       0x002C
#define     TCNTB3       0x0030
#define     TCMPB3       0x0034
#define     TCNTO3       0x0038
#define     TCNTB4       0x003C
#define     TCNTO4       0x0040
#define     TINT_CSTAT   0x0044

#define     TCNTB(x)    (0xC * (x))
#define     TCMPB(x)    (0xC * (x) + 1)
#define     TCNTO(x)    (0xC * (x) + 2)

#define GET_PRESCALER(reg, x) (((reg) & (0xFF << (8 * (x)))) >> 8 * (x))
#define GET_DIVIDER(reg, x) (1 << (((reg) & (0xF << (4 * (x)))) >> (4 * (x))))

/*
 * Attention! Timer4 doesn't have OUTPUT_INVERTER,
 * so Auto Reload bit is not accessible by macros!
 */
#define     TCON_TIMER_BASE(x)          (((x) ? 1 : 0) * 4 + 4 * (x))
#define     TCON_TIMER_START(x)         (1 << (TCON_TIMER_BASE(x) + 0))
#define     TCON_TIMER_MANUAL_UPD(x)    (1 << (TCON_TIMER_BASE(x) + 1))
#define     TCON_TIMER_OUTPUT_INV(x)    (1 << (TCON_TIMER_BASE(x) + 2))
#define     TCON_TIMER_AUTO_RELOAD(x)   (1 << (TCON_TIMER_BASE(x) + 3))
#define     TCON_TIMER4_AUTO_RELOAD     (1 << 22)

#define     TINT_CSTAT_STATUS(x)        (1 << (5 + (x)))
#define     TINT_CSTAT_ENABLE(x)        (1 << (x))

/* timer struct */
typedef struct {
    uint32_t    id;             /* timer id */
    qemu_irq    irq;            /* local timer irq */
    uint32_t    freq;           /* timer frequency */

    /* use ptimer.c to represent count down timer */
    ptimer_state *ptimer;       /* timer  */

    /* registers */
    uint32_t    reg_tcntb;      /* counter register buffer */
    uint32_t    reg_tcmpb;      /* compare register buffer */

    struct Exynos4210PWMState *parent;

} Exynos4210PWM;

#define TYPE_EXYNOS4210_PWM "exynos4210.pwm"
#define EXYNOS4210_PWM(obj) \
    OBJECT_CHECK(Exynos4210PWMState, (obj), TYPE_EXYNOS4210_PWM)

typedef struct Exynos4210PWMState {
    SysBusDevice parent_obj;

    MemoryRegion iomem;

    uint32_t    reg_tcfg[2];
    uint32_t    reg_tcon;
    uint32_t    reg_tint_cstat;

    Exynos4210PWM timer[EXYNOS4210_PWM_TIMERS_NUM];

} Exynos4210PWMState;

/*** VMState ***/
static const VMStateDescription vmstate_exynos4210_pwm = {
    .name = "exynos4210.pwm.pwm",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(id, Exynos4210PWM),
        VMSTATE_UINT32(freq, Exynos4210PWM),
        VMSTATE_PTIMER(ptimer, Exynos4210PWM),
        VMSTATE_UINT32(reg_tcntb, Exynos4210PWM),
        VMSTATE_UINT32(reg_tcmpb, Exynos4210PWM),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_exynos4210_pwm_state = {
    .name = "exynos4210.pwm",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(reg_tcfg, Exynos4210PWMState, 2),
        VMSTATE_UINT32(reg_tcon, Exynos4210PWMState),
        VMSTATE_UINT32(reg_tint_cstat, Exynos4210PWMState),
        VMSTATE_STRUCT_ARRAY(timer, Exynos4210PWMState,
            EXYNOS4210_PWM_TIMERS_NUM, 0,
        vmstate_exynos4210_pwm, Exynos4210PWM),
        VMSTATE_END_OF_LIST()
    }
};

/*
 * PWM update frequency
 */
static void exynos4210_pwm_update_freq(Exynos4210PWMState *s, uint32_t id)
{
    uint32_t freq;
    freq = s->timer[id].freq;
    if (id > 1) {
        s->timer[id].freq = 24000000 /
        ((GET_PRESCALER(s->reg_tcfg[0], 1) + 1) *
                (GET_DIVIDER(s->reg_tcfg[1], id)));
    } else {
        s->timer[id].freq = 24000000 /
        ((GET_PRESCALER(s->reg_tcfg[0], 0) + 1) *
                (GET_DIVIDER(s->reg_tcfg[1], id)));
    }

    if (freq != s->timer[id].freq) {
        ptimer_set_freq(s->timer[id].ptimer, s->timer[id].freq);
        DPRINTF("freq=%dHz\n", s->timer[id].freq);
    }
}

/*
 * Counter tick handler
 */
static void exynos4210_pwm_tick(void *opaque)
{
    Exynos4210PWM *s = (Exynos4210PWM *)opaque;
    Exynos4210PWMState *p = (Exynos4210PWMState *)s->parent;
    uint32_t id = s->id;
    bool cmp;

    DPRINTF("timer %d tick\n", id);

    /* set irq status */
    p->reg_tint_cstat |= TINT_CSTAT_STATUS(id);

    /* raise IRQ */
    if (p->reg_tint_cstat & TINT_CSTAT_ENABLE(id)) {
        DPRINTF("timer %d IRQ\n", id);
        qemu_irq_raise(p->timer[id].irq);
    }

    /* reload timer */
    if (id != 4) {
        cmp = p->reg_tcon & TCON_TIMER_AUTO_RELOAD(id);
    } else {
        cmp = p->reg_tcon & TCON_TIMER4_AUTO_RELOAD;
    }

    if (cmp) {
        DPRINTF("auto reload timer %d count to %x\n", id,
                p->timer[id].reg_tcntb);
        ptimer_set_count(p->timer[id].ptimer, p->timer[id].reg_tcntb);
        ptimer_run(p->timer[id].ptimer, 1);
    } else {
        /* stop timer, set status to STOP, see Basic Timer Operation */
        p->reg_tcon &= ~TCON_TIMER_START(id);
        ptimer_stop(p->timer[id].ptimer);
    }
}

/*
 * PWM Read
 */
static uint64_t exynos4210_pwm_read(void *opaque, hwaddr offset,
        unsigned size)
{
    Exynos4210PWMState *s = (Exynos4210PWMState *)opaque;
    uint32_t value = 0;
    int index;

    switch (offset) {
    case TCFG0: case TCFG1:
        index = (offset - TCFG0) >> 2;
        value = s->reg_tcfg[index];
        break;

    case TCON:
        value = s->reg_tcon;
        break;

    case TCNTB0: case TCNTB1:
    case TCNTB2: case TCNTB3: case TCNTB4:
        index = (offset - TCNTB0) / 0xC;
        value = s->timer[index].reg_tcntb;
        break;

    case TCMPB0: case TCMPB1:
    case TCMPB2: case TCMPB3:
        index = (offset - TCMPB0) / 0xC;
        value = s->timer[index].reg_tcmpb;
        break;

    case TCNTO0: case TCNTO1:
    case TCNTO2: case TCNTO3: case TCNTO4:
        index = (offset == TCNTO4) ? 4 : (offset - TCNTO0) / 0xC;
        value = ptimer_get_count(s->timer[index].ptimer);
        break;

    case TINT_CSTAT:
        value = s->reg_tint_cstat;
        break;

    default:
        fprintf(stderr,
                "[exynos4210.pwm: bad read offset " TARGET_FMT_plx "]\n",
                offset);
        break;
    }
    return value;
}

/*
 * PWM Write
 */
static void exynos4210_pwm_write(void *opaque, hwaddr offset,
        uint64_t value, unsigned size)
{
    Exynos4210PWMState *s = (Exynos4210PWMState *)opaque;
    int index;
    uint32_t new_val;
    int i;

    switch (offset) {
    case TCFG0: case TCFG1:
        index = (offset - TCFG0) >> 2;
        s->reg_tcfg[index] = value;

        /* update timers frequencies */
        for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) {
            exynos4210_pwm_update_freq(s, s->timer[i].id);
        }
        break;

    case TCON:
        for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) {
            if ((value & TCON_TIMER_MANUAL_UPD(i)) >
            (s->reg_tcon & TCON_TIMER_MANUAL_UPD(i))) {
                /*
                 * TCNTB and TCMPB are loaded into TCNT and TCMP.
                 * Update timers.
                 */

                /* this will start timer to run, this ok, because
                 * during processing start bit timer will be stopped
                 * if needed */
                ptimer_set_count(s->timer[i].ptimer, s->timer[i].reg_tcntb);
                DPRINTF("set timer %d count to %x\n", i,
                        s->timer[i].reg_tcntb);
            }

            if ((value & TCON_TIMER_START(i)) >
            (s->reg_tcon & TCON_TIMER_START(i))) {
                /* changed to start */
                ptimer_run(s->timer[i].ptimer, 1);
                DPRINTF("run timer %d\n", i);
            }

            if ((value & TCON_TIMER_START(i)) <
                    (s->reg_tcon & TCON_TIMER_START(i))) {
                /* changed to stop */
                ptimer_stop(s->timer[i].ptimer);
                DPRINTF("stop timer %d\n", i);
            }
        }
        s->reg_tcon = value;
        break;

    case TCNTB0: case TCNTB1:
    case TCNTB2: case TCNTB3: case TCNTB4:
        index = (offset - TCNTB0) / 0xC;
        s->timer[index].reg_tcntb = value;
        break;

    case TCMPB0: case TCMPB1:
    case TCMPB2: case TCMPB3:
        index = (offset - TCMPB0) / 0xC;
        s->timer[index].reg_tcmpb = value;
        break;

    case TINT_CSTAT:
        new_val = (s->reg_tint_cstat & 0x3E0) + (0x1F & value);
        new_val &= ~(0x3E0 & value);

        for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) {
            if ((new_val & TINT_CSTAT_STATUS(i)) <
                    (s->reg_tint_cstat & TINT_CSTAT_STATUS(i))) {
                qemu_irq_lower(s->timer[i].irq);
            }
        }

        s->reg_tint_cstat = new_val;
        break;

    default:
        fprintf(stderr,
                "[exynos4210.pwm: bad write offset " TARGET_FMT_plx "]\n",
                offset);
        break;

    }
}

/*
 * Set default values to timer fields and registers
 */
static void exynos4210_pwm_reset(DeviceState *d)
{
    Exynos4210PWMState *s = EXYNOS4210_PWM(d);
    int i;
    s->reg_tcfg[0] = 0x0101;
    s->reg_tcfg[1] = 0x0;
    s->reg_tcon = 0;
    s->reg_tint_cstat = 0;
    for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) {
        s->timer[i].reg_tcmpb = 0;
        s->timer[i].reg_tcntb = 0;

        exynos4210_pwm_update_freq(s, s->timer[i].id);
        ptimer_stop(s->timer[i].ptimer);
    }
}

static const MemoryRegionOps exynos4210_pwm_ops = {
    .read = exynos4210_pwm_read,
    .write = exynos4210_pwm_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

/*
 * PWM timer initialization
 */
static int exynos4210_pwm_init(SysBusDevice *dev)
{
    Exynos4210PWMState *s = EXYNOS4210_PWM(dev);
    int i;
    QEMUBH *bh;

    for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) {
        bh = qemu_bh_new(exynos4210_pwm_tick, &s->timer[i]);
        sysbus_init_irq(dev, &s->timer[i].irq);
        s->timer[i].ptimer = ptimer_init(bh);
        s->timer[i].id = i;
        s->timer[i].parent = s;
    }

    memory_region_init_io(&s->iomem, OBJECT(s), &exynos4210_pwm_ops, s,
                          "exynos4210-pwm", EXYNOS4210_PWM_REG_MEM_SIZE);
    sysbus_init_mmio(dev, &s->iomem);

    return 0;
}

static void exynos4210_pwm_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = exynos4210_pwm_init;
    dc->reset = exynos4210_pwm_reset;
    dc->vmsd = &vmstate_exynos4210_pwm_state;
}

static const TypeInfo exynos4210_pwm_info = {
    .name          = TYPE_EXYNOS4210_PWM,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(Exynos4210PWMState),
    .class_init    = exynos4210_pwm_class_init,
};

static void exynos4210_pwm_register_types(void)
{
    type_register_static(&exynos4210_pwm_info);
}

type_init(exynos4210_pwm_register_types)
Commit	Line	Data
62db8bf3 EV	1	/*
	2	* Samsung exynos4210 Pulse Width Modulation Timer
	3	*
	4	* Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
	5	* All rights reserved.
	6	*
	7	* Evgeny Voevodin <[email protected]>
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License as published by the
	11	* Free Software Foundation; either version 2 of the License, or (at your
	12	* option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
	17	* See the GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License along
	20	* with this program; if not, see <http://www.gnu.org/licenses/>.
	21	*/
	22
83c9f4ca	23	#include "hw/sysbus.h"
1de7afc9	24	#include "qemu/timer.h"
62db8bf3	25	#include "qemu-common.h"
6a1751b7	26	#include "qemu/main-loop.h"
83c9f4ca	27	#include "hw/ptimer.h"
62db8bf3	28
0d09e41a	29	#include "hw/arm/exynos4210.h"
62db8bf3 EV	30
	31	//#define DEBUG_PWM
	32
	33	#ifdef DEBUG_PWM
	34	#define DPRINTF(fmt, ...) \
	35	do { fprintf(stdout, "PWM: [%24s:%5d] " fmt, __func__, __LINE__, \
	36	## __VA_ARGS__); } while (0)
	37	#else
	38	#define DPRINTF(fmt, ...) do {} while (0)
	39	#endif
	40
	41	#define EXYNOS4210_PWM_TIMERS_NUM 5
	42	#define EXYNOS4210_PWM_REG_MEM_SIZE 0x50
	43
	44	#define TCFG0 0x0000
	45	#define TCFG1 0x0004
	46	#define TCON 0x0008
	47	#define TCNTB0 0x000C
	48	#define TCMPB0 0x0010
	49	#define TCNTO0 0x0014
	50	#define TCNTB1 0x0018
	51	#define TCMPB1 0x001C
	52	#define TCNTO1 0x0020
	53	#define TCNTB2 0x0024
	54	#define TCMPB2 0x0028
	55	#define TCNTO2 0x002C
	56	#define TCNTB3 0x0030
	57	#define TCMPB3 0x0034
	58	#define TCNTO3 0x0038
	59	#define TCNTB4 0x003C
	60	#define TCNTO4 0x0040
	61	#define TINT_CSTAT 0x0044
	62
	63	#define TCNTB(x) (0xC * (x))
	64	#define TCMPB(x) (0xC * (x) + 1)
	65	#define TCNTO(x) (0xC * (x) + 2)
	66
	67	#define GET_PRESCALER(reg, x) (((reg) & (0xFF << (8 * (x)))) >> 8 * (x))
	68	#define GET_DIVIDER(reg, x) (1 << (((reg) & (0xF << (4 * (x)))) >> (4 * (x))))
	69
	70	/*
	71	* Attention! Timer4 doesn't have OUTPUT_INVERTER,
	72	* so Auto Reload bit is not accessible by macros!
	73	*/
	74	#define TCON_TIMER_BASE(x) (((x) ? 1 : 0) * 4 + 4 * (x))
	75	#define TCON_TIMER_START(x) (1 << (TCON_TIMER_BASE(x) + 0))
	76	#define TCON_TIMER_MANUAL_UPD(x) (1 << (TCON_TIMER_BASE(x) + 1))
	77	#define TCON_TIMER_OUTPUT_INV(x) (1 << (TCON_TIMER_BASE(x) + 2))
	78	#define TCON_TIMER_AUTO_RELOAD(x) (1 << (TCON_TIMER_BASE(x) + 3))
	79	#define TCON_TIMER4_AUTO_RELOAD (1 << 22)
	80
	81	#define TINT_CSTAT_STATUS(x) (1 << (5 + (x)))
	82	#define TINT_CSTAT_ENABLE(x) (1 << (x))
	83
	84	/* timer struct */
	85	typedef struct {
	86	uint32_t id; /* timer id */
	87	qemu_irq irq; /* local timer irq */
	88	uint32_t freq; /* timer frequency */
	89
	90	/* use ptimer.c to represent count down timer */
	91	ptimer_state ptimer; / timer */
	92
	93	/* registers */
94	uint32_t reg_tcntb; /* counter register buffer */
95	uint32_t reg_tcmpb; /* compare register buffer */
96
97	struct Exynos4210PWMState *parent;
98
99	} Exynos4210PWM;
100
25fce9ad AF	101	#define TYPE_EXYNOS4210_PWM "exynos4210.pwm"
	102	#define EXYNOS4210_PWM(obj) \
	103	OBJECT_CHECK(Exynos4210PWMState, (obj), TYPE_EXYNOS4210_PWM)
62db8bf3 EV	104
62db8bf3 EV	105	typedef struct Exynos4210PWMState {
25fce9ad AF	106	SysBusDevice parent_obj;
25fce9ad AF	107
62db8bf3 EV	108	MemoryRegion iomem;
	109
	110	uint32_t reg_tcfg[2];
	111	uint32_t reg_tcon;
	112	uint32_t reg_tint_cstat;
	113
	114	Exynos4210PWM timer[EXYNOS4210_PWM_TIMERS_NUM];
	115
	116	} Exynos4210PWMState;
	117
	118	/* VMState */
	119	static const VMStateDescription vmstate_exynos4210_pwm = {
	120	.name = "exynos4210.pwm.pwm",
	121	.version_id = 1,
	122	.minimum_version_id = 1,
62db8bf3 EV	123	.fields = (VMStateField[]) {
	124	VMSTATE_UINT32(id, Exynos4210PWM),
	125	VMSTATE_UINT32(freq, Exynos4210PWM),
	126	VMSTATE_PTIMER(ptimer, Exynos4210PWM),
	127	VMSTATE_UINT32(reg_tcntb, Exynos4210PWM),
	128	VMSTATE_UINT32(reg_tcmpb, Exynos4210PWM),
	129	VMSTATE_END_OF_LIST()
	130	}
	131	};
	132
	133	static const VMStateDescription vmstate_exynos4210_pwm_state = {
	134	.name = "exynos4210.pwm",
	135	.version_id = 1,
	136	.minimum_version_id = 1,
62db8bf3 EV	137	.fields = (VMStateField[]) {
	138	VMSTATE_UINT32_ARRAY(reg_tcfg, Exynos4210PWMState, 2),
	139	VMSTATE_UINT32(reg_tcon, Exynos4210PWMState),
	140	VMSTATE_UINT32(reg_tint_cstat, Exynos4210PWMState),
	141	VMSTATE_STRUCT_ARRAY(timer, Exynos4210PWMState,
	142	EXYNOS4210_PWM_TIMERS_NUM, 0,
	143	vmstate_exynos4210_pwm, Exynos4210PWM),
	144	VMSTATE_END_OF_LIST()
	145	}
	146	};
	147
	148	/*
	149	* PWM update frequency
	150	*/
	151	static void exynos4210_pwm_update_freq(Exynos4210PWMState *s, uint32_t id)
	152	{
	153	uint32_t freq;
	154	freq = s->timer[id].freq;
	155	if (id > 1) {
	156	s->timer[id].freq = 24000000 /
	157	((GET_PRESCALER(s->reg_tcfg[0], 1) + 1) *
	158	(GET_DIVIDER(s->reg_tcfg[1], id)));
	159	} else {
	160	s->timer[id].freq = 24000000 /
	161	((GET_PRESCALER(s->reg_tcfg[0], 0) + 1) *
	162	(GET_DIVIDER(s->reg_tcfg[1], id)));
	163	}
	164
	165	if (freq != s->timer[id].freq) {
	166	ptimer_set_freq(s->timer[id].ptimer, s->timer[id].freq);
	167	DPRINTF("freq=%dHz\n", s->timer[id].freq);
	168	}
	169	}
	170
	171	/*
	172	* Counter tick handler
	173	*/
	174	static void exynos4210_pwm_tick(void *opaque)
	175	{
	176	Exynos4210PWM s = (Exynos4210PWM )opaque;
	177	Exynos4210PWMState p = (Exynos4210PWMState )s->parent;
	178	uint32_t id = s->id;
	179	bool cmp;
	180
	181	DPRINTF("timer %d tick\n", id);
	182
	183	/* set irq status */
	184	p->reg_tint_cstat \|= TINT_CSTAT_STATUS(id);
	185
	186	/* raise IRQ */
	187	if (p->reg_tint_cstat & TINT_CSTAT_ENABLE(id)) {
	188	DPRINTF("timer %d IRQ\n", id);
	189	qemu_irq_raise(p->timer[id].irq);
	190	}
	191
	192	/* reload timer */
	193	if (id != 4) {
	194	cmp = p->reg_tcon & TCON_TIMER_AUTO_RELOAD(id);
	195	} else {
	196	cmp = p->reg_tcon & TCON_TIMER4_AUTO_RELOAD;
	197	}
	198
	199	if (cmp) {
	200	DPRINTF("auto reload timer %d count to %x\n", id,
201	p->timer[id].reg_tcntb);
202	ptimer_set_count(p->timer[id].ptimer, p->timer[id].reg_tcntb);
203	ptimer_run(p->timer[id].ptimer, 1);
204	} else {
205	/* stop timer, set status to STOP, see Basic Timer Operation */
b631bc37	206	p->reg_tcon &= ~TCON_TIMER_START(id);
62db8bf3 EV	207	ptimer_stop(p->timer[id].ptimer);
	208	}
	209	}
	210
	211	/*
	212	* PWM Read
	213	*/
a8170e5e	214	static uint64_t exynos4210_pwm_read(void *opaque, hwaddr offset,
62db8bf3 EV	215	unsigned size)
	216	{
	217	Exynos4210PWMState s = (Exynos4210PWMState )opaque;
	218	uint32_t value = 0;
	219	int index;
	220
	221	switch (offset) {
	222	case TCFG0: case TCFG1:
	223	index = (offset - TCFG0) >> 2;
	224	value = s->reg_tcfg[index];
	225	break;
	226
	227	case TCON:
	228	value = s->reg_tcon;
	229	break;
	230
	231	case TCNTB0: case TCNTB1:
	232	case TCNTB2: case TCNTB3: case TCNTB4:
	233	index = (offset - TCNTB0) / 0xC;
	234	value = s->timer[index].reg_tcntb;
	235	break;
	236
	237	case TCMPB0: case TCMPB1:
	238	case TCMPB2: case TCMPB3:
	239	index = (offset - TCMPB0) / 0xC;
	240	value = s->timer[index].reg_tcmpb;
	241	break;
	242
	243	case TCNTO0: case TCNTO1:
	244	case TCNTO2: case TCNTO3: case TCNTO4:
	245	index = (offset == TCNTO4) ? 4 : (offset - TCNTO0) / 0xC;
	246	value = ptimer_get_count(s->timer[index].ptimer);
	247	break;
	248
	249	case TINT_CSTAT:
	250	value = s->reg_tint_cstat;
	251	break;
	252
	253	default:
	254	fprintf(stderr,
	255	"[exynos4210.pwm: bad read offset " TARGET_FMT_plx "]\n",
	256	offset);
	257	break;
	258	}
	259	return value;
	260	}
	261
	262	/*
	263	* PWM Write
	264	*/
a8170e5e	265	static void exynos4210_pwm_write(void *opaque, hwaddr offset,
62db8bf3 EV	266	uint64_t value, unsigned size)
	267	{
	268	Exynos4210PWMState s = (Exynos4210PWMState )opaque;
	269	int index;
	270	uint32_t new_val;
	271	int i;
	272
	273	switch (offset) {
	274	case TCFG0: case TCFG1:
	275	index = (offset - TCFG0) >> 2;
	276	s->reg_tcfg[index] = value;
	277
	278	/* update timers frequencies */
	279	for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) {
	280	exynos4210_pwm_update_freq(s, s->timer[i].id);
	281	}
	282	break;
	283
	284	case TCON:
	285	for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) {
	286	if ((value & TCON_TIMER_MANUAL_UPD(i)) >
	287	(s->reg_tcon & TCON_TIMER_MANUAL_UPD(i))) {
	288	/*
	289	* TCNTB and TCMPB are loaded into TCNT and TCMP.
	290	* Update timers.
	291	*/
	292
	293	/* this will start timer to run, this ok, because
	294	* during processing start bit timer will be stopped
	295	* if needed */
	296	ptimer_set_count(s->timer[i].ptimer, s->timer[i].reg_tcntb);
	297	DPRINTF("set timer %d count to %x\n", i,
	298	s->timer[i].reg_tcntb);
	299	}
	300
	301	if ((value & TCON_TIMER_START(i)) >
	302	(s->reg_tcon & TCON_TIMER_START(i))) {
	303	/* changed to start */
	304	ptimer_run(s->timer[i].ptimer, 1);
	305	DPRINTF("run timer %d\n", i);
	306	}
	307
	308	if ((value & TCON_TIMER_START(i)) <
	309	(s->reg_tcon & TCON_TIMER_START(i))) {
	310	/* changed to stop */
	311	ptimer_stop(s->timer[i].ptimer);
	312	DPRINTF("stop timer %d\n", i);
	313	}
	314	}
	315	s->reg_tcon = value;
	316	break;
	317
	318	case TCNTB0: case TCNTB1:
	319	case TCNTB2: case TCNTB3: case TCNTB4:
	320	index = (offset - TCNTB0) / 0xC;
	321	s->timer[index].reg_tcntb = value;
	322	break;
	323
	324	case TCMPB0: case TCMPB1:
	325	case TCMPB2: case TCMPB3:
	326	index = (offset - TCMPB0) / 0xC;
	327	s->timer[index].reg_tcmpb = value;
	328	break;
	329
330	case TINT_CSTAT:
331	new_val = (s->reg_tint_cstat & 0x3E0) + (0x1F & value);
332	new_val &= ~(0x3E0 & value);
333
334	for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) {
335	if ((new_val & TINT_CSTAT_STATUS(i)) <
336	(s->reg_tint_cstat & TINT_CSTAT_STATUS(i))) {
337	qemu_irq_lower(s->timer[i].irq);
338	}
339	}
340
341	s->reg_tint_cstat = new_val;
342	break;
343
344	default:
345	fprintf(stderr,
346	"[exynos4210.pwm: bad write offset " TARGET_FMT_plx "]\n",
347	offset);
348	break;
349
350	}
351	}
352
353	/*
354	* Set default values to timer fields and registers
355	*/
356	static void exynos4210_pwm_reset(DeviceState *d)
357	{
25fce9ad	358	Exynos4210PWMState *s = EXYNOS4210_PWM(d);
62db8bf3 EV	359	int i;
	360	s->reg_tcfg[0] = 0x0101;
	361	s->reg_tcfg[1] = 0x0;
	362	s->reg_tcon = 0;
	363	s->reg_tint_cstat = 0;
	364	for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) {
	365	s->timer[i].reg_tcmpb = 0;
	366	s->timer[i].reg_tcntb = 0;
	367
	368	exynos4210_pwm_update_freq(s, s->timer[i].id);
	369	ptimer_stop(s->timer[i].ptimer);
	370	}
	371	}
	372
	373	static const MemoryRegionOps exynos4210_pwm_ops = {
	374	.read = exynos4210_pwm_read,
	375	.write = exynos4210_pwm_write,
	376	.endianness = DEVICE_NATIVE_ENDIAN,
	377	};
	378
	379	/*
	380	* PWM timer initialization
	381	*/
	382	static int exynos4210_pwm_init(SysBusDevice *dev)
	383	{
25fce9ad	384	Exynos4210PWMState *s = EXYNOS4210_PWM(dev);
62db8bf3 EV	385	int i;
	386	QEMUBH *bh;
	387
	388	for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) {
	389	bh = qemu_bh_new(exynos4210_pwm_tick, &s->timer[i]);
	390	sysbus_init_irq(dev, &s->timer[i].irq);
	391	s->timer[i].ptimer = ptimer_init(bh);
	392	s->timer[i].id = i;
	393	s->timer[i].parent = s;
	394	}
	395
853dca12 PB	396	memory_region_init_io(&s->iomem, OBJECT(s), &exynos4210_pwm_ops, s,
853dca12 PB	397	"exynos4210-pwm", EXYNOS4210_PWM_REG_MEM_SIZE);
62db8bf3 EV	398	sysbus_init_mmio(dev, &s->iomem);
	399
	400	return 0;
	401	}
	402
	403	static void exynos4210_pwm_class_init(ObjectClass klass, void data)
	404	{
	405	DeviceClass *dc = DEVICE_CLASS(klass);
	406	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	407
	408	k->init = exynos4210_pwm_init;
	409	dc->reset = exynos4210_pwm_reset;
	410	dc->vmsd = &vmstate_exynos4210_pwm_state;
	411	}
	412
8c43a6f0	413	static const TypeInfo exynos4210_pwm_info = {
25fce9ad	414	.name = TYPE_EXYNOS4210_PWM,
62db8bf3 EV	415	.parent = TYPE_SYS_BUS_DEVICE,
	416	.instance_size = sizeof(Exynos4210PWMState),
	417	.class_init = exynos4210_pwm_class_init,
	418	};
	419
	420	static void exynos4210_pwm_register_types(void)
	421	{
	422	type_register_static(&exynos4210_pwm_info);
	423	}
	424
	425	type_init(exynos4210_pwm_register_types)