[qemu.git] / target-i386 / misc_helper.c

/*
 *  x86 misc helpers
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/cpu_ldst.h"
#include "exec/address-spaces.h"

void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)
{
#ifdef CONFIG_USER_ONLY
    fprintf(stderr, "outb: port=0x%04x, data=%02x\n", port, data);
#else
    address_space_stb(&address_space_io, port, data,
                      cpu_get_mem_attrs(env), NULL);
#endif
}

target_ulong helper_inb(CPUX86State *env, uint32_t port)
{
#ifdef CONFIG_USER_ONLY
    fprintf(stderr, "inb: port=0x%04x\n", port);
    return 0;
#else
    return address_space_ldub(&address_space_io, port,
                              cpu_get_mem_attrs(env), NULL);
#endif
}

void helper_outw(CPUX86State *env, uint32_t port, uint32_t data)
{
#ifdef CONFIG_USER_ONLY
    fprintf(stderr, "outw: port=0x%04x, data=%04x\n", port, data);
#else
    address_space_stw(&address_space_io, port, data,
                      cpu_get_mem_attrs(env), NULL);
#endif
}

target_ulong helper_inw(CPUX86State *env, uint32_t port)
{
#ifdef CONFIG_USER_ONLY
    fprintf(stderr, "inw: port=0x%04x\n", port);
    return 0;
#else
    return address_space_lduw(&address_space_io, port,
                              cpu_get_mem_attrs(env), NULL);
#endif
}

void helper_outl(CPUX86State *env, uint32_t port, uint32_t data)
{
#ifdef CONFIG_USER_ONLY
    fprintf(stderr, "outw: port=0x%04x, data=%08x\n", port, data);
#else
    address_space_stl(&address_space_io, port, data,
                      cpu_get_mem_attrs(env), NULL);
#endif
}

target_ulong helper_inl(CPUX86State *env, uint32_t port)
{
#ifdef CONFIG_USER_ONLY
    fprintf(stderr, "inl: port=0x%04x\n", port);
    return 0;
#else
    return address_space_ldl(&address_space_io, port,
                             cpu_get_mem_attrs(env), NULL);
#endif
}

void helper_into(CPUX86State *env, int next_eip_addend)
{
    int eflags;

    eflags = cpu_cc_compute_all(env, CC_OP);
    if (eflags & CC_O) {
        raise_interrupt(env, EXCP04_INTO, 1, 0, next_eip_addend);
    }
}

void helper_cpuid(CPUX86State *env)
{
    uint32_t eax, ebx, ecx, edx;

    cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0);

    cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX],
                  &eax, &ebx, &ecx, &edx);
    env->regs[R_EAX] = eax;
    env->regs[R_EBX] = ebx;
    env->regs[R_ECX] = ecx;
    env->regs[R_EDX] = edx;
}

#if defined(CONFIG_USER_ONLY)
target_ulong helper_read_crN(CPUX86State *env, int reg)
{
    return 0;
}

void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
{
}
#else
target_ulong helper_read_crN(CPUX86State *env, int reg)
{
    target_ulong val;

    cpu_svm_check_intercept_param(env, SVM_EXIT_READ_CR0 + reg, 0);
    switch (reg) {
    default:
        val = env->cr[reg];
        break;
    case 8:
        if (!(env->hflags2 & HF2_VINTR_MASK)) {
            val = cpu_get_apic_tpr(x86_env_get_cpu(env)->apic_state);
        } else {
            val = env->v_tpr;
        }
        break;
    }
    return val;
}

void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
{
    cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0);
    switch (reg) {
    case 0:
        cpu_x86_update_cr0(env, t0);
        break;
    case 3:
        cpu_x86_update_cr3(env, t0);
        break;
    case 4:
        cpu_x86_update_cr4(env, t0);
        break;
    case 8:
        if (!(env->hflags2 & HF2_VINTR_MASK)) {
            cpu_set_apic_tpr(x86_env_get_cpu(env)->apic_state, t0);
        }
        env->v_tpr = t0 & 0x0f;
        break;
    default:
        env->cr[reg] = t0;
        break;
    }
}
#endif

void helper_lmsw(CPUX86State *env, target_ulong t0)
{
    /* only 4 lower bits of CR0 are modified. PE cannot be set to zero
       if already set to one. */
    t0 = (env->cr[0] & ~0xe) | (t0 & 0xf);
    helper_write_crN(env, 0, t0);
}

void helper_invlpg(CPUX86State *env, target_ulong addr)
{
    X86CPU *cpu = x86_env_get_cpu(env);

    cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0);
    tlb_flush_page(CPU(cpu), addr);
}

void helper_rdtsc(CPUX86State *env)
{
    uint64_t val;

    if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
        raise_exception_ra(env, EXCP0D_GPF, GETPC());
    }
    cpu_svm_check_intercept_param(env, SVM_EXIT_RDTSC, 0);

    val = cpu_get_tsc(env) + env->tsc_offset;
    env->regs[R_EAX] = (uint32_t)(val);
    env->regs[R_EDX] = (uint32_t)(val >> 32);
}

void helper_rdtscp(CPUX86State *env)
{
    helper_rdtsc(env);
    env->regs[R_ECX] = (uint32_t)(env->tsc_aux);
}

void helper_rdpmc(CPUX86State *env)
{
    if ((env->cr[4] & CR4_PCE_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
        raise_exception_ra(env, EXCP0D_GPF, GETPC());
    }
    cpu_svm_check_intercept_param(env, SVM_EXIT_RDPMC, 0);

    /* currently unimplemented */
    qemu_log_mask(LOG_UNIMP, "x86: unimplemented rdpmc\n");
    raise_exception_err(env, EXCP06_ILLOP, 0);
}

#if defined(CONFIG_USER_ONLY)
void helper_wrmsr(CPUX86State *env)
{
}

void helper_rdmsr(CPUX86State *env)
{
}
#else
void helper_wrmsr(CPUX86State *env)
{
    uint64_t val;

    cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1);

    val = ((uint32_t)env->regs[R_EAX]) |
        ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);

    switch ((uint32_t)env->regs[R_ECX]) {
    case MSR_IA32_SYSENTER_CS:
        env->sysenter_cs = val & 0xffff;
        break;
    case MSR_IA32_SYSENTER_ESP:
        env->sysenter_esp = val;
        break;
    case MSR_IA32_SYSENTER_EIP:
        env->sysenter_eip = val;
        break;
    case MSR_IA32_APICBASE:
        cpu_set_apic_base(x86_env_get_cpu(env)->apic_state, val);
        break;
    case MSR_EFER:
        {
            uint64_t update_mask;

            update_mask = 0;
            if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_SYSCALL) {
                update_mask |= MSR_EFER_SCE;
            }
            if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
                update_mask |= MSR_EFER_LME;
            }
            if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
                update_mask |= MSR_EFER_FFXSR;
            }
            if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_NX) {
                update_mask |= MSR_EFER_NXE;
            }
            if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
                update_mask |= MSR_EFER_SVME;
            }
            if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
                update_mask |= MSR_EFER_FFXSR;
            }
            cpu_load_efer(env, (env->efer & ~update_mask) |
                          (val & update_mask));
        }
        break;
    case MSR_STAR:
        env->star = val;
        break;
    case MSR_PAT:
        env->pat = val;
        break;
    case MSR_VM_HSAVE_PA:
        env->vm_hsave = val;
        break;
#ifdef TARGET_X86_64
    case MSR_LSTAR:
        env->lstar = val;
        break;
    case MSR_CSTAR:
        env->cstar = val;
        break;
    case MSR_FMASK:
        env->fmask = val;
        break;
    case MSR_FSBASE:
        env->segs[R_FS].base = val;
        break;
    case MSR_GSBASE:
        env->segs[R_GS].base = val;
        break;
    case MSR_KERNELGSBASE:
        env->kernelgsbase = val;
        break;
#endif
    case MSR_MTRRphysBase(0):
    case MSR_MTRRphysBase(1):
    case MSR_MTRRphysBase(2):
    case MSR_MTRRphysBase(3):
    case MSR_MTRRphysBase(4):
    case MSR_MTRRphysBase(5):
    case MSR_MTRRphysBase(6):
    case MSR_MTRRphysBase(7):
        env->mtrr_var[((uint32_t)env->regs[R_ECX] -
                       MSR_MTRRphysBase(0)) / 2].base = val;
        break;
    case MSR_MTRRphysMask(0):
    case MSR_MTRRphysMask(1):
    case MSR_MTRRphysMask(2):
    case MSR_MTRRphysMask(3):
    case MSR_MTRRphysMask(4):
    case MSR_MTRRphysMask(5):
    case MSR_MTRRphysMask(6):
    case MSR_MTRRphysMask(7):
        env->mtrr_var[((uint32_t)env->regs[R_ECX] -
                       MSR_MTRRphysMask(0)) / 2].mask = val;
        break;
    case MSR_MTRRfix64K_00000:
        env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
                        MSR_MTRRfix64K_00000] = val;
        break;
    case MSR_MTRRfix16K_80000:
    case MSR_MTRRfix16K_A0000:
        env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
                        MSR_MTRRfix16K_80000 + 1] = val;
        break;
    case MSR_MTRRfix4K_C0000:
    case MSR_MTRRfix4K_C8000:
    case MSR_MTRRfix4K_D0000:
    case MSR_MTRRfix4K_D8000:
    case MSR_MTRRfix4K_E0000:
    case MSR_MTRRfix4K_E8000:
    case MSR_MTRRfix4K_F0000:
    case MSR_MTRRfix4K_F8000:
        env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
                        MSR_MTRRfix4K_C0000 + 3] = val;
        break;
    case MSR_MTRRdefType:
        env->mtrr_deftype = val;
        break;
    case MSR_MCG_STATUS:
        env->mcg_status = val;
        break;
    case MSR_MCG_CTL:
        if ((env->mcg_cap & MCG_CTL_P)
            && (val == 0 || val == ~(uint64_t)0)) {
            env->mcg_ctl = val;
        }
        break;
    case MSR_TSC_AUX:
        env->tsc_aux = val;
        break;
    case MSR_IA32_MISC_ENABLE:
        env->msr_ia32_misc_enable = val;
        break;
    default:
        if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
            && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
            (4 * env->mcg_cap & 0xff)) {
            uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
            if ((offset & 0x3) != 0
                || (val == 0 || val == ~(uint64_t)0)) {
                env->mce_banks[offset] = val;
            }
            break;
        }
        /* XXX: exception? */
        break;
    }
}

void helper_rdmsr(CPUX86State *env)
{
    uint64_t val;

    cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0);

    switch ((uint32_t)env->regs[R_ECX]) {
    case MSR_IA32_SYSENTER_CS:
        val = env->sysenter_cs;
        break;
    case MSR_IA32_SYSENTER_ESP:
        val = env->sysenter_esp;
        break;
    case MSR_IA32_SYSENTER_EIP:
        val = env->sysenter_eip;
        break;
    case MSR_IA32_APICBASE:
        val = cpu_get_apic_base(x86_env_get_cpu(env)->apic_state);
        break;
    case MSR_EFER:
        val = env->efer;
        break;
    case MSR_STAR:
        val = env->star;
        break;
    case MSR_PAT:
        val = env->pat;
        break;
    case MSR_VM_HSAVE_PA:
        val = env->vm_hsave;
        break;
    case MSR_IA32_PERF_STATUS:
        /* tsc_increment_by_tick */
        val = 1000ULL;
        /* CPU multiplier */
        val |= (((uint64_t)4ULL) << 40);
        break;
#ifdef TARGET_X86_64
    case MSR_LSTAR:
        val = env->lstar;
        break;
    case MSR_CSTAR:
        val = env->cstar;
        break;
    case MSR_FMASK:
        val = env->fmask;
        break;
    case MSR_FSBASE:
        val = env->segs[R_FS].base;
        break;
    case MSR_GSBASE:
        val = env->segs[R_GS].base;
        break;
    case MSR_KERNELGSBASE:
        val = env->kernelgsbase;
        break;
    case MSR_TSC_AUX:
        val = env->tsc_aux;
        break;
#endif
    case MSR_MTRRphysBase(0):
    case MSR_MTRRphysBase(1):
    case MSR_MTRRphysBase(2):
    case MSR_MTRRphysBase(3):
    case MSR_MTRRphysBase(4):
    case MSR_MTRRphysBase(5):
    case MSR_MTRRphysBase(6):
    case MSR_MTRRphysBase(7):
        val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
                             MSR_MTRRphysBase(0)) / 2].base;
        break;
    case MSR_MTRRphysMask(0):
    case MSR_MTRRphysMask(1):
    case MSR_MTRRphysMask(2):
    case MSR_MTRRphysMask(3):
    case MSR_MTRRphysMask(4):
    case MSR_MTRRphysMask(5):
    case MSR_MTRRphysMask(6):
    case MSR_MTRRphysMask(7):
        val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
                             MSR_MTRRphysMask(0)) / 2].mask;
        break;
    case MSR_MTRRfix64K_00000:
        val = env->mtrr_fixed[0];
        break;
    case MSR_MTRRfix16K_80000:
    case MSR_MTRRfix16K_A0000:
        val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
                              MSR_MTRRfix16K_80000 + 1];
        break;
    case MSR_MTRRfix4K_C0000:
    case MSR_MTRRfix4K_C8000:
    case MSR_MTRRfix4K_D0000:
    case MSR_MTRRfix4K_D8000:
    case MSR_MTRRfix4K_E0000:
    case MSR_MTRRfix4K_E8000:
    case MSR_MTRRfix4K_F0000:
    case MSR_MTRRfix4K_F8000:
        val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
                              MSR_MTRRfix4K_C0000 + 3];
        break;
    case MSR_MTRRdefType:
        val = env->mtrr_deftype;
        break;
    case MSR_MTRRcap:
        if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
            val = MSR_MTRRcap_VCNT | MSR_MTRRcap_FIXRANGE_SUPPORT |
                MSR_MTRRcap_WC_SUPPORTED;
        } else {
            /* XXX: exception? */
            val = 0;
        }
        break;
    case MSR_MCG_CAP:
        val = env->mcg_cap;
        break;
    case MSR_MCG_CTL:
        if (env->mcg_cap & MCG_CTL_P) {
            val = env->mcg_ctl;
        } else {
            val = 0;
        }
        break;
    case MSR_MCG_STATUS:
        val = env->mcg_status;
        break;
    case MSR_IA32_MISC_ENABLE:
        val = env->msr_ia32_misc_enable;
        break;
    default:
        if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
            && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
            (4 * env->mcg_cap & 0xff)) {
            uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
            val = env->mce_banks[offset];
            break;
        }
        /* XXX: exception? */
        val = 0;
        break;
    }
    env->regs[R_EAX] = (uint32_t)(val);
    env->regs[R_EDX] = (uint32_t)(val >> 32);
}
#endif

static void do_pause(X86CPU *cpu)
{
    CPUState *cs = CPU(cpu);

    /* Just let another CPU run.  */
    cs->exception_index = EXCP_INTERRUPT;
    cpu_loop_exit(cs);
}

static void do_hlt(X86CPU *cpu)
{
    CPUState *cs = CPU(cpu);
    CPUX86State *env = &cpu->env;

    env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
    cs->halted = 1;
    cs->exception_index = EXCP_HLT;
    cpu_loop_exit(cs);
}

void helper_hlt(CPUX86State *env, int next_eip_addend)
{
    X86CPU *cpu = x86_env_get_cpu(env);

    cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0);
    env->eip += next_eip_addend;

    do_hlt(cpu);
}

void helper_monitor(CPUX86State *env, target_ulong ptr)
{
    if ((uint32_t)env->regs[R_ECX] != 0) {
        raise_exception_ra(env, EXCP0D_GPF, GETPC());
    }
    /* XXX: store address? */
    cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0);
}

void helper_mwait(CPUX86State *env, int next_eip_addend)
{
    CPUState *cs;
    X86CPU *cpu;

    if ((uint32_t)env->regs[R_ECX] != 0) {
        raise_exception_ra(env, EXCP0D_GPF, GETPC());
    }
    cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0);
    env->eip += next_eip_addend;

    cpu = x86_env_get_cpu(env);
    cs = CPU(cpu);
    /* XXX: not complete but not completely erroneous */
    if (cs->cpu_index != 0 || CPU_NEXT(cs) != NULL) {
        do_pause(cpu);
    } else {
        do_hlt(cpu);
    }
}

void helper_pause(CPUX86State *env, int next_eip_addend)
{
    X86CPU *cpu = x86_env_get_cpu(env);

    cpu_svm_check_intercept_param(env, SVM_EXIT_PAUSE, 0);
    env->eip += next_eip_addend;

    do_pause(cpu);
}

void helper_debug(CPUX86State *env)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));

    cs->exception_index = EXCP_DEBUG;
    cpu_loop_exit(cs);
}
Commit	Line	Data
f7b2429f BS	1	/*
	2	* x86 misc helpers
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
b6a0aa05	20	#include "qemu/osdep.h"
f7b2429f	21	#include "cpu.h"
2ef6175a	22	#include "exec/helper-proto.h"
f08b6170	23	#include "exec/cpu_ldst.h"
3f7d8464	24	#include "exec/address-spaces.h"
92fc4b58	25
3f7d8464	26	void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)
f7b2429f	27	{
3f7d8464 PB	28	#ifdef CONFIG_USER_ONLY
	29	fprintf(stderr, "outb: port=0x%04x, data=%02x\n", port, data);
	30	#else
	31	address_space_stb(&address_space_io, port, data,
	32	cpu_get_mem_attrs(env), NULL);
	33	#endif
f7b2429f BS	34	}
f7b2429f BS	35
3f7d8464	36	target_ulong helper_inb(CPUX86State *env, uint32_t port)
f7b2429f	37	{
3f7d8464 PB	38	#ifdef CONFIG_USER_ONLY
	39	fprintf(stderr, "inb: port=0x%04x\n", port);
	40	return 0;
	41	#else
	42	return address_space_ldub(&address_space_io, port,
	43	cpu_get_mem_attrs(env), NULL);
	44	#endif
f7b2429f BS	45	}
f7b2429f BS	46
3f7d8464	47	void helper_outw(CPUX86State *env, uint32_t port, uint32_t data)
f7b2429f	48	{
3f7d8464 PB	49	#ifdef CONFIG_USER_ONLY
	50	fprintf(stderr, "outw: port=0x%04x, data=%04x\n", port, data);
	51	#else
	52	address_space_stw(&address_space_io, port, data,
	53	cpu_get_mem_attrs(env), NULL);
	54	#endif
f7b2429f BS	55	}
f7b2429f BS	56
3f7d8464	57	target_ulong helper_inw(CPUX86State *env, uint32_t port)
f7b2429f	58	{
3f7d8464 PB	59	#ifdef CONFIG_USER_ONLY
	60	fprintf(stderr, "inw: port=0x%04x\n", port);
	61	return 0;
	62	#else
	63	return address_space_lduw(&address_space_io, port,
	64	cpu_get_mem_attrs(env), NULL);
	65	#endif
f7b2429f BS	66	}
f7b2429f BS	67
3f7d8464	68	void helper_outl(CPUX86State *env, uint32_t port, uint32_t data)
f7b2429f	69	{
3f7d8464 PB	70	#ifdef CONFIG_USER_ONLY
	71	fprintf(stderr, "outw: port=0x%04x, data=%08x\n", port, data);
	72	#else
	73	address_space_stl(&address_space_io, port, data,
	74	cpu_get_mem_attrs(env), NULL);
	75	#endif
f7b2429f BS	76	}
f7b2429f BS	77
3f7d8464	78	target_ulong helper_inl(CPUX86State *env, uint32_t port)
f7b2429f	79	{
3f7d8464 PB	80	#ifdef CONFIG_USER_ONLY
	81	fprintf(stderr, "inl: port=0x%04x\n", port);
	82	return 0;
	83	#else
	84	return address_space_ldl(&address_space_io, port,
	85	cpu_get_mem_attrs(env), NULL);
	86	#endif
f7b2429f BS	87	}
f7b2429f BS	88
4a7443be	89	void helper_into(CPUX86State *env, int next_eip_addend)
f7b2429f BS	90	{
	91	int eflags;
	92
f0967a1a	93	eflags = cpu_cc_compute_all(env, CC_OP);
f7b2429f BS	94	if (eflags & CC_O) {
	95	raise_interrupt(env, EXCP04_INTO, 1, 0, next_eip_addend);
	96	}
	97	}
	98
4a7443be	99	void helper_cpuid(CPUX86State *env)
f7b2429f BS	100	{
	101	uint32_t eax, ebx, ecx, edx;
	102
	103	cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0);
	104
90a2541b LG	105	cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX],
90a2541b LG	106	&eax, &ebx, &ecx, &edx);
4b34e3ad	107	env->regs[R_EAX] = eax;
70b51365	108	env->regs[R_EBX] = ebx;
a4165610	109	env->regs[R_ECX] = ecx;
00f5e6f2	110	env->regs[R_EDX] = edx;
f7b2429f BS	111	}
	112
	113	#if defined(CONFIG_USER_ONLY)
4a7443be	114	target_ulong helper_read_crN(CPUX86State *env, int reg)
f7b2429f BS	115	{
	116	return 0;
	117	}
	118
4a7443be	119	void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
f7b2429f BS	120	{
f7b2429f BS	121	}
f7b2429f	122	#else
4a7443be	123	target_ulong helper_read_crN(CPUX86State *env, int reg)
f7b2429f BS	124	{
	125	target_ulong val;
	126
	127	cpu_svm_check_intercept_param(env, SVM_EXIT_READ_CR0 + reg, 0);
	128	switch (reg) {
	129	default:
	130	val = env->cr[reg];
	131	break;
	132	case 8:
	133	if (!(env->hflags2 & HF2_VINTR_MASK)) {
02e51483	134	val = cpu_get_apic_tpr(x86_env_get_cpu(env)->apic_state);
f7b2429f BS	135	} else {
	136	val = env->v_tpr;
	137	}
	138	break;
	139	}
	140	return val;
	141	}
	142
4a7443be	143	void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
f7b2429f BS	144	{
	145	cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0);
	146	switch (reg) {
	147	case 0:
	148	cpu_x86_update_cr0(env, t0);
	149	break;
	150	case 3:
	151	cpu_x86_update_cr3(env, t0);
	152	break;
	153	case 4:
	154	cpu_x86_update_cr4(env, t0);
	155	break;
	156	case 8:
	157	if (!(env->hflags2 & HF2_VINTR_MASK)) {
02e51483	158	cpu_set_apic_tpr(x86_env_get_cpu(env)->apic_state, t0);
f7b2429f BS	159	}
	160	env->v_tpr = t0 & 0x0f;
	161	break;
	162	default:
	163	env->cr[reg] = t0;
	164	break;
	165	}
	166	}
f7b2429f BS	167	#endif
f7b2429f BS	168
4a7443be	169	void helper_lmsw(CPUX86State *env, target_ulong t0)
f7b2429f BS	170	{
	171	/* only 4 lower bits of CR0 are modified. PE cannot be set to zero
	172	if already set to one. */
	173	t0 = (env->cr[0] & ~0xe) \| (t0 & 0xf);
4a7443be	174	helper_write_crN(env, 0, t0);
f7b2429f BS	175	}
f7b2429f BS	176
4a7443be	177	void helper_invlpg(CPUX86State *env, target_ulong addr)
f7b2429f	178	{
31b030d4 AF	179	X86CPU *cpu = x86_env_get_cpu(env);
31b030d4 AF	180
f7b2429f	181	cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0);
31b030d4	182	tlb_flush_page(CPU(cpu), addr);
f7b2429f BS	183	}
f7b2429f BS	184
4a7443be	185	void helper_rdtsc(CPUX86State *env)
f7b2429f BS	186	{
	187	uint64_t val;
	188
	189	if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
4054cdec	190	raise_exception_ra(env, EXCP0D_GPF, GETPC());
f7b2429f BS	191	}
	192	cpu_svm_check_intercept_param(env, SVM_EXIT_RDTSC, 0);
	193
	194	val = cpu_get_tsc(env) + env->tsc_offset;
4b34e3ad	195	env->regs[R_EAX] = (uint32_t)(val);
00f5e6f2	196	env->regs[R_EDX] = (uint32_t)(val >> 32);
f7b2429f BS	197	}
f7b2429f BS	198
4a7443be	199	void helper_rdtscp(CPUX86State *env)
f7b2429f	200	{
4a7443be	201	helper_rdtsc(env);
a4165610	202	env->regs[R_ECX] = (uint32_t)(env->tsc_aux);
f7b2429f BS	203	}
f7b2429f BS	204
4a7443be	205	void helper_rdpmc(CPUX86State *env)
f7b2429f BS	206	{
f7b2429f BS	207	if ((env->cr[4] & CR4_PCE_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
4054cdec	208	raise_exception_ra(env, EXCP0D_GPF, GETPC());
f7b2429f BS	209	}
	210	cpu_svm_check_intercept_param(env, SVM_EXIT_RDPMC, 0);
	211
	212	/* currently unimplemented */
	213	qemu_log_mask(LOG_UNIMP, "x86: unimplemented rdpmc\n");
	214	raise_exception_err(env, EXCP06_ILLOP, 0);
	215	}
	216
	217	#if defined(CONFIG_USER_ONLY)
4a7443be	218	void helper_wrmsr(CPUX86State *env)
f7b2429f BS	219	{
	220	}
	221
4a7443be	222	void helper_rdmsr(CPUX86State *env)
f7b2429f BS	223	{
	224	}
	225	#else
4a7443be	226	void helper_wrmsr(CPUX86State *env)
f7b2429f BS	227	{
	228	uint64_t val;
	229
	230	cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1);
	231
90a2541b LG	232	val = ((uint32_t)env->regs[R_EAX]) \|
90a2541b LG	233	((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
f7b2429f	234
a4165610	235	switch ((uint32_t)env->regs[R_ECX]) {
f7b2429f BS	236	case MSR_IA32_SYSENTER_CS:
	237	env->sysenter_cs = val & 0xffff;
	238	break;
	239	case MSR_IA32_SYSENTER_ESP:
	240	env->sysenter_esp = val;
	241	break;
	242	case MSR_IA32_SYSENTER_EIP:
	243	env->sysenter_eip = val;
	244	break;
	245	case MSR_IA32_APICBASE:
02e51483	246	cpu_set_apic_base(x86_env_get_cpu(env)->apic_state, val);
f7b2429f BS	247	break;
	248	case MSR_EFER:
	249	{
	250	uint64_t update_mask;
	251
	252	update_mask = 0;
0514ef2f	253	if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_SYSCALL) {
f7b2429f BS	254	update_mask \|= MSR_EFER_SCE;
f7b2429f BS	255	}
0514ef2f	256	if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
f7b2429f BS	257	update_mask \|= MSR_EFER_LME;
f7b2429f BS	258	}
0514ef2f	259	if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
f7b2429f BS	260	update_mask \|= MSR_EFER_FFXSR;
f7b2429f BS	261	}
0514ef2f	262	if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_NX) {
f7b2429f BS	263	update_mask \|= MSR_EFER_NXE;
f7b2429f BS	264	}
0514ef2f	265	if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
f7b2429f BS	266	update_mask \|= MSR_EFER_SVME;
f7b2429f BS	267	}
0514ef2f	268	if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
f7b2429f BS	269	update_mask \|= MSR_EFER_FFXSR;
	270	}
	271	cpu_load_efer(env, (env->efer & ~update_mask) \|
	272	(val & update_mask));
	273	}
	274	break;
	275	case MSR_STAR:
	276	env->star = val;
	277	break;
	278	case MSR_PAT:
	279	env->pat = val;
	280	break;
	281	case MSR_VM_HSAVE_PA:
	282	env->vm_hsave = val;
	283	break;
	284	#ifdef TARGET_X86_64
	285	case MSR_LSTAR:
	286	env->lstar = val;
	287	break;
	288	case MSR_CSTAR:
	289	env->cstar = val;
	290	break;
	291	case MSR_FMASK:
	292	env->fmask = val;
	293	break;
	294	case MSR_FSBASE:
	295	env->segs[R_FS].base = val;
	296	break;
	297	case MSR_GSBASE:
	298	env->segs[R_GS].base = val;
	299	break;
	300	case MSR_KERNELGSBASE:
	301	env->kernelgsbase = val;
	302	break;
	303	#endif
	304	case MSR_MTRRphysBase(0):
	305	case MSR_MTRRphysBase(1):
	306	case MSR_MTRRphysBase(2):
	307	case MSR_MTRRphysBase(3):
	308	case MSR_MTRRphysBase(4):
	309	case MSR_MTRRphysBase(5):
	310	case MSR_MTRRphysBase(6):
	311	case MSR_MTRRphysBase(7):
90a2541b LG	312	env->mtrr_var[((uint32_t)env->regs[R_ECX] -
90a2541b LG	313	MSR_MTRRphysBase(0)) / 2].base = val;
f7b2429f BS	314	break;
	315	case MSR_MTRRphysMask(0):
	316	case MSR_MTRRphysMask(1):
	317	case MSR_MTRRphysMask(2):
	318	case MSR_MTRRphysMask(3):
	319	case MSR_MTRRphysMask(4):
	320	case MSR_MTRRphysMask(5):
	321	case MSR_MTRRphysMask(6):
	322	case MSR_MTRRphysMask(7):
90a2541b LG	323	env->mtrr_var[((uint32_t)env->regs[R_ECX] -
90a2541b LG	324	MSR_MTRRphysMask(0)) / 2].mask = val;
f7b2429f BS	325	break;
f7b2429f BS	326	case MSR_MTRRfix64K_00000:
90a2541b LG	327	env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
90a2541b LG	328	MSR_MTRRfix64K_00000] = val;
f7b2429f BS	329	break;
	330	case MSR_MTRRfix16K_80000:
	331	case MSR_MTRRfix16K_A0000:
90a2541b LG	332	env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
90a2541b LG	333	MSR_MTRRfix16K_80000 + 1] = val;
f7b2429f BS	334	break;
	335	case MSR_MTRRfix4K_C0000:
	336	case MSR_MTRRfix4K_C8000:
	337	case MSR_MTRRfix4K_D0000:
	338	case MSR_MTRRfix4K_D8000:
	339	case MSR_MTRRfix4K_E0000:
	340	case MSR_MTRRfix4K_E8000:
	341	case MSR_MTRRfix4K_F0000:
	342	case MSR_MTRRfix4K_F8000:
90a2541b LG	343	env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
90a2541b LG	344	MSR_MTRRfix4K_C0000 + 3] = val;
f7b2429f BS	345	break;
	346	case MSR_MTRRdefType:
	347	env->mtrr_deftype = val;
	348	break;
	349	case MSR_MCG_STATUS:
	350	env->mcg_status = val;
	351	break;
	352	case MSR_MCG_CTL:
	353	if ((env->mcg_cap & MCG_CTL_P)
	354	&& (val == 0 \|\| val == ~(uint64_t)0)) {
	355	env->mcg_ctl = val;
	356	}
	357	break;
	358	case MSR_TSC_AUX:
	359	env->tsc_aux = val;
	360	break;
	361	case MSR_IA32_MISC_ENABLE:
	362	env->msr_ia32_misc_enable = val;
	363	break;
	364	default:
a4165610	365	if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
90a2541b LG	366	&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
90a2541b LG	367	(4 * env->mcg_cap & 0xff)) {
a4165610	368	uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
f7b2429f BS	369	if ((offset & 0x3) != 0
	370	\|\| (val == 0 \|\| val == ~(uint64_t)0)) {
	371	env->mce_banks[offset] = val;
	372	}
	373	break;
	374	}
	375	/* XXX: exception? */
	376	break;
	377	}
	378	}
	379
4a7443be	380	void helper_rdmsr(CPUX86State *env)
f7b2429f BS	381	{
	382	uint64_t val;
	383
	384	cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0);
	385
a4165610	386	switch ((uint32_t)env->regs[R_ECX]) {
f7b2429f BS	387	case MSR_IA32_SYSENTER_CS:
	388	val = env->sysenter_cs;
	389	break;
	390	case MSR_IA32_SYSENTER_ESP:
	391	val = env->sysenter_esp;
	392	break;
	393	case MSR_IA32_SYSENTER_EIP:
	394	val = env->sysenter_eip;
	395	break;
	396	case MSR_IA32_APICBASE:
02e51483	397	val = cpu_get_apic_base(x86_env_get_cpu(env)->apic_state);
f7b2429f BS	398	break;
	399	case MSR_EFER:
	400	val = env->efer;
	401	break;
	402	case MSR_STAR:
	403	val = env->star;
	404	break;
	405	case MSR_PAT:
	406	val = env->pat;
	407	break;
	408	case MSR_VM_HSAVE_PA:
	409	val = env->vm_hsave;
	410	break;
	411	case MSR_IA32_PERF_STATUS:
	412	/* tsc_increment_by_tick */
	413	val = 1000ULL;
	414	/* CPU multiplier */
	415	val \|= (((uint64_t)4ULL) << 40);
	416	break;
	417	#ifdef TARGET_X86_64
	418	case MSR_LSTAR:
	419	val = env->lstar;
	420	break;
	421	case MSR_CSTAR:
	422	val = env->cstar;
	423	break;
	424	case MSR_FMASK:
	425	val = env->fmask;
	426	break;
	427	case MSR_FSBASE:
	428	val = env->segs[R_FS].base;
	429	break;
	430	case MSR_GSBASE:
	431	val = env->segs[R_GS].base;
	432	break;
	433	case MSR_KERNELGSBASE:
	434	val = env->kernelgsbase;
	435	break;
	436	case MSR_TSC_AUX:
	437	val = env->tsc_aux;
	438	break;
	439	#endif
	440	case MSR_MTRRphysBase(0):
	441	case MSR_MTRRphysBase(1):
	442	case MSR_MTRRphysBase(2):
	443	case MSR_MTRRphysBase(3):
	444	case MSR_MTRRphysBase(4):
	445	case MSR_MTRRphysBase(5):
	446	case MSR_MTRRphysBase(6):
	447	case MSR_MTRRphysBase(7):
90a2541b LG	448	val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
90a2541b LG	449	MSR_MTRRphysBase(0)) / 2].base;
f7b2429f BS	450	break;
	451	case MSR_MTRRphysMask(0):
	452	case MSR_MTRRphysMask(1):
	453	case MSR_MTRRphysMask(2):
	454	case MSR_MTRRphysMask(3):
	455	case MSR_MTRRphysMask(4):
	456	case MSR_MTRRphysMask(5):
	457	case MSR_MTRRphysMask(6):
	458	case MSR_MTRRphysMask(7):
90a2541b LG	459	val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
90a2541b LG	460	MSR_MTRRphysMask(0)) / 2].mask;
f7b2429f BS	461	break;
	462	case MSR_MTRRfix64K_00000:
	463	val = env->mtrr_fixed[0];
	464	break;
	465	case MSR_MTRRfix16K_80000:
	466	case MSR_MTRRfix16K_A0000:
90a2541b LG	467	val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
90a2541b LG	468	MSR_MTRRfix16K_80000 + 1];
f7b2429f BS	469	break;
	470	case MSR_MTRRfix4K_C0000:
	471	case MSR_MTRRfix4K_C8000:
	472	case MSR_MTRRfix4K_D0000:
	473	case MSR_MTRRfix4K_D8000:
	474	case MSR_MTRRfix4K_E0000:
	475	case MSR_MTRRfix4K_E8000:
	476	case MSR_MTRRfix4K_F0000:
	477	case MSR_MTRRfix4K_F8000:
90a2541b LG	478	val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
90a2541b LG	479	MSR_MTRRfix4K_C0000 + 3];
f7b2429f BS	480	break;
	481	case MSR_MTRRdefType:
	482	val = env->mtrr_deftype;
	483	break;
	484	case MSR_MTRRcap:
0514ef2f	485	if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
f7b2429f BS	486	val = MSR_MTRRcap_VCNT \| MSR_MTRRcap_FIXRANGE_SUPPORT \|
	487	MSR_MTRRcap_WC_SUPPORTED;
	488	} else {
	489	/* XXX: exception? */
	490	val = 0;
	491	}
	492	break;
	493	case MSR_MCG_CAP:
	494	val = env->mcg_cap;
	495	break;
	496	case MSR_MCG_CTL:
	497	if (env->mcg_cap & MCG_CTL_P) {
	498	val = env->mcg_ctl;
	499	} else {
	500	val = 0;
	501	}
	502	break;
	503	case MSR_MCG_STATUS:
	504	val = env->mcg_status;
	505	break;
	506	case MSR_IA32_MISC_ENABLE:
	507	val = env->msr_ia32_misc_enable;
	508	break;
	509	default:
a4165610	510	if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
90a2541b LG	511	&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
90a2541b LG	512	(4 * env->mcg_cap & 0xff)) {
a4165610	513	uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
f7b2429f BS	514	val = env->mce_banks[offset];
	515	break;
	516	}
	517	/* XXX: exception? */
	518	val = 0;
	519	break;
	520	}
4b34e3ad	521	env->regs[R_EAX] = (uint32_t)(val);
00f5e6f2	522	env->regs[R_EDX] = (uint32_t)(val >> 32);
f7b2429f BS	523	}
	524	#endif
	525
81f3053b PB	526	static void do_pause(X86CPU *cpu)
81f3053b PB	527	{
27103424	528	CPUState *cs = CPU(cpu);
81f3053b PB	529
81f3053b PB	530	/* Just let another CPU run. */
27103424	531	cs->exception_index = EXCP_INTERRUPT;
5638d180	532	cpu_loop_exit(cs);
81f3053b PB	533	}
81f3053b PB	534
259186a7	535	static void do_hlt(X86CPU *cpu)
f7b2429f	536	{
259186a7 AF	537	CPUState *cs = CPU(cpu);
	538	CPUX86State *env = &cpu->env;
	539
f7b2429f	540	env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
259186a7	541	cs->halted = 1;
27103424	542	cs->exception_index = EXCP_HLT;
5638d180	543	cpu_loop_exit(cs);
f7b2429f BS	544	}
f7b2429f BS	545
4a7443be	546	void helper_hlt(CPUX86State *env, int next_eip_addend)
f7b2429f	547	{
259186a7 AF	548	X86CPU *cpu = x86_env_get_cpu(env);
259186a7 AF	549
f7b2429f	550	cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0);
a78d0eab	551	env->eip += next_eip_addend;
f7b2429f	552
259186a7	553	do_hlt(cpu);
f7b2429f BS	554	}
f7b2429f BS	555
4a7443be	556	void helper_monitor(CPUX86State *env, target_ulong ptr)
f7b2429f	557	{
a4165610	558	if ((uint32_t)env->regs[R_ECX] != 0) {
4054cdec	559	raise_exception_ra(env, EXCP0D_GPF, GETPC());
f7b2429f BS	560	}
	561	/* XXX: store address? */
	562	cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0);
	563	}
	564
4a7443be	565	void helper_mwait(CPUX86State *env, int next_eip_addend)
f7b2429f	566	{
259186a7 AF	567	CPUState *cs;
259186a7 AF	568	X86CPU *cpu;
55e5c285	569
a4165610	570	if ((uint32_t)env->regs[R_ECX] != 0) {
4054cdec	571	raise_exception_ra(env, EXCP0D_GPF, GETPC());
f7b2429f BS	572	}
f7b2429f BS	573	cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0);
a78d0eab	574	env->eip += next_eip_addend;
f7b2429f	575
259186a7 AF	576	cpu = x86_env_get_cpu(env);
259186a7 AF	577	cs = CPU(cpu);
f7b2429f	578	/* XXX: not complete but not completely erroneous */
bdc44640	579	if (cs->cpu_index != 0 \|\| CPU_NEXT(cs) != NULL) {
81f3053b	580	do_pause(cpu);
f7b2429f	581	} else {
259186a7	582	do_hlt(cpu);
f7b2429f BS	583	}
	584	}
	585
81f3053b PB	586	void helper_pause(CPUX86State *env, int next_eip_addend)
	587	{
	588	X86CPU *cpu = x86_env_get_cpu(env);
	589
	590	cpu_svm_check_intercept_param(env, SVM_EXIT_PAUSE, 0);
	591	env->eip += next_eip_addend;
	592
	593	do_pause(cpu);
	594	}
	595
4a7443be	596	void helper_debug(CPUX86State *env)
f7b2429f	597	{
27103424 AF	598	CPUState *cs = CPU(x86_env_get_cpu(env));
	599
	600	cs->exception_index = EXCP_DEBUG;
5638d180	601	cpu_loop_exit(cs);
f7b2429f	602	}