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[qemu.git] / tests / ivshmem-test.c
CommitLineData
bbfc2efe
AF
1/*
2 * QTest testcase for ivshmem
3 *
4 * Copyright (c) 2014 SUSE LINUX Products GmbH
ddef6a0d 5 * Copyright (c) 2015 Red Hat, Inc.
bbfc2efe
AF
6 *
7 * This work is licensed under the terms of the GNU GPL, version 2 or later.
8 * See the COPYING file in the top-level directory.
9 */
10
681c28a3 11#include "qemu/osdep.h"
ddef6a0d 12#include <glib/gstdio.h>
ddef6a0d 13#include <sys/mman.h>
ddef6a0d
MAL
14#include "contrib/ivshmem-server/ivshmem-server.h"
15#include "libqos/pci-pc.h"
bbfc2efe 16#include "libqtest.h"
ddef6a0d 17#include "qemu-common.h"
bbfc2efe 18
ddef6a0d
MAL
19#define TMPSHMSIZE (1 << 20)
20static char *tmpshm;
21static void *tmpshmem;
22static char *tmpdir;
23static char *tmpserver;
bbfc2efe 24
ddef6a0d 25static void save_fn(QPCIDevice *dev, int devfn, void *data)
bbfc2efe 26{
ddef6a0d
MAL
27 QPCIDevice **pdev = (QPCIDevice **) data;
28
29 *pdev = dev;
30}
31
1760048a 32static QPCIDevice *get_device(QPCIBus *pcibus)
ddef6a0d
MAL
33{
34 QPCIDevice *dev;
ddef6a0d 35
16130947 36 dev = NULL;
ddef6a0d
MAL
37 qpci_device_foreach(pcibus, 0x1af4, 0x1110, save_fn, &dev);
38 g_assert(dev != NULL);
39
40 return dev;
41}
42
43typedef struct _IVState {
44 QTestState *qtest;
45 void *reg_base, *mem_base;
1760048a 46 QPCIBus *pcibus;
ddef6a0d
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47 QPCIDevice *dev;
48} IVState;
49
50enum Reg {
51 INTRMASK = 0,
52 INTRSTATUS = 4,
53 IVPOSITION = 8,
54 DOORBELL = 12,
55};
56
57static const char* reg2str(enum Reg reg) {
58 switch (reg) {
59 case INTRMASK:
60 return "IntrMask";
61 case INTRSTATUS:
62 return "IntrStatus";
63 case IVPOSITION:
64 return "IVPosition";
65 case DOORBELL:
66 return "DoorBell";
67 default:
68 return NULL;
69 }
70}
71
72static inline unsigned in_reg(IVState *s, enum Reg reg)
73{
74 const char *name = reg2str(reg);
75 QTestState *qtest = global_qtest;
76 unsigned res;
77
78 global_qtest = s->qtest;
79 res = qpci_io_readl(s->dev, s->reg_base + reg);
80 g_test_message("*%s -> %x\n", name, res);
81 global_qtest = qtest;
82
83 return res;
84}
85
86static inline void out_reg(IVState *s, enum Reg reg, unsigned v)
87{
88 const char *name = reg2str(reg);
89 QTestState *qtest = global_qtest;
90
91 global_qtest = s->qtest;
92 g_test_message("%x -> *%s\n", v, name);
93 qpci_io_writel(s->dev, s->reg_base + reg, v);
94 global_qtest = qtest;
95}
96
1760048a
MAL
97static void cleanup_vm(IVState *s)
98{
99 g_free(s->dev);
100 qpci_free_pc(s->pcibus);
101 qtest_quit(s->qtest);
102}
103
ddef6a0d
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104static void setup_vm_cmd(IVState *s, const char *cmd, bool msix)
105{
106 uint64_t barsize;
107
108 s->qtest = qtest_start(cmd);
1760048a
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109 s->pcibus = qpci_init_pc();
110 s->dev = get_device(s->pcibus);
ddef6a0d 111
99826172
MA
112 s->reg_base = qpci_iomap(s->dev, 0, &barsize);
113 g_assert_nonnull(s->reg_base);
114 g_assert_cmpuint(barsize, ==, 256);
ddef6a0d
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115
116 if (msix) {
117 qpci_msix_enable(s->dev);
118 }
119
99826172
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120 s->mem_base = qpci_iomap(s->dev, 2, &barsize);
121 g_assert_nonnull(s->mem_base);
122 g_assert_cmpuint(barsize, ==, TMPSHMSIZE);
ddef6a0d
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123
124 qpci_device_enable(s->dev);
125}
126
127static void setup_vm(IVState *s)
128{
5400c02b
MA
129 char *cmd = g_strdup_printf("-object memory-backend-file"
130 ",id=mb1,size=1M,share,mem-path=/dev/shm%s"
131 " -device ivshmem-plain,memdev=mb1", tmpshm);
ddef6a0d
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132
133 setup_vm_cmd(s, cmd, false);
134
135 g_free(cmd);
136}
137
138static void test_ivshmem_single(void)
139{
140 IVState state, *s;
141 uint32_t data[1024];
142 int i;
143
144 setup_vm(&state);
145 s = &state;
146
4958fe5d
MA
147 /* initial state of readable registers */
148 g_assert_cmpuint(in_reg(s, INTRMASK), ==, 0);
149 g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 0);
150 g_assert_cmpuint(in_reg(s, IVPOSITION), ==, 0);
ddef6a0d 151
4958fe5d 152 /* trigger interrupt via registers */
ddef6a0d
MAL
153 out_reg(s, INTRMASK, 0xffffffff);
154 g_assert_cmpuint(in_reg(s, INTRMASK), ==, 0xffffffff);
155 out_reg(s, INTRSTATUS, 1);
4958fe5d 156 /* check interrupt status */
ddef6a0d 157 g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 1);
4958fe5d
MA
158 /* reading clears */
159 g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 0);
160 /* TODO intercept actual interrupt (needs qtest work) */
ddef6a0d 161
4958fe5d 162 /* invalid register access */
ddef6a0d 163 out_reg(s, IVPOSITION, 1);
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164 in_reg(s, DOORBELL);
165
166 /* ring the (non-functional) doorbell */
ddef6a0d
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167 out_reg(s, DOORBELL, 8 << 16);
168
4958fe5d 169 /* write shared memory */
ddef6a0d
MAL
170 for (i = 0; i < G_N_ELEMENTS(data); i++) {
171 data[i] = i;
172 }
173 qtest_memwrite(s->qtest, (uintptr_t)s->mem_base, data, sizeof(data));
174
4958fe5d 175 /* verify write */
ddef6a0d
MAL
176 for (i = 0; i < G_N_ELEMENTS(data); i++) {
177 g_assert_cmpuint(((uint32_t *)tmpshmem)[i], ==, i);
178 }
179
4958fe5d 180 /* read it back and verify read */
ddef6a0d 181 memset(data, 0, sizeof(data));
ddef6a0d
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182 qtest_memread(s->qtest, (uintptr_t)s->mem_base, data, sizeof(data));
183 for (i = 0; i < G_N_ELEMENTS(data); i++) {
184 g_assert_cmpuint(data[i], ==, i);
185 }
186
1760048a 187 cleanup_vm(s);
ddef6a0d
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188}
189
190static void test_ivshmem_pair(void)
191{
192 IVState state1, state2, *s1, *s2;
193 char *data;
194 int i;
195
196 setup_vm(&state1);
197 s1 = &state1;
198 setup_vm(&state2);
199 s2 = &state2;
200
201 data = g_malloc0(TMPSHMSIZE);
202
203 /* host write, guest 1 & 2 read */
204 memset(tmpshmem, 0x42, TMPSHMSIZE);
205 qtest_memread(s1->qtest, (uintptr_t)s1->mem_base, data, TMPSHMSIZE);
206 for (i = 0; i < TMPSHMSIZE; i++) {
207 g_assert_cmpuint(data[i], ==, 0x42);
208 }
209 qtest_memread(s2->qtest, (uintptr_t)s2->mem_base, data, TMPSHMSIZE);
210 for (i = 0; i < TMPSHMSIZE; i++) {
211 g_assert_cmpuint(data[i], ==, 0x42);
212 }
213
214 /* guest 1 write, guest 2 read */
215 memset(data, 0x43, TMPSHMSIZE);
216 qtest_memwrite(s1->qtest, (uintptr_t)s1->mem_base, data, TMPSHMSIZE);
217 memset(data, 0, TMPSHMSIZE);
218 qtest_memread(s2->qtest, (uintptr_t)s2->mem_base, data, TMPSHMSIZE);
219 for (i = 0; i < TMPSHMSIZE; i++) {
220 g_assert_cmpuint(data[i], ==, 0x43);
221 }
222
223 /* guest 2 write, guest 1 read */
224 memset(data, 0x44, TMPSHMSIZE);
225 qtest_memwrite(s2->qtest, (uintptr_t)s2->mem_base, data, TMPSHMSIZE);
226 memset(data, 0, TMPSHMSIZE);
227 qtest_memread(s1->qtest, (uintptr_t)s2->mem_base, data, TMPSHMSIZE);
228 for (i = 0; i < TMPSHMSIZE; i++) {
229 g_assert_cmpuint(data[i], ==, 0x44);
230 }
231
1760048a
MAL
232 cleanup_vm(s1);
233 cleanup_vm(s2);
ddef6a0d
MAL
234 g_free(data);
235}
236
237typedef struct ServerThread {
238 GThread *thread;
239 IvshmemServer *server;
240 int pipe[2]; /* to handle quit */
241} ServerThread;
242
243static void *server_thread(void *data)
244{
245 ServerThread *t = data;
246 IvshmemServer *server = t->server;
247
248 while (true) {
249 fd_set fds;
250 int maxfd, ret;
251
252 FD_ZERO(&fds);
253 FD_SET(t->pipe[0], &fds);
254 maxfd = t->pipe[0] + 1;
255
256 ivshmem_server_get_fds(server, &fds, &maxfd);
257
258 ret = select(maxfd, &fds, NULL, NULL, NULL);
259
260 if (ret < 0) {
261 if (errno == EINTR) {
262 continue;
263 }
264
265 g_critical("select error: %s\n", strerror(errno));
266 break;
267 }
268 if (ret == 0) {
269 continue;
270 }
271
272 if (FD_ISSET(t->pipe[0], &fds)) {
273 break;
274 }
275
276 if (ivshmem_server_handle_fds(server, &fds, maxfd) < 0) {
277 g_critical("ivshmem_server_handle_fds() failed\n");
278 break;
279 }
280 }
281
282 return NULL;
283}
284
00ffc3c1 285static void setup_vm_with_server(IVState *s, int nvectors, bool msi)
ddef6a0d
MAL
286{
287 char *cmd = g_strdup_printf("-chardev socket,id=chr0,path=%s,nowait "
5400c02b
MA
288 "-device ivshmem%s,chardev=chr0,vectors=%d",
289 tmpserver,
290 msi ? "-doorbell" : ",size=1M,msi=off",
291 nvectors);
ddef6a0d 292
00ffc3c1 293 setup_vm_cmd(s, cmd, msi);
ddef6a0d
MAL
294
295 g_free(cmd);
296}
297
00ffc3c1 298static void test_ivshmem_server(bool msi)
ddef6a0d
MAL
299{
300 IVState state1, state2, *s1, *s2;
301 ServerThread thread;
302 IvshmemServer server;
303 int ret, vm1, vm2;
304 int nvectors = 2;
305 guint64 end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND;
306
3625c739 307 ret = ivshmem_server_init(&server, tmpserver, tmpshm, true,
ddef6a0d
MAL
308 TMPSHMSIZE, nvectors,
309 g_test_verbose());
310 g_assert_cmpint(ret, ==, 0);
311
312 ret = ivshmem_server_start(&server);
313 g_assert_cmpint(ret, ==, 0);
314
ddef6a0d
MAL
315 thread.server = &server;
316 ret = pipe(thread.pipe);
317 g_assert_cmpint(ret, ==, 0);
318 thread.thread = g_thread_new("ivshmem-server", server_thread, &thread);
319 g_assert(thread.thread != NULL);
320
3a55fc0f
MA
321 setup_vm_with_server(&state1, nvectors, msi);
322 s1 = &state1;
323 setup_vm_with_server(&state2, nvectors, msi);
324 s2 = &state2;
ddef6a0d
MAL
325
326 /* check got different VM ids */
327 vm1 = in_reg(s1, IVPOSITION);
328 vm2 = in_reg(s2, IVPOSITION);
3a55fc0f
MA
329 g_assert_cmpint(vm1, >=, 0);
330 g_assert_cmpint(vm2, >=, 0);
331 g_assert_cmpint(vm1, !=, vm2);
ddef6a0d 332
41b65e5e 333 /* check number of MSI-X vectors */
ddef6a0d 334 global_qtest = s1->qtest;
00ffc3c1
MAL
335 if (msi) {
336 ret = qpci_msix_table_size(s1->dev);
337 g_assert_cmpuint(ret, ==, nvectors);
338 }
ddef6a0d 339
41b65e5e
MA
340 /* TODO test behavior before MSI-X is enabled */
341
342 /* ping vm2 -> vm1 on vector 0 */
00ffc3c1
MAL
343 if (msi) {
344 ret = qpci_msix_pending(s1->dev, 0);
345 g_assert_cmpuint(ret, ==, 0);
346 } else {
41b65e5e 347 g_assert_cmpuint(in_reg(s1, INTRSTATUS), ==, 0);
00ffc3c1 348 }
ddef6a0d
MAL
349 out_reg(s2, DOORBELL, vm1 << 16);
350 do {
351 g_usleep(10000);
00ffc3c1 352 ret = msi ? qpci_msix_pending(s1->dev, 0) : in_reg(s1, INTRSTATUS);
ddef6a0d
MAL
353 } while (ret == 0 && g_get_monotonic_time() < end_time);
354 g_assert_cmpuint(ret, !=, 0);
355
41b65e5e 356 /* ping vm1 -> vm2 on vector 1 */
ddef6a0d 357 global_qtest = s2->qtest;
00ffc3c1 358 if (msi) {
41b65e5e 359 ret = qpci_msix_pending(s2->dev, 1);
00ffc3c1
MAL
360 g_assert_cmpuint(ret, ==, 0);
361 } else {
41b65e5e 362 g_assert_cmpuint(in_reg(s2, INTRSTATUS), ==, 0);
00ffc3c1 363 }
41b65e5e 364 out_reg(s1, DOORBELL, vm2 << 16 | 1);
ddef6a0d
MAL
365 do {
366 g_usleep(10000);
41b65e5e 367 ret = msi ? qpci_msix_pending(s2->dev, 1) : in_reg(s2, INTRSTATUS);
ddef6a0d
MAL
368 } while (ret == 0 && g_get_monotonic_time() < end_time);
369 g_assert_cmpuint(ret, !=, 0);
370
1760048a
MAL
371 cleanup_vm(s2);
372 cleanup_vm(s1);
ddef6a0d
MAL
373
374 if (qemu_write_full(thread.pipe[1], "q", 1) != 1) {
375 g_error("qemu_write_full: %s", g_strerror(errno));
376 }
377
378 g_thread_join(thread.thread);
379
380 ivshmem_server_close(&server);
381 close(thread.pipe[1]);
382 close(thread.pipe[0]);
383}
384
00ffc3c1
MAL
385static void test_ivshmem_server_msi(void)
386{
387 test_ivshmem_server(true);
388}
389
390static void test_ivshmem_server_irq(void)
391{
392 test_ivshmem_server(false);
393}
394
ddef6a0d
MAL
395#define PCI_SLOT_HP 0x06
396
397static void test_ivshmem_hotplug(void)
398{
399 gchar *opts;
400
401 qtest_start("");
402
403 opts = g_strdup_printf("'shm': '%s', 'size': '1M'", tmpshm);
404
405 qpci_plug_device_test("ivshmem", "iv1", PCI_SLOT_HP, opts);
406 qpci_unplug_acpi_device_test("iv1", PCI_SLOT_HP);
407
408 qtest_end();
409 g_free(opts);
410}
411
d9453c93
MAL
412static void test_ivshmem_memdev(void)
413{
414 IVState state;
415
416 /* just for the sake of checking memory-backend property */
417 setup_vm_cmd(&state, "-object memory-backend-ram,size=1M,id=mb1"
5400c02b 418 " -device ivshmem-plain,memdev=mb1", false);
d9453c93 419
1760048a 420 cleanup_vm(&state);
d9453c93
MAL
421}
422
ddef6a0d
MAL
423static void cleanup(void)
424{
425 if (tmpshmem) {
426 munmap(tmpshmem, TMPSHMSIZE);
427 tmpshmem = NULL;
428 }
429
430 if (tmpshm) {
431 shm_unlink(tmpshm);
432 g_free(tmpshm);
433 tmpshm = NULL;
434 }
435
436 if (tmpserver) {
437 g_unlink(tmpserver);
438 g_free(tmpserver);
439 tmpserver = NULL;
440 }
441
442 if (tmpdir) {
443 g_rmdir(tmpdir);
444 tmpdir = NULL;
445 }
446}
447
448static void abrt_handler(void *data)
449{
450 cleanup();
451}
452
453static gchar *mktempshm(int size, int *fd)
454{
455 while (true) {
456 gchar *name;
457
458 name = g_strdup_printf("/qtest-%u-%u", getpid(), g_random_int());
459 *fd = shm_open(name, O_CREAT|O_RDWR|O_EXCL,
460 S_IRWXU|S_IRWXG|S_IRWXO);
461 if (*fd > 0) {
462 g_assert(ftruncate(*fd, size) == 0);
463 return name;
464 }
465
466 g_free(name);
467
468 if (errno != EEXIST) {
469 perror("shm_open");
470 return NULL;
471 }
472 }
bbfc2efe
AF
473}
474
475int main(int argc, char **argv)
476{
bbfc2efe 477 int ret, fd;
ddef6a0d
MAL
478 gchar dir[] = "/tmp/ivshmem-test.XXXXXX";
479
480#if !GLIB_CHECK_VERSION(2, 31, 0)
481 if (!g_thread_supported()) {
482 g_thread_init(NULL);
483 }
484#endif
bbfc2efe
AF
485
486 g_test_init(&argc, &argv, NULL);
bbfc2efe 487
ddef6a0d
MAL
488 qtest_add_abrt_handler(abrt_handler, NULL);
489 /* shm */
490 tmpshm = mktempshm(TMPSHMSIZE, &fd);
491 if (!tmpshm) {
492 return 0;
493 }
494 tmpshmem = mmap(0, TMPSHMSIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
495 g_assert(tmpshmem != MAP_FAILED);
496 /* server */
497 if (mkdtemp(dir) == NULL) {
498 g_error("mkdtemp: %s", g_strerror(errno));
499 }
500 tmpdir = dir;
501 tmpserver = g_strconcat(tmpdir, "/server", NULL);
bbfc2efe 502
ddef6a0d 503 qtest_add_func("/ivshmem/single", test_ivshmem_single);
ddef6a0d 504 qtest_add_func("/ivshmem/hotplug", test_ivshmem_hotplug);
d9453c93 505 qtest_add_func("/ivshmem/memdev", test_ivshmem_memdev);
2048a2a4
MAL
506 if (g_test_slow()) {
507 qtest_add_func("/ivshmem/pair", test_ivshmem_pair);
00ffc3c1
MAL
508 qtest_add_func("/ivshmem/server-msi", test_ivshmem_server_msi);
509 qtest_add_func("/ivshmem/server-irq", test_ivshmem_server_irq);
2048a2a4 510 }
bbfc2efe
AF
511
512 ret = g_test_run();
513
ddef6a0d 514 cleanup();
bbfc2efe
AF
515
516 return ret;
517}
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