[qemu.git] / hw / lance.c

/*
 * QEMU Lance emulation
 * 
 * Copyright (c) 2003-2005 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

/* debug LANCE card */
//#define DEBUG_LANCE

#ifdef DEBUG_LANCE
#define DPRINTF(fmt, args...) \
do { printf("LANCE: " fmt , ##args); } while (0)
#else
#define DPRINTF(fmt, args...)
#endif

#ifndef LANCE_LOG_TX_BUFFERS
#define LANCE_LOG_TX_BUFFERS 4
#define LANCE_LOG_RX_BUFFERS 4
#endif

#define LE_CSR0 0
#define LE_CSR1 1
#define LE_CSR2 2
#define LE_CSR3 3
#define LE_NREGS (LE_CSR3 + 1)
#define LE_MAXREG LE_CSR3

#define LE_RDP  0
#define LE_RAP  1

#define LE_MO_PROM      0x8000  /* Enable promiscuous mode */

#define	LE_C0_ERR	0x8000	/* Error: set if BAB, SQE, MISS or ME is set */
#define	LE_C0_BABL	0x4000	/* BAB:  Babble: tx timeout. */
#define	LE_C0_CERR	0x2000	/* SQE:  Signal quality error */
#define	LE_C0_MISS	0x1000	/* MISS: Missed a packet */
#define	LE_C0_MERR	0x0800	/* ME:   Memory error */
#define	LE_C0_RINT	0x0400	/* Received interrupt */
#define	LE_C0_TINT	0x0200	/* Transmitter Interrupt */
#define	LE_C0_IDON	0x0100	/* IFIN: Init finished. */
#define	LE_C0_INTR	0x0080	/* Interrupt or error */
#define	LE_C0_INEA	0x0040	/* Interrupt enable */
#define	LE_C0_RXON	0x0020	/* Receiver on */
#define	LE_C0_TXON	0x0010	/* Transmitter on */
#define	LE_C0_TDMD	0x0008	/* Transmitter demand */
#define	LE_C0_STOP	0x0004	/* Stop the card */
#define	LE_C0_STRT	0x0002	/* Start the card */
#define	LE_C0_INIT	0x0001	/* Init the card */

#define	LE_C3_BSWP	0x4     /* SWAP */
#define	LE_C3_ACON	0x2	/* ALE Control */
#define	LE_C3_BCON	0x1	/* Byte control */

/* Receive message descriptor 1 */
#define LE_R1_OWN       0x80    /* Who owns the entry */
#define LE_R1_ERR       0x40    /* Error: if FRA, OFL, CRC or BUF is set */
#define LE_R1_FRA       0x20    /* FRA: Frame error */
#define LE_R1_OFL       0x10    /* OFL: Frame overflow */
#define LE_R1_CRC       0x08    /* CRC error */
#define LE_R1_BUF       0x04    /* BUF: Buffer error */
#define LE_R1_SOP       0x02    /* Start of packet */
#define LE_R1_EOP       0x01    /* End of packet */
#define LE_R1_POK       0x03    /* Packet is complete: SOP + EOP */

#define LE_T1_OWN       0x80    /* Lance owns the packet */
#define LE_T1_ERR       0x40    /* Error summary */
#define LE_T1_EMORE     0x10    /* Error: more than one retry needed */
#define LE_T1_EONE      0x08    /* Error: one retry needed */
#define LE_T1_EDEF      0x04    /* Error: deferred */
#define LE_T1_SOP       0x02    /* Start of packet */
#define LE_T1_EOP       0x01    /* End of packet */
#define LE_T1_POK	0x03	/* Packet is complete: SOP + EOP */

#define LE_T3_BUF       0x8000  /* Buffer error */
#define LE_T3_UFL       0x4000  /* Error underflow */
#define LE_T3_LCOL      0x1000  /* Error late collision */
#define LE_T3_CLOS      0x0800  /* Error carrier loss */
#define LE_T3_RTY       0x0400  /* Error retry */
#define LE_T3_TDR       0x03ff  /* Time Domain Reflectometry counter */

#define TX_RING_SIZE			(1 << (LANCE_LOG_TX_BUFFERS))
#define TX_RING_MOD_MASK		(TX_RING_SIZE - 1)
#define TX_RING_LEN_BITS		((LANCE_LOG_TX_BUFFERS) << 29)

#define RX_RING_SIZE			(1 << (LANCE_LOG_RX_BUFFERS))
#define RX_RING_MOD_MASK		(RX_RING_SIZE - 1)
#define RX_RING_LEN_BITS		((LANCE_LOG_RX_BUFFERS) << 29)

#define PKT_BUF_SZ		1544
#define RX_BUFF_SIZE            PKT_BUF_SZ
#define TX_BUFF_SIZE            PKT_BUF_SZ

struct lance_rx_desc {
	unsigned short rmd0;        /* low address of packet */
	unsigned char  rmd1_bits;   /* descriptor bits */
	unsigned char  rmd1_hadr;   /* high address of packet */
	short    length;    	    /* This length is 2s complement (negative)!
				     * Buffer length
				     */
	unsigned short mblength;    /* This is the actual number of bytes received */
};

struct lance_tx_desc {
	unsigned short tmd0;        /* low address of packet */
	unsigned char  tmd1_bits;   /* descriptor bits */
	unsigned char  tmd1_hadr;   /* high address of packet */
	short length;          	    /* Length is 2s complement (negative)! */
	unsigned short misc;
};

/* The LANCE initialization block, described in databook. */
/* On the Sparc, this block should be on a DMA region     */
struct lance_init_block {
	unsigned short mode;		/* Pre-set mode (reg. 15) */
	unsigned char phys_addr[6];     /* Physical ethernet address */
	unsigned filter[2];		/* Multicast filter. */

	/* Receive and transmit ring base, along with extra bits. */
	unsigned short rx_ptr;		/* receive descriptor addr */
	unsigned short rx_len;		/* receive len and high addr */
	unsigned short tx_ptr;		/* transmit descriptor addr */
	unsigned short tx_len;		/* transmit len and high addr */
    
	/* The Tx and Rx ring entries must aligned on 8-byte boundaries. */
	struct lance_rx_desc brx_ring[RX_RING_SIZE];
	struct lance_tx_desc btx_ring[TX_RING_SIZE];
    
	char   tx_buf [TX_RING_SIZE][TX_BUFF_SIZE];
	char   pad[2];			/* align rx_buf for copy_and_sum(). */
	char   rx_buf [RX_RING_SIZE][RX_BUFF_SIZE];
};

#define LEDMA_REGS 4
#define LEDMA_MAXADDR (LEDMA_REGS * 4 - 1)

typedef struct LANCEState {
    VLANClientState *vc;
    uint8_t macaddr[6]; /* init mac address */
    uint32_t leptr;
    uint16_t addr;
    uint16_t regs[LE_NREGS];
    uint8_t phys[6]; /* mac address */
    int irq;
    unsigned int rxptr, txptr;
    uint32_t ledmaregs[LEDMA_REGS];
} LANCEState;

static void lance_send(void *opaque);

static void lance_reset(void *opaque)
{
    LANCEState *s = opaque;
    memcpy(s->phys, s->macaddr, 6);
    s->rxptr = 0;
    s->txptr = 0;
    memset(s->regs, 0, LE_NREGS * 2);
    s->regs[LE_CSR0] = LE_C0_STOP;
    memset(s->ledmaregs, 0, LEDMA_REGS * 4);
}

static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)
{
    LANCEState *s = opaque;
    uint32_t saddr;

    saddr = addr & LE_MAXREG;
    switch (saddr >> 1) {
    case LE_RDP:
	DPRINTF("read dreg[%d] = %4.4x\n", s->addr, s->regs[s->addr]);
	return s->regs[s->addr];
    case LE_RAP:
	DPRINTF("read areg = %4.4x\n", s->addr);
	return s->addr;
    default:
	DPRINTF("read unknown(%d)\n", saddr>>1);
	break;
    }
    return 0;
}

static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    LANCEState *s = opaque;
    uint32_t saddr;
    uint16_t reg;

    saddr = addr & LE_MAXREG;
    switch (saddr >> 1) {
    case LE_RDP:
	DPRINTF("write dreg[%d] = %4.4x\n", s->addr, val);
	switch(s->addr) {
	case LE_CSR0:
	    if (val & LE_C0_STOP) {
		s->regs[LE_CSR0] = LE_C0_STOP;
		break;
	    }

	    reg = s->regs[LE_CSR0];

	    // 1 = clear for some bits
	    reg &= ~(val & 0x7f00);

	    // generated bits
	    reg &= ~(LE_C0_ERR | LE_C0_INTR);
	    if (reg & 0x7100)
		reg |= LE_C0_ERR;
	    if (reg & 0x7f00)
		reg |= LE_C0_INTR;

	    // direct bit
	    reg &= ~LE_C0_INEA;
	    reg |= val & LE_C0_INEA;

	    // exclusive bits
	    if (val & LE_C0_INIT) {
		reg |= LE_C0_IDON | LE_C0_INIT;
		reg &= ~LE_C0_STOP;
	    }
	    else if (val & LE_C0_STRT) {
		reg |= LE_C0_STRT | LE_C0_RXON | LE_C0_TXON;
		reg &= ~LE_C0_STOP;
	    }

	    s->regs[LE_CSR0] = reg;
	    break;
	case LE_CSR1:
	    s->leptr = (s->leptr & 0xffff0000) | (val & 0xffff);
	    s->regs[s->addr] = val;
	    break;
	case LE_CSR2:
	    s->leptr = (s->leptr & 0xffff) | ((val & 0xffff) << 16);
	    s->regs[s->addr] = val;
	    break;
	case LE_CSR3:
	    s->regs[s->addr] = val;
	    break;
	}
	break;
    case LE_RAP:
	DPRINTF("write areg = %4.4x\n", val);
	if (val < LE_NREGS)
	    s->addr = val;
	break;
    default:
	DPRINTF("write unknown(%d) = %4.4x\n", saddr>>1, val);
	break;
    }
    lance_send(s);
}

static CPUReadMemoryFunc *lance_mem_read[3] = {
    lance_mem_readw,
    lance_mem_readw,
    lance_mem_readw,
};

static CPUWriteMemoryFunc *lance_mem_write[3] = {
    lance_mem_writew,
    lance_mem_writew,
    lance_mem_writew,
};


#define MIN_BUF_SIZE 60

static int lance_can_receive(void *opaque)
{
    return 1;
}

static void lance_receive(void *opaque, const uint8_t *buf, int size)
{
    LANCEState *s = opaque;
    uint32_t dmaptr = s->leptr + s->ledmaregs[3];
    struct lance_init_block *ib;
    unsigned int i, old_rxptr;
    uint16_t temp16;
    uint8_t temp8;

    DPRINTF("receive size %d\n", size);
    if ((s->regs[LE_CSR0] & LE_C0_STOP) == LE_C0_STOP)
	return;

    ib = (void *) iommu_translate(dmaptr);

    old_rxptr = s->rxptr;
    for (i = s->rxptr; i != ((old_rxptr - 1) & RX_RING_MOD_MASK); i = (i + 1) & RX_RING_MOD_MASK) {
	cpu_physical_memory_read((uint32_t)&ib->brx_ring[i].rmd1_bits, (void *) &temp8, 1);
	if (temp8 == (LE_R1_OWN)) {
	    s->rxptr = (s->rxptr + 1) & RX_RING_MOD_MASK;
	    temp16 = size + 4;
	    bswap16s(&temp16);
	    cpu_physical_memory_write((uint32_t)&ib->brx_ring[i].mblength, (void *) &temp16, 2);
	    cpu_physical_memory_write((uint32_t)&ib->rx_buf[i], buf, size);
	    temp8 = LE_R1_POK;
	    cpu_physical_memory_write((uint32_t)&ib->brx_ring[i].rmd1_bits, (void *) &temp8, 1);
	    s->regs[LE_CSR0] |= LE_C0_RINT | LE_C0_INTR;
	    if (s->regs[LE_CSR0] & LE_C0_INEA)
		pic_set_irq(s->irq, 1);
	    DPRINTF("got packet, len %d\n", size);
	    return;
	}
    }
}

static void lance_send(void *opaque)
{
    LANCEState *s = opaque;
    uint32_t dmaptr = s->leptr + s->ledmaregs[3];
    struct lance_init_block *ib;
    unsigned int i, old_txptr;
    uint16_t temp16;
    uint8_t temp8;
    char pkt_buf[PKT_BUF_SZ];

    DPRINTF("sending packet? (csr0 %4.4x)\n", s->regs[LE_CSR0]);
    if ((s->regs[LE_CSR0] & LE_C0_STOP) == LE_C0_STOP)
	return;

    ib = (void *) iommu_translate(dmaptr);

    DPRINTF("sending packet? (dmaptr %8.8x) (ib %p) (btx_ring %p)\n", dmaptr, ib, &ib->btx_ring);
    old_txptr = s->txptr;
    for (i = s->txptr; i != ((old_txptr - 1) & TX_RING_MOD_MASK); i = (i + 1) & TX_RING_MOD_MASK) {
	cpu_physical_memory_read((uint32_t)&ib->btx_ring[i].tmd1_bits, (void *) &temp8, 1);
	if (temp8 == (LE_T1_POK|LE_T1_OWN)) {
	    cpu_physical_memory_read((uint32_t)&ib->btx_ring[i].length, (void *) &temp16, 2);
	    bswap16s(&temp16);
	    temp16 = (~temp16) + 1;
	    cpu_physical_memory_read((uint32_t)&ib->tx_buf[i], pkt_buf, temp16);
	    DPRINTF("sending packet, len %d\n", temp16);
	    qemu_send_packet(s->vc, pkt_buf, temp16);
	    temp8 = LE_T1_POK;
	    cpu_physical_memory_write((uint32_t)&ib->btx_ring[i].tmd1_bits, (void *) &temp8, 1);
	    s->txptr = (s->txptr + 1) & TX_RING_MOD_MASK;
	    s->regs[LE_CSR0] |= LE_C0_TINT | LE_C0_INTR;
	}
    }
    if ((s->regs[LE_CSR0] & LE_C0_INTR) && (s->regs[LE_CSR0] & LE_C0_INEA))
	pic_set_irq(s->irq, 1);
}

static uint32_t ledma_mem_readl(void *opaque, target_phys_addr_t addr)
{
    LANCEState *s = opaque;
    uint32_t saddr;

    saddr = (addr & LEDMA_MAXADDR) >> 2;
    return s->ledmaregs[saddr];
}

static void ledma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    LANCEState *s = opaque;
    uint32_t saddr;

    saddr = (addr & LEDMA_MAXADDR) >> 2;
    s->ledmaregs[saddr] = val;
}

static CPUReadMemoryFunc *ledma_mem_read[3] = {
    ledma_mem_readl,
    ledma_mem_readl,
    ledma_mem_readl,
};

static CPUWriteMemoryFunc *ledma_mem_write[3] = {
    ledma_mem_writel,
    ledma_mem_writel,
    ledma_mem_writel,
};

static void lance_save(QEMUFile *f, void *opaque)
{
    LANCEState *s = opaque;
    int i;
    
    qemu_put_be32s(f, &s->leptr);
    qemu_put_be16s(f, &s->addr);
    for (i = 0; i < LE_NREGS; i ++)
	qemu_put_be16s(f, &s->regs[i]);
    qemu_put_buffer(f, s->phys, 6);
    qemu_put_be32s(f, &s->irq);
    for (i = 0; i < LEDMA_REGS; i ++)
	qemu_put_be32s(f, &s->ledmaregs[i]);
}

static int lance_load(QEMUFile *f, void *opaque, int version_id)
{
    LANCEState *s = opaque;
    int i;
    
    if (version_id != 1)
        return -EINVAL;

    qemu_get_be32s(f, &s->leptr);
    qemu_get_be16s(f, &s->addr);
    for (i = 0; i < LE_NREGS; i ++)
	qemu_get_be16s(f, &s->regs[i]);
    qemu_get_buffer(f, s->phys, 6);
    qemu_get_be32s(f, &s->irq);
    for (i = 0; i < LEDMA_REGS; i ++)
	qemu_get_be32s(f, &s->ledmaregs[i]);
    return 0;
}

void lance_init(NICInfo *nd, int irq, uint32_t leaddr, uint32_t ledaddr)
{
    LANCEState *s;
    int lance_io_memory, ledma_io_memory;

    s = qemu_mallocz(sizeof(LANCEState));
    if (!s)
        return;

    s->irq = irq;

    lance_io_memory = cpu_register_io_memory(0, lance_mem_read, lance_mem_write, s);
    cpu_register_physical_memory(leaddr, 4, lance_io_memory);

    ledma_io_memory = cpu_register_io_memory(0, ledma_mem_read, ledma_mem_write, s);
    cpu_register_physical_memory(ledaddr, 16, ledma_io_memory);

    memcpy(s->macaddr, nd->macaddr, 6);

    lance_reset(s);

    s->vc = qemu_new_vlan_client(nd->vlan, lance_receive, lance_can_receive, s);

    snprintf(s->vc->info_str, sizeof(s->vc->info_str),
             "lance macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
             s->macaddr[0],
             s->macaddr[1],
             s->macaddr[2],
             s->macaddr[3],
             s->macaddr[4],
             s->macaddr[5]);

    register_savevm("lance", leaddr, 1, lance_save, lance_load, s);
    qemu_register_reset(lance_reset, s);
}
Commit	Line	Data
420557e8 FB	1	/*
	2	* QEMU Lance emulation
	3	*
66321a11	4	* Copyright (c) 2003-2005 Fabrice Bellard
420557e8 FB	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "vl.h"
	25
	26	/* debug LANCE card */
8d5f07fa	27	//#define DEBUG_LANCE
420557e8	28
66321a11 FB	29	#ifdef DEBUG_LANCE
	30	#define DPRINTF(fmt, args...) \
	31	do { printf("LANCE: " fmt , ##args); } while (0)
	32	#else
	33	#define DPRINTF(fmt, args...)
	34	#endif
	35
420557e8 FB	36	#ifndef LANCE_LOG_TX_BUFFERS
	37	#define LANCE_LOG_TX_BUFFERS 4
	38	#define LANCE_LOG_RX_BUFFERS 4
	39	#endif
	40
420557e8 FB	41	#define LE_CSR0 0
	42	#define LE_CSR1 1
	43	#define LE_CSR2 2
	44	#define LE_CSR3 3
66321a11 FB	45	#define LE_NREGS (LE_CSR3 + 1)
66321a11 FB	46	#define LE_MAXREG LE_CSR3
420557e8 FB	47
	48	#define LE_RDP 0
	49	#define LE_RAP 1
	50
	51	#define LE_MO_PROM 0x8000 /* Enable promiscuous mode */
	52
	53	#define LE_C0_ERR 0x8000 /* Error: set if BAB, SQE, MISS or ME is set */
	54	#define LE_C0_BABL 0x4000 /* BAB: Babble: tx timeout. */
	55	#define LE_C0_CERR 0x2000 /* SQE: Signal quality error */
	56	#define LE_C0_MISS 0x1000 /* MISS: Missed a packet */
	57	#define LE_C0_MERR 0x0800 /* ME: Memory error */
	58	#define LE_C0_RINT 0x0400 /* Received interrupt */
	59	#define LE_C0_TINT 0x0200 /* Transmitter Interrupt */
	60	#define LE_C0_IDON 0x0100 /* IFIN: Init finished. */
	61	#define LE_C0_INTR 0x0080 /* Interrupt or error */
	62	#define LE_C0_INEA 0x0040 /* Interrupt enable */
	63	#define LE_C0_RXON 0x0020 /* Receiver on */
	64	#define LE_C0_TXON 0x0010 /* Transmitter on */
	65	#define LE_C0_TDMD 0x0008 /* Transmitter demand */
	66	#define LE_C0_STOP 0x0004 /* Stop the card */
	67	#define LE_C0_STRT 0x0002 /* Start the card */
	68	#define LE_C0_INIT 0x0001 /* Init the card */
	69
	70	#define LE_C3_BSWP 0x4 /* SWAP */
	71	#define LE_C3_ACON 0x2 /* ALE Control */
	72	#define LE_C3_BCON 0x1 /* Byte control */
	73
	74	/* Receive message descriptor 1 */
	75	#define LE_R1_OWN 0x80 /* Who owns the entry */
	76	#define LE_R1_ERR 0x40 /* Error: if FRA, OFL, CRC or BUF is set */
	77	#define LE_R1_FRA 0x20 /* FRA: Frame error */
	78	#define LE_R1_OFL 0x10 /* OFL: Frame overflow */
	79	#define LE_R1_CRC 0x08 /* CRC error */
	80	#define LE_R1_BUF 0x04 /* BUF: Buffer error */
	81	#define LE_R1_SOP 0x02 /* Start of packet */
	82	#define LE_R1_EOP 0x01 /* End of packet */
	83	#define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */
	84
	85	#define LE_T1_OWN 0x80 /* Lance owns the packet */
	86	#define LE_T1_ERR 0x40 /* Error summary */
	87	#define LE_T1_EMORE 0x10 /* Error: more than one retry needed */
	88	#define LE_T1_EONE 0x08 /* Error: one retry needed */
	89	#define LE_T1_EDEF 0x04 /* Error: deferred */
	90	#define LE_T1_SOP 0x02 /* Start of packet */
	91	#define LE_T1_EOP 0x01 /* End of packet */
	92	#define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */
	93
	94	#define LE_T3_BUF 0x8000 /* Buffer error */
	95	#define LE_T3_UFL 0x4000 /* Error underflow */
	96	#define LE_T3_LCOL 0x1000 /* Error late collision */
	97	#define LE_T3_CLOS 0x0800 /* Error carrier loss */
	98	#define LE_T3_RTY 0x0400 /* Error retry */
	99	#define LE_T3_TDR 0x03ff /* Time Domain Reflectometry counter */
	100
	101	#define TX_RING_SIZE (1 << (LANCE_LOG_TX_BUFFERS))
	102	#define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
	103	#define TX_RING_LEN_BITS ((LANCE_LOG_TX_BUFFERS) << 29)
	104
	105	#define RX_RING_SIZE (1 << (LANCE_LOG_RX_BUFFERS))
	106	#define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
	107	#define RX_RING_LEN_BITS ((LANCE_LOG_RX_BUFFERS) << 29)
	108
	109	#define PKT_BUF_SZ 1544
	110	#define RX_BUFF_SIZE PKT_BUF_SZ
111	#define TX_BUFF_SIZE PKT_BUF_SZ
112
113	struct lance_rx_desc {
114	unsigned short rmd0; /* low address of packet */
115	unsigned char rmd1_bits; /* descriptor bits */
116	unsigned char rmd1_hadr; /* high address of packet */
117	short length; /* This length is 2s complement (negative)!
118	* Buffer length
119	*/
120	unsigned short mblength; /* This is the actual number of bytes received */
121	};
122
123	struct lance_tx_desc {
124	unsigned short tmd0; /* low address of packet */
125	unsigned char tmd1_bits; /* descriptor bits */
126	unsigned char tmd1_hadr; /* high address of packet */
127	short length; /* Length is 2s complement (negative)! */
128	unsigned short misc;
129	};
130
131	/* The LANCE initialization block, described in databook. */
132	/* On the Sparc, this block should be on a DMA region */
133	struct lance_init_block {
134	unsigned short mode; /* Pre-set mode (reg. 15) */
135	unsigned char phys_addr[6]; /* Physical ethernet address */
136	unsigned filter[2]; /* Multicast filter. */
137
138	/* Receive and transmit ring base, along with extra bits. */
139	unsigned short rx_ptr; /* receive descriptor addr */
140	unsigned short rx_len; /* receive len and high addr */
141	unsigned short tx_ptr; /* transmit descriptor addr */
142	unsigned short tx_len; /* transmit len and high addr */
143
144	/* The Tx and Rx ring entries must aligned on 8-byte boundaries. */
145	struct lance_rx_desc brx_ring[RX_RING_SIZE];
146	struct lance_tx_desc btx_ring[TX_RING_SIZE];
147
148	char tx_buf [TX_RING_SIZE][TX_BUFF_SIZE];
149	char pad[2]; /* align rx_buf for copy_and_sum(). */
150	char rx_buf [RX_RING_SIZE][RX_BUFF_SIZE];
151	};
152
153	#define LEDMA_REGS 4
e80cfcfc	154	#define LEDMA_MAXADDR (LEDMA_REGS * 4 - 1)
420557e8	155
420557e8	156	typedef struct LANCEState {
7c9d8e07 FB	157	VLANClientState *vc;
7c9d8e07 FB	158	uint8_t macaddr[6]; /* init mac address */
420557e8 FB	159	uint32_t leptr;
420557e8 FB	160	uint16_t addr;
66321a11	161	uint16_t regs[LE_NREGS];
420557e8 FB	162	uint8_t phys[6]; /* mac address */
420557e8 FB	163	int irq;
e80cfcfc FB	164	unsigned int rxptr, txptr;
e80cfcfc FB	165	uint32_t ledmaregs[LEDMA_REGS];
420557e8 FB	166	} LANCEState;
420557e8 FB	167
420557e8 FB	168	static void lance_send(void *opaque);
420557e8 FB	169
e80cfcfc	170	static void lance_reset(void *opaque)
420557e8	171	{
e80cfcfc	172	LANCEState *s = opaque;
7c9d8e07	173	memcpy(s->phys, s->macaddr, 6);
e80cfcfc FB	174	s->rxptr = 0;
e80cfcfc FB	175	s->txptr = 0;
66321a11	176	memset(s->regs, 0, LE_NREGS * 2);
420557e8	177	s->regs[LE_CSR0] = LE_C0_STOP;
e80cfcfc	178	memset(s->ledmaregs, 0, LEDMA_REGS * 4);
420557e8 FB	179	}
	180
	181	static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)
	182	{
	183	LANCEState *s = opaque;
	184	uint32_t saddr;
	185
e80cfcfc	186	saddr = addr & LE_MAXREG;
420557e8 FB	187	switch (saddr >> 1) {
420557e8 FB	188	case LE_RDP:
66321a11	189	DPRINTF("read dreg[%d] = %4.4x\n", s->addr, s->regs[s->addr]);
420557e8 FB	190	return s->regs[s->addr];
420557e8 FB	191	case LE_RAP:
66321a11	192	DPRINTF("read areg = %4.4x\n", s->addr);
420557e8 FB	193	return s->addr;
420557e8 FB	194	default:
66321a11	195	DPRINTF("read unknown(%d)\n", saddr>>1);
420557e8 FB	196	break;
	197	}
	198	return 0;
	199	}
	200
	201	static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
	202	{
	203	LANCEState *s = opaque;
	204	uint32_t saddr;
8d5f07fa	205	uint16_t reg;
420557e8	206
e80cfcfc	207	saddr = addr & LE_MAXREG;
420557e8 FB	208	switch (saddr >> 1) {
420557e8 FB	209	case LE_RDP:
66321a11	210	DPRINTF("write dreg[%d] = %4.4x\n", s->addr, val);
420557e8 FB	211	switch(s->addr) {
	212	case LE_CSR0:
	213	if (val & LE_C0_STOP) {
	214	s->regs[LE_CSR0] = LE_C0_STOP;
	215	break;
	216	}
	217
	218	reg = s->regs[LE_CSR0];
	219
	220	// 1 = clear for some bits
	221	reg &= ~(val & 0x7f00);
	222
	223	// generated bits
	224	reg &= ~(LE_C0_ERR \| LE_C0_INTR);
	225	if (reg & 0x7100)
	226	reg \|= LE_C0_ERR;
	227	if (reg & 0x7f00)
	228	reg \|= LE_C0_INTR;
	229
	230	// direct bit
	231	reg &= ~LE_C0_INEA;
	232	reg \|= val & LE_C0_INEA;
	233
	234	// exclusive bits
	235	if (val & LE_C0_INIT) {
	236	reg \|= LE_C0_IDON \| LE_C0_INIT;
	237	reg &= ~LE_C0_STOP;
	238	}
	239	else if (val & LE_C0_STRT) {
	240	reg \|= LE_C0_STRT \| LE_C0_RXON \| LE_C0_TXON;
	241	reg &= ~LE_C0_STOP;
	242	}
	243
	244	s->regs[LE_CSR0] = reg;
420557e8 FB	245	break;
	246	case LE_CSR1:
	247	s->leptr = (s->leptr & 0xffff0000) \| (val & 0xffff);
	248	s->regs[s->addr] = val;
	249	break;
	250	case LE_CSR2:
	251	s->leptr = (s->leptr & 0xffff) \| ((val & 0xffff) << 16);
	252	s->regs[s->addr] = val;
	253	break;
	254	case LE_CSR3:
	255	s->regs[s->addr] = val;
	256	break;
	257	}
	258	break;
	259	case LE_RAP:
66321a11 FB	260	DPRINTF("write areg = %4.4x\n", val);
66321a11 FB	261	if (val < LE_NREGS)
420557e8 FB	262	s->addr = val;
	263	break;
	264	default:
66321a11	265	DPRINTF("write unknown(%d) = %4.4x\n", saddr>>1, val);
420557e8 FB	266	break;
	267	}
	268	lance_send(s);
	269	}
	270
	271	static CPUReadMemoryFunc *lance_mem_read[3] = {
	272	lance_mem_readw,
	273	lance_mem_readw,
	274	lance_mem_readw,
	275	};
	276
	277	static CPUWriteMemoryFunc *lance_mem_write[3] = {
	278	lance_mem_writew,
	279	lance_mem_writew,
	280	lance_mem_writew,
	281	};
	282
	283
420557e8 FB	284	#define MIN_BUF_SIZE 60
420557e8 FB	285
07435f74	286	static int lance_can_receive(void *opaque)
d861b05e PB	287	{
	288	return 1;
	289	}
	290
420557e8 FB	291	static void lance_receive(void opaque, const uint8_t buf, int size)
	292	{
	293	LANCEState *s = opaque;
e80cfcfc	294	uint32_t dmaptr = s->leptr + s->ledmaregs[3];
420557e8	295	struct lance_init_block *ib;
66321a11 FB	296	unsigned int i, old_rxptr;
	297	uint16_t temp16;
	298	uint8_t temp8;
420557e8	299
66321a11	300	DPRINTF("receive size %d\n", size);
420557e8 FB	301	if ((s->regs[LE_CSR0] & LE_C0_STOP) == LE_C0_STOP)
	302	return;
	303
	304	ib = (void *) iommu_translate(dmaptr);
	305
e80cfcfc FB	306	old_rxptr = s->rxptr;
e80cfcfc FB	307	for (i = s->rxptr; i != ((old_rxptr - 1) & RX_RING_MOD_MASK); i = (i + 1) & RX_RING_MOD_MASK) {
66321a11 FB	308	cpu_physical_memory_read((uint32_t)&ib->brx_ring[i].rmd1_bits, (void *) &temp8, 1);
66321a11 FB	309	if (temp8 == (LE_R1_OWN)) {
e80cfcfc	310	s->rxptr = (s->rxptr + 1) & RX_RING_MOD_MASK;
66321a11 FB	311	temp16 = size + 4;
	312	bswap16s(&temp16);
	313	cpu_physical_memory_write((uint32_t)&ib->brx_ring[i].mblength, (void *) &temp16, 2);
e80cfcfc	314	cpu_physical_memory_write((uint32_t)&ib->rx_buf[i], buf, size);
66321a11 FB	315	temp8 = LE_R1_POK;
66321a11 FB	316	cpu_physical_memory_write((uint32_t)&ib->brx_ring[i].rmd1_bits, (void *) &temp8, 1);
420557e8	317	s->regs[LE_CSR0] \|= LE_C0_RINT \| LE_C0_INTR;
66321a11	318	if (s->regs[LE_CSR0] & LE_C0_INEA)
420557e8	319	pic_set_irq(s->irq, 1);
66321a11	320	DPRINTF("got packet, len %d\n", size);
420557e8 FB	321	return;
	322	}
	323	}
	324	}
	325
	326	static void lance_send(void *opaque)
	327	{
	328	LANCEState *s = opaque;
e80cfcfc	329	uint32_t dmaptr = s->leptr + s->ledmaregs[3];
420557e8	330	struct lance_init_block *ib;
66321a11 FB	331	unsigned int i, old_txptr;
	332	uint16_t temp16;
	333	uint8_t temp8;
420557e8 FB	334	char pkt_buf[PKT_BUF_SZ];
420557e8 FB	335
66321a11	336	DPRINTF("sending packet? (csr0 %4.4x)\n", s->regs[LE_CSR0]);
420557e8 FB	337	if ((s->regs[LE_CSR0] & LE_C0_STOP) == LE_C0_STOP)
	338	return;
	339
	340	ib = (void *) iommu_translate(dmaptr);
	341
66321a11	342	DPRINTF("sending packet? (dmaptr %8.8x) (ib %p) (btx_ring %p)\n", dmaptr, ib, &ib->btx_ring);
e80cfcfc FB	343	old_txptr = s->txptr;
e80cfcfc FB	344	for (i = s->txptr; i != ((old_txptr - 1) & TX_RING_MOD_MASK); i = (i + 1) & TX_RING_MOD_MASK) {
66321a11 FB	345	cpu_physical_memory_read((uint32_t)&ib->btx_ring[i].tmd1_bits, (void *) &temp8, 1);
	346	if (temp8 == (LE_T1_POK\|LE_T1_OWN)) {
	347	cpu_physical_memory_read((uint32_t)&ib->btx_ring[i].length, (void *) &temp16, 2);
	348	bswap16s(&temp16);
	349	temp16 = (~temp16) + 1;
	350	cpu_physical_memory_read((uint32_t)&ib->tx_buf[i], pkt_buf, temp16);
	351	DPRINTF("sending packet, len %d\n", temp16);
7c9d8e07	352	qemu_send_packet(s->vc, pkt_buf, temp16);
66321a11 FB	353	temp8 = LE_T1_POK;
66321a11 FB	354	cpu_physical_memory_write((uint32_t)&ib->btx_ring[i].tmd1_bits, (void *) &temp8, 1);
e80cfcfc	355	s->txptr = (s->txptr + 1) & TX_RING_MOD_MASK;
420557e8 FB	356	s->regs[LE_CSR0] \|= LE_C0_TINT \| LE_C0_INTR;
	357	}
	358	}
66321a11 FB	359	if ((s->regs[LE_CSR0] & LE_C0_INTR) && (s->regs[LE_CSR0] & LE_C0_INEA))
66321a11 FB	360	pic_set_irq(s->irq, 1);
420557e8 FB	361	}
420557e8 FB	362
420557e8 FB	363	static uint32_t ledma_mem_readl(void *opaque, target_phys_addr_t addr)
420557e8 FB	364	{
e80cfcfc	365	LANCEState *s = opaque;
420557e8 FB	366	uint32_t saddr;
420557e8 FB	367
e80cfcfc FB	368	saddr = (addr & LEDMA_MAXADDR) >> 2;
e80cfcfc FB	369	return s->ledmaregs[saddr];
420557e8 FB	370	}
	371
	372	static void ledma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	373	{
e80cfcfc	374	LANCEState *s = opaque;
420557e8 FB	375	uint32_t saddr;
420557e8 FB	376
e80cfcfc FB	377	saddr = (addr & LEDMA_MAXADDR) >> 2;
e80cfcfc FB	378	s->ledmaregs[saddr] = val;
420557e8 FB	379	}
	380
	381	static CPUReadMemoryFunc *ledma_mem_read[3] = {
	382	ledma_mem_readl,
	383	ledma_mem_readl,
	384	ledma_mem_readl,
	385	};
	386
	387	static CPUWriteMemoryFunc *ledma_mem_write[3] = {
	388	ledma_mem_writel,
	389	ledma_mem_writel,
	390	ledma_mem_writel,
	391	};
	392
e80cfcfc FB	393	static void lance_save(QEMUFile f, void opaque)
	394	{
	395	LANCEState *s = opaque;
	396	int i;
	397
	398	qemu_put_be32s(f, &s->leptr);
	399	qemu_put_be16s(f, &s->addr);
66321a11	400	for (i = 0; i < LE_NREGS; i ++)
e80cfcfc FB	401	qemu_put_be16s(f, &s->regs[i]);
	402	qemu_put_buffer(f, s->phys, 6);
	403	qemu_put_be32s(f, &s->irq);
	404	for (i = 0; i < LEDMA_REGS; i ++)
	405	qemu_put_be32s(f, &s->ledmaregs[i]);
	406	}
	407
	408	static int lance_load(QEMUFile f, void opaque, int version_id)
	409	{
	410	LANCEState *s = opaque;
	411	int i;
	412
	413	if (version_id != 1)
	414	return -EINVAL;
	415
	416	qemu_get_be32s(f, &s->leptr);
	417	qemu_get_be16s(f, &s->addr);
66321a11	418	for (i = 0; i < LE_NREGS; i ++)
e80cfcfc FB	419	qemu_get_be16s(f, &s->regs[i]);
	420	qemu_get_buffer(f, s->phys, 6);
	421	qemu_get_be32s(f, &s->irq);
	422	for (i = 0; i < LEDMA_REGS; i ++)
	423	qemu_get_be32s(f, &s->ledmaregs[i]);
	424	return 0;
	425	}
	426
7c9d8e07	427	void lance_init(NICInfo *nd, int irq, uint32_t leaddr, uint32_t ledaddr)
420557e8 FB	428	{
420557e8 FB	429	LANCEState *s;
8d5f07fa	430	int lance_io_memory, ledma_io_memory;
420557e8 FB	431
	432	s = qemu_mallocz(sizeof(LANCEState));
	433	if (!s)
	434	return;
	435
8d5f07fa FB	436	s->irq = irq;
8d5f07fa FB	437
420557e8	438	lance_io_memory = cpu_register_io_memory(0, lance_mem_read, lance_mem_write, s);
66321a11	439	cpu_register_physical_memory(leaddr, 4, lance_io_memory);
8d5f07fa	440
e80cfcfc	441	ledma_io_memory = cpu_register_io_memory(0, ledma_mem_read, ledma_mem_write, s);
8d5f07fa	442	cpu_register_physical_memory(ledaddr, 16, ledma_io_memory);
420557e8	443
7c9d8e07 FB	444	memcpy(s->macaddr, nd->macaddr, 6);
7c9d8e07 FB	445
420557e8	446	lance_reset(s);
7c9d8e07	447
d861b05e	448	s->vc = qemu_new_vlan_client(nd->vlan, lance_receive, lance_can_receive, s);
7c9d8e07 FB	449
	450	snprintf(s->vc->info_str, sizeof(s->vc->info_str),
	451	"lance macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
	452	s->macaddr[0],
	453	s->macaddr[1],
	454	s->macaddr[2],
	455	s->macaddr[3],
	456	s->macaddr[4],
	457	s->macaddr[5]);
	458
e80cfcfc FB	459	register_savevm("lance", leaddr, 1, lance_save, lance_load, s);
e80cfcfc FB	460	qemu_register_reset(lance_reset, s);
420557e8 FB	461	}
420557e8 FB	462