[qemu.git] / hw / vga_int.h

/*
 * QEMU internal VGA defines.
 * 
 * Copyright (c) 2003-2004 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#define MSR_COLOR_EMULATION 0x01
#define MSR_PAGE_SELECT     0x20

#define ST01_V_RETRACE      0x08
#define ST01_DISP_ENABLE    0x01

/* bochs VBE support */
#define CONFIG_BOCHS_VBE

#define VBE_DISPI_MAX_XRES              1600
#define VBE_DISPI_MAX_YRES              1200
#define VBE_DISPI_MAX_BPP               32

#define VBE_DISPI_INDEX_ID              0x0
#define VBE_DISPI_INDEX_XRES            0x1
#define VBE_DISPI_INDEX_YRES            0x2
#define VBE_DISPI_INDEX_BPP             0x3
#define VBE_DISPI_INDEX_ENABLE          0x4
#define VBE_DISPI_INDEX_BANK            0x5
#define VBE_DISPI_INDEX_VIRT_WIDTH      0x6
#define VBE_DISPI_INDEX_VIRT_HEIGHT     0x7
#define VBE_DISPI_INDEX_X_OFFSET        0x8
#define VBE_DISPI_INDEX_Y_OFFSET        0x9
#define VBE_DISPI_INDEX_NB              0xa
      
#define VBE_DISPI_ID0                   0xB0C0
#define VBE_DISPI_ID1                   0xB0C1
#define VBE_DISPI_ID2                   0xB0C2
  
#define VBE_DISPI_DISABLED              0x00
#define VBE_DISPI_ENABLED               0x01
#define VBE_DISPI_GETCAPS               0x02
#define VBE_DISPI_8BIT_DAC              0x20
#define VBE_DISPI_LFB_ENABLED           0x40
#define VBE_DISPI_NOCLEARMEM            0x80
  
#define VBE_DISPI_LFB_PHYSICAL_ADDRESS  0xE0000000

#ifdef CONFIG_BOCHS_VBE

#define VGA_STATE_COMMON_BOCHS_VBE              \
    uint16_t vbe_index;                         \
    uint16_t vbe_regs[VBE_DISPI_INDEX_NB];      \
    uint32_t vbe_start_addr;                    \
    uint32_t vbe_line_offset;                   \
    uint32_t vbe_bank_mask;

#else

#define VGA_STATE_COMMON_BOCHS_VBE

#endif /* !CONFIG_BOCHS_VBE */

#define CH_ATTR_SIZE (160 * 100)
#define VGA_MAX_HEIGHT 2048

#define VGA_STATE_COMMON                                                \
    uint8_t *vram_ptr;                                                  \
    unsigned long vram_offset;                                          \
    unsigned int vram_size;                                             \
    unsigned long bios_offset;                                          \
    unsigned int bios_size;                                             \
    PCIDevice *pci_dev;                                                 \
    uint32_t latch;                                                     \
    uint8_t sr_index;                                                   \
    uint8_t sr[256];                                                    \
    uint8_t gr_index;                                                   \
    uint8_t gr[256];                                                    \
    uint8_t ar_index;                                                   \
    uint8_t ar[21];                                                     \
    int ar_flip_flop;                                                   \
    uint8_t cr_index;                                                   \
    uint8_t cr[256]; /* CRT registers */                                \
    uint8_t msr; /* Misc Output Register */                             \
    uint8_t fcr; /* Feature Control Register */                         \
    uint8_t st00; /* status 0 */                                        \
    uint8_t st01; /* status 1 */                                        \
    uint8_t dac_state;                                                  \
    uint8_t dac_sub_index;                                              \
    uint8_t dac_read_index;                                             \
    uint8_t dac_write_index;                                            \
    uint8_t dac_cache[3]; /* used when writing */                       \
    uint8_t palette[768];                                               \
    int32_t bank_offset;                                                \
    int (*get_bpp)(struct VGAState *s);                                 \
    void (*get_offsets)(struct VGAState *s,                             \
                        uint32_t *pline_offset,                         \
                        uint32_t *pstart_addr);                         \
    void (*get_resolution)(struct VGAState *s,                          \
                        int *pwidth,                                    \
                        int *pheight);                                  \
    VGA_STATE_COMMON_BOCHS_VBE                                          \
    /* display refresh support */                                       \
    DisplayState *ds;                                                   \
    uint32_t font_offsets[2];                                           \
    int graphic_mode;                                                   \
    uint8_t shift_control;                                              \
    uint8_t double_scan;                                                \
    uint32_t line_offset;                                               \
    uint32_t line_compare;                                              \
    uint32_t start_addr;                                                \
    uint32_t plane_updated;                                             \
    uint8_t last_cw, last_ch;                                           \
    uint32_t last_width, last_height; /* in chars or pixels */          \
    uint32_t last_scr_width, last_scr_height; /* in pixels */           \
    uint8_t cursor_start, cursor_end;                                   \
    uint32_t cursor_offset;                                             \
    unsigned int (*rgb_to_pixel)(unsigned int r,                        \
                                 unsigned int g, unsigned b);           \
    /* hardware mouse cursor support */                                 \
    uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32];                  \
    void (*cursor_invalidate)(struct VGAState *s);                      \
    void (*cursor_draw_line)(struct VGAState *s, uint8_t *d, int y);    \
    /* tell for each page if it has been updated since the last time */ \
    uint32_t last_palette[256];                                         \
    uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */


typedef struct VGAState {
    VGA_STATE_COMMON
} VGAState;

static inline int c6_to_8(int v)
{
    int b;
    v &= 0x3f;
    b = v & 1;
    return (v << 2) | (b << 1) | b;
}

void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base, 
                     unsigned long vga_ram_offset, int vga_ram_size);
uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val);
void vga_invalidate_scanlines(VGAState *s, int y1, int y2);

void vga_draw_cursor_line_8(uint8_t *d1, const uint8_t *src1, 
                            int poffset, int w, 
                            unsigned int color0, unsigned int color1,
                            unsigned int color_xor);
void vga_draw_cursor_line_16(uint8_t *d1, const uint8_t *src1, 
                             int poffset, int w, 
                             unsigned int color0, unsigned int color1,
                             unsigned int color_xor);
void vga_draw_cursor_line_32(uint8_t *d1, const uint8_t *src1, 
                             int poffset, int w, 
                             unsigned int color0, unsigned int color1,
                             unsigned int color_xor);

extern const uint8_t sr_mask[8];
extern const uint8_t gr_mask[16];
Commit	Line	Data
798b0c25 FB	1	/*
	2	* QEMU internal VGA defines.
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#define MSR_COLOR_EMULATION 0x01
	25	#define MSR_PAGE_SELECT 0x20
	26
	27	#define ST01_V_RETRACE 0x08
	28	#define ST01_DISP_ENABLE 0x01
	29
	30	/* bochs VBE support */
	31	#define CONFIG_BOCHS_VBE
	32
8454df8b FB	33	#define VBE_DISPI_MAX_XRES 1600
	34	#define VBE_DISPI_MAX_YRES 1200
	35	#define VBE_DISPI_MAX_BPP 32
798b0c25 FB	36
	37	#define VBE_DISPI_INDEX_ID 0x0
	38	#define VBE_DISPI_INDEX_XRES 0x1
	39	#define VBE_DISPI_INDEX_YRES 0x2
	40	#define VBE_DISPI_INDEX_BPP 0x3
	41	#define VBE_DISPI_INDEX_ENABLE 0x4
	42	#define VBE_DISPI_INDEX_BANK 0x5
	43	#define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
	44	#define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
	45	#define VBE_DISPI_INDEX_X_OFFSET 0x8
	46	#define VBE_DISPI_INDEX_Y_OFFSET 0x9
	47	#define VBE_DISPI_INDEX_NB 0xa
	48
	49	#define VBE_DISPI_ID0 0xB0C0
	50	#define VBE_DISPI_ID1 0xB0C1
	51	#define VBE_DISPI_ID2 0xB0C2
	52
	53	#define VBE_DISPI_DISABLED 0x00
	54	#define VBE_DISPI_ENABLED 0x01
8454df8b FB	55	#define VBE_DISPI_GETCAPS 0x02
8454df8b FB	56	#define VBE_DISPI_8BIT_DAC 0x20
798b0c25 FB	57	#define VBE_DISPI_LFB_ENABLED 0x40
	58	#define VBE_DISPI_NOCLEARMEM 0x80
	59
	60	#define VBE_DISPI_LFB_PHYSICAL_ADDRESS 0xE0000000
	61
798b0c25	62	#ifdef CONFIG_BOCHS_VBE
4e3e9d0b FB	63
	64	#define VGA_STATE_COMMON_BOCHS_VBE \
	65	uint16_t vbe_index; \
	66	uint16_t vbe_regs[VBE_DISPI_INDEX_NB]; \
	67	uint32_t vbe_start_addr; \
	68	uint32_t vbe_line_offset; \
798b0c25	69	uint32_t vbe_bank_mask;
4e3e9d0b FB	70
	71	#else
	72
	73	#define VGA_STATE_COMMON_BOCHS_VBE
	74
	75	#endif /* !CONFIG_BOCHS_VBE */
	76
798b0c25	77	#define CH_ATTR_SIZE (160 * 100)
8454df8b	78	#define VGA_MAX_HEIGHT 2048
4e3e9d0b FB	79
	80	#define VGA_STATE_COMMON \
	81	uint8_t *vram_ptr; \
	82	unsigned long vram_offset; \
	83	unsigned int vram_size; \
d5295253 FB	84	unsigned long bios_offset; \
d5295253 FB	85	unsigned int bios_size; \
d2269f6f	86	PCIDevice *pci_dev; \
4e3e9d0b FB	87	uint32_t latch; \
	88	uint8_t sr_index; \
	89	uint8_t sr[256]; \
	90	uint8_t gr_index; \
	91	uint8_t gr[256]; \
	92	uint8_t ar_index; \
	93	uint8_t ar[21]; \
	94	int ar_flip_flop; \
	95	uint8_t cr_index; \
	96	uint8_t cr[256]; /* CRT registers */ \
	97	uint8_t msr; /* Misc Output Register */ \
	98	uint8_t fcr; /* Feature Control Register */ \
	99	uint8_t st00; /* status 0 */ \
	100	uint8_t st01; /* status 1 */ \
	101	uint8_t dac_state; \
	102	uint8_t dac_sub_index; \
	103	uint8_t dac_read_index; \
	104	uint8_t dac_write_index; \
	105	uint8_t dac_cache[3]; /* used when writing */ \
	106	uint8_t palette[768]; \
	107	int32_t bank_offset; \
	108	int (get_bpp)(struct VGAState s); \
	109	void (get_offsets)(struct VGAState s, \
	110	uint32_t *pline_offset, \
	111	uint32_t *pstart_addr); \
a130a41e FB	112	void (get_resolution)(struct VGAState s, \
	113	int *pwidth, \
	114	int *pheight); \
4e3e9d0b FB	115	VGA_STATE_COMMON_BOCHS_VBE \
	116	/* display refresh support */ \
	117	DisplayState *ds; \
	118	uint32_t font_offsets[2]; \
	119	int graphic_mode; \
	120	uint8_t shift_control; \
	121	uint8_t double_scan; \
	122	uint32_t line_offset; \
	123	uint32_t line_compare; \
	124	uint32_t start_addr; \
546fa6ab	125	uint32_t plane_updated; \
4e3e9d0b FB	126	uint8_t last_cw, last_ch; \
	127	uint32_t last_width, last_height; /* in chars or pixels */ \
	128	uint32_t last_scr_width, last_scr_height; /* in pixels */ \
	129	uint8_t cursor_start, cursor_end; \
	130	uint32_t cursor_offset; \
	131	unsigned int (*rgb_to_pixel)(unsigned int r, \
	132	unsigned int g, unsigned b); \
a8aa669b FB	133	/* hardware mouse cursor support */ \
	134	uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32]; \
	135	void (cursor_invalidate)(struct VGAState s); \
	136	void (cursor_draw_line)(struct VGAState s, uint8_t *d, int y); \
4e3e9d0b FB	137	/* tell for each page if it has been updated since the last time */ \
4e3e9d0b FB	138	uint32_t last_palette[256]; \
798b0c25	139	uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
4e3e9d0b FB	140
	141
	142	typedef struct VGAState {
	143	VGA_STATE_COMMON
798b0c25 FB	144	} VGAState;
798b0c25 FB	145
a8aa669b FB	146	static inline int c6_to_8(int v)
	147	{
	148	int b;
	149	v &= 0x3f;
	150	b = v & 1;
	151	return (v << 2) \| (b << 1) \| b;
	152	}
	153
798b0c25 FB	154	void vga_common_init(VGAState s, DisplayState ds, uint8_t *vga_ram_base,
	155	unsigned long vga_ram_offset, int vga_ram_size);
	156	uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
	157	void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val);
a8aa669b FB	158	void vga_invalidate_scanlines(VGAState *s, int y1, int y2);
	159
	160	void vga_draw_cursor_line_8(uint8_t d1, const uint8_t src1,
	161	int poffset, int w,
	162	unsigned int color0, unsigned int color1,
	163	unsigned int color_xor);
	164	void vga_draw_cursor_line_16(uint8_t d1, const uint8_t src1,
	165	int poffset, int w,
	166	unsigned int color0, unsigned int color1,
	167	unsigned int color_xor);
	168	void vga_draw_cursor_line_32(uint8_t d1, const uint8_t src1,
	169	int poffset, int w,
	170	unsigned int color0, unsigned int color1,
	171	unsigned int color_xor);
798b0c25 FB	172
	173	extern const uint8_t sr_mask[8];
	174	extern const uint8_t gr_mask[16];