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7d13299d
FB		 1/*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0
FB		 16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7d13299d 19 */
e4533c7a 20#include "config.h"
93ac68bc 21#include "exec.h"
956034d7 22#include "disas.h"
7d13299d 23
fbf9eeb3
FB		 24#if !defined(CONFIG_SOFTMMU)
25#undef EAX
26#undef ECX
27#undef EDX
28#undef EBX
29#undef ESP
30#undef EBP
31#undef ESI
32#undef EDI
33#undef EIP
34#include <signal.h>
35#include <sys/ucontext.h>
36#endif
37
36bdbe54
FB		 38int tb_invalidated_flag;
39
dc99065b 40//#define DEBUG_EXEC
9de5e440 41//#define DEBUG_SIGNAL
7d13299d 42
93ac68bc 43#if defined(TARGET_ARM) || defined(TARGET_SPARC)
e4533c7a
FB		 44/* XXX: unify with i386 target */
45void cpu_loop_exit(void)
46{
47 longjmp(env->jmp_env, 1);
48}
49#endif
50
fbf9eeb3
FB		 51/* exit the current TB from a signal handler. The host registers are
52 restored in a state compatible with the CPU emulator
53 */
54void cpu_resume_from_signal(CPUState *env1, void *puc)
55{
56#if !defined(CONFIG_SOFTMMU)
57 struct ucontext *uc = puc;
58#endif
59
60 env = env1;
61
62 /* XXX: restore cpu registers saved in host registers */
63
64#if !defined(CONFIG_SOFTMMU)
65 if (puc) {
66 /* XXX: use siglongjmp ? */
67 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
68 }
69#endif
70 longjmp(env->jmp_env, 1);
71}
72
7d13299d
FB		 73/* main execution loop */
74
e4533c7a 75int cpu_exec(CPUState *env1)
7d13299d 76{
e4533c7a
FB		 77 int saved_T0, saved_T1, saved_T2;
78 CPUState *saved_env;
04369ff2
FB		 79#ifdef reg_EAX
80 int saved_EAX;
81#endif
82#ifdef reg_ECX
83 int saved_ECX;
84#endif
85#ifdef reg_EDX
86 int saved_EDX;
87#endif
88#ifdef reg_EBX
89 int saved_EBX;
90#endif
91#ifdef reg_ESP
92 int saved_ESP;
93#endif
94#ifdef reg_EBP
95 int saved_EBP;
96#endif
97#ifdef reg_ESI
98 int saved_ESI;
99#endif
100#ifdef reg_EDI
101 int saved_EDI;
8c6939c0
FB		 102#endif
103#ifdef __sparc__
104 int saved_i7, tmp_T0;
04369ff2 105#endif
68a79315 106 int code_gen_size, ret, interrupt_request;
7d13299d 107 void (*gen_func)(void);
9de5e440 108 TranslationBlock *tb, **ptb;
dab2ed99 109 uint8_t *tc_ptr, *cs_base, *pc;
6dbad63e 110 unsigned int flags;
8c6939c0 111
7d13299d
FB		 112 /* first we save global registers */
113 saved_T0 = T0;
114 saved_T1 = T1;
e4533c7a 115 saved_T2 = T2;
7d13299d
FB		 116 saved_env = env;
117 env = env1;
e4533c7a
FB		 118#ifdef __sparc__
119 /* we also save i7 because longjmp may not restore it */
120 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
121#endif
122
123#if defined(TARGET_I386)
04369ff2
FB		 124#ifdef reg_EAX
125 saved_EAX = EAX;
126 EAX = env->regs[R_EAX];
127#endif
128#ifdef reg_ECX
129 saved_ECX = ECX;
130 ECX = env->regs[R_ECX];
131#endif
132#ifdef reg_EDX
133 saved_EDX = EDX;
134 EDX = env->regs[R_EDX];
135#endif
136#ifdef reg_EBX
137 saved_EBX = EBX;
138 EBX = env->regs[R_EBX];
139#endif
140#ifdef reg_ESP
141 saved_ESP = ESP;
142 ESP = env->regs[R_ESP];
143#endif
144#ifdef reg_EBP
145 saved_EBP = EBP;
146 EBP = env->regs[R_EBP];
147#endif
148#ifdef reg_ESI
149 saved_ESI = ESI;
150 ESI = env->regs[R_ESI];
151#endif
152#ifdef reg_EDI
153 saved_EDI = EDI;
154 EDI = env->regs[R_EDI];
155#endif
7d13299d 156
9de5e440 157 /* put eflags in CPU temporary format */
fc2b4c48
FB		 158 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
159 DF = 1 - (2 * ((env->eflags >> 10) & 1));
9de5e440 160 CC_OP = CC_OP_EFLAGS;
fc2b4c48 161 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a
FB		 162#elif defined(TARGET_ARM)
163 {
164 unsigned int psr;
165 psr = env->cpsr;
166 env->CF = (psr >> 29) & 1;
167 env->NZF = (psr & 0xc0000000) ^ 0x40000000;
168 env->VF = (psr << 3) & 0x80000000;
169 env->cpsr = psr & ~0xf0000000;
170 }
93ac68bc 171#elif defined(TARGET_SPARC)
67867308 172#elif defined(TARGET_PPC)
e4533c7a
FB		 173#else
174#error unsupported target CPU
175#endif
3fb2ded1 176 env->exception_index = -1;
9d27abd9 177
7d13299d 178 /* prepare setjmp context for exception handling */
3fb2ded1
FB		 179 for(;;) {
180 if (setjmp(env->jmp_env) == 0) {
ee8b7021 181 env->current_tb = NULL;
3fb2ded1
FB		 182 /* if an exception is pending, we execute it here */
183 if (env->exception_index >= 0) {
184 if (env->exception_index >= EXCP_INTERRUPT) {
185 /* exit request from the cpu execution loop */
186 ret = env->exception_index;
187 break;
188 } else if (env->user_mode_only) {
189 /* if user mode only, we simulate a fake exception
190 which will be hanlded outside the cpu execution
191 loop */
83479e77 192#if defined(TARGET_I386)
3fb2ded1
FB		 193 do_interrupt_user(env->exception_index,
194 env->exception_is_int,
195 env->error_code,
196 env->exception_next_eip);
83479e77 197#endif
3fb2ded1
FB		 198 ret = env->exception_index;
199 break;
200 } else {
83479e77 201#if defined(TARGET_I386)
3fb2ded1
FB		 202 /* simulate a real cpu exception. On i386, it can
203 trigger new exceptions, but we do not handle
204 double or triple faults yet. */
205 do_interrupt(env->exception_index,
206 env->exception_is_int,
207 env->error_code,
d05e66d2 208 env->exception_next_eip, 0);
ce09776b
FB		 209#elif defined(TARGET_PPC)
210 do_interrupt(env);
83479e77 211#endif
3fb2ded1
FB		 212 }
213 env->exception_index = -1;
214 }
3fb2ded1
FB		 215 T0 = 0; /* force lookup of first TB */
216 for(;;) {
8c6939c0 217#ifdef __sparc__
3fb2ded1
FB		 218 /* g1 can be modified by some libc? functions */
219 tmp_T0 = T0;
8c6939c0 220#endif
68a79315 221 interrupt_request = env->interrupt_request;
2e255c6b 222 if (__builtin_expect(interrupt_request, 0)) {
68a79315
FB		 223#if defined(TARGET_I386)
224 /* if hardware interrupt pending, we execute it */
225 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
3f337316
FB		 226 (env->eflags & IF_MASK) &&
227 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
68a79315 228 int intno;
fbf9eeb3 229 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
a541f297 230 intno = cpu_get_pic_interrupt(env);
f193c797 231 if (loglevel & CPU_LOG_TB_IN_ASM) {
68a79315
FB		 232 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
233 }
d05e66d2 234 do_interrupt(intno, 0, 0, 0, 1);
907a5b26
FB		 235 /* ensure that no TB jump will be modified as
236 the program flow was changed */
237#ifdef __sparc__
238 tmp_T0 = 0;
239#else
240 T0 = 0;
241#endif
68a79315 242 }
ce09776b 243#elif defined(TARGET_PPC)
9fddaa0c
FB		 244#if 0
245 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
246 cpu_ppc_reset(env);
247 }
248#endif
249 if (msr_ee != 0) {
ce09776b 250 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
9fddaa0c
FB		 251 /* Raise it */
252 env->exception_index = EXCP_EXTERNAL;
253 env->error_code = 0;
ce09776b
FB		 254 do_interrupt(env);
255 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
9fddaa0c
FB		 256 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
257 /* Raise it */
258 env->exception_index = EXCP_DECR;
259 env->error_code = 0;
260 do_interrupt(env);
261 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
262 }
ce09776b 263 }
68a79315 264#endif
bf3e8bf1
FB		 265 if (interrupt_request & CPU_INTERRUPT_EXITTB) {
266 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
267 /* ensure that no TB jump will be modified as
268 the program flow was changed */
269#ifdef __sparc__
270 tmp_T0 = 0;
271#else
272 T0 = 0;
273#endif
274 }
68a79315
FB		 275 if (interrupt_request & CPU_INTERRUPT_EXIT) {
276 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
277 env->exception_index = EXCP_INTERRUPT;
278 cpu_loop_exit();
279 }
3fb2ded1 280 }
7d13299d 281#ifdef DEBUG_EXEC
f193c797 282 if (loglevel & CPU_LOG_EXEC) {
e4533c7a 283#if defined(TARGET_I386)
3fb2ded1
FB		 284 /* restore flags in standard format */
285 env->regs[R_EAX] = EAX;
286 env->regs[R_EBX] = EBX;
287 env->regs[R_ECX] = ECX;
288 env->regs[R_EDX] = EDX;
289 env->regs[R_ESI] = ESI;
290 env->regs[R_EDI] = EDI;
291 env->regs[R_EBP] = EBP;
292 env->regs[R_ESP] = ESP;
293 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
68a79315 294 cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP);
3fb2ded1 295 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 296#elif defined(TARGET_ARM)
1b21b62a 297 env->cpsr = compute_cpsr();
3fb2ded1 298 cpu_arm_dump_state(env, logfile, 0);
1b21b62a 299 env->cpsr &= ~0xf0000000;
93ac68bc 300#elif defined(TARGET_SPARC)
93a40ea9 301 cpu_sparc_dump_state (env, logfile, 0);
67867308
FB		 302#elif defined(TARGET_PPC)
303 cpu_ppc_dump_state(env, logfile, 0);
e4533c7a
FB		 304#else
305#error unsupported target CPU
306#endif
3fb2ded1 307 }
7d13299d 308#endif
3f337316
FB		 309 /* we record a subset of the CPU state. It will
310 always be the same before a given translated block
311 is executed. */
e4533c7a 312#if defined(TARGET_I386)
2e255c6b 313 flags = env->hflags;
3f337316 314 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
3fb2ded1
FB		 315 cs_base = env->segs[R_CS].base;
316 pc = cs_base + env->eip;
e4533c7a 317#elif defined(TARGET_ARM)
3fb2ded1
FB		 318 flags = 0;
319 cs_base = 0;
320 pc = (uint8_t *)env->regs[15];
93ac68bc 321#elif defined(TARGET_SPARC)
67867308 322 flags = 0;
ce09776b 323 cs_base = (uint8_t *)env->npc;
67867308
FB		 324 pc = (uint8_t *) env->pc;
325#elif defined(TARGET_PPC)
326 flags = 0;
327 cs_base = 0;
328 pc = (uint8_t *)env->nip;
e4533c7a
FB		 329#else
330#error unsupported CPU
331#endif
3fb2ded1
FB		 332 tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
333 flags);
d4e8164f 334 if (!tb) {
1376847f
FB		 335 TranslationBlock **ptb1;
336 unsigned int h;
337 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
338
339
3fb2ded1 340 spin_lock(&tb_lock);
1376847f
FB		 341
342 tb_invalidated_flag = 0;
343
344 /* find translated block using physical mappings */
345 phys_pc = get_phys_addr_code(env, (unsigned long)pc);
346 phys_page1 = phys_pc & TARGET_PAGE_MASK;
347 phys_page2 = -1;
348 h = tb_phys_hash_func(phys_pc);
349 ptb1 = &tb_phys_hash[h];
350 for(;;) {
351 tb = *ptb1;
352 if (!tb)
353 goto not_found;
354 if (tb->pc == (unsigned long)pc &&
355 tb->page_addr[0] == phys_page1 &&
356 tb->cs_base == (unsigned long)cs_base &&
357 tb->flags == flags) {
358 /* check next page if needed */
b516f85c
FB		 359 if (tb->page_addr[1] != -1) {
360 virt_page2 = ((unsigned long)pc & TARGET_PAGE_MASK) +
361 TARGET_PAGE_SIZE;
1376847f
FB		 362 phys_page2 = get_phys_addr_code(env, virt_page2);
363 if (tb->page_addr[1] == phys_page2)
364 goto found;
365 } else {
366 goto found;
367 }
368 }
369 ptb1 = &tb->phys_hash_next;
370 }
371 not_found:
3fb2ded1 372 /* if no translated code available, then translate it now */
d4e8164f 373 tb = tb_alloc((unsigned long)pc);
3fb2ded1
FB		 374 if (!tb) {
375 /* flush must be done */
b453b70b 376 tb_flush(env);
3fb2ded1
FB		 377 /* cannot fail at this point */
378 tb = tb_alloc((unsigned long)pc);
379 /* don't forget to invalidate previous TB info */
380 ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
381 T0 = 0;
382 }
383 tc_ptr = code_gen_ptr;
384 tb->tc_ptr = tc_ptr;
385 tb->cs_base = (unsigned long)cs_base;
386 tb->flags = flags;
facc68be 387 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
1376847f
FB		 388 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
389
390 /* check next page if needed */
391 virt_page2 = ((unsigned long)pc + tb->size - 1) & TARGET_PAGE_MASK;
392 phys_page2 = -1;
393 if (((unsigned long)pc & TARGET_PAGE_MASK) != virt_page2) {
394 phys_page2 = get_phys_addr_code(env, virt_page2);
395 }
396 tb_link_phys(tb, phys_pc, phys_page2);
397
398 found:
36bdbe54
FB		 399 if (tb_invalidated_flag) {
400 /* as some TB could have been invalidated because
401 of memory exceptions while generating the code, we
402 must recompute the hash index here */
403 ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
404 while (*ptb != NULL)
405 ptb = &(*ptb)->hash_next;
406 T0 = 0;
407 }
1376847f 408 /* we add the TB in the virtual pc hash table */
3fb2ded1
FB		 409 *ptb = tb;
410 tb->hash_next = NULL;
411 tb_link(tb);
25eb4484 412 spin_unlock(&tb_lock);
9de5e440 413 }
9d27abd9 414#ifdef DEBUG_EXEC
f193c797 415 if (loglevel & CPU_LOG_EXEC) {
3fb2ded1
FB		 416 fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
417 (long)tb->tc_ptr, (long)tb->pc,
418 lookup_symbol((void *)tb->pc));
419 }
9d27abd9 420#endif
8c6939c0 421#ifdef __sparc__
3fb2ded1 422 T0 = tmp_T0;
8c6939c0 423#endif
facc68be 424 /* see if we can patch the calling TB. */
bf3e8bf1
FB		 425 if (T0 != 0
426#if defined(TARGET_I386) && defined(USE_CODE_COPY)
427 && (tb->cflags & CF_CODE_COPY) ==
428 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
429#endif
430 ) {
3fb2ded1
FB		 431 spin_lock(&tb_lock);
432 tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
97eb5b14
FB		 433#if defined(USE_CODE_COPY)
434 /* propagates the FP use info */
435 ((TranslationBlock *)(T0 & ~3))->cflags |=
436 (tb->cflags & CF_FP_USED);
437#endif
3fb2ded1
FB		 438 spin_unlock(&tb_lock);
439 }
3fb2ded1 440 tc_ptr = tb->tc_ptr;
83479e77 441 env->current_tb = tb;
3fb2ded1
FB		 442 /* execute the generated code */
443 gen_func = (void *)tc_ptr;
8c6939c0 444#if defined(__sparc__)
3fb2ded1
FB		 445 __asm__ __volatile__("call %0\n\t"
446 "mov %%o7,%%i0"
447 : /* no outputs */
448 : "r" (gen_func)
449 : "i0", "i1", "i2", "i3", "i4", "i5");
8c6939c0 450#elif defined(__arm__)
3fb2ded1
FB		 451 asm volatile ("mov pc, %0\n\t"
452 ".global exec_loop\n\t"
453 "exec_loop:\n\t"
454 : /* no outputs */
455 : "r" (gen_func)
456 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
bf3e8bf1
FB		 457#elif defined(TARGET_I386) && defined(USE_CODE_COPY)
458{
459 if (!(tb->cflags & CF_CODE_COPY)) {
97eb5b14
FB		 460 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
461 save_native_fp_state(env);
462 }
bf3e8bf1
FB		 463 gen_func();
464 } else {
97eb5b14
FB		 465 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
466 restore_native_fp_state(env);
467 }
bf3e8bf1
FB		 468 /* we work with native eflags */
469 CC_SRC = cc_table[CC_OP].compute_all();
470 CC_OP = CC_OP_EFLAGS;
471 asm(".globl exec_loop\n"
472 "\n"
473 "debug1:\n"
474 " pushl %%ebp\n"
475 " fs movl %10, %9\n"
476 " fs movl %11, %%eax\n"
477 " andl $0x400, %%eax\n"
478 " fs orl %8, %%eax\n"
479 " pushl %%eax\n"
480 " popf\n"
481 " fs movl %%esp, %12\n"
482 " fs movl %0, %%eax\n"
483 " fs movl %1, %%ecx\n"
484 " fs movl %2, %%edx\n"
485 " fs movl %3, %%ebx\n"
486 " fs movl %4, %%esp\n"
487 " fs movl %5, %%ebp\n"
488 " fs movl %6, %%esi\n"
489 " fs movl %7, %%edi\n"
490 " fs jmp *%9\n"
491 "exec_loop:\n"
492 " fs movl %%esp, %4\n"
493 " fs movl %12, %%esp\n"
494 " fs movl %%eax, %0\n"
495 " fs movl %%ecx, %1\n"
496 " fs movl %%edx, %2\n"
497 " fs movl %%ebx, %3\n"
498 " fs movl %%ebp, %5\n"
499 " fs movl %%esi, %6\n"
500 " fs movl %%edi, %7\n"
501 " pushf\n"
502 " popl %%eax\n"
503 " movl %%eax, %%ecx\n"
504 " andl $0x400, %%ecx\n"
505 " shrl $9, %%ecx\n"
506 " andl $0x8d5, %%eax\n"
507 " fs movl %%eax, %8\n"
508 " movl $1, %%eax\n"
509 " subl %%ecx, %%eax\n"
510 " fs movl %%eax, %11\n"
511 " fs movl %9, %%ebx\n" /* get T0 value */
512 " popl %%ebp\n"
513 :
514 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
515 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
516 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
517 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
518 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
519 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
520 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
521 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
522 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
523 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
524 "a" (gen_func),
525 "m" (*(uint8_t *)offsetof(CPUState, df)),
526 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
527 : "%ecx", "%edx"
528 );
529 }
530}
ae228531 531#else
3fb2ded1 532 gen_func();
ae228531 533#endif
83479e77 534 env->current_tb = NULL;
4cbf74b6
FB		 535 /* reset soft MMU for next block (it can currently
536 only be set by a memory fault) */
537#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
3f337316
FB		 538 if (env->hflags & HF_SOFTMMU_MASK) {
539 env->hflags &= ~HF_SOFTMMU_MASK;
4cbf74b6
FB		 540 /* do not allow linking to another block */
541 T0 = 0;
542 }
543#endif
3fb2ded1
FB		 544 }
545 } else {
7d13299d 546 }
3fb2ded1
FB		 547 } /* for(;;) */
548
7d13299d 549
e4533c7a 550#if defined(TARGET_I386)
97eb5b14
FB		 551#if defined(USE_CODE_COPY)
552 if (env->native_fp_regs) {
553 save_native_fp_state(env);
554 }
555#endif
9de5e440 556 /* restore flags in standard format */
fc2b4c48 557 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
9de5e440 558
7d13299d 559 /* restore global registers */
04369ff2
FB		 560#ifdef reg_EAX
561 EAX = saved_EAX;
562#endif
563#ifdef reg_ECX
564 ECX = saved_ECX;
565#endif
566#ifdef reg_EDX
567 EDX = saved_EDX;
568#endif
569#ifdef reg_EBX
570 EBX = saved_EBX;
571#endif
572#ifdef reg_ESP
573 ESP = saved_ESP;
574#endif
575#ifdef reg_EBP
576 EBP = saved_EBP;
577#endif
578#ifdef reg_ESI
579 ESI = saved_ESI;
580#endif
581#ifdef reg_EDI
582 EDI = saved_EDI;
8c6939c0 583#endif
e4533c7a 584#elif defined(TARGET_ARM)
1b21b62a 585 env->cpsr = compute_cpsr();
93ac68bc 586#elif defined(TARGET_SPARC)
67867308 587#elif defined(TARGET_PPC)
e4533c7a
FB		 588#else
589#error unsupported target CPU
590#endif
8c6939c0
FB		 591#ifdef __sparc__
592 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
04369ff2 593#endif
7d13299d
FB		 594 T0 = saved_T0;
595 T1 = saved_T1;
e4533c7a 596 T2 = saved_T2;
7d13299d
FB		 597 env = saved_env;
598 return ret;
599}
6dbad63e 600
fbf9eeb3
FB		 601/* must only be called from the generated code as an exception can be
602 generated */
603void tb_invalidate_page_range(target_ulong start, target_ulong end)
604{
dc5d0b3d
FB		 605 /* XXX: cannot enable it yet because it yields to MMU exception
606 where NIP != read address on PowerPC */
607#if 0
fbf9eeb3
FB		 608 target_ulong phys_addr;
609 phys_addr = get_phys_addr_code(env, start);
610 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
dc5d0b3d 611#endif
fbf9eeb3
FB		 612}
613
1a18c71b 614#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
e4533c7a 615
6dbad63e
FB		 616void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
617{
618 CPUX86State *saved_env;
619
620 saved_env = env;
621 env = s;
a412ac57 622 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
a513fe19 623 selector &= 0xffff;
2e255c6b
FB		 624 cpu_x86_load_seg_cache(env, seg_reg, selector,
625 (uint8_t *)(selector << 4), 0xffff, 0);
a513fe19 626 } else {
b453b70b 627 load_seg(seg_reg, selector);
a513fe19 628 }
6dbad63e
FB		 629 env = saved_env;
630}
9de5e440 631
d0a1ffc9
FB		 632void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
633{
634 CPUX86State *saved_env;
635
636 saved_env = env;
637 env = s;
638
639 helper_fsave(ptr, data32);
640
641 env = saved_env;
642}
643
644void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
645{
646 CPUX86State *saved_env;
647
648 saved_env = env;
649 env = s;
650
651 helper_frstor(ptr, data32);
652
653 env = saved_env;
654}
655
e4533c7a
FB		 656#endif /* TARGET_I386 */
657
67b915a5
FB		 658#if !defined(CONFIG_SOFTMMU)
659
3fb2ded1
FB		 660#if defined(TARGET_I386)
661
b56dad1c 662/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6
FB		 663 the effective address of the memory exception. 'is_write' is 1 if a
664 write caused the exception and otherwise 0'. 'old_set' is the
665 signal set which should be restored */
2b413144 666static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 667 int is_write, sigset_t *old_set,
668 void *puc)
9de5e440 669{
a513fe19
FB		 670 TranslationBlock *tb;
671 int ret;
68a79315 672
83479e77
FB		 673 if (cpu_single_env)
674 env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6 675#if defined(DEBUG_SIGNAL)
bf3e8bf1
FB		 676 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
677 pc, address, is_write, *(unsigned long *)old_set);
9de5e440 678#endif
25eb4484 679 /* XXX: locking issue */
fbf9eeb3 680 if (is_write && page_unprotect(address, pc, puc)) {
fd6ce8f6
FB		 681 return 1;
682 }
fbf9eeb3 683
3fb2ded1 684 /* see if it is an MMU fault */
93a40ea9
FB		 685 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
686 ((env->hflags & HF_CPL_MASK) == 3), 0);
3fb2ded1
FB		 687 if (ret < 0)
688 return 0; /* not an MMU fault */
689 if (ret == 0)
690 return 1; /* the MMU fault was handled without causing real CPU fault */
691 /* now we have a real cpu fault */
a513fe19
FB		 692 tb = tb_find_pc(pc);
693 if (tb) {
9de5e440
FB		 694 /* the PC is inside the translated code. It means that we have
695 a virtual CPU fault */
bf3e8bf1 696 cpu_restore_state(tb, env, pc, puc);
3fb2ded1 697 }
4cbf74b6 698 if (ret == 1) {
3fb2ded1 699#if 0
4cbf74b6
FB		 700 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
701 env->eip, env->cr[2], env->error_code);
3fb2ded1 702#endif
4cbf74b6
FB		 703 /* we restore the process signal mask as the sigreturn should
704 do it (XXX: use sigsetjmp) */
705 sigprocmask(SIG_SETMASK, old_set, NULL);
706 raise_exception_err(EXCP0E_PAGE, env->error_code);
707 } else {
708 /* activate soft MMU for this block */
3f337316 709 env->hflags |= HF_SOFTMMU_MASK;
fbf9eeb3 710 cpu_resume_from_signal(env, puc);
4cbf74b6 711 }
3fb2ded1
FB		 712 /* never comes here */
713 return 1;
714}
715
e4533c7a 716#elif defined(TARGET_ARM)
3fb2ded1 717static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 718 int is_write, sigset_t *old_set,
719 void *puc)
3fb2ded1
FB		 720{
721 /* XXX: do more */
722 return 0;
723}
93ac68bc
FB		 724#elif defined(TARGET_SPARC)
725static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 726 int is_write, sigset_t *old_set,
727 void *puc)
93ac68bc 728{
b453b70b 729 /* XXX: locking issue */
fbf9eeb3 730 if (is_write && page_unprotect(address, pc, puc)) {
b453b70b
FB		 731 return 1;
732 }
733 return 0;
93ac68bc 734}
67867308
FB		 735#elif defined (TARGET_PPC)
736static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 737 int is_write, sigset_t *old_set,
738 void *puc)
67867308
FB		 739{
740 TranslationBlock *tb;
ce09776b 741 int ret;
67867308 742
ce09776b 743#if 1
67867308
FB		 744 if (cpu_single_env)
745 env = cpu_single_env; /* XXX: find a correct solution for multithread */
746#endif
747#if defined(DEBUG_SIGNAL)
748 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
749 pc, address, is_write, *(unsigned long *)old_set);
750#endif
751 /* XXX: locking issue */
fbf9eeb3 752 if (is_write && page_unprotect(address, pc, puc)) {
67867308
FB		 753 return 1;
754 }
755
ce09776b 756 /* see if it is an MMU fault */
7f957d28 757 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
ce09776b
FB		 758 if (ret < 0)
759 return 0; /* not an MMU fault */
760 if (ret == 0)
761 return 1; /* the MMU fault was handled without causing real CPU fault */
762
67867308
FB		 763 /* now we have a real cpu fault */
764 tb = tb_find_pc(pc);
765 if (tb) {
766 /* the PC is inside the translated code. It means that we have
767 a virtual CPU fault */
bf3e8bf1 768 cpu_restore_state(tb, env, pc, puc);
67867308 769 }
ce09776b 770 if (ret == 1) {
67867308 771#if 0
ce09776b
FB		 772 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
773 env->nip, env->error_code, tb);
67867308
FB		 774#endif
775 /* we restore the process signal mask as the sigreturn should
776 do it (XXX: use sigsetjmp) */
bf3e8bf1 777 sigprocmask(SIG_SETMASK, old_set, NULL);
9fddaa0c 778 do_raise_exception_err(env->exception_index, env->error_code);
ce09776b
FB		 779 } else {
780 /* activate soft MMU for this block */
fbf9eeb3 781 cpu_resume_from_signal(env, puc);
ce09776b 782 }
67867308
FB		 783 /* never comes here */
784 return 1;
785}
e4533c7a
FB		 786#else
787#error unsupported target CPU
788#endif
9de5e440 789
2b413144
FB		 790#if defined(__i386__)
791
bf3e8bf1
FB		 792#if defined(USE_CODE_COPY)
793static void cpu_send_trap(unsigned long pc, int trap,
794 struct ucontext *uc)
795{
796 TranslationBlock *tb;
797
798 if (cpu_single_env)
799 env = cpu_single_env; /* XXX: find a correct solution for multithread */
800 /* now we have a real cpu fault */
801 tb = tb_find_pc(pc);
802 if (tb) {
803 /* the PC is inside the translated code. It means that we have
804 a virtual CPU fault */
805 cpu_restore_state(tb, env, pc, uc);
806 }
807 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
808 raise_exception_err(trap, env->error_code);
809}
810#endif
811
e4533c7a
FB		 812int cpu_signal_handler(int host_signum, struct siginfo *info,
813 void *puc)
9de5e440 814{
9de5e440
FB		 815 struct ucontext *uc = puc;
816 unsigned long pc;
bf3e8bf1 817 int trapno;
97eb5b14 818
d691f669
FB		 819#ifndef REG_EIP
820/* for glibc 2.1 */
fd6ce8f6
FB		 821#define REG_EIP EIP
822#define REG_ERR ERR
823#define REG_TRAPNO TRAPNO
d691f669 824#endif
fc2b4c48 825 pc = uc->uc_mcontext.gregs[REG_EIP];
bf3e8bf1
FB		 826 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
827#if defined(TARGET_I386) && defined(USE_CODE_COPY)
828 if (trapno == 0x00 || trapno == 0x05) {
829 /* send division by zero or bound exception */
830 cpu_send_trap(pc, trapno, uc);
831 return 1;
832 } else
833#endif
834 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
835 trapno == 0xe ?
836 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
837 &uc->uc_sigmask, puc);
2b413144
FB		 838}
839
bc51c5c9
FB		 840#elif defined(__x86_64__)
841
842int cpu_signal_handler(int host_signum, struct siginfo *info,
843 void *puc)
844{
845 struct ucontext *uc = puc;
846 unsigned long pc;
847
848 pc = uc->uc_mcontext.gregs[REG_RIP];
849 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
850 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
851 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
852 &uc->uc_sigmask, puc);
853}
854
83fb7adf 855#elif defined(__powerpc__)
2b413144 856
83fb7adf
FB		 857/***********************************************************************
858 * signal context platform-specific definitions
859 * From Wine
860 */
861#ifdef linux
862/* All Registers access - only for local access */
863# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
864/* Gpr Registers access */
865# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
866# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
867# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
868# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
869# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
870# define LR_sig(context) REG_sig(link, context) /* Link register */
871# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
872/* Float Registers access */
873# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
874# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
875/* Exception Registers access */
876# define DAR_sig(context) REG_sig(dar, context)
877# define DSISR_sig(context) REG_sig(dsisr, context)
878# define TRAP_sig(context) REG_sig(trap, context)
879#endif /* linux */
880
881#ifdef __APPLE__
882# include <sys/ucontext.h>
883typedef struct ucontext SIGCONTEXT;
884/* All Registers access - only for local access */
885# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
886# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
887# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
888# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
889/* Gpr Registers access */
890# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
891# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
892# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
893# define CTR_sig(context) REG_sig(ctr, context)
894# define XER_sig(context) REG_sig(xer, context) /* Link register */
895# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
896# define CR_sig(context) REG_sig(cr, context) /* Condition register */
897/* Float Registers access */
898# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
899# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
900/* Exception Registers access */
901# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
902# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
903# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
904#endif /* __APPLE__ */
905
d1d9f421 906int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a 907 void *puc)
2b413144 908{
25eb4484 909 struct ucontext *uc = puc;
25eb4484 910 unsigned long pc;
25eb4484
FB		 911 int is_write;
912
83fb7adf 913 pc = IAR_sig(uc);
25eb4484
FB		 914 is_write = 0;
915#if 0
916 /* ppc 4xx case */
83fb7adf 917 if (DSISR_sig(uc) & 0x00800000)
25eb4484
FB		 918 is_write = 1;
919#else
83fb7adf 920 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
25eb4484
FB		 921 is_write = 1;
922#endif
923 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 924 is_write, &uc->uc_sigmask, puc);
2b413144
FB		 925}
926
2f87c607
FB		 927#elif defined(__alpha__)
928
e4533c7a 929int cpu_signal_handler(int host_signum, struct siginfo *info,
2f87c607
FB		 930 void *puc)
931{
932 struct ucontext *uc = puc;
933 uint32_t *pc = uc->uc_mcontext.sc_pc;
934 uint32_t insn = *pc;
935 int is_write = 0;
936
8c6939c0 937 /* XXX: need kernel patch to get write flag faster */
2f87c607
FB		 938 switch (insn >> 26) {
939 case 0x0d: // stw
940 case 0x0e: // stb
941 case 0x0f: // stq_u
942 case 0x24: // stf
943 case 0x25: // stg
944 case 0x26: // sts
945 case 0x27: // stt
946 case 0x2c: // stl
947 case 0x2d: // stq
948 case 0x2e: // stl_c
949 case 0x2f: // stq_c
950 is_write = 1;
951 }
952
953 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 954 is_write, &uc->uc_sigmask, puc);
2f87c607 955}
8c6939c0
FB		 956#elif defined(__sparc__)
957
e4533c7a
FB		 958int cpu_signal_handler(int host_signum, struct siginfo *info,
959 void *puc)
8c6939c0
FB		 960{
961 uint32_t *regs = (uint32_t *)(info + 1);
962 void *sigmask = (regs + 20);
963 unsigned long pc;
964 int is_write;
965 uint32_t insn;
966
967 /* XXX: is there a standard glibc define ? */
968 pc = regs[1];
969 /* XXX: need kernel patch to get write flag faster */
970 is_write = 0;
971 insn = *(uint32_t *)pc;
972 if ((insn >> 30) == 3) {
973 switch((insn >> 19) & 0x3f) {
974 case 0x05: // stb
975 case 0x06: // sth
976 case 0x04: // st
977 case 0x07: // std
978 case 0x24: // stf
979 case 0x27: // stdf
980 case 0x25: // stfsr
981 is_write = 1;
982 break;
983 }
984 }
985 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 986 is_write, sigmask, NULL);
8c6939c0
FB		 987}
988
989#elif defined(__arm__)
990
e4533c7a
FB		 991int cpu_signal_handler(int host_signum, struct siginfo *info,
992 void *puc)
8c6939c0
FB		 993{
994 struct ucontext *uc = puc;
995 unsigned long pc;
996 int is_write;
997
998 pc = uc->uc_mcontext.gregs[R15];
999 /* XXX: compute is_write */
1000 is_write = 0;
1001 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1002 is_write,
1003 &uc->uc_sigmask);
1004}
1005
38e584a0
FB		 1006#elif defined(__mc68000)
1007
1008int cpu_signal_handler(int host_signum, struct siginfo *info,
1009 void *puc)
1010{
1011 struct ucontext *uc = puc;
1012 unsigned long pc;
1013 int is_write;
1014
1015 pc = uc->uc_mcontext.gregs[16];
1016 /* XXX: compute is_write */
1017 is_write = 0;
1018 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1019 is_write,
bf3e8bf1 1020 &uc->uc_sigmask, puc);
38e584a0
FB		 1021}
1022
9de5e440 1023#else
2b413144 1024
3fb2ded1 1025#error host CPU specific signal handler needed
2b413144 1026
9de5e440 1027#endif
67b915a5
FB		 1028
1029#endif /* !defined(CONFIG_SOFTMMU) */
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